ANALOG DEVICES AD712 Dual Precision Low Cost High Speed BiFET Op Amp handbook
Contents
1. 100 2 S 40 ul o z a B 10 E 2 n 5 zn HER 0 01 1k 10k 100k 1M 10M FREQUENCY Hz Figure 6 Output Impedance vs Frequency 5 0 4 5 4 0 3 5 UNITY GAIN BANDWIDTH MHz 3 0 60 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 9 Unity Gain Bandwiath vs Temperature REV B OPEN LOOP GAIN dB PHASE MARGIN C 20 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 10 Open Loop Gain and Phase Margin vs Frequency CMR dB FREQUENCY Hz Figure 13 Common Mode Rejec tion vs Frequency THD dB 100 1k 10k 100k FREQUENCY Hz Figure 16 Total Harmonic Distor tion vs Frequency REV B N a N eo E Em a OPEN LOOP GAIN dB E e eo 95 0 5 10 15 20 SUPPLY VOLTAGE Volts Figure 11 Open Loop Gain vs Supply Voltage N oa N eo a OUTPUT VOLTAGE Volts p p S INPUT FREQUENCY Hz Figure 14 Lar2. In addition to a significant improvement in settling time the low offset voltage low offset voltage drift and high open loop gain of the AD711 AD712 family assures 12 bit accuracy over the full operating temperature range The excellent high speed performance of the AD712 is shown in the oscilloscope photos of Figure 25 Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712 both photos show the worst case situation a full scale input transition The DAC s 4 kQ 10 kO 8 KQ 4 4 KQ output impedance together with a 10 kO feedback resistor produce an op amp noise gain of 3 25 The current output from the DAC produces a 10 V step at the op amp output 0 to 10 V Figure 25a 10 V to 0 V Figure 25b Therefore with an ideal op amp settling to 1 2 LSB 40 01 requires that 375 uV or less appears at the summing junction This means that the error between the input and output that voltage which appears at the AD712 summing junction must be less than 375 uV As shown in Figure 25 the total settling time for the AD712 AD565 combination is 1 2 microseconds OUTPUT 10V TO 10V TOPPE gii d SUMMING I 1 JUNCTION e a E b Full Scale Positive Transition Figure 25 Settling Characteristics for AD712 with AD565A REV B AD712 OP AMP SETTLING TIME A MATHEMATICAL MODEL The design of the AD712 gives careful attention to optimizing individua
3. 18 V the absolute maximum input voltage is equal to the supply voltage ORDERING GUIDE Temperature Package Package Model Range Description Option AD712ACHIPS 40 C to 85 C Bare Die AD712AH 40 C to 85 C 8 Lead Metal Can H 08A AD712AQ 40 C to 85 C 8 Lead Ceramic DIP Q 8 AD712BH 40 C to 85 C 8 Lead Metal Can H 08A AD712BQ 40 C to 85 C 8 Lead Ceramic DIP Q 8 AD712CH 40 C to 85 C 8 Lead Metal Can H 08A AD712CN 40 C to 85 C 8 Lead Plastic DIP N 8 AD712JN 0 C to 70 C 8 Lead Plastic DIP N 8 AD712 R 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712JR REEL 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712JR REEL7 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712KN 0 C to 70 C 8 Lead Plastic DIP N 8 AD712KR 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712KR REEL 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712KR REEL7 0 C to 70 C 8 Lead Plastic SOIC R 8 AD712SCHIPS 55 C to 125 C Bare Die AD712SQ 55 C to 125 C 8 Lead Ceramic DIP Q 8 AD712SQ 883B 55 C to 125 C 8 Lead Ceramic DIP Q 8 AD712TQ 55 C to 125 C 8 Lead Ceramic DIP Q 8 AD712TQ 883B 55 C to 125 C 8 Lead Ceramic DIP Q 8 METALIZATION PHOTOGRAPH Dimensions shown in inches and mm Contact factory for latest dimensions 0 1126 2 860 V OUTPUT IN 8 7 6 i Quer am B ROI 9 z 5 N 0 07205 1 830 1 OUTPUT pe db 2 3 4 IN N V REV B AD712 Typical Performance Charact
4. 034 0 86 1 27 0 013 0 33 0 0098 0 25 0 040 1 01 TUN 0 034 0 86 PLANE 0 016 0 40 b 0 021 0 53 0 028 0 71 BSC 0 0075 0 19 INSULATION 0 016 0 41 O08 127 MAX BASE amp SEATING PLANE on EQUALLY SPACED REV B 15 C1020c 1 4 98 PRINTED IN U S A
5. Figure 28b Settling Characteristics 0 V to 10 V Step Upper Trace Output of AD712 Under Test 5 V Div Lower Trace Amplified Error Voltage 0 01 Div 5109 OR EQUIVALENT FLAT TOP PULSE GENERATION O O 15V 15V The input of the settling time fixture is driven by a flat top pulse generator The error signal output from the false summing node of Al is clamped amplified by A2 and then clamped again The error signal is thus clamped twice once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp The Tektronix oscilloscope preamp type 1426 was carefully chosen because it does not overload with these input levels Amplifier A2 needs to be a very high speed FET input op amp it provides a gain of 10 amplifying the error signal output of A1 GUARDING The low input bias current 15 pA and low noise characteristics of the AD712 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current to voltage converters The use of a guarding technique such as that shown in Figure 30 in printed circuit board layout and construction is critical to minimize leakage currents The guard ring is connected to a low impedance potential at the same level as the inputs High impedance signal lines should not be extended for any unnecessary length on the printed circuit board TO 99 H PACKAGE PLASTIC MINI DIP N PACKAGE CERD
6. 0 0 Ab7A 0 0 ANALOG DEVICES Dual Precision Low Cost High Speed BiFET Op Amp AD712 FEATURES Enhanced Replacements for LF412 and TL082 AC PERFORMANCE Settles to 0 01 in 1 0 ms 16 V s min Slew Rate AD712J 3 MHz min Unity Gain Bandwidth AD712J DC PERFORMANCE 0 30 mV max Offset Voltage AD712C 5 pV C max Drift AD712C 200 V mV min Open Loop Gain AD712K 4 uV p p max Noise 0 1 Hz to 10 Hz AD712C Surface Mount Available in Tape and Reel in Accor dance with EIA 481A Standard MIL STD 883B Parts Available Single Version Available AD711 Quad Version AD713 Available in Plastic Mini DIP Plastic SOIC Hermetic Cerdip Hermetic Metal Can Packages and Chip Form PRODUCT DESCRIPTION The AD712 is a high speed precision monolithic operational amplifier offering high performance at very modest prices Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and in many cases bipolar op amps The superior ac and dc performance of this op amp makes it suitable for active filter applications With a slew rate of 16 Vis and a settling time of 1 us to 0 01 the AD712 is ideal as a buffer for 12 bit D A and A D Converters and as a high speed integrator The settling time is unmatched by any similar IC amplifier The combination of excellent
7. GE Differential t20 20 20 V Common Mode Voltage 14 5 11 5 14 5 11 5 14 5 11 5 Tmn to Tmax Vs 4 Vs 2 Vs 4 Vs 2 Vs 4 TVs 2 V Common Mode Rejection Ratio Vem 10 V 76 88 80 88 86 94 dB Tmn to Tmax 76 76 76 84 80 84 86 90 dB Vem 7 11 V 70 84 76 84 76 90 dB Tmn to Tmax 70 70 70 80 74 80 74 84 dB INPUT VOLTAGE NOISE 2 2 2 LV p p 45 45 45 nVAHz 22 22 22 nV VHz 18 18 18 nV VHz 16 16 16 nVAHz INPUT CURRENT NOISE 0 01 0 01 0 01 pA AHz OPEN LOOP GAIN 150 400 200 400 200 400 V mV 100 100 100 100 100 V mV OUTPUT CHARACTERISTICS Voltage 13 12 5 13 9 13 3 13 12 5 13 9 13 3 13 12 5 13 9 13 3 V 12 12 12 13 8 13 1 12 13 8 13 1 12 13 8 13 1 V Current 25 25 25 mA POWER SUPPLY Rated Performance 15 15 15 V Operating Range 4 5 18 4 5 18 4 5 18 V Quiescent Current 5 0 6 8 5 0 6 0 5 0 5 6 mA NOTES Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T4 25 C Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T 25 C For higher temperatures the current doubles every 10 C Defined as voltage between inputs such that neither exceeds 10 V from ground ypically exceeding 14 1 V negative common mode voltage on either input results in an output phase reversal Specifications in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing qu
8. IP Q PACKAGE AND SOIC R PACKAGE Sy E E P Figure 30 Board Layout for Guarding Inputs TEKTRONIX 7A26 OSCILLOSCOPE PREAMP Verror X 5 INPUT SECTION I T quer HP2835 m 5pF O O 15V 15V 10kQ 0 2 0 6pF Figure 29 Settling Time Test Circuit REV B AD712 D A CONVERTER APPLICATIONS The AD712 is an excellent output amplifier for CMOS DACs It can be used to perform both 2 quadrant and 4 quadrant op eration The output impedance of a DAC using an inverted R 2R ladder approaches R for codes containing many 1s 3R for codes containing a single 1 and for codes containing all zero the output impedance is infinite For example the output resistance of the AD7545 will modu late between 11 kQ and 33 kQ Therefore with the DAC s internal feedback resistance of 11 kQ the noise gain will vary from 2 to 4 3 This changing noise gain modulates the effect of the input offset voltage of the amplifier resulting in nonlinear DAC amplifier performance The AD712K with guaranteed 700 uV offset voltage minimizes this effect to achieve 12 bit performance Figures 31 and 32 show the AD712 and AD7545 12 bit CMOS DAC configured for unipolar binary 2 quadrant multi plication or bipolar 4 quadrant multiplication operation Capacitor C1 provides phase compensation to reduce overshoot and ringing GAIN ADJUST DATA INPUT FOR VALUES OF R1 AND R2 SEE TABLE I ANALOG V COMMON
9. UT OUTPUT NONINVERTING INVERTING OUTPUT INPUT v NONINVERTING INPUT screening includes 168 hour burn in as well as other environ mental and physical tests The AD712 is available in an 8 lead plastic mini DIP SOIC cerdip TO 99 metal can or in chip form PRODUCT HIGHLIGHTS 1 The AD712 offers excellent overall performance at very competitive prices 2 Analog Devices advanced processing technology and with 100 testing guarantees a low input offset voltage 0 3 mV max C grade 3 mV max J grade Input offset voltage is specified in the warmed up condition Analog Devices laser wafer drift trimming process reduces input offset voltage drifts to 5 wV C max on the AD712C 3 Along with precision dc performance the AD712 offers excellent dynamic response It settles to 0 01 in 1 us and has a minimum slew rate of 16 V us Thus this device is ideal for applications such as DAC and ADC buffers which re quire a combination of superior ac and dc performance 4 The AD712 has a guaranteed and tested maximum voltage noise of 4 uV p p 0 1 Hz to 10 Hz AD712C 5 Analog Devices well matched ion implanted JFETs ensure a guaranteed input bias current at either input of 50 pA max AD712C and an input offset current of 10 pA max AD712C Both input bias current and input offset current are guaranteed in the warmed up condition One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Worl
10. Vpp R2A GAIN ADJUST VIN o R1A REFER TO ANALOG TABLE COMMON DB11 DBO Vpp R2B O GAIN ADJUST VIN o R1B REFER TO TABLE ANALOG COMMON 15V DB11 DB0 Figure 31 Unipolar Binary Operation R1 and R2 calibrate the zero offset and gain error of the DAC Specific values for these resistors depend upon the grade of AD7545 and are shown below Table I Recommended Trim Resistor Values vs Grades of the AD7545 for Vpp 5 V Figure 32 Bipolar Operation 10 Trim Resistor JNIAQISD KN BQ TD LN UD GLN GUD R1 500 Q 200 Q 100 Q 20 Q R2 150 Q 68 Q 330 6 8 Q R4 20kQ 1 R5 20kQ 1 OVouT REV B AD712 Figures 33a and 33b show the settling time characteristics of the AD712 when used as a DAC output buffer for the AD7545 b Full Scale Negative Transition Figure 33 Settling Characteristics for AD712 with AD7545 NOISE CHARACTERISTICS The random nature of noise particularly in the 1 f region makes it difficult to specify in practical terms At the same time designers of precision instrumentation require certain guaran teed maximum noise levels to realize the full accuracy of their equipment The AD712C grade is specified at a maximum level of 4 0 uV p p in a 0 1 Hz to 10 Hz bandwidth Each AD712C receives a 10096 noise test for two 10 second intervals devices with any excursion in excess of 4 0 uV are rejected The screened lot is th
11. ality levels All min and max specifications are guaranteed although only those shown in boldface are tested on all production units Specifications subject to change without notice 2 REV B AD712 ABSOLUTE MAXIMUM RATINGS Supply Voltage credenu cece eee ee ene 18 V Internal Power Dissipation Input Voltage lesse 18 V Output Short Circuit Duration Indefinite Differential Input Voltage Vs and Vs ee 65 C to 150 C hd eet Se 65 C to 125 C Storage Temperature Range Q H Storage Temperature Range N R Operating Temperature Range ADTI2JK 543 ERAI Ret 0 C to 70 C AD TT 2AIB C ex state ace tU 6 oh aoe 40 C to 85 C ADTIA2SAD3 2i e236 RIP 55 C to 125 C Lead Temperature Range Soldering 60 sec 300 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics 8 Lead Plastic Package 8 Lead Cerdip Package za 165 C Watt 8c 22 C Watt 64 110 C Watt 8 Lead Metal Can Package jc 65 C Watt 0j4 150 C Watt 8 Lead SOIC Package 6j 100 C gt For supply voltages less than
12. ch enables the amplifier to drive capacitive loads exceeding 1500 pF the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit Low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the 100 Q series resistor and the load capacitance Cj Figure 37 shows a typical transient response for this connection sil o INPUT TYPICAL CAPACITANCE LIMIT FOR VARIOUS LOAD RESISTORS Ry C UP TO 2k 1500pF Vin 10kQ 1500pF 200 1000pF Figure 36 Circuit for Driving a Large Capacitive Load 12 REV B AD712 SECOND ORDER LOW PASS FILTER Figure 38 depicts the AD712 configured as a second order oe femal RANGE X ee ee Butterworth low pass filter With the values as shown the corner frequency will be 20 kHz however the wide bandwidth of the AD712 permits a corner frequency as high as several hundred kilohertz Equations for component selection are shown below R1 R2 user selected typical values 10 RQ 100 RQ 1 414 Q 707 ci ds i n fed Oa Fag MRD E Qua XRD C1 560pF CENTER 5 000 000 0 Hz SPAN 10 000 000 0 Hz RBW 30 kHz VBW 30 kHz ST 8 SEC Figure 39 Figure 38 Second Order Low Pass Filter An important property of filters is their out of band rejection The simple 20 kHz low pass filter shown in Figure 38 might be used to condition a signal contaminated with clock pulses or sampling glitches which have
13. considerable energy content at high frequencies The low output impedance and high bandwidth of the AD712 minimize high frequency feedthrough as shown in Figure 39 The upper trace is that of another low cost BIFET op amp showing 17 dB more feedthrough at 5 MHz REV B a3 AD712 28000 61900 64900 61900 28000 0 0011 F 4 99kQ SEE TEXT Figure 40 9 Pole Chebychev Filter 9 POLE CHEBYCHEV FILTER REF 5 0 dBm MARKER 96 800 0 Hz Figure 40 shows the AD712 and its dual counterpart the IU dB DIV A RANGECSO dBm s29dBm AD711 as a 9 pole Chebychev filter using active frequency dependent negative resistors FDNR With a cutoff frequency of 50 kHz and better than 90 dB rejection it may be used as an antialiasing filter for a 12 bit Data Acquisition System with 100 kHz throughput As shown in Figure 40 the filter is comprised of four FDNRs A B C D having values of 4 9395 x 107 and 5 9276 X 107 farad seconds Each FDNR active network provides a two pole response for a total of 8 poles The 9th pole consists of a 0 001 uF capacitor and a 124 KQ resistor at Pin 3 of ampli fier A2 Figure 41 depicts the circuits for each FDNR with the proper selection of R To achieve optimal performance the 0 001 uF capacitors must be selected for 1 or better matching START 0 Hz STOP 200 000 0 Hz and all resistors should have 196 or better tolerance RBW3DUHz VBW30Hz gt ST 09 6 SEC Figure 42 High Frequency Response for 9 Po
14. d Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 AD 1 1 2 SPEC FI CATI 0 NS Vs 15 V T 25 C unless otherwise noted AD712J AIS AD712K B T AD712C Parameter Min Typ Max Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE Initial Offset 0 3 3 1 1 0 2 1 0 0 7 0 7 0 1 0 3 mV Tmn to Tmax 4 2 12 2 0 1 5 1 5 0 6 mV vs Temp 7 20 20 20 7 10 3 5 uV C vs Supply 76 95 80 100 86 110 dB Tmn to Tmax 76 76 76 80 86 dB Long Term Offset Stability 15 15 15 uV Month INPUT BIAS CURRENT Vom 70V 25 75 20 75 20 50 pA Vom 0 V Tmax 0 6 1 6 26 1 7 4 8 77 0 5 1 3 20 1 7 4 8 77 1 3 3 2 nA Vem 10 V 100 100 75 pA INPUT OFFSET CURRENT Vom 0V 10 25 5 25 5 10 pA Vom 0 V Tmax 0 3 0 7 11 0 6 1 6 26 0 1 0 3 5 0 6 1 6 26 0 3 0 7 nA MATCHING CHARACTERISTICS Input Offset Voltage 3 1 1 1 0 0 7 0 7 0 3 mV Tmn to Tmax 4 2 12 2 0 1 5 1 5 0 6 mV Input Offset Voltage Drift 20 20 20 10 5 uV C Input Bias Current 25 25 10 pA Crosstalk f 1 kHz 120 120 120 dB f 100 kHz 90 90 90 dB FREQUENCY RESPONSE Small Signal Bandwidth 3 0 4 0 3 4 4 0 3 4 4 0 MHz Full Power Response 200 200 200 kHz Slew Rate 16 20 18 20 18 20 V us Settling Time to 0 01 1 0 1 2 1 0 1 2 1 0 1 2 us Total Harmonic Distortion 0 0003 0 0003 0 0003 INPUT IMPEDANCE Differential 3 x 10 2 5 5 3 x 10 2 5 5 3 x 1012 5 5 O pF Common Mode 3 x 105 5 3 x 105 5 3 x 10 2 5 5 O pF INPUT VOLTAGE RAN
15. en submitted to Quality Control for verification on an AQL basis All other grades of the AD712 are sample tested on an AQL basis to a limit of 6 uV p p 0 1 Hz to 10 Hz REV B DRIVING THE ANALOG INPUT OF AN A D CONVERTER An op amp driving the analog input of an A D converter such as that shown in Figure 34 must be capable of maintaining a constant output voltage under dynamically changing load condi tions In successive approximation converters the input current is compared to a series of switched trial currents The compari son point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of A D input current The output impedance of a feedback amplifier is made artificially low by the loop gain At high frequencies where the loop gain is low the amplifier output impedance can approach its open loop value Most IC amplifiers exhibit a minimum open loop output impedance of 25 Q due to current limiting resistors OFFSET ADJUST 15v ANALOG COM Figure 34 AD712 as ADC Unity Gain Buffer A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage If the A D conversion speed is not excessive and the bandwidth of the amplifier is sufficient the amplifier s output will return to the nominal value before the converter makes its comparison However many amplifiers have relatively narrow bandwidth yielding slow recovery from o
16. eristics 20 2 gt 15 o z o W 10 E R 2kO 3 25 C 55 a zZ 0 0 5 10 15 20 SUPPLY VOLTAGE Volts Figure 1 Input Voltage Swing vs Supply Voltage QUIESCENT CURRENT mA N o B a o 5 10 15 20 SUPPLY VOLTAGE Volts eo Figure 4 Quiescent Current vs Supply Voltage MAX J GRADE LIMITS INPUT BIAS CURRENT pA COMMON MODE VOLTAGE Volts Figure 7 Input Bias Current vs Common Mode Voltage 20 15 10 OUTPUT VOLTAGE SWING Volts 0 5 10 15 20 SUPPLY VOLTAGE Volts Figure 2 Output Voltage Swing vs Supply Voltage INPUT BIAS CURRENT Ve 0 Amps 12 10 60 40 40 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 5 Input Bias Current vs Temperature OUTPUT CURRENT SHORT CIRCUIT CURRENT LIMIT mA 10 60 40 20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE C Figure 8 Short Circuit Current Limit vs Temperature 30 Q i o 25 o gt f c 20 zZ A 15V SUPPLIES w 15 fe o 10 gt E 5 R5 2 o 0 10 100 1k 10k LOAD RESISTANCE Q Figure 3 Output Voltage Swing vs Load Resistance
17. ge Signal Frequency Response 100 10 INPUT NOISE VOLTAGE nV Hz 1 10 100 1k 10k 100k FREQUENCY Hz Figure 17 Input Noise Voltage Spectral Density POWER SUPPLY REJECTION dB 0 10 100 1k 10k 100k 1M SUPPLY MODULATION FREQUENCY Hz Figure 12 Power Supply Rejection vs Frequency o H 8 9 3 8 ga gt 22 1 0 1 0 01 o 0 o ERROR 1 0 1 0 01 g a 5 m 8 E 2 o 10 0 5 0 6 0 7 0 8 0 9 1 0 SETTLING TIME ps Figure 15 Output Swing and Error vs Settling Time 25 20 15 10 SLEW RATE V us 0 0 100 200 300 400 500 600 700 800 900 INPUT ERROR SIGNAL mV AT SUMMING JUNCTION Figure 18 Slew Rate vs Input Error Signal AD712 25 20 SLEW RATE V us Figure 20 T H D Test Circuit Vour O 15 60 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 19 Slew Rate vs Temperature CROSSTALK 20 Loc TOVN i Figure 22c Unity Gain Follower Figure 22a Unity Gain Follower Figure 22b Unity Gain Follower Pulse Response Sma
18. itance of the op amp since the two are in parallel Figure 26a Simplified Model of the AD712 Used as a Current Out DAC Buffer When Ro and Io are replaced with their Thevenin Vy and Ry equivalents the general purpose inverting amplifier of Figure 26b is created Note that when using this general model capaci tance Cy is EITHER the input capacitance of the op amp if a simple inverting op amp is being simulated OR it is the com bined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled Figure 26b Simplified Model of the AD712 Used as an Inverter In either case the capacitance Cy causes the system to go from a one pole to a two pole response this additional pole increases settling time by introducing peaking or ringing in the op amp output Since the value of Cx can be estimated with reasonable accuracy Equation 2 can be used to choose a small capacitor Cz to cancel the input pole and optimize amplifier response Figure 27 is a graphical solution of Equation 2 for the AD712 with R 4 KQ 0 10 20 30 40 50 60 Figure 27 Value of Capacitor Cr vs Value of Cx 8 REV B AD712 The photos of Figures 28a and 28b show the dynamic response of the AD712 in the settling test circuit of Figure 29 Figure 28a Settling Characteristics 0 V to 10 V Step Upper Trace Output of AD712 Under Test 5 V Div Lower Trace Amplified Error Voltage 0 01 Div
19. l circuit components in addition a careful trade off was made the gain bandwidth product 4 MHz and slew rate 20 V us were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin and therefore stability Thus designed the AD712 settles to 0 01 with a 10 V output step in under 1 us while retaining the ability to drive a 250 pF load capaci tance when operating as a unity gain follower If an op amp is modeled as an ideal integrator with a unity gain crossover frequency of 9 21 Equation 1 will accurately de scribe the small signal behavior of the circuit of Figure 26a consisting of an op amp connected as an I to V converter at the output of a bipolar or CMOS DAC This equation would com pletely describe the output of the system if not for the op amp s finite slew rate and other nonlinear effects Equation 1 Voa R I R C 2C IN f x 2 2 ERC fo T Oo o where 3 op amp s unity gain frequency T R Gy noise gain of circuit This equation may then be solved for Cg Equation 2 c 22 Gn 24 RC y amp 1 Gy A Ro Ro o o In these equations capacitor Cx is the total capacitor appearing the inverting terminal of the op amp When modeling a DAC buffer application the Norton equivalent circuit of Figure 26a can be used directly capacitance Cy is the total capacitance of the output of the DAC plus the input capac
20. le Chebychev Filter R 24 9kO FOR 4 9395E 15 29 4kQ FOR 5 9276E 15 Figure 41 FDNR for 9 Pole Chebychev Filter 14 REV B AD712 OUTLINE DIMENSIONS Dimensions shown in inches and mm Mini DIP Cerdip N 8 Q 8 0 390 9 91 E 0 005 0 13 0 055 1 35 sae ea E MAX 5 S Sud 0 250 0 310 6 35 7 87 Cu i 0 300 7 62 0 310 7 87 X N y REL 0 220 5 59 PIN1 0 035 0 01 0 165 0 01 0 890 0 25 p 0 195 4 95 4 19 0 25 i 0 115 2 93 0 220 5 59 p N Y NOR F 0 18 0 01 es wee a 000 029 0 015 0 38 0 310 7 87 0 125 3 18 JL las 0 76 I 0 060 1 52 MIN elke SEATING 0 011 0 003 0 200 5 08 0 018 0 003 0 100 0 033 0 84 SLANE 0 204 0 081 MAXy HAA 0 150 0 460 0 081 2 54 NOM gt e 0 125 3 18 d t 3 81 ole TYP 15 0 200 5 08 pe i gt a E ATING 1 0 008 0 20 0 014 0 36 0 100 0 030 0 76 D ANE 15 0 015 0 38 0 023 0 58 2 54 0 070 1 78 o BSC TO 99 SOIC H 08A R 8 REFERENCE PLANE aise kod 0 500 12 70 B 0 1890 4 80 0 185 4 70 MIN HR 0 165 4 19 8 5 i 0 2440 6 20 0 1574 4 00 0 2284 5 80 4 4 0 1497 3 80 lt 2 8 RIR S i Wn Slo oM PIN 1 0 0688 1 75 0 0196 0 50 E euo 0 0532 1 35 lt 0 0099 0 25 45 9 E lj 2 s SS 0 0098 0 25 y n 0 0040 0 10 4 amp j mil Fi wv wee 8 gt seamh 98509 288050 aoogolozg ooon BSC 0
21. ll Signal Pulse Response Large Signal NI SNFENERMNNMN TVET ME ALT Figure 23c Unity Gain Inverter Pulse Response Small Signal Figure 23a Unity Gain Inverter Figure 23b Unity Gain Inverter Pulse Response Large Signal 6 REV B AD712 OPTIMIZING SETTLING TIME Most bipolar high speed D A converters have current outputs therefore for most applications an external op amp is required for current to voltage conversion The settling time of the con verter op amp combination depends on the settling time of the DAC and output amplifier A good approximation is ts Total ts DACY ts AMP The settling time of an op amp DAC buffer will vary with the noise gain of the circuit the DAC output capacitance and with the amount of external compensation capacitance across the DAC output scaling resistor Settling time for a bipolar DAC is typically 100 ns to 500 ns Previously conventional op amps have required much longer settling times than have typical state of the art DACs therefore the amplifier settling time has been the major limitation to a high speed voltage output D to A function The introduction of the AD711 AD712 family of op amps with their 1 us to 0 01 of final value settling time now permits the full high speed capabilities of most modern DACs to be realized 0 1p F les OUT BIPOLAR sme L JN eae a Full Scale Negative Transition OFFSET ADJUST
22. noise performance and low input current also make the AD712 useful for photo diode preamps Common mode rejection of 88 dB and open loop gain of 400 V mV ensure 12 bit performance even in high speed unity gain buffer circuits The AD712 is pinned out in a standard op amp configuration and is available in seven performance grades The AD712 and AD712K are rated over the commercial temperature range of 0 C to 70 C The AD712A AD712B and AD712C are rated over the industrial temperature range of 40 C to 85 C The AD712S and AD712T are rated over the military temperature range of 55 C to 125 C and are available processed to MIL STD 883 B Rev C Extended reliability PLUS screening is available specified over the commercial and industrial temperature ranges PLUS REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices CONNECTION DIAGRAMS TO 99 H Package AMPLIFIER NO 1 Vs AMPLIFIER NO 2 O OUTPUT 1j 7 OUTPUT G vamus A soar o G NONINVERTING MN OUTPUT o 4 S INPUT Vs Plastic Mini DIP N Package SOIC R Package and Cerdip Q Package AMPLIFIER NO 1 AMPLIFIER NO 2 OUTPUT 1 s V INVERTING OUTP
23. utput transients The AD712 is ideally suited to drive high speed A D converters since it offers both wide bandwidth and high open loop gain 11 AD712 BUSNEEZCIN EESEEZNEEIE Eee ea SE EXE uet pA EA fe ee Ale ARA Ep PEN ea a E et pty eT Eee pn Figure 37 Transient Response R 2 kQ C 500 pF ACTIVE FILTER APPLICATIONS In active filter applications using op amps the dc accuracy of the amplifier is critical to optimal filter performance The amplifier s offset voltage and bias current contribute to output error Offset voltage will be passed by the filter and may be amplified to produce excessive output offset For low frequency applications requiring large value input resistors bias currents flowing through these resistors will also generate an offset voltage In addition at higher frequencies an op amp s dynamics must be carefully considered Here slew rate bandwidth and open loop gain play a major role in op amp selection The slew b Sink Current 1 mA rate must be fast as well as symmetrical to minimize distortion Figure 35 ADC Input Unity Gain Buffer Recovery Times The amplifier s bandwidth in conjunction with the filter s gain will dictate the frequency response of the filter DRIVING A LARGE CAPACITIVE LOAD The use of a high performance amplifier such as the AD712 will The circuit in Figure 36 employs a 100 Q isolation resistor minimize both dc and ac errors in all active filter applications whi
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