ANALOG DEVICES AD7112* LC 2 MOS LOGDAC Dual Logarithmic D/A Converter handbook
Contents
1. where Rpac isthe DAC ladder resistance N isthe DAC code in D ecimal 0xN lt 240 DACSsA1 and B1 control the gain and Q of the filter character istic while DACs A2 and B2 control the cutoff frequency Circuit equations 1 02 83 84 87 88 Resonant frequency fy 1 2 R3C1 Quality factor R6 R8 x 2 is the feedback resistance of DAC B1 in Figure 22 Bandpass Gain R2 R1 Programmable range for component values shown is fy 0 kHz to 15 kHz and Q 0 3 to 4 5 LOW PASS OUTPUT BANDPASS OUTPUT Figure 22 Programmable State Variable Filter REV 0 11 AD7112 OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Pin Plastic DIP N 20 20 11 PIN1 0 280 7 11 NP 0 240 rin 10 0 325 8 25 1 060 26 90 0 300 7 62 0 925 23 50 0 060 1 1 0 195 4 95 0 210 0 015 0 38 5 33 0 115 2 93 MAX 0 130 0 160 4 06 An 3 30 0 015 0 381 0 115 2 93 0 008 0 204 e gt je 0 022 0 558 0 100 2 54 0 070 aS SEATING 0 014 0 356 BSC 0 045 1 15 PLANE 20 Pin SOIC R 20 0 5118 13 00 0 4961 12 60 20 11 0 2992 7 60 0 2914 7 40 PIN 1 0 4193 10 65 0 3937 10 00 1 10 gt je 0 0500 1 27 0 1043 2 65 0 0291 0 74 je BSC 0 0926 2 35 0 0098 0 25 ree UC Nr gt e 0 0118 0 30 0 0192 0 49 0 0125 ls 32 20529 0 27 0500 ae ml 02. 7 Vit NOTES 1 ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10 TO 90 OF Vpp tF 20ns 2 CONTROL TIMING MEASUREMENT REFERENCE LEVEL Vy V 2 Figure 3 Write Cycle Timing Diagram DYNAMIC PERFORMANCE T he dynamic performance of the AD 7112 will depend on the gain and phase characteristics of the output amplifier together with the optimum choice of PC board layout and decoupling components Circuit layout is most important if the optimum performance of the AD 7112 is to be achieved M ost application problems stem from either poor layout grounding errors or in appropriate choice of amplifier Ensure that the layout of the printed circuit board has the digital and analog lines separated as much as possible T ake care not to run any digital track alongside an analog signal track Establish a single point analog ground star ground separate from the logic system ground Place this ground as close as possible to the AD 7112 Connect all analog grounds to this star ground and also connect the AD 7112 DGND to this ground Do not connect any other digi tal grounds to this analog ground point Low impedance analog and digital power supply common returns are essential for low noise and high performance of these converters therefore the foil width of these tracks should be as wide as possible T he use of ground planes is recommended as this minimizes impedance paths and also guards the analog circuitry from digita
3. AGND DGND 0 V Vy A AC PERFORMANCE CHARACTE RISTICS Viy B 10 V Output amplifier AD712 except where noted Ta Ta 40C to Parameter 25 C 85 C Units Conditions Comments DC Supply Rejection A Gain A Vpp 0 001 0 005 dB max AVpp 5 Input Code 00000000 D igital to Analog Glitch Impulse 10 10 nV styp M easured with AD 843 as output amplifier for input code transition 10000000 to 00000000 Output Capacitance Cout Cours 50 50 pF max AC Feedthrough Vin Ato OUT A 94 90 dB max Vin A Vin B 26V rmsat 1 kHz DAC Registers loaded with all 1s Viu B to OUT B 94 90 dB max C hannel to C hannel Isolation Vin A to OUT B 87 87 dB typ Vin A 26V rmsat 10 kHz sine wave Vin B 20 V DAC Registers loaded with all Os Vin BtoOUT A 87 87 dB typ Vin B 26V rms at 10 kHz sine wave Vin A 20 V DAC Registers loaded with all Os Digital eedthrough 1 1 nV styp M easured with input code transitions of all Os to all 1s Output N oise Voltage D ensity 30 Hz to 50 kHz 15 15 nV NHz typ Measured between Reg A and OUT A or between Reg B and OUT B T otal armonic Distortion 91 91 dB typ Vin A Vin 6V rms at 1 kHz DAC Registers loaded with all Os NOTES 1G uaranteed by design not production tested Specifications subject to change without notice REV 0 3 AD7112 ABSOLUTE MAXIMUM RATINGS Lead T emperature Soldering 10 secs 300 C to AGND orDGND 0 3 V
4. 7 V Power Dissipation SOIC 1W AGND to DGND 0 3 V 0 3V Thermal Impedance 75 C Digital InputstoDGND 0 3V Vpp 0 3V L ead T emperature Soldering OUT A OUT B to AGND 0 3 V 0 3 V Vapor Phase 60 secs 215 C Vin A V Bto AGND 25 V Infrared 15 secs 220 C Vnra A Verg tO AGND 25 V Stresses above those listed under Absolute M aximum Ratings may cause Operating T emperature Range permanent damage to the device This is a stress rating only and functional All Versions 40 C to 85 C operation of the device at these or any other conditions above those listed in the Junction Temperature 150 C Operational sections of this specification is not implied Exposure to absolute Storage T emperature 65 C to 150 C maximum rating conditions for extended periods may affect device reliability Only lanes EX pat FETTE At ett on one Absolute M aximum Rating may be applied at any one time Power Dissipation DIP 1W Oja Thermal Impedance 102 C W CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can dischar
5. Hz TEMPERATURE C Figure 8 Distortion vs Frequency Figure 11 Output Leakage Current vs Temperature 20V SINE WAVE DATA INPUTS 1 FROM 00H TO 80H 5 2 o rI Vpp 5V uw DD 0712 u Ty 25 OUTPUT VA AGND 103 104 105 106 FREQUENCY Hz Figure 9 Feedthrough vs Frequency Figure 12 Digital to Analog Glitch Impulse Vpp 5V 25 C VinA 20V p p SINE WAVE VinB OV BOTH DAC LATCHES LOADED WITH 0000 0000 Hz Vpp 5V Vin OV DAC CODE 0000 0000 INCLUDES OP275 AMPLIFIER NOISE NOISE SPECTRAL DENSITY nV 10 10 104 105 106 102 10 104 105 FREQUENCY Hz FREQUENCY Hz Figure 10 Channel to Channel Isolation vs Frequency Figure 13 Noise Spectral Density vs Frequency 8 0 AD7112 MONOTONICITY FOR 1 5 dB ATTENUATION STEPS Reng nee ATENA TON STERN ERROR dB ERROR dB 2 0 3 6 9 12 15 18 21 24 27 30 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 ATTENUATION dB ATTENUATION dB Figure 14 Typical Attenuation Error for 0 75 dB Steps Figure 16 Accuracy Specification for B Grade Devices at Ta 425 C MONOTONICITY FOR 1 5 dB ATTENUATION STEPS ERROR dB ERROR dB
6. Vy A Vy B 10 V Output amplifier 0712 except where noted All specifications Ty to Tmax unless otherwise noted C Version B Version Ta Ta Ta Ta Parameter 25 C Tmax T25C Tmax Units Conditions C omments ACCURACY Resolution 0 375 0 375 0 375 0 375 dB Accuracy Relative to Guaranteed Attenuation 0 dB Attenuation Ranges for Specified Step Sizes 0 375 dB Steps Accuracy lt 0 17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min M onotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min 0 75 dB Steps Accuracy lt 0 35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min M onotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1 5 dB Steps Accuracy lt 0 7 dB 0 to 54 0 to 48 0 to 48 0 to 42 dB min M onotonic Full Range 0 to 78 0to85 5 01072 dB min Full Range Is 0 dB to 88 5 dB 3 0 dB Steps Accuracy lt 1 4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min M onotonic Full Range Full Range Full Range Full Range dB min 6 0 dB Steps Accuracy lt 2 7 dB 0 to 72 0 to 60 0 to 60 0 to 60 dB min M onotonic Full Range Full Range Full Range Full Range dB min Gain Error 0 1 0 15 0 15 0 2 dB max M easured Using Reg A Reg B Both DAC Registers Loaded With All Os Output Leakage Current OUT A OUT B 50 400 50 400 nA max Input Resistance Vin A Vin B 9 15 9 15 9 15 9 15 min max T ypically 12 Input Resistance M atch 1 1 2 2 F eedback Resistance Reg A Reg B 9 35 7 9 3 15 7 9 3 15 7 9
7. 0 6 ATTENUATION dB 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 ATTENUATION dB Figure 15 Typical Attenuation Error for 3 dB Steps vs Figure 17 Accuracy Specification for C Grade Devices at Temperature Ta 25 REV 0 9 AD7112 MICROPROCESSOR INTERFACING Figures 18 to 20 show interfaces between the AD 7112 and three popular 8 bit microprocessor systems the M C 68008 8085A 8088 and the 8051 In the M C 68008 and 8085 8088 in terfaces the AD 7112 is memory mapped with separate ad dresses for each DAC AD7112 8085A 8088 INTERFACE Figure 18 shows a connection diagram for interfacing the AD 7112 to both the 8085A and the 8088 microprocessors T his scheme is also suited to the Z80 microprocessor but the Z80 address data bus does not have to be demultiplexed T he AD7112 is memory mapped with separate memory addresses for DAC A and DAC B ADDRESS BUS ADDRESS O DECODE DBO P ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY DECODED ADDRESS FOR AD7112 DAC A A 1 DECODED ADDRESS FOR AD7112 DAC B Figure 18 AD7112 8085A 8088 Interface Circuit AD7112 68008 INTERFACE Figure 19 shows a connection diagram for interfacing the AD7112 to the 68008 microprocessor T he AD 7112 is again memory mapped with separate memory addresses for DAC A and DAC B ADDRESS DECODE DACA DACB ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY A DECODED ADDRESS FOR AD
8. 0010 0011 000 001 011 100 101 100 1011 110 101 1 0000 0 000 0 375 0750 1 125 1 500 1 875 2 250 2 625 3 000 3 375 3 750 4 125 4 500 4 875 5 250 5 625 0001 6 000 6 375 6 750 7 125 7 500 7 875 8 250 8 625 9 000 9 375 9 750 10 125 10 500 10 875 11 250 11 625 0010 12 000 12 375 12 750 13 125 13 500 13 875 14 250 14 625 15 000 15 375 15 750 16 125 16 500 16 875 17 250 17 625 0011 18 000 18 375 18 750 19 125 19 500 19 875 20 250 20 625 21 000 21 375 21 750 22 125 22 500 22 875 23 250 23 625 0100 24 000 24 375 24 750 25 125 25 500 25 875 26 250 26 625 27 000 27 375 27 750 28 125 28 500 28 875 29 250 29 625 0101 30 000 30 375 30 750 31 125 31 500 31 875 32 250 32 625 33 000 33 375 33 750 34 125 34 500 34 875 35 250 35 625 0110 36 000 36 375 36 750 37 125 37 500 37 875 38 250 38 625 39 000 39 375 39 750 40 125 40 500 40 875 41 250 41 625 0111 42 000 42 375 42 750 43 125 43 500 43 875 44 250 44 625 45 000 45 375 45 750 46 125 46 500 46 875 47 250 47 625 1000 48 000 48 375 48 750 49 125 49 500 49 875 50 250 50 625 51 000 51 375 51 750 52 125 52 500 52 875 53 250 53 625 1001 54 000 54 375 54 750 55 125 55 500 55 875 56 250 56 625 57 000 57 375 57 750 58 125 58 500 58 875 59 250 59 625 1010 60 000 60 375 60 750 61 125 61 500 61 875 62 250 62 625 63 000 63 375 63 750 64 125 64 500 64 875 65 250 65 625 1011 66 000 66 375 66 750 67 125 67 500 67 875 68 250 68 625 69 000 69 375 69 750 70 125 70 500 70 875 71 250 71 625 1100 72 000 72 375 72 750 73 125 73 500 73 875
9. binary input into a 17 bit word which is used to drive the D A converter Figure 2 shows a typical circuit configuration for the AD 7112 T he transfer function for the circuit of Figure 2 is given by Vo V iN x 10 exp 937 or Vo dB 0 375N Vin where 0 375 is the step size resolution in dB and N isthe input code in decimal for values 0 to 239 For 240 lt N lt 255 the output is zero T able gives the output attenuation relative to 0 dB for all possible input codes Figure 1 Simplified D A Circuit of 1 2 AD7112 Figures 16 and 17 give a pictorial representation of the specified accuracy and monotonic ranges for all grades of the AD 7112 High attenuation levels are specified with less accuracy than low attenuation levels T he range of monotonic behavior depends upon the attenuation step size used T o achieve monotonic op eration over the entire 88 5 dB range it is necessary to select in put codes so that the attenuation step size at any point is consistent with the step size guaranteed for monotonic opera tion at that point O Vour 5 1 1 2 AD712 cs 1 2 275 DAC A DAC B 6 NOTES 1 ONLY ONE DAC IS SHOWN FOR CLARITY 2 DATA INPUT CONNECTIONS ARE OMITTED 3 C1 PHASE COMPENSATION 5 15pF MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER Figure 2 Typical Circuit Configuration 2 3 Tablel Ideal Attenuation in dB vs Input Code o D7 D4 0000 0001
10. the average output voltage of the automatic gain control system remains constant Figure 21 shows a block diagram of a typical AGC control loop using 1 2 AD 7112 asthe gain attenu ation element Whenever the input signal is outside the dynamic range of the programmable gain element in the AGC loop there should bea stable well defined input output relationship REV 0 AD7112 VARIABLE GAIN ELEMENT 1 2 AD7112 INPUT O O OUTPUT UP DOWN COUNTER U D END STOP AND CONTROL LOGIC Figure 21 Automatic Gain Control System Programmable State Variable Filter 7112 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications The circuit of Figure 22 shows its use in a state variable filter design T his type of filter has three outputs low pass bandpass and high pass T he particular version shown in Figure 22 uses two AD 7112 to control the critical parameters f Q and Ao In stead of several fixed resistors the circuit uses the DAC equiva lent resistances as circuit elements T hus R1 in Figure 22 is controlled by the 8 bit word loaded to DAC A1 of the AD 7112 This is also the case with R2 R3 and R4 NOTES 1 A1 A2 A3 A4 1 4 x AD713 2 15 A COMPENSATION CAPACITOR TO ELIMINATE AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN BANDWIDTH LIMITATIONS DAC Equivalent Resistance Re Roac 0 10 x EXP 0 375 N 20
11. 0040 0 10 0 0138 0 35 0 0091 0 23 40 12 0 1692 10 7 92 PRINTED IN U S A
12. 2 AGND ORDERING INFORMATION Specified Temperature Accuracy Package Model Range Range Option AD7112BN 40 C to 85 0 60 4 N 20 AD7112CN 40 C to 85 0 4 0 72 N 20 AD7112BR 40 C to 85 0 060 R 20 7112 40 C to 85 04807248 R 20 N Plastic DIP R SOIC PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1 AGND Analog Ground 2 OUTA Current Output Terminal of DAC A 3 Rfg A Feedback Resistor for DAC A 4 VinA Reference Input to DAC A 5 DGND Digital Ground 6 DAC A Selects Which DAC Can Accept Data from DAC B Input Port 7 14 DB7 DBO 8Datalnputs 15 CS Chip Select Input Active Low 16 WR W rite Input Active L ow 17 Vpp Power Supply Input 5 V 5 18 IVB Reference Input to DAC B 19 RfgB Feedback Resistor for DAC B 20 OUTB Current Output Terminal of DAC PIN CONFIGURATION DIP SOIC AGND 1 e 20 ourB our A 2 Reg Rpg A 18 VinB Vin A 4 Vpp s 497112 Fe wa DAC A DAC B 6 Notto Scale 15 CS MSB DB7 114 DBo LSB 6 8 13 DB1 pes 9 12 DB2 10 11 DBS REV 0 AD7112 CIRCUIT DESCRIPTION GENERAL CIRCUIT INFORMATION 7112 consists of a dual 17 bit R 2R CM OS multiplying D A converter with extensive digital logic Figure 1 shows a sim plified circuit of the D A converter section of the AD 7112 T he logic translates the 8 bit
13. 3 15 7 min max LOGIC INPUTS CS WR DAC A DAC B 7 Input Low Voltage Vin 0 8 0 8 0 8 0 8 V max Input High Voltage Ving 2 4 2 4 2 4 2 4 V min Input Leakage Current 1 10 1 10 max Input Capacitance 10 10 10 10 pF max POWER REQUIREMENTS Vpp Range 4 75 5 25 4 75 5 25 4 75 5 25 4 75 5 25 V min max For Specified Performance 2 2 2 2 mA max Logic Inputs Vi or Viu 2 2 2 2 mA max Logic Inputs 0 V or Vpp NOTES IT emperature range as follows B C Versions 40 C to 85 C 2 uaranteed by design not production tested T he part will function with 5 V 10 with degraded performance Specifications subject to change without notice 295 REV 0 AD7112 TIMING SPECIFICATIONS Voo 5 V x 5 OUTA OUT B AGND DGND O V Vn A 10 V Parameter Ta 25C 40 to 85 C Units Conditions C omments CS to WR Setup Time tcs 0 0 ns min See Figure 3 CS to WR Hold Time tcu 0 0 ns min DAC Select to WR Setup T ime tas 4 4 ns min DAC Select to WR Hold Time tan 0 0 ns min D ata Valid to WR Setup Time tos 55 55 ns min Data Valid to WR Hold Time toy 10 10 ns min WR Pulse Width 53 53 ns min NOTES 1T iming specifications guaranteed by design not production tested All input signals are specified with tr tf 5 ns 10 to 9096 of 5 V and timed from a voltage level of 1 6 V Specifications subject to change without notice Voo 5 V x 5 OUT A OUT B
14. 7112 DAC A A 1 DECODED ADDRESS FOR AD7112 DAC B Figure 19 AD7112 68008 Interface Circuit 10 AD7112 80511NTERFACE Figure 20 shows a connection diagram between the AD 7112 and the 8051 microprocessor T he AD 7112 is port mapped in this interface T he loading structure is as follows Data to be loaded to the DAC is output to Port 1 P3 0 P3 1 and P3 2 are bit addressable port lines and are used to control the DAC select CS and WR inputs A sample routine for writing to DAC A is shown below MOV A DATA Data to be written is loaded to the accumulator CLR 3 2 Select DAC A CLR 3 0 Bring CS low CLR 3 1 Bring WR low MOV A P1 Write datato DAC SET B 3 1 Deactivate WR SET B 3 0 Deactivate CS DAC A DACB AD7112 ANALOG CIRCUITRY OMITTED FOR CLARITY Figure 20 AD7112 8051 Interface Circuit APPLICATIONS Automatic Gain Control In an automatic gain control system an input signal is attenuated or amplified so that its average output level remains constant TheAD7112 D A converter is used here as a variable gain or at tenuation element that adjusts the output signal relative to the input level A feedback loop consisting of a detector comparator and up down counter continuously adjusts the contents of the counter and hence the gain or attenuation of the circuit so that the signal level at the output remains constant and equal to the reference input signal T he negative feedback action of the loop ensures that
15. 74 250 74 625 75 000 75 375 75 750 76 125 76 500 76 875 77 250 77 625 1101 78 000 78 375 78 750 79 125 79 500 79 875 80 250 80 625 81 000 81 375 81 750 82 125 82 500 82 875 83 250 83 625 1110 84 000 84 375 84 750 85 125 85 500 85 875 86 250 86 625 87 000 87 375 87 750 88 125 88 500 88 875 89 250 89 625 1111 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE REV 0 i5 AD7112 INTERFACE LOGIC INFORMATION DAC Selection Both DAC latches share a common 8 bit port T he control in put DAC A DAC B selects which DAC can accept data from the input port Mode Selection Inputs CS and WR control the operating mode of the selected DAC See the M ode Selection T able below Write Mode When CS and WR are both low the DAC is in the write mode T he input data latches of the selected DAC are transparent and its analog output responds to activity on DBO DB7 Hold Mode T he selected DAC latch retains the data which was present on D B0 DB7 just prior to CS and WR assuming a high state Both analog outputs remain at the values corresponding to the data in their respective latches Mode Selection T able DACA __ m DAC CS WR DACA DACB L L L WRITE HOLD H L L HOLD WRITE X H X HOLD HOLD X X H HOLD HOLD L Low State Vu High State Viu X Don t Care tos gt e ton cs i DAC gt l ts E twr gt WR bee ee
16. AS iG A D 711244 V RS ANALOG DEVICES LC MOS LOGDAC Dual Logarithmic D A Converter AD7112 FEATURES Dynamic Range 88 5 dB Resolution 0 375 dB On Chip Data Latches for Both DACs Four Quadrant Multiplication 45 V Operation Pin Compatible with AD7528 Low Power APPLICATIONS Audio Attenuators Sonar Systems Function Generators GENERAL DESCRIPTION TheLOGDACG AD7112 is a monolithic dual multiplying D A converter featuring wide dynamic range and excellent D AC to DAC matching Both DACs can attenuate an analog input sig nal over the range 0 dB to 88 5 dB in 0 375 dB steps It is available in skinny 0 3 wide 20 pin DIPs and in 20 terminal surface mount packages T he degree of attenuation in either channel is determined by the 8 bit word applied to the onboard decode logic T his 8 bit word is decoded into a 17 bit word which is then loaded into one of the 17 bit data latches determined by DACA DACB T he fine step resolution over the entire dynamic range is due to the use of these 17 bit DACs The AD 7112 is easily interfaced to a standard 8 bit M PU bus via an 8 bit data port and standard microprocessor control lines It should be noted that the AD 7112 is exactly pin compatible with the AD 7528 an industry standard dual 8 bit multiplying DAC This allows an easy upgrading of existing AD 7528 de signs which would benefit both from the wider dynamic range and the finer step resolution offered by the AD 7112
17. TheAD7112 is fabricated in Linear Compatible CM OS LC M 05 an advanced mixed technology process that com bines precision bipolar circuits with low power CM OS logic Protected by U S Patent No 4521764 LOGDAC is a registered trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM Vpp Vin A O OUT A 17 BIT DAC A 17 BIT LATCH Q 8 BIT DECODE LOGIC DB7 BUFFER 2 CONTROL O OUT B 17 BITDACB Ee 5 CS WR DGND DAC B AGND PRODUCT HIGHLIGHTS 1 DAC to DAC Matching Since both of the AD 7112 DACs are fabricated at the same time on the same chip precise matching and tracking between the two DACs is inherent 2 Small Package T he AD 7112 is available in a 20 pin DIP and a 20 terminal SOIC package 3 Fast M icroprocessor Interface T he AD 7112 has bus inter face timing compatible with all modern microprocessors One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD7112 SPECIFICATIONS 5 V 5 OUT A OUTB AGND DGND 0 V
18. e that the manu facturing process for circuits using the AD 7112 does not allow such films to form Otherwise the feedthrough accuracy and maximum usable range will be affected STATIC ACCURACY PERFORMANCE T he D A converter section of the AD 7112 consists of a 17 bit R 2R type converter T o obtain optimum static performance at this level of resolution it is necessary to pay great attention to amplifier selection circuit grounding etc Amplifier input bias current results in a dc offset at the output of the amplifier due to current flowing in the feedback resistor Reg It is recommended that amplifiers with input bias currents of less than 10 nA be used eg AD 712 to minimize this offset REV 0 AD7112 Another error arises from the output amplifier s input offset volt age T he amplifier is operated with a fixed feedback resistance but the equivalent source impedance the AD 7112 output im pedance varies as a function of the attenuation level T his has the effect of varying the noise gain of the amplifier thus creating a varying error due to amplifier offset voltage It is recom mended that an amplifier with less than 50 uV of input offset be used such as the AD 712 or ADOPO7 in dc applications Am plifiers with a large input offset voltage may cause audible thumps in audio applications due to dc output changes T he TYPICAL PERFORMANCE CHARACTERISTICS DATA CHANGE FROM 00H TO 80H C1 OpF C1 15pF F
19. ge without detection Although the AD 7112 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING erin 4 ESD SENSITIVE DEVICE TERMINOLOGY RESOLUTION Nominal change in attenuation when moving between two adjacent codes MONOTONICITY The device is monotonic if the analog out put decreases or remains constant as the wdigital code in creases FEEDTHROUGH ERROR T hat portion of the input signal which reaches the output when all digital inputs are high OUTPUT CAPACITANCE Capacitance from OUT A or OUT B to ground GAIN ERROR Gain error results from a mismatch between Reg the feedback resistance and the R 2R ladder resistance Its effect in aLOGDAC isto produce a constant additive at tenuation error in dB over the whole range of the DAC ACCURACY T he difference measured in dB between the ideal transfer function as listed in T ablel and the actual trans fer function as measured with the device DIGITAL TO ANALOG GLITCH IMPULSE The amount of charge injected from the digital inputs to the analog output when the inputs change state T his is normally specified as the area of the glitch in either pA s or nV s depending on whether the glitch is measured as a current or voltage signal Glitch im pulse is measured with Viy
20. igure 4 Response of AD7112 with AD712 DATA CHANGE FROM 00H TO 80H C1 OpF C1 15pF Figure 5 Response of AD7112 with OP275 REV 0 AD 7112 accuracy is specified and tested using only the internal feedback resistor Any gain error i e mismatch of Reg to the R 2R ladder that may exist in the AD 7112 D A converter cir cuit results in a constant attenuation error over the whole range The AD 7112 accuracy is specified relative to 0 dB attenuation hence gain trim resistors can be used to adjust Vout Vin pre cisely i e 0 dB attenuation with input code 00000000 For further information on gain error refer to the CM OS DAC Ap plication Guide which is available from Analog D evices Publi cation N umber G 872b 8 1 89 25 ALL DIGITAL INPUT TIED TOGETHER 2 3 Vin Volts Figure 6 Supply Current vs Logic Input Level DATA INPUT CODE 0000 0000 Vin 1V rms NORMALIZED GAIN WITH RESPECT TO 1kHz FREQUENCY Hz Figure 7 Frequency Response with AD712 and OP275 Vin 6V rms INPUT CODE 0000 0000 25 1 15pF Vpp 5V Vin 10V DATA INPUT 1111 XXXX A TOTAL HARMONIC DISTORTION dB OUTPUT LEAKAGE CURRENT loy nA 10 10 10 10 10 40 15 10 35 60 85 FREQUENCY
21. l noise It is recommended that when using the AD 7112 with a high speed amplifier a capacitor C1 be connected in the feedback path as shown in Figure 2 T his capacitor which should be be tween 5 pF and 15 pF compensates for the phase lag intro duced by the output capacitance of the D A converter Figures 4 and 5 show the performance of the AD 7112 using the AD 712 a high speed low cost BiFET amplifier and the OP275 a dual bipolar F ET amplifier suitable for audio appli cations T he performance with and without the compensation capacitor is shown in both cases For operation beyond 250 kHz capacitor C 1 may be reduced in value T his gives an increase in bandwidth at the expense of a poorer transient re sponse as shown in F igure 7 In circuits where C 1 is not in cluded the high frequency roll off point is primarily determined by the characteristics of the output amplifier and not the AD 7112 Feedthrough and accuracy are sensitive to output leakage cur rents effects For this reason it is recommended that the operat ing temperature of the AD 7112 be kept as close to 25 C as is practically possible particularly where the devices performance at high attenuation levels is important A typical plot of leakage current vs temperature is shown in Figure 11 Some solder fluxes and cleaning materials can form slightly conductive films which cause leakage effects between analog in put and output T he user is cautioned to ensur
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