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ANALOG DEVICES AD7111/AD7111A handbook

1. INPUT VOLTAGE Volts Figure 6 Typical Supply Current vs Logic Input Level ERROR dB 0 3 6 9 12 15 18 21 24 27 30 ATTENUATION dB Figure 7 Typical Attenuation Error for 0 75 dB Steps REV 0 AD7111 AD7111A D A converter circuit results in a constant attenuation error over the whole range The AD 7111 AD 7111A accuracy is specified relative to 0 dB attenuation hence Gain trim resistors R1 and R2 in Figure 1 can be used to adjust Vout Vin precisely i e 0 dB attenuation with input code 00000000 T he accuracy and monotonic range specifications of the AD7111 AD 7111A are not affected in any way by this gain trim procedure For the AD 7111 AD 7111A L C U grades suit able values for R1 and R2 of Figure 1 are R1 500Q R2 180 Q for the K B T grades suitable value are R1 1000 Q R2 270 Q For additional information on gain error the reader is referred to the CMOS DAC Application Guide available from Analog Devices Inc Publication N umber G 872b 8 1 89 ERROR dB 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 ATTENUATION dB Figure 8 Typical Attenuation Error for 3 dB Steps vs Temperature XXXXX MONOTONICITY FOR 1 5dB ATTENUATION STEPS XXX XXX XXAKKAXAKAAAN _ RASA 27888 arrenvaTion srers TNA SSS 25E VLLLLLL 0375 attenuation stes 48 54 ATTENUA
2. LCCC R SOIC ACCURACY T he difference measured in dB between the ideal transfer function as listed in T able and the actual transfer function as measured with the device OUTPUT CAPACITANCE Capacitance from lour to ground DIGITAL TO ANALOG GLITCH IMPULSE T he amount of charge injected from the digital inputs to the analog output when the inputs change state T his is normally specified as the area of the glitch in either pA secs or nV secs depending upon whether the glitch is measured as a current or voltage signal Glitch impulse is measured with Viy AGND PROPAGATION DELAY T his is a measure of the internal delays of the circuit and is defined as the time from a digital in put change to the analog output current reaching 90 of its final value REV 0 tes teH AD7111 AD7111A vop PIN CONFIGURATIONS CHIP DIP SOIC LCCC SELECT DATA IN AD7111 pees DGND 4 18 Voo D0 D7 R Par oe DyIMSB S AD7111 ave NOTES Not to Scale NC 6 TOP VIEW 16 NC TEASURED PROM 16 TO S04 OF Nis Mop m DOILSB D6 7 Not to Scale 15 CS 5V te ty 20ns D5 8 14 DO LSB 2 TIMING MEASUREMENT REFERENCE LEVEL 1s Yi Mu 9 10 11 12 13 4 oO a N e tarau NOT REQUIRED ON THE AD7111A AS THE WR INPUT Nee AG GONNEST o2 8008 Write Cycle Timing Diagram CIRCUIT DESCRIPTION where 0 375 is the step size resolution in dB and N is the in GENERAL CIRCUIT DESCRIPTION put code in decimal for values 0 to 239 For 240 lt N lt 255 the The A
3. 0 0 0 375 0 75 1 125 15 1 875 2 25 2 625 3 0 3 375 3 75 4 125 45 4 875 5 25 5 625 0001 6 0 6 375 6 75 7 125 7 5 7 875 8 25 8 625 9 0 9 375 9 75 10 125 10 5 10 875 11 25 11 625 0010 12 0 12 375 12 75 13 125 13 5 13 875 14 25 14 625 15 0 15 375 15 75 16 125 16 5 16 875 17 25 17 625 0011 18 0 18 375 18 75 19 125 19 5 19 875 20 25 20 625 21 0 21 375 21 75 22 125 22 5 22 875 23 25 23 625 0100 24 0 24 375 24 75 25 125 25 5 25 875 26 25 26 625 27 0 27 375 27 75 28 125 28 5 28 875 29 25 29 625 0101 30 0 30 375 30 75 31 125 31 5 31 875 32 25 32 625 33 0 33 375 33 75 34 125 34 5 34 875 35 25 35 625 0110 36 0 36 375 36 75 37 125 37 5 37 875 38 25 38 625 39 0 39 375 39 75 40 125 40 5 40 875 41 25 41 625 0111 42 0 42 375 42 75 43 125 43 5 43 875 44 25 44 625 45 0 45 375 45 75 46 125 46 5 46 875 47 25 47 625 1000 48 0 48 375 48 75 49 125 49 5 49 875 50 25 50 625 51 0 51 375 51 75 52 125 52 5 52 875 53 25 53 625 1001 54 0 54 375 54 75 55 125 55 5 55 875 56 25 56 625 57 0 57 375 57 75 58 125 58 5 58 875 59 25 59 625 1010 60 0 60 375 60 75 61 125 61 5 61 875 62 25 62 625 63 0 63 375 63 75 64 125 64 5 64 875 65 25 65 625 1011 66 0 66 375 66 75 67 125 67 5 67 875 68 25 68 625 69 0 69 375 69 75 70 125 70 5 70 875 71 25 71 625 1100 72 0 72 375 72 75 73 125 73 5 73 875 74 25 74 625 75 0 75 375 75 75 76 125 76 5 76 875 77 25 77 625 1101 78 0 78 375 78 75 79 125 79 5 79 875 80 25 80 625 81 0 81 375 81 75 82 125 82 5 82 875 83 25 83 625 1110 84 0 84 375 84 75 85 125 85 5 85 875 8
4. 40 C to 85 C 0dB to60dB N 16 AD7111ACN 40 C to 85 C OdBto72dB N 16 AD7111ABR_ 40 C to 85 C 0dB to60dB R 16 AD7111ACR 40 C to 85 C 0dB to 72dB R 16 NOTE IN Plastic DIP R SOIC TERMINOLOGY RESOLUTION Nominal change in attenuation when moving between two adjacent codes MONOTONICITY T he device is monotonic if the analog out put decreases or remains constant as the digital code increases FEEDTHROUGH ERROR T hat portion of the input signal which reaches the output when all digital inputs are high See section on Applications OUTPUT LEAKAGE CURRENT Current which appears on the lour terminal with all digital inputs high TOTAL HARMONIC DISTORTION A measure of the harmonics introduced by the circuit when a pure sinusoid is applied to the input It is expressed as the harmonic energy divided by the fundamental energy at the output Specified Temperature Accuracy Package Model Range Range Option AD7111KN 0 C to 70 C 0 dB to 60 dB N 16 AD7111BQ 40 C to 85 C 0 dB to 60 dB Q 16 AD7111LN 0 C to 70 C 0 dB to 72 dB N 16 AD7111CQ 40 C to 85 C 0 dB to 72 dB Q 16 AD 7111U Q 883B 55 C to 125 C 0 dB to 72 dB Q 16 AD7111T E 883B 55 C to 125 C 0 dB to 60 dB E 20A NOTES 1T o order MIL ST D 883B Class B processed parts add 883B to part number Contact local sales office for military data sheet and availability N Plastic DIP Q Cerdip E
5. 5 and Pin 16 7 7 7 7 pF max Feedthrough at 1 kHz 94 72 94 68 dB max T otal H armonic Distortion 91 91 91 91 dB typ Vin 6V rms at 1 kHz Output Noise Voltage D ensity 70 70 70 70 nV VHz max Includes AD 711 Amplifier N oise Digital Input Capacitance 7 7 7 7 pF max Specifications subject to change without notice 2 REV 0 AD7111A ELECTRICAL CHARACTERISTICS AD7111 AD7111A Voo 5 V Vin 10 V dc lovr AGND DGND O V output amplifier AD711 except where noted AD7111AC Grade AD7111AB Grade Parameter Ta 425C Ta Tmw Tmax Ta t 28C Ta Tmnw Tmax Units Conditions C omments NOMINAL RESOLUTION 0 375 0 375 0 375 0 375 dB ACCURACY RELATIVE TO 0 dB ATTENUATION 0 375 dB Steps Accuracy lt 0 17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min Guaranteed Attenuation Ranges M onotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min for Specified Step Sizes 0 75 dB Steps Accuracy lt 0 35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min M onotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1 5 dB Steps Accuracy lt 0 7 dB 0 to 54 0 to 48 0 to 48 0 to 42 dB min Full Range Is from 0 dB M onotonic Full Range 0to78 0 to 85 5 0 to 72 dB min to 88 5 dB 3 0 dB Steps Accuracy lt 1 4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min M onotonic Full Range Full Range Full Range Full Range dB min 6 0 dB Steps Accuracy lt 2 7 dB 0 to 72 0 to 60 0 to 60 0 to 48 dB min M onotonic Full Range Full Range Full Range Full Range dB min GAIN
6. 6 25 86 625 87 0 87 375 87 75 88 125 88 5 88 875 89 25 89 625 1111 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE REV 0 5 AD7111 AD7111A For example the AD 7111L is guaranteed monotonic in 0 375 dB steps from 0 dB to 54 dB inclusive and in 0 75 dB steps from 0 dB to 72 dB inclusive T o achieve monotonic operation over the entire 88 5 dB range it is necessary to select input codes so that the attenuation step size at any point is consistent with the step size guaranteed for monotonic operation at that point EQUIVALENT CIRCUIT ANALYSIS Figure 2 shows a simplified circuit of the D A converter section of the AD 7111 AD7111A and Figure 3 gives an approximate equivalent circuit T he current source leakage is composed of surface and junc tion leakages T he resistor Rg as shown in Figure 3 is the equivalent output resistance of the device which varies with in put code excluding all 0s code from 0 8R to 2R R is typically 12 kQ Cour is the capacitance due to the N channel switches and varies from about 20 pF to 50 pF depending upon the digi tal input For further information on CM OS multiplying D A converters refer to CMOS DAC Application Guide which is available from Analog D evices Publication N umber G 872b 8 1 89 AGND i SWITCH DRIVERS Figure 2 Simplified D A Circuit of AD7111 AD7111A gi Vin N fixo AGND Vin N IS THE THEVENIN EQUIVALENT V
7. AD711IA with 1 2 OP275 In conventional CM OS D A converter design parasitic capaci tance in N channel D A converter switches can give rise to glitches on the D A converter output T hese glitches result from digital feedthrough The AD 7111 AD 7111A has been designed to minimize these glitches as much as possible For operation beyond 250 kHz capacitor C1 may be reduced in value T his gives an increase in bandwidth at the expense of a poorer transient response as shown in Figures 5 and 11 In cir cuits where C1 is not included the high frequency roll off point is primarily determined by the characteristics of the output am plifier and not the AD 7111 AD 7111A Feedthrough and absolute accuracy are sensitive to output leak age current effects For this reason it is recommended that the operating temperature of the AD 7111 AD 7111A be kept as close to 25 C as is practically possible particularly where the device s performance at high attenuation levels is important A typi cal plot of leakage current vs temperature is shown in Figure 10 Some solder fluxes and cleaning materials can form slightly con ductive films which cause leakage effects between analog input and output T he user is cautioned to ensure that the manufacturing process for circuits using thc AD 7111 AD 7111A does not allow such films to form Otherwise the feedthrough accuracy and maximum usable range will be affected STATIC ACCURACY PERFORMANCE The D A conve
8. ASi8 A D711 144 AA ANALOG DEVICES LC MOS LOGDAC Logarithmic D A Converter AD7111 AD7111A FEATURES Dynamic Range 88 5 dB Resolution 0 375 dB On Chip Data Latches 5 V Operation AD7111A Pin Compatible with AD7524 Low Power APPLICATIONS Audio Attenuators Sonar Systems Function Generators Digitally Controlled AGC System GENERAL DESCRIPTION The LOGDAC AD7111 AD 7111A are monolithic multiplying D A converters featuring wide dynamic range in a small pack age Both DACs can attenuate an analog input signal over the range 0 dB to 88 5 dB in 0 375 dB steps T hey are available in 16 pin DIPs and SOIC packages The AD 7111 is also available in a 20 terminal LCCC package T he degree of attenuation across the DAC is determined by an 8 bit word applied to the onboard decode logic T his 8 bit word is decoded into a 17 bit word which is then applied to a 17 bit R 2R ladder T he very fine step resolution which is available over the entire dynamic range is due to the use of this 17 bit DAC The AD7111 AD 7111A are easily interfaced to a standard 8 bit M PU bus via an 8 bit data port and standard microprocessor control lines The AD 7111 WR input is edge triggered and re quires a rising edge to load new data to the DAC The AD7111A WR is level triggered to allow transparent operation of the latches if required It should also be noted that the AD 7111A is exactly pin and function compatible with the AD 7524 an in du
9. D7111 AD 7111A consists of a 17 bit R 2R CMOS mul output is zero T able gives the output attenuation relative to tiplying D A converter with extensive digital logic T he logic 0 dB for all possible input codes translates the 8 bit binary input into a 17 bit word which is used to drive the D A converter Input data on the D 7 D 0 bus is loaded into the input data latches using CS and WR control signals When using the AD 7111 the rising edge of WR latches Voo R2 the input data and initiates the internal data transfer to the de coder A minimum time tresy the refresh time is required for wm Vo the data to propagate through the decoder before a new data AD711 OR write is attempted cs ae In contrast the AD 7111A WR input is level triggered to allow transparent operation of the latches if required C 15pF TYPICAL T he transfer function for the circuit of Figure 1 is given by Figure 1 Typical Circuit Configuration ee eT 0 375 N Ore vance Ap 20 T he graphs on the last page give a pictorial representation of the specified accuracy and monotonic ranges for all grades of the o AD7111 AD 7111A High attenuation levels are specified with Viy OB 0 375N less accuracy than low attenuation levels T he range of mono tonic behavior depends upon the attenuation step size used or Tablel Ideal Attenuation in dB vs Input Code D3 DO D7 D4 0000 0001 0010 0011 0100 0101 O110 0111 1000 1001 1010 1011 1100 1101 110 111 0000
10. DENTIFED BY DOT OR NOTCH fe LEADS ARE SOLDER OF TIN PLATED KOVAR OR ALLOY 42 ues Cerdip Q 16 Te 4 0 080 4 H F ae 1 27 OT aoe oie San 0 01 0 254 0 050 1 27 REF 0 019 0 483 0 014 0 356 STANDOFF 0 30 _ 7 62 oes fen LCCC E 20A 0 32 8 128 2082 eas 0 29 7 366 i os 0 785 19 94 0 360 0 008 cc 0 040 x a5 0 75 19 6 89 0 20 hers PLCS 0 18 4 572 0 155 3 937 MIN 0 14 3 56 0 025 0 003 aa 0 635 0 075 0 20 5 08 F f 0018 10 380 ok 0 125 13 175 0 008 0 203 9 07 1 778 0 023 0 584 0 11 2 794 15 0 03 0 762 0 015 0 381 0 09 2 28 0 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OF TIN PLATED KOVAR OR ALLOY 42 RY NKR KK MONOTONICITY FOR 1 5dB ATTENUATION STEPS RKXRKRERRR KKK OREN ERY ANNAA VIIL Lf 03722 aenar ses 7777 7 Figure 13 Accuracy Specification for L C U Grade REV 0 C1687 10 7 92 PRINTED IN U S A
11. ERROR 0 1 0 15 0 15 0 20 dB max Vin INPUT RESISTANCE 9 11 15 9 11 15 7 11 18 7 11 18 kQ min typ max Rfg INPUT RESISTANCE 9 3 11 5 15 7 9 3 11 5 15 7 7 3 11 5 18 8 7 3 11 5 18 8 kQ min typ max DIGITAL INPUTS Vin Input High Voltage 2 4 2 4 2 4 2 4 V min Vit Input H igh Voltage 0 8 0 8 0 8 0 8 V max Input Leakage Current EL 10 1 10 uA max Digital Inputs Vpp SWITCHING CHARACTERISTICS tcs 0 0 0 0 ns min Chip Select to Write Setup T ime tcH 0 0 0 0 ns min Chip Select to Write H old T ime twr 57 57 57 57 ns min Write Pulse Width tos 25 25 25 25 ns min Data Valid to Write Setup Time tox 10 10 10 10 ns min Data Valid to Write Hold Time POWER SUPPLY Vpop 5 5 5 5 V D igital Inputs V or Vi lbp 1 2 1 2 mA max CS WR 0V 1 1 1 1 mA max Digital Inputs 0 V or Vpp See Figure 6 NOTE Sample tested at 25 C to ensure compliance Specifications subject to change without notice AC PERFORMANCE CHARACTERI STI CS These characteristics are included for design guidance only and are not subject to test Vpp 5 V Vin 10 V dc except where noted lovr AGND DGND O V output amplifier AD711 except where noted AD7111AC Grade AD7111AB Grade Parameter Ta t25C Ta Tmw Tmax Ta t 25C Ty Tmnw Tmax Units Conditions C omments DC Supply Rejection AG ain AV pp 0 001 0 005 0 001 0 005 dB per max AVpp 10 Input C ode 00000000 Propagation D elay 1 1 5 1 1 5 us m
12. Input Leakage Current 1 10 1 10 yA max Digital Inputs Vpp SWITCHING CHARACTERISTICS tcs 0 0 0 0 ns min Chip Select to Write Setup T ime tcH 0 0 0 0 ns min Chip Select to Write H old T ime twr 350 500 350 500 ns min Write Pulse Width tos 175 250 175 250 ns min Data Valid to Write Setup Time tox 10 10 10 10 ns min Data Valid to Write H old Time tresH 3 4 5 3 45 us min Refresh T ime POWER SUPPLY Vpp 5 5 5 5 V lbp 1 4 1 4 mA max Digital Inputs Vi or Vip 500 1000 500 1000 uA max Digital Inputs 0 V or Vpp See Figure 6 NOTE 1Sample tested at 25 C to ensure compliance Specifications subject to change without notice AC PERFORMANCE CHARACTERI STl CS These characteristics are included for design guidance only and are not subject to test Voo 5 V Vin 10 V dc except where noted lour AGND DGND O V output amplifier AD711 except where noted AD7111L C U Grades AD7111K B T Grades Parameter Ta t25C Ta Tmw Tmax Ta t 25 C Ty Tmnw Tmax Units Conditions C omments DC Supply Rejection AG ain AV pp 0 001 0 005 0 001 0 005 dB per max AVpp 10 Input Code 00000000 Propagation D elay 3 0 45 3 0 4 5 us max Full Scale C hange M easured from WR Going High CS 0 V Digital to A nalog Glitch Impulse 100 100 nV secs typ M easured with AD 843 as Output Amplifier for Code Transition 10000000 to 00000000 C1 of Figure 1 is 0 pF Output Capacitance Pin 1 185 185 185 185 pF max Input Capacitance Pin 1
13. OLTAGE GENERATOR DUE TO THE INPUT VOLTAGE Viy THE BINARY ATTENUATION FACTOR N AND THE TRANSFER FUNCTION OF THE R 2R LADDER Figure 3 Equivalent Analog Output Circuit of AD7111 AD7111A DYNAMIC PERFORMANCE T he dynamic performance of the AD 7111 AD 7111A will depend upon the gain and phase characteristics of the output amplifier together with the optimum choice of PC board layout and decoupling components Circuit layout is most important if the optimum performance of the AD 7111 AD 7111A is to be achieved M ost application problems stem from either poor lay out grounding errors or inappropriate choice of amplifier It is recommended that when using thc AD 7111 AD 7111A with a high speed amplifier a capacitor C1 he connected in the feedback path as shown in Figure 1 This capacitor which should be between 10 pF and 30 pF compensates for the phase lag introduced by the output capacitance of the D A converter Figures 4 and 5 show the performance of the AD7111 AD 7111A using the AD 711 a high speed low cost BiFET amplifier and the OP275 a dual bipolar JFET audio amplifier T he perfor mance without C 1 is shown in the middle trace and the re sponse with C1 in circuit shown in the bottom trace MSB DATA CHANGE C1 OpF C1 15pF DATA CHANGE FROM 80H TO 00H Figure 4 Response of AD7111 AD711IA with AD711 MSB DATA CHANGE C1 OpF C1 15pF DATA CHANGE FROM 80H TO 00H Figure 5 Response of AD7111
14. S Voo 5 V Vin 10 V dc lovr AGND DGND O V output amplifier AD7111 ELECTRICAL CHARACTERISTICS AD711 except where noted AD7111L C U Grades AD7111K B T Grades Parameter Ta t25C Ta Tein Tmax Ta t25C Ta Twinw Tmax Units Conditions C omments NOMINAL RESOLUTION 0 375 0 375 0 375 0 375 dB ACCURACY RELATIVE TO 0 dB ATTENUATION 0 375 dB Steps Accuracy lt 0 17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min Guaranteed Attenuation R anges M onotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min for Specified Step Sizes 0 75 dB Steps Accuracy lt 0 35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min M onotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1 5 dB Steps Accuracy lt 0 7 dB 0 to 54 0 to 48 0 to 42 0 to 42 dB min Full Range Is from 0 dB M onotonic Full Range 0to78 0 to 85 5 0 to 72 dB min to 88 5 dB 3 0 dB Steps Accuracy lt 1 4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min M onotonic Full Range Full Range Full Range Full Range dB min 6 0 dB Steps Accuracy lt 2 7 dB 0 to 72 0 to 60 0 to 60 0 to 48 dB min M onotonic Full Range Full Range Full Range Full Range dB min GAIN ERROR 0 1 0 15 0 15 0 20 dB max Vin INPUT RESISTANCE 9 11 15 9 11 15 7 11 18 7 11 18 kQ min typ max Rfg INPUT RESISTANCE 9 3 11 5 15 7 9 3 11 5 15 7 7 3 11 5 18 8 7 3 11 5 18 8 kQ min typ max DIGITAL INPUTS Vin Input High Voltage 2 4 2 4 2 4 2 4 V min Vit Input Low Voltage 0 8 0 8 0 8 0 8 V max
15. TION dB Figure 9 Accuracy Specification for K B T Grade Devices at Ta 425 C AD7111 AD7111A Typical Performance Characteristics 2 0 pp 5V Vin 10V DATA INPUT 1111XXXX Vin 6V rms INPUT CODE 0000 0000 Ty 25 C a C1 15pF OUTPUT LEAKAGE CURRENT Igy NA o a 15 10 35 TEMPERATURE C Figure 10 Output Leakage Current vs Temperature 1 2 OP 275 1 TOTAL HARMONIC DISTORTION dB 60 85 10 10 104 10 FREQUENCY Hz Figure 12 Distortion vs Frequency Vpp 5V Ta 25 C DATA INPUT CODE 0000 0000 Vin 1V rms NORMALIZED GAIN WITH RESPECT TO 1kHz 10 104 10 FREQUENCY Hz Figure 11 Frequency Response with 1 2 OP275 and AD711 Amplifiers Plastic DIP N 16 10 ERROR dB 10 Devices at Ta 425 C OUTLINE DIMENSIONS Dimensions shown in inches and mm 6 12 18 24 30 36 42 48B 54 ATTENUATION dB SOIC R 16 0 413 10 49 0 398 10 11 Oo H 0 26 6 61 0 24 6 1 0 755 119 18 0 306 17 78 0 745 18 83 0 294 7 47 0 14 3 56 419 10 64 oe 0 12 3 08 a 394 10 01 0 175 4 45 0 12 3 06 w 9 H h i 0 012 0 305 0 065 1 66 0 02 0 508 0 106 2 67 0 008 0 203 0 045 115 0015 038 0 095 2 42 coz 0 500 xas C DNO 1 I
16. ax Full Scale C hange M easured from WR Going High CS 0 V Digital to A nalog Glitch Impulse 10 20 10 20 nV secs typ M easured with AD 843 as Output Amplifier for Code T ransition 10000000 to 00000000 C1 of Figure 1 is 0 pF Output Capacitance Pin 1 50 50 50 50 pF max Input Capacitance Pin 15 and Pin 16 7 7 7 7 pF max Feedthrough at 1 kHz 94 90 92 90 dB max Total H armonic D istortion 91 91 91 91 dB typ Vin 6V rmsat 1 kHz Output Noise Voltage D ensity 70 70 70 70 nV VHz max Includes AD 711 Amplifier N oise Digital Input Capacitance 7 7 7 7 pF max Specifications subject to change without notice REV 0 3 AD7111 AD7111A ABSOLUTE MAXIMUM RATINGS T a 25 C unless otherwise noted Vip t0 D GND 16 aa tao eat a Showa 7V Vin tO AGND ove is eck catia ca headin a callie 35V Digital Input VoltagetoDGND 0 3 V to Vpp 0 3 V lout tO AGN D sieis irate what aed wad Dhue 0 3 V to Vpp Virs to AGND aritarita ar ey e E 35 V Extended T U Versions AGND toDGND cece 0 to Vpp Storage T emperature Range DGND toAGND easier anii cece eee 0 to Vpp Power Dissipation DIP 0 ce eee eee ee 1W Oja Thermal Impedance 000e 117 C W Lead Temperature Soldering 10 secs 300 C Power Dissipation SOIC 1 eee eee 1W Oja Thermal Impedance cece eee 75 C W Lead T emperature Soldering Vapor Phase 60 secs 00 cece eee eee 215 C Infrared 15 secs naua
17. n a 220 C CAUTION Power Dissipation LCCC cece eae 1W Oja Thermal Impedance 0 ee ae 76 C W Lead Temperature Soldering 10 secs 300 C Operating T emperature Range Commercial K L Versions 0 C to 70 C Industrial B C Versions 40 C to 85 C beh abiee aaa tid 55 C to 125 C cnn bute nas 65 C to 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD7111 AD7111A features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING E 4s ESD SENSITIVE DEVICE ORDERING GUIDES AD7111A ORDERING GUIDE AD7111 ORDERING GUIDE Specified Temperature Accuracy Package Model Range Range Option AD7111ABN_
18. rter section of the AD 7111 AD 7111A consists of a 17 bit R 2R type converter T o obtain optimum static perfor mance at this level of resolution it is necessary to pay great attention to amplifier selection circuit grounding etc Amplifier input has current results in a dc offset at the output of the amplifier due to the current flowing through the feedback resistor Reg It is recommended that an amplifier with an input bias current of less than 10 nA be used e g AD 711 to mini mize this offset REV 0 AD7111 AD7111A Another error arises from the output amplifier s input offset voltage T he amplifier is operated with a fixed feedback resis tance but the equivalent source impedance the AD 7111 AD7111A output impedance varies as a function of attenuation level T his has the effect of varying thc noise gain of the amplifier thus creating a varying error due to amplifier offset voltage It is recommended that an amplifier with less than 50 uV of input offset be used such as the AD OPO7 in dc appli cations Amplifiers with higher offset voltage may cause audible thumps in ac applications due to dc output changes TheAD7111 AD7111A accuracy is specified and tested using only the internal feedback resistor Any gain error i e mis match of Reg to the R 2R ladder that may exist in the Typical Performance Characteristics Vpp 5V Ty 425 C Vin APPLIED TO ALL DATA INPUTS CS WR 0V
19. stry standard 8 bit multiplying DAC T his allows an easy up grading of existing AD 7524 designs which would benefit both from the wider dynamic range and the finer step resolution of fered by the AD7111A TheAD7111 AD 7111A are fabricated in Linear Compatible CMOS LC2MOS an advanced mixed technology process that combines precision bipolar circuits with low power CM OS logic LOGDAC is a registered trademark of Analog D evices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAMS Vpp Vin Q P PRODUCT HIGHLIGHTS 1 Wide D ynamic Range 0 dB to 88 5 dB attenuation range in 0 375 dB steps 2 Small Package The AD 7111 AD 7111A are available in 16 pin DIPs and SOIC packages 3 Transparent Latch Operation By tying the CS and WR in puts low the DAC latches in the AD 7111A can be made transparent 4 Fast Microprocessor Interface D ata setup times of 25 ns and write pulse width of 57 ns make the AD 7111A compatible with modern microprocessors One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD7111 AD7111A SPECIFICATION

ANALOG DEVICES AD7111/AD7111A handbook

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