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ANALOG DEVICES Ultralow Drift Op Amp AD707 handbook

1. 0 01 0 1 1 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 12 Open Loop Gain and Phase vs Frequency 140 0 0 001 0 01 0 1 1 10 100 1k 10k 100k FREQUENCY Hz Figure 15 Power Supply Rejection vs Frequency 20mV DIV CH1 TIME 2ps DIV Figure 18 Small Signal Transient Response Ay 1 R 2 kQ C 1000 pF AD707 OFFSET NULLING The input offset voltage of the AD707 is the lowest available in a bipolar op amp but if additional nulling is required the circuit shown in Figure 19 offers a null range of 200 uV For wider null capability omit R1 and substitute a 20 KQ potenti ometer for R2 OFFSET ADJUST Figure 19 External Offset Nulling and Power Supply Bypassing GAIN LINEARITY INTO A 1 KO LOAD The gain and gain linearity of the AD707 are the highest available among monolithic bipolar amplifiers Unlike other dc precision amplifiers the AD707 shows no degradation in gain or gain linearity when driving loads in excess of 1 kQ overa 10V output swing This means high gain accuracy is assured over the output range Figure 20 shows the gain of the AD707 OP07 and the OP77 amplifiers when driving a 1 kQ load The AD707 will drive 10 mA of output current with no signifi cant effect on its gain or linearity OP77 25 C Roan 1ka CHANGE IN OFFSET VOLTAGE 10pV Div 15 10 5 0 5
2. 1 5 Sy f G a n s w 20 oa ou g 15V SUPPLIES ao a gt w S a a 15 BP n5 oe S za Ee 5 10 W E 10 Ba S S 0 N v Fu gt H 3 r O 5 Q E 0 5 E Vs Vs 0 0 5 10 15 20 25 0 5 10 15 20 25 10 100 1k 10k SUPPLY VOLTAGE V SUPPLY VOLTAGE V LOAD RESISTANCE 0 Figure 1 Input Common Mode Figure 2 Output Voltage Swing Figure 3 Output Voltage Swing Range vs Supply Voltage vs Supply Voltage vs Load Resistance 100 90 256 UNITS 80 TESTED 55 C TO 125 C S B 70 9 N zZ zZ HC 5 60 lt q 5 5 2 go S S DUAL IN LINE PACKAGE m 40 E A PLASTIC N or CERDIP Q S z x z 30 5 9 METAL CAN H PACKAGE 20 Q 10 0 0 0001 0 1 2 3 4 0 4 0 3 0 2 0 1 0 0 1 0 2 03 04 0 1 1 10 100 1k 10k 100k TIME AFTER POWER ON Minutes OFFSET VOLTAGE DRIFT pV C FREQUENCY Hz Figure 4 Offset Voltage Warm Up Figure 5 Typical Distribution of Figure 6 Output Impedance vs Drift Offset Voltage Drift Frequency 40 45 f 40 N d 5 30 z a o g 1 30 ae ee E T oe ae tt ttt R 20 a a ce 20 2 G lt O 3 a La z zz a15 G 10 Z lt z f 5 10 5 2 gt a Z i g S Q 5 z 0 0 TIME 1sec Div 0 1 10 100 0 01 0 1 1 10 100 DIFFERENTIAL VOLTAGE V FREQUENCY Hz Figure 7 Input Current vs Fi
3. 0 045 1 14 sagar Pl pt 0021 0 53 REU 0 016 0 41 45 L BASE amp SEATING PLANE BSC 8 Pin Cerdip Q 8 0 005 0 13 MIN 0 055 1 4 MAX 0 310 7 87 0 220 5 59 0 320 8 13 0 405 10 29 MAX et 0 290 7 37 0 060 1 52 0 200 0 015 0 38 5 08 MAX 0 150 0 015 0 38 0 200 5 08 3 81 0 008 0 20 0 125 3 18 MIN 15 ay T 0 023 a S Sea 100 070 L 78 0 0 014 0 36 G G 0 030 0 76 Geol 8 Pin Plastic DIP N 8 0 430 10 92 0 348 8 84 0 280 7 11 0 240 6 10 y 0 325 8 25 0 300 7 62 PIN 1 0 060 1 52 0 015 0 38 0 210 5 33 0 38 1 Sree MAX LJ LJ L 0 130 0 115 2 93 0 160 4 06 WN 0 115 2 93 ig sE ATING 0 015 0 381 0 022 0 558 0 070 1 77 PLANE 0 008 0 204 0 014 0 356 2 54 0 045 1 15 BSC 8 Lead SOIC SO 8 0 1968 5 00 a 0 1890 na A 8 5 0 1574 4 00 0 2440 6 20 0 1497 3 80 4 0 2284 5 80 PIN 1 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 0 0099 0 25 0 0040 0 10 LH gt ke ke 8 gt l ie SEATING 00300 0 0192 0 49 0098 0 25 0 0500 1 27 1 27 RSE PLANE gsc 0 0138 0 35 0 0075 0 19 0 0160 0 41 8 REV B C1164a 2 12 95 PRINTED IN U S A
4. 10 15 OUTPUT VOLTAGE V Figure 20 Gain Linearity of the AD707 vs Other DC Precision Op Amps OPERATION WITH A GAIN OF 100 Demonstrating the outstanding dc precision of the AD707 in practical applications Table I shows an error budget calculation for the gain of 100 configuration shown in Figure 21 Table I Error Budget Maximum Error Contribution Av 100 C Grade Error Source Full Scale Vour 10 V Vin 100 mV Vos 15 uV 100 mV 150 ppm Ios 100 Q 1 nA 100 mV 1 ppm Gain 2 kQ Load 100 V 8 x 10 100 mV 13 ppm Noise 0 35 uV 100 mV 4ppm Vos Drift 0 1 V C 100 mV 1 ppm C 168 ppm 1 ppm C Total Unadjusted Error 25 C 55 C to 125 C With Offset Calibrated Out 25 C 55 C to 125 C 168 ppm gt 12 Bits 268 ppm gt 11 Bits 17 ppm gt 15 Bits 117 ppm gt 13 Bits 10kQ Figure 21 Gain of 100 Configuration Although the initial offset voltage of the AD707 is very low it is nonetheless the major contributor to system error In cases requiring additional accuracy the circuit shown in Figure 19 can be used to null out the initial offset voltage This method will also cancel the effects of input offset current error With the offsets nulled the AD707C will add less than 17 ppm of error This error budget assumes no error in the resistor ratio and no errors from power supply variation the 120 dB minimum PSRR of the AD707C makes this a good assumption
5. STD 883B Rev C and tape amp reel parts are also available REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices NC NO CONNECT NOTE PIN 4 CONNECTED TO CASE Plastic N and Cerdip Q Packages SOIC R Package NULL 7 8 NULL IN 2 Va IN a 6 OUTPUT vs a 5 Nc NC NO CONNECT NC NO CONNECT APPLICATION HIGHLIGHTS 1 The AD707 s 13 VWV typical open loop gain and 140 dB typical common mode rejection ratio make it ideal for precision instrumentation applications 2 The precision of the AD707 makes tighter error budgets possible at a lower cost 3 The low offset voltage drift and low noise of the AD707 allow the designer to amplify very small signals without sacrificing overall system performance 4 The AD707 can be used where chopper amplifiers are required but without the inherent noise and application problems 5 The AD707 is an improved pin for pin replacement for the LT1001 Analog Devices Inc 1995 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD 707 SPEC Fl CATI 0 NS 25 C and 15 V unless otherwise n
6. The external resistors can cause gain error from mismatch and drift over temperature REV B AD707 18 BIT SETTLING TIME Figure 22 shows the AD707 settling to within 80 UY of its final value for a 20 V output step in less than 100 us in the test con figuration shown in Figure 23 To achieve settling to 18 bits any amplifier specified to have a gain of 4 V uV would appear to be good enough however this is not the case In order to truly achieve 18 bit accuracy the gain linearity must be better than 4 ppm The gain nonlinearity of the AD707 does not contribute to the error and the gain itself only contributes 0 1 ppm The gain error along with the Vos and Vos drift errors do not comprise 1 LSB of error in an 18 bit system over the military temperature range If calibration is used to null offset errors the AD707 resolves up to 20 bits at 25 C REFERENCE SIGNAL 10V Div D U T OUTPUT ERROR 50yV Div OUTPUT 10V Div TIME 50ps Div Figure 22 18 Bit Settling FLAT TOP PULSE GENERATOR DYNAMICS l l l i DATA 5109 l l OR EQUIVALENT Figure 23 Op Amp Settling Time Test Circuit REV B 140 dB CMRR INSTRUMENTATION AMPLIFIER The extremely tight dc specifications of the AD707 enable the designer to build very high performance high gain instrumenta tion amplifiers without having to select matched op amps for the crucial first stage For the second stage the lowest grade AD7
7. 07 is ideally suited The CMRR is typically the same as the high grade parts but does not exact a premium for drift performance which is less critical in the second stage Figure 24 shows an example of the classic instrumentation amp Figure 25 shows that the circuit has at least 140 dB of common mode rejection for a 10 V common mode input at a gain of 1001 Rg 20 Q 20 000 CIRCUIT GAIN Figure 24 A 3 Op Amp Instrumentation Amplifier High CMRR is obtained by first adjusting Recm until the output does not change as the input is swept through the full common mode range The value of Rg should then be selected to achieve the desired gain Matched resistors should be used for the output stage so that Roy is as small as possible The smaller the value Of Rc the lower the noise introduced by potentiometer wiper vibrations To maintain the CMRR at 140 dB over a 20 C range the resistor ratios in the output stage R1 R2 and R3 R4 must track each other better than 10 ppm C INPUT COMMON MODE SIGNAL 10V Div CH1 COMMON MODE ERROR REFERRED TO INPUT 5uV Div CH2 TIME 2 sec Div Figure 25 Instrumentation Amplifier Common Mode Rejection AD707 PRECISION CURRENT TRANSMITTER The AD707 s excellent dc performance especially the low offset voltage low offset voltage drift and high CMRR makes it possible to make a high precision voltage controlled current transmitter using a variation of the Howla
8. A Power Consumption No Load Vs 15V 75 90 75 90 mW Vs 1 3V 7 5 9 0 7 5 9 0 mW NOTES All min and max specifications are guaranteed Specifications in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels Specifications subject to change without notice 2 REV B AD707 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage PREPS HERE AT EA ATA SN Temperature Package Package Internal Power Dissipation 500 mW me 2 Model Range Description Option Input Voltage a seis leer oh Venice T eae a Paes Aes ed TV Output Short Circuit Duration Indefinite AD707AH 40 C to 85 C 8 Pin Metal Can H 08A Differential Input Voltage Vs and Vs AD707AQ 40 C to 85 C 8 Pin Ceramic DIP Q 8 Storage Temperature Range Q H 65 C to 150 C AD707AR 40 C to 85 C 8 Pin Plastic SOIC SO 8 Storage Temperature Range N R 65 C to 125 C AD707AR REEL 40 C to 85 C 8 Pin Plastic SOIC SO 8 Lead Temperature Range Soldering 60 sec 300 C AD707AR REEL7 40 C to 85 C 8 Pin Plastic SOIC SO 8 NOTES AD707BQ 40 C to 85 C 8 Pin Ceramic DIP Q 8 Stresses above those listed under Absolute Maximum Ratings may cause AD707JN 0 C to 70 C 8 Pin Plastic DIP N 8 permanent camat an Sie POT to E maximum rating condi AD707JR 0 C to 70 C 8 Pin P
9. AHAD TOE AY FS ANALOG DEVICES Ultralow Drift Op Amp AD707 CONNECTION DIAGRAMS TO 99 H Package FEATURES Very High DC Precision 15 pV max Offset Voltage 0 1 pV C max Offset Voltage Drift 0 35 uV p p max Voltage Noise 0 1 Hz to 10 Hz 8 V pV min Open Loop Gain 130 dB min CMRR 120 dB min PSRR 1 nA max Input Bias Current AC Performance 0 3 V s Slew Rate 0 9 MHz Closed Loop Bandwidth Dual Version AD708 Available in Tape and Reel in Accordance with EIA 481A Standard PRODUCT DESCRIPTION The AD707 is a low cost high precision op amp with state of the art performance that makes it ideal for a wide range of precision applications The offset voltage spec of less than 15 uV is the best available in a bipolar op amp and maximum input offset current is 1 0 nA The top grade is the first bipolar monolithic op amp to offer a maximum offset voltage drift of 0 1 UV C and offset current drift and input bias current drift are both specified at 25 pA C maximum The AD707 s open loop gain is 8 V UV minimum over the full 10 V output range when driving a 1 kQ load Maximum input voltage noise is 350 nV p p 0 1 Hz to 10 Hz CMRR and PSRR are 130 dB and 120 dB minimum respectively The AD707 is available in versions specified over commercial industrial and military temperature ranges It is offered in 8 pin plastic mini DIP small outline SOIC hermetic cerdip and hermetic TO 99 metal can packages Chips MIL
10. gure 8 Input Noise Spectral Figure 9 0 1 Hz to 10 Hz Voltage Differential Input Voltage Density Noise EE REV B N o OPEN LOOP GAIN V V 0 60 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C Figure 10 Open Loop Gain vs Temperature a L B D N o t o a o D COMMON MODE REJECTION d N o o 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 13 Common Mode Rejection vs Frequency SUPPLY CURRENT mA 0 3 6 9 12 15 18 21 24 SUPPLY VOLTAGE V Figure 16 Supply Current vs Supply Voltage REV B OPEN LOOP GAIN V V 0 5 10 15 20 25 SUPPLY VOLTAGE V Figure 11 Open Loop Gain vs Supply Voltage N a N a r OUTPUT VOLTAGE V p p 0 1k 10k 100k 1M FREQUENCY Hz Figure 14 Large Signal Frequency Response 20mV DIV CH1 TIME 2ps DIV Figure 17 Small Signal Transient Response Ay 1 R 2 kQ C 50 pF OPEN LOOP GAIN V pV POWER SUPPLY REJECTION dB 140 0 120 BL 2kQ 139 GL 1000pF g 100 60 D 9 80 go D PHASE ii 60 MARGIN 120 2 58 x Nee A a 40 150 GAIN 20 180 10
11. lastic SOIC SO 8 ions tor extende er1ods may attiec evice reliability N 8 pin plastic ace Di 165 C Watt 8 pin cerdip aes Oy 110 C Watt AD707JR REEL 0 C to 70 C SFin Plastic SOIC SO 8 8 pin small outline package H 155 C Watt 8 pin header package Oy AD707JR REEL7 0 C to 70 C 8 Pin Plastic SOIC SO 8 200 C Watt AD707KN 0 C to 70 C 8 Pin Plastic DIP N 8 AD707KR 0 C to 70 C 8 Pin Plastic SOIC SO 8 AD707KR REEL 0 C to 70 C 8 Pin Plastic SOIC SO 8 AD707KR REEL7 0 C to 70 C 8 Pin Plastic SOIC SO 8 METALIZATION PHOTOGRAPH Dimensions shown in inches and mm Contact factory for latest dimensions CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human body and test equipment and can discharge without detection Although the AD707 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality prin 4 ESD SENSITIVE DEVICE REV B AD707 Typical Characteristics Vs 35 gt T 0 5 Dd C 8 V gt w 30 Z 1 0 Z 2 oa 25 wO Z O a o gt gt gt lt a gt
12. nd Current Source circuit Figure 26 This circuit provides a bidirectional load current which is derived from a differential input voltage R3 R4 100kQ 100kQ RscaLe Rgcate a yh Figure 26 Precision Current Source Sink The performance and accuracy of this circuit will depend almost entirely on the tolerance and selection of the resistors The scale resistor Rscarz and the four feedback resistors directly affect the accuracy of the load current and should be chosen carefully or trimmed As an example of the accuracy achievable assume I must be 10 mA and the available Vyn is only 10 mV Rscare 10 mV 10 mA 1Q Terror due to the AD707C Maximum lennon 2 Vos Rscatz 2 Vos Drift Rscarz Ios 100 k Rscare 2 15 uV 1 Q 2 0 1 WYS Q 1 nA 100 MD Q 1 5 nA 125 C 30 pA 0 2 uA C 100 pA 150 pA 125 C 130 uA 10 mA 1 3 25 C 180 uA 10 mA 1 8 125 C Low drift high accuracy resistors are required to achieve high precision OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Pin Metal Can H 08A REFERENCE PLANE 0 750 19 05 0 185 4 70 0 500 12 70 0 165 4 19 0 250 6 35 0 050 MIN 0 100 0 160 4 06 0 110 2 79 1 27 2 54 je MAX BSC 0 335 8 51 L A 0 045 1 14 0 305 7 75 Den Were a ki 7 0 69 0 370 9 40 0 335 8 51 0 040 1 02 MAX 0 019 0 48 x a 0 016 0 41 BSC 0 034 0 86
13. oted AD707J IA AD707K B Conditions Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE Initial 30 90 10 25 uV vs Temperature 0 3 10 01 03 uV C TMn to Tmax 50 100 15 45 uV Long Term Stability 0 3 0 3 uV month Adjustment Range R2 20 kQ Figure 19 t4 4 mV INPUT BIAS CURRENT 10 2 5 0 5 2 0 nA Tmn to Tmax 2 0 4 0 1 5 4 0 nA Average Drift 15 40 15 40 40 40 pA C OFFSET CURRENT Vcem 0V 0 5 2 0 0 3 1 5 nA Tmn to Tmax 2 0 4 0 1 0 2 0 nA Average Drift 2 40 1 25 25 35 pA C INPUT VOLTAGE NOISE 0 1 Hz to 10 Hz 0 23 0 6 0 23 0 6 LV p p f 10Hz 10 3 28 10 3 18 nV VHz f 100 Hz 10 0 13 0 10 0 12 nV VHz f 1kHz 9 6 11 0 9 6 11 0 nV VHz INPUT CURRENT NOISE 0 1 Hz to 10 Hz 14 35 14 30 pA p p f 10 Hz 0 32 0 9 0 32 0 8 pA VHz f 100 Hz 0 14 0 27 0 14 0 23 pA VHz f 1 kHz 0 12 0 18 0 12 0 17 pA VHz COMMON MODE REJECTION RATIO Vom 13 V 120 140 130 140 dB OPEN LOOP GAIN Vo 410V Tmn to Tmax 3 13 3 13 V V POWER SUPPLY REJECTION RATIO Vs 3 V tot 18 V 110 130 115 130 dB FREQUENCY RESPONSE Closed Loop Bandwidth 0 4 0 9 0 4 09 MHz Slew Rate 0 12 0 3 0 12 0 3 V us INPUT RESISTANCE Differential 24 100 45 200 MQ Common Mode 200 300 GO OUTPUT CHARACTERISTICS Voltage R aan 2 10 kQ 13 5 14 13 5 14 V R aan 2 2 KQ 12 5 13 0 12 5 13 0 V R aan Z 1 KQ 12 0 12 5 12 0 12 5 V R aan 2 2 KQ Tun to Tmax 12 0 13 0 12 0 13 0 V OPEN LOOP OUTPUT RESISTANCE 60 60 Q POWER SUPPLY Current Quiescent 25 3 25 3 m

ANALOG DEVICES Ultralow Drift Op Amp AD707 handbook

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