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ANALOG DEVICES AD7008 handbook

1. START 0 Hz STOP 25 000 000 0 Hz CENTER 16 500 000 0 Hz SPAN 25 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 5 6 SEI RBW 3 kHz VBW 10 kHz ST 5 6 SEC Figure 29 fck 50 MHz foyr 9 1 MHz Figure 32 50 MHz foyr 16 5 MHz REF 5 0 dBm OFFSET 11 100 000 0 Hz 10 dB DIV RANGE 5 0 dBm 54 1 dB 130 120 110 a a 100 R E 90 tc 80 o 70 60 START 0 Hz STOP 25 000 000 0 Hz 50 RBW 3 kHz VBW 10 kHz T 5 6 SEC 0 10 20 30 40 50 MASTER CLOCK MHz Figure 30 50 MHz foyr 11 1 MHz Figure 33 Typical Current Consumption vs Frequency REF 5 0 dBm OFFSET 10 675 000 0 Hz 10 dB DIV RANGE 5 0 dBm 47 0 dB 40 45 50 1 Q 55 N a lt 60 ta a 65 70 CENTER 13 100 000 0 Hz SPAN 25 000 000 0 Hz 75 RBW 3 kHz VBW 10 kHz ST 5 6 SEC 0 10 20 30 40 50 MASTER CLOCK MHz Figure 31 fcuk 50 MHz four 13 1 MHz Figure 34 Typical Plot of SFDR vs Master Clock Frequency When four Frequency Word 5671C71C Hex 14 REV B AD7008 AD7008 PCB DDS EVALUATION BOARD The AD7008 PCB DDS Evaluation Board allows designers to evaluate the high performance AD7008 DDS Modulator with a minimum amount of effort To prove this DDS will meet the user s waveform synthesis re qu
2. CENTER 6 500 000 0 Hz RBW 3 kHz SPAN 10 000 000 0 Hz VBW 10 kHz ST 2 4 SEC Figure 24 fork 20 MHz four 6 5 MHz REF 4 3 dBm OFFSET 6 304 000 0 10 dB DIV RANGE 5 0 dBm 2 56 3 dB START 0 Hz STOP 16 000 000 0 Hz RBW 3 kHz ST3 6 SEC VBW 10 kHz Figure 25 fork 50 MHz four 2 1 MHz 13 REF 4 3 dBm OFFSET 14 500 000 0 Hz 10 dB DIV RANGE 5 0 dBm 52 4 dB CENTER 16 000 000 0 Hz RBW 3 kHz SPAN 25 000 000 0 Hz VBW 10 kHz ST 5 6 SEC Figure 26 fork 50 MHz four 7 1 MHz REF 5 0 dBm OFFSET 1 280 000 0 Hz 10 dB DIV RANGE 5 0 dBm 51 8 dB START 0 Hz RBW 3 kHz STOP 10 000 000 0 Hz VBW 10 kHz ST 2 4 SEC Figure 27 fork 20 MHz four 7 1 MHz REF 4 3 dBm OFFSET 15 300 000 0 Hz 10 dB DIV RANGE 5 0 dBm 51 8 dB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 eee ae Ve E Leu ElIlIlIp 4 4 1 1 1 1 1 1 1 1 1 1 1 START 0 Hz STOP 25 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 5 6 SEC Figure 28 fork 50 MHz four 5 1 MHz AD7008 Typical Performance Characteristics REF 5 0 dBm OFFSET 4 500 000 0 Hz REF 5 0 dBm OFFSET 500 000 0 Hz 10 dB DIV RANGE 5 0 dBm 54 7 dB 10 dB DIV RANGE 5 0 dBm 44 8 dB
3. 7008 hv 9 ANALOG DEVICES CMOS DDS Modulator AD7008 FEATURES Single 5 V Supply 32 Bit Phase Accumulator On Chip COSINE and SINE Look Up Tables On Chip 10 Bit DAC Frequency Phase and Amplitude Modulation Parallel and Serial Loading Software and Hardware Power Down Options 20 MHz and 50 MHz Speed Grades 44 Pin PLCC APPLICATIONS Frequency Synthesizers Frequency Phase or Amplitude Modulators DDS Tuning Digital Modulation PRODUCT DESCRIPTION The AD7008 direct digital synthesis chip is a numerically con trolled oscillator employing a 32 bit phase accumulator sine and cosine look up tables and a 10 bit D A converter integrated on a single CMOS chip Modulation capabilities are provided for phase modulation frequency modulation and both in phase and quadrature amplitude modulation suitable for QAM and SSB generation Clock rates up to 20 MHz and 50 MHz are supported Fre quency accuracy can be controlled to one part in 4 billion Modulation may be effected by loading registers either through the parallel microprocessor interface or the serial interface A frequency select pin permits selection between two frequencies on a per cycle basis The serial and parallel interfaces may be operated independently and asynchronously from the DDS clock the transfer control signals are internally synchronized to prevent metastability prob lems The synchronizer can be bypassed to reduce the transfer latenc
4. 8 2 9 Cer Chip Cap 0 1 uF Murata Grm42 6 CLOCK FSEL SMB Submin Snap on Male PCB MT Plug SCLK SDATA 1 FSADJ RN55 Res Met Film 392 1 HDR SIP 3 Pin Male 1 Shunt 530153 2 1 P1 36 Pin D Conn Rt Ang Pcmt Fem AMP 1 P2 PC Voltage Ter Blk w Screws Augat RDI R1 R3 RN55 Res Met Film 10k R4 R5 RN55 Res Met Film 49 9 1 RZ1 10P Bussed Res Ntwk 10k CSC10A01103G 1 RZ2 6P Bussed Res Ntwk 4 7k CSC06A01472G 1 UI AD7008 JP50 CMOS DDS Modulator 1 U2 74HC74 Dual D type Pos Ed Trigd Flip Flop 1 VREF Pin Terminal Testpoint 1 XTAL OSC XTAL Fox F1100H 50 MHz Socket Methode 213 044 501 4 Support Nylon 1 PCB 48295 26 Pin Sockets Closed End 15 AD7008 Controlling the AD7008 PCB The AD7008 PCB is designed to allow control frequency specification reset etc through the parallel printer port of a standard IBM compatible PC The user simply disconnects the printer cable from the printer and inserts it into edge connector P1 of the evaluation board The printer port provides information to the AD7008 PCB through eight data lines and four control lines Control signals are latched on the AD7008 PCB to prevent problems with long printer cables A 3 5 floppy disk containing software to control the AD7008 is provided with the AD7008 PCB This software was developed using C The C source code is provided in a file named A AD7008 C which the user may view run o
5. 1 0 V Terminated into 50 O Externally CMOS clock input HIGH 4 1 to 5 V CMOS clock input LOW 0 0 to 0 5 V USING THE AD7008 PCB DDS EVALUATION BOARD The AD7008 PCB evaluation kit is a test system designed to simplify the evaluation of the AD7008 50 MHz Direct Digital Synthesizer Provisions to control the AD7008 from the printer port of an IBM compatible PC are included along with the REV B necessary software This data sheet provides information on operating the evaluation board additional details are available from the ADI technical assistance line 1 800 ANALOGD Prototyping Area An area near one edge of the board is intentionally left void of components to allow the user to add additional circuits to the evaluation test set Users may want to build custom analog fil ters for the outputs or add buffers and operational amplifiers used in the final applications XO vs External Clock The reference clock of the AD7008 PCB is normally provided by a 50 MHz CMOS oscillator This oscillator can be removed and an external CMOS clock connected to CLOCK If an ex ternal clock is used a 50 resistor R6 should be installed Power Supply Power for the AD7008 PCB must be provided externally through the pin connections as described in the Inputs Outputs The power leads should be twisted to reduce ground loops AD7008 PCB BILL OF MATERIAL Quantity Reference Description 1 Cl Tant Cap 10 uF 35 V 20
6. or QAM to be performed CR3 Synchronizer Logic Enabled The FSELECT LOAD and TC3 TCO signals are passed through a 4 stage pipeline to synchronize them with the CLOCK avoiding metastability problems 1 Synchronizer Logic Disabled The FSELECT LOAD and TC3 TCO signals bypass the synchronization logic This allows for faster response to the control signals The Command Register can only be loaded from the parallel assembly register REV B 1 AD7008 CIRCUIT DESCRIPTION The AD7008 provides an exciting new level of integration for the RF Communications system designer The AD7008 com bines the numerically controlled oscillator NCO SINE CO SINE look up tables frequency phase and IQ modulators and a digital to analog converter on a single integrated circuit The internal circuitry of the AD7008 consists of four main sec tions These are Numerically Controlled Oscillator NCO Phase Modulator SINE and COSINE Look Up Tables In Phase and Quadrature Modulators Digital to Analog Converter The AD7008 is a fully integrated Direct Digital Synthesis DDS chip The chip requires one reference clock two low precision resistors and six decoupling capacitors to provide digitally created sine waves up to 25 MHz In addition to the generation of this RF signal the chip is fully capable of a broad range of simple and complex modulation schemes These modulation schemes are fully implemented in the digital domain all
7. phase range 0 to 2 Outside this range of numbers the sinu soidal functions repeat themselves in a periodic manner The digital implementation is no different The accumulator simply scales the range of phase numbers into a multibit digital word The phase accumulator in the AD7008 is implemented with 32 bits Therefore in the AD7008 2 2 Likewise the APhase term is scaled into this range of numbers 0 lt APhase lt 2 1 Making these substitutions into the equation above APhase x f 23 With a clock signal of 50 MHz and a phase word of 051 852 hex J CLOCK where Q lt APhase lt 27 _ 51EB852x50 MHz f 232 The input to the phase accumulator i e the phase step can be selected either from the FREQO Register or FREQI Register and this is controlled by the FSELECT pin The phase accu mulator in the AD7008 inherently generates a continuous 32 bit phase signal thus avoiding any output discontinuity when switching between frequencies This facilitates complex fre quency modulation schemes such as GMSK 1 000000000931 MHz Following the NCO a phase offset can be added to perform phase modulation using the 12 bit PHASE Register The con tents of this register are added to the most significant bits of the NCO Sine and Cosine Look Up Tables To make the output useful the signal must be converted from phase information into a sinusoidal value Since phase informa tion maps directly int
8. 1 1 1 1 1 1 1 1 1 1 1 1 1 LAU n Earned 4 1 1 1 1 1 1 1 1 1 1 START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 19 fork 20 MHz four 3 1 MHz REF 5 0 dBm OFFSET 4 640 000 0 Hz 10 dB DIV RANGE 5 0 dBm 54 8 dB START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 20 fork 20 MHz four 5 1 MHz REF 4 3 dBm OFFSET 6 320 000 0 Hz 10 dB DIV RANGE 5 0 dBm 61 3 dB START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 21 fork 20 MHz four 2 1 MHz REF 5 0 dBm OFFSET 490 000 0 Hz 10 dB DIV RANGE 5 0 dBm 63 4 dB START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 22 fork 20 MHz four 4 1 MHz REV REV B Typical Performance Characteristics AD 7008 REF 5 0 dBm OFFSET 1 680 000 0 Hz 10 dB DIV RANGE 5 0 dBm 52 8 dB T 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T 1 1 1 1 4 4 1 1 1 1 1 1 1 1 1 START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 23 fork 20 MHz four 6 1 MHz REF 4 3 dBm OFFSET 500 000 0 Hz 10 dB DIV RANGE 5 0 dBm 51 7 dB
9. 3 V Digital I O Voltage to DGND 0 3 V to Vpp 0 3 V ee WORD Analog I O Voltage to AGND 0 3 V to Vpp 0 3 V Operating Temperature Range MOST SIGNIFICANT WORD IS LOADED FIRST Commercial J Version 0 2 vss OC proe Faure s 16 Bit Parallel Port Loading Sequence Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 secs 300 C 4 32 BIT PARALLEL ASSEMBLY REGISTER gt Junction Temperature 115 C MSB LSB PLCC 65 Thermal Impedance 53 8 C W Thermal Impedance 222222222222 241 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional ABYTE B BYTE 07 00 B BYTE operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ABYTE B BYTE C BYTE D7 D0 C BYTE ORDERING GUIDE oro bene emperature ackage ackage Model MOST SIGNIFICANT BYTE IS LOADED FIRST AD7008AP20 40 C to 85 C 44 Pin PLCC P 44A Figure 6 8 Bit Parallel Port Loading Sequence AD7008JP50 09 to 70 C 44 Pin PLCC P 44A AD7008 PCB 1 3 5 Disk AD7008 PCB DDS Evaluation Kit assembled and tested Kit inc
10. 6 00 A BSC 0 59 14 99 TOR VIEW 0 021 0 53 PINS DOWN 0 013 0 33 0 032 0 81 T 4 0 026 0 66 y AN 0 020 0 040 1 01 0 50 0 656 16 66 _ gt Bg 0 025 0 64 R 0 650 16 51 a 0 695 17 65 6110 4270 529 0 685 17 40 si f 2 REV B C1791a 10 2 95 PRINTED IN U S A
11. CLOCK IS LOW LOAD 36 FSEL 31 TCO TC3 32 35 TRANSFER CONTROL TC REGISTER D Q r3 L3 rai x6 QD orb a PASS x6 x6 x6 x6 gt gt gt gt PHASE SUMMATION RESET SYNCHRONIZATION RESET 38 TO SIN COS SUMMATION D gt gt CLK CLOCK 30 ACCUMULATOR CLK RESET Figure 8 AD7008 Register and Control Logic 6 REV B TO PHASE ACCUMULATOR AD7008 Table I Latency Table Latency Function Synchronizer Enabled CR3 0 FSelect 14t Phase 13 IQ Mod llt NOTE All latencies are reduced by 4t when 1 synchronizer disabled 1t is equal to one pipeline delay Table II Source and Destination Register TC3 TC2 TC1 TCO LOAD Source Register Destination Register x X X X 0 N A N A 0 0 X X 1 Parallel COMMAND 1 0 0 0 1 Parallel FREQO 1 0 0 1 1 Parallel FREQ1 1 0 1 0 1 Parallel PHASE 1 0 1 1 1 Parallel IOMOD 1 1 0 0 1 Serial FREQO 1 1 0 1 1 Serial FREQI 1 1 1 0 1 Serial PHASE 1 1 1 1 1 Serial IQMOD The Command Register can only be loaded from the parallel assembly registers Table III AD7008 Control Registers Register Size Reset State Description COMMAND 4 Bits CR2 CRO All Zeros Command Register This is written to using the parallel assembly register 0 REG 32 Bits DB31 DBO All Zeros Frequency Register 0 This defines the output frequency when FSELE
12. CT 0 as a fraction of the CLOCK frequency FREQ1 REG 32 Bits DB31 DBO All Zeros Frequency Register 1 This defines the output frequency when FSELECT 1 as a fraction of the CLOCK frequency PHASE REG 12 Bits DB11 DBO0 All Zeros Phase Offset Register The contents of this register is added to the output of the phase accumulator IQMOD REG 20 Bits DB19 DBO All Zeros I and Q Amplitude Modulation Register This defines the amplitude of the I and Q signals as 10 bit twos complement binary fractions DB 19 10 is multiplied by the Quadrature sine component and multiplied by the In Phase cosine component On power up the Command Register should be configured by the user for the desired mode before operation Table IV Command Register Bits CRO 0 Eight Bit Databus Pins D15 D8 are ignored and the parallel assembly register shifts eight places left on each write Hence four successive writes are required to load the 32 bit parallel assembly register Figure 6 1 Sixteen Bit Databus The parallel assembly register shifts 16 places left on each write Hence two successive writes are required to load the 32 bit parallel assembly register Figure 5 CRI Normal Operation 1 Low Power Sleep Mode Internal Clocks and the DAC current sources are turned off CR2 Amplitude Modulation Bypass The output of the sine LUT is directly sent to the DAC 1 Amplitude Modulation Enable IQ modulation is enabled allowing AM
13. Output Compliance 1 1 Volts DC Accuracy Integral Nonlinearity 1 LSB Differential Nonlinearity 1 LSB DDS SPECIFICATIONS Update Rate fmax 20 50 MSPS Dynamic Specifications Signal to Noise 50 50 dB forx four 2MHz Total Harmonic Distortion 55 53 fck fuax four 2 MHz Spurious Free Dynamic Range SFDR Narrow Band 50 kHz 70 70 dBc forx 6 25 MHz four 2 11 MHz Wide Band 2 MHz 55 55 dBc VOLTAGE REFERENCE Internal Reference 25 C 1 2 1 27 1 35 1 2 1 27 1 35 Volts Reference TC 300 300 ppm C Overdrive 0 2 0 2 V LOGIC INPUTS Vim Input High Voltage Vpp 0 9 Vpp 0 9 Volts Vii Input Low Voltage 0 9 0 9 Volts Input Current 10 10 Cm Input Capacitance 10 10 pF POWER SUPPLIES Vpp 4 75 5 25 4 75 5 25 Volts 26 26 3900 Ipp 22 1 5 MHz 22 1 5 MHz mA Iaa Ipp fork 80 110 125 160 mA Sleep Vpp 10 20 mA NOTES Operating temperature ranges as follows A Version 40 C to 85 C J Version 0 C to 70 C 2 dynamic specifications are measured using IOUT 100 Production tested 6 25 MHz Frequency Word 5671C71C HEX four 2 11 MHz Ver may be externally driven between 0 and Vpp gt Do not allow reference current to cause power dissipation beyond the limit of I aa Ipp shown above Specifications subject to change without notice 2 REV B AD7008 Tl M NG C HARACTERISTICS Vag Von 5 V 526 T Tum tO Tmax unles
14. allel or serial assembly registers The load pin must be high at least 1t See Table TC3 TCO Transfer Control address bus digital inputs This address determines the source and destination registers that are used during a transfer The source register can either be the parallel assembly register or the serial assembly regis ter The destination register can be any of the following COMMAND REG FREQO REG FREQ1 REG PHASE REG or IQMOD REG TC3 TCO should be valid prior to LOAD rising and should not change until LOAD falls The Command Register can only be loaded from the parallel assembly register See Table II CS Chip Select active low digital input This input in conjunction with WR is used when writing to the parallel assembly register WR Write active low digital input This input in conjunction with CS is used when writing to the parallel assembly register D7 DO Data Bus digital inputs These represent the low byte of the 16 bit data input port used to write to the 32 bit parallel assembly register The databus can configured for either a 8 bit or 16 bit MPU DSP ports D15 D8 Data Bus digital inputs These represent the high byte of the 16 bit data input port used to write to the 32 bit parallel assembly register The databus can be configured for either a 8 bit or 16 bit MPU DSP ports When the databus is configured for 8 bit operation D8 D15 should be tied to DGND SCLK Serial Clock digital input SCLK is used in conjunction w
15. ausing the AD7008 to modulate the carrier frequency between the two values F SELECT AD7008 Figure 14 FSK Modulator The AD7008 has three registers that can be used for modula tion Besides the example of frequency modulation shown above the frequency registers can be updated dynamically as can the phase register and the IQMOD register These can be modulated at rates up to 16 5 MHz The example shown below along with code fragment shows how to implement the AD7008 in an amplitude modulation scheme Other modulation schemes can be implemented in a similar fashion 10 BIT DAC IOUT Figure 15 Amplitude Modulation IRQ3 Interrupt Vector in_audio is a port used to sample the audio signal This signal is assumed to be twos complement This interrupt should be serviced at an audio sample rate This routine assumes that the AD7008 has been set up with the Ampli tude Modulation Enabled irq3_asserted Get audio sample r6 dm in audio REV B This section converts the twos complement au dio into offset binary scaled for modulating the AD7008 If twos complement is used the modulation scheme will instead be double side band suppressed carrier r5 0x80000000 r6 r6 xor r5 r6 lshift r6 by 1 r6 r6 xor r5 r4 lshift r6 by 6 Load parallel assembly register with modula tion data portion set to midscale I portion with scaled data r5 0x00000004 dm dds para r5 d
16. e inputs of REV B TC3 TCO At some time after the second falling edge of WR the LOAD signal may go high As long as the load signal is high 5 ns see setup time before the rising edge of the CLOCK sig nal data will be transferred to the destination register The limiting factor of this technique is the WR period which is 30 ns Thus the CLOCK may run up to 33 MSPS using this technique and the effective update rate would be one half or 16 5 MHz See timing Figure 10 for timing details LOAD Figure 10 Accelerated Data Load Sequence APPLICATIONS Serial Configuration Data is written to the AD7008 in serial mode using the two sig nal lines SDATA and SCLK Data is accumulated in the serial assembly register with the most significant bit loaded first The data bits are loaded on the rising edge of the serial clock Once data is loaded in the serial assembly register it must be trans ferred to the appropriate register on chip This is accomplished by setting the TC bits according to Tables II and If you want to load the serial assembly register into FREQ register the TC bits should be 1101 When the LOAD pin is raised data is transferred directly to the FREQ register When oper ating in serial mode some functions must still operate in parallel mode such as loading the TC bits and updating the Command register which is accessed only through the parallel assembly register See Figure 11 for a typical serial mode configurat
17. e to the parallel assembly register Serial data is input to the chip on the rising edge of SCLK most significant bit first Figure 4 The data in the assembly regis ters can be transferred to the modulation registers by means of the transfer control pins Maximum Updating of the AD7008 Updating the AD7008 need not take place in a synchronous fashion However in asynchronous systems most of the exter nal clock pulses LOAD and SCLK must be high for greater than one system clock period This insures that at least one CLOCK rising edge will occur successfully completing the latch function Figure 1 However if the AD7008 is run in a synchronous mode with the controlling DSP or microcontroller the AD7008 may be loaded very rapidly Optimal speed is attained when operated in the 16 bit load mode the following discussion will assume that mode is used Each of the modulation registers require two 16 bit loads This data is latched into the parallel assembly register on the falling edge of the WR command This strobe is not qualified by the CLOCK pulse but must be held low for a mini mum of 20 ns and only need be high for 10 ns The two 16 bit words may be loaded in succession While the second 16 bit word is being latched into the parallel assembly register the Transfer and Control word may be presented to the TC3 TCO pins If the designation register is always the same an external register can be used to store the information on th
18. ion U3 AD7008 FSELECT CLK RESET SLEEP Figure 11 General Purpose Serial Interface AD7008 Parallel Configuration sleep mode amplitude control and synchronization logic At The AD7008 functions fully in the parallel mode There are reset the chip defaults to 8 bit bus no amplitude control and two parallel modes of operation Both are similar but are tai logic synchronized The code fragment below indicates how lored for different bus widths 8 and 16 bits All modes of op the initialization code for the AD7008 might look using the eration can be controlled by the parallel interface ADSP 21020 On power up and reset the chip must be configured by instruc dds_para is a port define to decode for ting the command register how to operate The command reg the parallel assembly register write pulse ister may be used to set the device up for 8 or 16 bit mode dds_cont is a port defined to decode for NM the TC control Load pin The Command reg ister must first be loaded with configura tion information In this example the chip is set up for 16 bits data See Table III for details r4 0x00010000 16 bits Normal Op AM disabled Synchronizer enabled dm dds para r4 write data to parallel assembly register r4 0x00000000 dm dds cont r5 No data written data is just transferred from parallel assembly register to the command register r4 0 051 0000 1 MHz 051EB852 load high word fir
19. irements the only things needed are the AD7008 PCB DDS Evaluation Board 5 V power supply an IBM compatible PC and a spectrum analyzer The evaluation setup is shown below The DDS evaluation kit includes a populated tested AD7008 PCB board software which controls the AD7008 through the parallel printer port in a DOS or Windows environment and an AD7008P The AD7008 direct digital synthesis chip is a numerically controlled oscillator employing a 32 bit phase accumulator sine and cosine look up tables and a 10 bit D A converter integrated on a single CMOS chip Modulation capabilities are provided for phase modulation frequency modulation and both in phase and quadrature amplitude modulation suitable for SSB generation Clock rates up to 20 MHz and 50 MHz are supported Fre quency accuracy can be controlled to one part in four billion EXTERNAL POWER SUPPLY OPTIONAL POWER TTL CLOCK CLOCK OSCILLATOR QGUPPLY GENERATOR INTERFACE pits rosie CMOS DDS STANDARD PRINTER CABLE Na SOFTWARE PROVIDED AD7008 DDS EVALUATION BOARD 500 CABLE nun anu nu SPECTRUM ANALYZER IBM COMPATIBLE PC Figure 35 AD7008 DDS Evaluation Board Setup Table IV AD7008 PCB Typical Electrical Characteristics Nominal power supplies CLK 50 MHz Typical Characteristics Value Units 5 0 V Supply Current 125 mA AD7008 Output Voltage 0 to
20. ith SDATA to clock data into the 32 bit serial assem bly register SDATA Serial Data digital input Serial data is clocked on the rising edge of SCLK Most Significant Bit MSB first SLEEP Low power sleep control active high digital input SLEEP puts the AD7008 into a low power sleep mode Inter nal clocks are disabled while also turning off the DAC current sources A SLEEP bit is also provided in the COMMAND REG to put the AD7008 into a low power sleep mode RESET Register Reset active high digital input RESET clears the COMMAND REG and all the modulation registers to Zero TEST Test Mode This is used for factory test only and should be left as a No Connect REV B 5 AD7008 14 PIPELINE DELAYS 13 PIPELINE DELAYS PHASE ACCUMULATOR AD7008 REGISTER PHASE SUMMATION AND CONTROL LOGIC 11 PIPELINE DELAYS SIN COS SUMMATION IOUT IOUT SLEEP 37 COMMAND REGISTER LK 41 Ur SCLK 41 Da 23 SDATA 42 32 a P ASSEMBLY REGISTER x4 L gt CLK N 32 BIT PARALLEL i ASSEMBLY REGISTER D gt o Mee REGISTER DO D15 15 8 7 0 MUX DO BUS MODE 19 26 8 15 So se UNS D3__ SYNCHRO LOGIC WR 16 1 5 27 c D FLIP FLOPS ARE MASTER SLAVE Ease Se LATCHING DATA ON CLK RISING EDGE FREQUENCY PASS FLIP FLOPS ARE TRANSPARENT REGISTERS WHEN THE
21. ludes an AD7008 P50 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection WARNING c Although the AD7008 features proprietary ESD protection circuitry permanent damage may Ah occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE PIN CONFIGURATION PLCC i o 3 lt a HZ 4 256338 5 5 8 0 0 9689296 6 DGND 7 Vpp D8 PIN NO 1 IDENTIFIER RESET D9 SLEEP D10 LOAD D11 AD7008 PLCC Tes 12 VIEW TC2 NOT TO SCALE FSELECT CLOCK DGND DGND 4 REV B AD7008 PIN DESCRIPTION Mnemonic Function POWER SUPPLY Vaa Positive power supply for the analog section 0 1 decoupling capacitor should be connected between Va and AGND This is 5 V 5 AGND Analog Ground Vpp Positive power supply for the digital section A 0 1 uF decoupling capacitor should be connected between Vpp and DGND This is 5 V 5 Both and Vpp should be externally tied together DGND Digital Ground both AGND and DGND should be externally tied together ANALOG SIGNAL AND REFERENCE IOUT IOUT Current Output This is a high impedance current source A load resistor should be con
22. m dds para r4 Transfer parallel assembly register to IQMOD register r4 0xb0000000 dm dds cont r4 rti Many applications require precise control of the output ampli tude such as in local oscillators signal generators and modula tors There are several methods to control signal amplitude The most direct is to program the amplitude using the IQMOD register on the AD7008 Other methods include selecting the load resistor value or changing the value of Rsgr Another op tion is to place a voltage out DAC on the ground side of as in Figure 16 This allows easy control of the output amplitude without affecting other functions of the AD7008 Any combina tion of these techniques may be used as long as the full scale voltage developed across the load does not exceed 1 volt U3 AD7008 DMDXX DATA BITS DMAXX ADDRESS BITS 74HC138 VOLTAGE OUT DAC i e AD7245A 1 VOLTS 6233 x Vaer Voao Rset 16 External Gain Adjustment 11 AD7008 Typical Performance Characteristics Figure 17 Equivalent Reference Circuit REF 4 3 dBm OFFSET 3 330 000 0 Hz 10 dB DIV RANGE 5 0 dBm 63 6 dB START 0 Hz STOP 10 000 000 0 Hz RBW 3 kHz VBW 10 kHz ST 2 4 SEC Figure 18 fork 20 MHz four 1 1 MHz REF 4 3 dBm OFFSET 4 500 000 0 Hz 10 dB DIV RANGE 5 0 dBm 61 1 dB 1 1 1 1 1 1
23. nected between IOUT and AGND IOUT should be either tied directly to AGND or through an external load resistor to AGND FS ADJUST Full Scale Adjust Control A resistor Rsgr is connected between this pin and AGND This determines the mag nitude of the full scale DAC current The relationship between and the full scale current is as follows 6233 x VREF IOUT gyi t scALE mA R VREF 1 27 V nominal Rser 3900 typical SET VREF Voltage Reference Input A 0 1 uF decoupling ceramic capacitor should be connected between and Vaa There is an internal 1 27 volt reference which can be overdriven by an external reference if required See specifications for maximum range COMP Compensation pin This is a compensation pin for the internal reference amplifier A 0 1 uF decoupling ceramic capacitor should be connected between COMP and DIGITAL INTERFACE AND CONTROL CLOCK Digital Clock Input for DAC and NCO DDS output frequencies are expressed as a binary fraction of the fre quency of this clock The output frequency accuracy and phase noise is determined by this clock FSELECT Frequency Select Input FSELECT controls which frequency register FREQO or FREQI is used in the phase accumulator Frequency selection can be done on a cycle per cycle basis See Tables I II and III LOAD Register load active high digital Input This pin in conjunction with control loading of internal regis ters from either the par
24. ntial ended operation IOUT can be tied directly to AGND for single ended operation or through a load resistor to develop an output volt age The load resistor can be any value required as long as the full scale voltage developed across it does not exceed 1 volt Since full scale current is controlled by Rsgr adjustments to can balance changes made to the load resistor DSP and MPU Interfacing The AD7008 contains a 32 bit parallel assembly register and a 32 bit serial assembly register Each of the modulation registers can be loaded from either assembly register under control of the LOAD pin and the Transfer Control TC pins See Table IT The Command register can be loaded only from the parallel as sembly register In practical use both serial and parallel inter faces can be used simultaneously if the application requires TC3 TCO should be stable before the LOAD signal rises and should not change until after LOAD falls Figure 2 The DSP MPU asserts both WR and CS to load the parallel as sembly register Figure 3 At the end of each write the parallel assembly register is shifted left by 8 or 16 bits Depending on CRO and the new data is loaded into the low bits Hence two 16 bit writes or four 8 bit writes are used to load the parallel as sembly register When loading parallel data it is only necessary to write as much data as will be used by that register For in stance the Command Register requires only one writ
25. o amplitude a ROM look up table con verts the phase information into amplitude To do this the digital phase information is used to address a Sine Cosine ROM LUT Only the most significant 12 bits are used for this pur pose The remaining 20 bits provide frequency resolution and minimize the effects of quantization of the phase to amplitude conversion In Phase and Quadrature Modulators Two 10 bit amplitude multipliers are provided allowing the easy implementation of either Quadrature Amplitude Modulation QAM or Amplitude Modulation AM The 20 bit IOMOD Register is used to control the amplitude of the I cos and Q sin signals IOMOD 9 0 controls the I amplitude and IQMOD 19 10 controls the Q amplitude The user should ensure that when summing the I and Q signals the sum should not exceed the value that a 10 bit accumulator can hold The AD7008 does not clip the digital output the output will roll over instead of clip REV B AD7008 When amplitude modulation is not required the IQ multipliers can be bypassed CR 2 The sine output is directly sent to the 10 bit DAC Digital to Analog Converter The AD7008 includes a high impedance current source 10 bit DAC capable of driving a wide range of loads at different speeds Full scale output current can be adjusted for optimum power and external load requirements through the use of a single external resistor The DAC can be configured for single or differe
26. owing accurate and simple realization of complex modulation algorithms using DSP techniques THEORY OF OPERATION Sine waves are typically thought of in terms of their amplitude form a t sin 00 or a t cos t However these are non linear and not easy to generate except through piece wise con struction On the other hand the angular information is linear in nature That is the phase angle rotates though a fixed angle for each unit of time The angular rate depends on the fre quency of the signal by the traditional rate of 2 nf MAGNITUDE 1 0 PHASE 0 Figure 9 Knowing that the phase of a sine wave is linear and given ref erence interval clock period the phase rotation for that period can be determined APhase wdt Solving for w APhase I E 2 nf Solving for f and substituting the reference clock frequency for _ APhase X fr ock 2n 1 the reference period The AD7008 builds the output based on this simple equation A simple DDS chip will implement this equation with 3 major subcircuits The AD7008 has an extra section for I and Q modulation Numerically Controlled Oscillator Phase Modulator This consists of two frequency select registers a phase accumu lator and a phase offset register The main component of the NCO is a 32 bit phase accumulator which assembles the phase component of the output signal Continuous time signals have a
27. r modify An executable version of this software is also provided and can be executed from DOS by typing A AD7008 The software prompts the user to provide the necessary information needed by the program Additional information is included in a test file named A readme txt A windows 3 1 executable called WIN7008 is also included U1 DUT7008P FSADJUST c3 c4 c5 0 1pF O 1pF 0 1 0 1pF 5V T 10uF T 0 1pF DGND DGND 45V U2 74HC74 5 LLOAD TEST U2 LWR LATCH Figure 36 C36DRPF 10k P1 10PB45 RZ1 2 3 4 5 6 7 8 9 10 50 RESET 52 OPTIONAL 4 7k 6PB 5 RZ2 LATCH 2 RESET 4 LOAD WR 6 INPUTS OUTPUTS Name Description P1 36 pin edge connector to connect to parallel port of PC CLOCK CMOS input for clock R6 provides termination FSEL CMOS input to select between Freq 0 and Freq 1 Low selects Freq 0 SDATA CMOS input for serial input pin SCLK CMOS input for clocking in SDATA lour Analog output IourN Complementary analog output VREF Test point for Vggr pin P2 5 V and ground power connection External sleep command input 16 OUTLINE DIMENSIONS Dimensions shown in inches and mm 44 Pin PLCC P 44A 0 180 4 57 0 165 4 19 0 048 1 21 0 056 1 42 0 042 1 07 0 042 1 07 gt Seo 0 048 1 21 _ EN 8 043 1 07 PIN 1 Y 0 050 IDENTIFIER 1 27 0 63 1
28. s otherwise noted 7008 20 AD7008JP50 Parameter Min Typ Max Min Typ Max Units Test Conditions Comments ty 50 20 ns CLOCK Period ty 20 8 ns CLOCK High Duration t3 20 8 ns CLOCK Low Duration t4 5 5 ns CLOCK to Control Setup Time t5 3 3 ns CLOCK to Control Hold Time te 4t 4t ns LOAD Period ty 2t 2t ns LOAD High Duration tg 5 5 ns LOAD High to TCO TC3 Setup Time to 5 5 ns LOAD High to TCO TC3 Hold Time tio 10 10 ns WR Falling to CS Low Setup Time tu 10 10 ns WR Falling to CS Low Hold Time 112 20 20 ns Minimum WR Low Duration 10 10 ns Minimum WR High Duration ti4 3 3 ns WR to D0 D15 Setup Time ts 3 3 ns WR to D0 D15 Hold Time tie 20 20 ns SCLK Period 07 8 8 ns SCLK High Duration tig 8 8 ns SCLK Low Duration tio 10 10 ns SCLK Rising to SDATA Setup Time too 10 10 ns SCLK Rising to SDATA Hold Time NOTE May be reduced to It if LOAD is synchronized to CLOCK and Setup t4 and Hold t5 Times for LOAD to CLOCK are observed CLOCK FSEL LOAD TC3 TCO Figure 1 Clock Synchronization Timing LOAD ty Figure 2 Register Transfer Timing REV B Figure 3 Parallel Port Timing SCLK SDATA tia I tis Figure 4 Serial Port Timing AD7008 ABSOLUTE MAXIMUM RATINGS 4 32 BIT PARALLEL ASSEMBLY REGISTER gt T4 25 C unless otherwise noted MSB LSB 0 3 Vto 7 V D15 D0 A WORD AGND to DGND 0 3 V to 0
29. st DMDXX DATA BITS DMAXX ADDRESS BITS 74HC138 dm dds_para r4 r4 0xB8520000 Now load low word dm dds_para r4 r4 0x80000000 Transfer data from the parallel assembly register to Freq0 dm dds_cont r4 Figure 12 Parallel Interface to a 16 or 32 Bit DSP or Microprocessor Local Oscillator The AD7008 is well suited for applications such as local oscilla tors used in super heterodyne receivers Although the AD7008 can be used in a variety of receiver designs one simple local os AM OUTPUT mus 9 PLL INPUT ANTENNA FM OUTPUT MIDPOINT BIAS GENERATOR RECEIVED SIGNAL STRENGTH INDICATOR Figure 13 AD7008 and AD607 Receiver Circuit 40 REV B AD7008 cillator application is with the AD607 Monoceiver tm This unique two chip combination provides a complete receiver sub system with digital frequency control RSSI and demodulated outputs for AM FM and complex I Q SSB or QAM See Figure 13 Direct Digital Modulator In addition to the basic DDS function provided by the AD7008 the device also offers several modulation capabilities useful in a wide variety of application The simplest modulation scheme is frequency shift keying or FSK In this application each of the two frequency registers is loaded with a different value one rep resenting the space frequency and the other the mark frequency The digital data stream is fed to the FSELECT pin c
30. y in the event that the microprocessor clock is synchro nous with the DDS clock A power down pin allows external control of a power down mode also accessible through the microprocessor interface The AD7008 is available in 44 pin PLCC PRODUCT HIGHLIGHT 1 Low Power 2 DSP uP Interface 3 Completely Integrated FUNCTIONAL BLOCK DIAGRAM AA GND CLOCK FSELECT 32 BIT PARALLEL REGISTER MPU INTERFACE REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices TCO TC3 LOAD TEST FS ADJUST LX FULLSCALE ADJUST 1 C IOUT oor 10 BIT DAC gt i T C IOUT IQMOD 19 10 AD7008 RESET SLEEP Analog Devices Inc 1995 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD7008 SPECIFICATIONS IOUT and IOUT unless otherwise noted Vay Vpp z 45V t 596 Th 10 Tax Rser 390 Rioap 1 for AD7008AP20 AD7008JP50 Test Conditions Parameter Min Typ Max Min Typ Max Units Comments SIGNAL DAC SPECIFICATIONS Resolution 10 10 Bits Update Rate fmax 20 50 MSPS IOUT Full Scale 20 20 mA

ANALOG DEVICES AD7008 handbook

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