ANALOG DEVICES 4-/6-Channel Digital Potentiometers AD5204/AD5206 handbook
Contents
1. Figure 8 Bandwidth vs Code 10K Version FREQUENCY Hz 0 Se DATA 804 m DATA 404 o 10kQ E DATA 204 Lu DATA 10 d 2 Voo 27V 24 H o ss a s a Va 100mV rms s DATA 08 Ba 30 u DATA 804 al 2 Ta 25 C 50kQ Z DATA 04y lt 36 E Q27V 100kO DATA 024 o m RETT DATA 014 E Vpp 27V Va Vss 27V 54 Va 100mV rms KITO Ta 25 C 60 1k 10k 100k 1M 1k 10k 100k 1M Figure 6 3 dB Bandwidth vs Terminal Resistance FREQUENCY Hz 2 7 V Single Supply Operation Figure 9 Bandwidth vs Code 50K Version FREQUENCY Hz REV 0 AD5204 AD5206 0 2 DATA 804 DATA 404 12 Nm DATA 204 DATA 104 24 S DATA 084 30 z z DATA 04 amp 36 DATA 024 42 DATA 01g 48 Vpp 27V Va Vgs A 54 F v 100mV rms Ty 25 C 60 1k 10k OP42 100k 1M FREQUENCY Hz Figure 10 Bandwidth vs Code 100K Version Yop Vss SINGLE SUPPLY DUAL SUPPLY Vss OV TRIP POINT V 1 0 2 0 3 0 4 0 5 0 6 0 SUPPLY VOLTAGE Vpp Volts Figure 11 Digital Input Trip Point vs Supply Voltage 100 Iss AT Vpp Vss 2 7V TA 25 C2. 10 Ipp AT Vpp Vss 5 5V 0V Ipp AT Vpp Vgg 2 7V 0 1 SUPPLY CURRENT mA 0 01 0 001 0 1 2 Ipp AT Vpp Vss 2 7V 0V 3 4 5 6 INCREMENTAL INPUT LOGIC VOLTAGE Volts Figure 12 Supply Current vs Input Logic Voltage REV 0 8 TA 25 C 7 6 Ion Vpp Vss 5 5V 0V DATA 55H G JS t Iss Vpp Vss 2 7V DATA 55H z S 4 S lbp Vpp Vss 5 5V 0V DATA FFH 3 H ds Iss Vpp Vss 2 7V DATA FFH E 2 2 lbp Vpp Vss 2 7V 0V DATA FFH hor DIEI NET lbp Vpp Vss 2 7V 0V DATA 55H 1 0 10k 100k 1M 10M FREQUENCY Hz Figure 13 Supply Current vs Clock Frequency PSRR dB 10 100 1k 10k 100k FREQUENCY Hz Figure 14 Power Supply Rejection vs Frequency 1 0 Vpp 2 7V Vss 2 7V 1 Ta 425 C H Rap 10kO 2 W o O 0 01 2 NONINVERTING TEST CIRCUIT a ebe F 0 001 INVERTING TEST CIRCUIT 0 0001 10 100 1k 10k 100k FREQUENCY Hz Figure 15 Total Harmonic Distortion Plus Noise vs Frequency AD5204 AD5206 OPERATION The AD5204 AD5206 provides a four six channel 256 position digitally controlled variable resist
3. 2 23 WA Wiper RDAC 4 addr 011 22 A4 A Terminal RDAC 4 24 B4 B Terminal RDAC 4 23 W4 Wiper RDAC 4 addr 011 24 B4 B Terminal RDAC 4 REV 0 CH AD5204 AD5206 Typical Performance Characteristics 120 110 Vpp Vss 2 7V 0V 100 G m i 0 10kQ u 90 9 Z 2 Vpp 2 7V 80 3 Ves 2 7V o a AL Va 100mV rms o N DATA 804 RE v I Vpp Vss 5 5V 0V i A P 60 Vpp Vss 2 7V A S 100kQ S z OP42 50 40 po EAT 30 3 0 2 0 10 0 10 20 30 40 50 60 1k 10k 100k 1M COMMON MODE V FREQUENCY Hz Figure 4 Incremental Wiper ON Resistance vs Voltage Figure 7 3 dB Bandwidth vs Terminal Resistance 2 7 V Dual Supply Operation 5 99 0 BS E DATA 804 6 01 ud DATA 40 6 02 b DATA 204 10kQ DATA 10H 6 03 24 E Vpp 27V 50kQ 8 DATA 08 1 7904 H Vss 27V 1 20 MRRRE z Va 100mV rms z amp 6 05 DATA 80 Ler G 36 een pau TA 25 C DATA 024 6 06 F ov m DATA 01y 6 07 48 Vpp 2 7V Va OP42 Vss 2 7V 6 08 Vg 0V 54 VA 100mV rms OP42 Ta 25 C 6 09 60 100 1k 10k 100k 1k 10k 100k 1M FREQUENCY Hz Figure 5 Gain Flatness vs Frequency
4. 10 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5206BR10 10 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5206BRU10 10 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 AD5206BN50 50 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5206BR50 50 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5206BRU50 50 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 AD5206BN100 100 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5206BR100 100 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5206BRU100 100 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 The AD5204 AD5206 contains 5 925 transistors Die size 92 mil x 114 mil 10 488 sq mil REV 0 AD5204 AD5206 AD5204 PIN CONFIGURATION AD5206 PIN CONFIGURATION AD5204 AD5206 NOT TO SCALE NOT TO SCALE NC NO CONNECT AD5204 PIN FUNCTION DESCRIPTIONS AD5206 PIN FUNCTION DESCRIPTIONS Pin Pin No Name Description No Name Description 1 2 1 A6 A Terminal RDAC 6 12 NC Not Connected 2 W6 Wiper RDAC 6 addr 101 3 GND Ground 3 B6 B Terminal RDAC 6 4 CS Chip Select Input Active Low When CS 4 GND Ground returns high data in the serial input register 5 GS Chip Select Input Active Low When CS is decoded based on the address bits and returns high data in the serial input register E loaded into the target RDAC latch is decoded based on the address bits and 5 PR Active low
5. preset to midscale sets RDAC loaded into the target RDAC latch registers to 80H 6 Non Positive power supply specified for 6 Vpp Positive power supply specified for operation at both 3 V or 5 V Sum of operation at both 3 V or 5 V Sum of Non Vgs 5 5 V kio FE Vas S9 Vs 7 SDI Serial Data Input MSB First 7 SHDN Active low input Terminal A open circuit 8 CLK Serial Clock Input positive edge triggered Shutdown controls Variable Resistors 1 through 4 9 Vss Negative Power Supply specified for 8 SDI Serial Data Input MSB First Spesation ar hont OY cso Ns Suet Vool Vss 5 5 V 9 CLK Serial Clock Input positive edge triggered 10 B5 B Terminal RDAC 5 10 SDO Serial Data Output Open Drain transistor 11 W5 Wiper RDAC 5 addr 100 im Meee FE ae SECH 12 A5 A Terminal RDAC 5 egative Power Supply specified for EECH at both OV d ES V Sum of T p B Terminal Eo Vppl Vss 5 5 V 14 W3 Wiper RDAC 3 addr 010 13 B3 B Terminal RDAC 3 15 A3 A Terminal RDAC 3 14 W3 Wiper RDAC 3 addr 010 16 Bl B Terminal RDAC 1 15 A3 A Terminal RDAC 3 17 Wi Wiper RDAC 1 addr 000 16 Bl B Terminal RDAC 1 18 Al A Terminal RDAC 1 17 Wl Wiper RDAC 1 addr 000 19 A2 A Terminal RDAC 2 18 Al A Terminal RDAC 1 20 W2 Wiper RDAC 2 addr 001 19 A2 A Terminal RDAC 2 21 B2 B Terminal RDAC 2 20 W2 Wiper RDAC 2 addr 001 22 A4 A Terminal RDAC 4 21 B2 B Terminal RDAC
6. 2 AD8403 products One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 AD5204 AD5206 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vpp z 45V x 10 or 3V 10 Nee 0 V Va TVpp Vp 0 V 40 C lt Ta lt 85 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL R DNL Ryg Va No Connect 1 1 4 1 LSB Resistor Nonlinearity Error R INL Bop Va No Connect 2 1 2 2 LSB Nominal Resistor Tolerance ARag Ta 25 C 30 30 Resistance Temperature Coefficient ARap AT Vas Vpp Wiper No Connect 700 ppm C Nominal Resistance Match AR Rag CHI to 2 3 4 or 5 6 Vag Vpp 0 25 1 5 Wiper Resistance Ry Iw 1 V R Vpp 5 V 50 100 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 1 4 1 LSB Integral Nonlinearity INL 2 t1 2 2 LSB Voltage Divider Temperature Coefficient AVyw AT Code 404 15 ppm C Full Scale Error Noten Code 7Fy 2 1 0 LSB Zero Scale Error VwzsE Code 004 0 1 2 LSB RESISTOR TERMINALS Voltage Range Va Vp Vw Vss Vpp V Capacitance Ax Bx Ca Cg f 1 MHz Measured to GND Code 404 45 pF Capacitance Wx Cw f 1 MHz Measured to GND Code 40g 60 pF
7. Shutdown Current IA sp 0 01 5 pA Common Mode Leakage Icm Va Vg Vw 0 Vpp 2 7 V Vss 2 5 V 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Vm Vpp 5 V 3 V 2 4 2 1 V Input Logic Low Vir Vpp 5 V 3 V 0 8 0 6 V Output Logic High Vou Rpuri vp 1 KQ to 5 V 4 9 V Output Logic Low Vor Lou 1 6 mA Viogic 5 V 0 4 V Input Current In Vin 0 V or 5 V 1 uA Input Capacitance Cr 5 pF POWER SUPPLIES Power Single Supply Range Vpp Range Vss 0 V 2 7 5 5 V Power Dual Supply Range Vppiss Range 32 3 32 7 V Positive Supply Current Ipp Vin 5 V or Vy 0 V 12 60 uA Negative Supply Current Iss Vss 2 5 V Vpp 42 7 V 12 60 uA Power Dissipation Ppiss Vin 5 V or Vi 0 V 0 3 mW Power Supply Sensitivity PSS AVpp 5 V t 10 0 0002 0 005 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW 10K Ras 10 kQ 721 kHz BW 50K Ras 50 kQ 137 kHz BW 100K Ras 100 kQ 69 kHz Total Harmonic Distortion THDw Va 1 414 Vrms Vg 0 V dc f 1 kHz 0 004 Vw Settling Time 10K 50K 100K ts Va 5 V Vg 0 V 1 LSB Error Band 2 9 18 us Resistor Noise Voltage CH WB Ben 5 kQ f 1 kHz PR 0 9 nV AHz INTERFACE TIMING CHARACTERISTICS Applies to All Parts Input Clock Pulsewidth tcH tcL Clock Level High or Low 20 ns Data Setup Time tps 5 ns Data Hold Time toy 5 ns CLK to SDO Propagation Delay tPD Ry 2 kQ Cy lt 20 pF 1 150 ns CS Setup Time tcss 15 ns CS High Pulsewidth tcsw 40 ns Reset Pulsewidth tns 90 ns CLK Fall to CS Fall Setup
8. ail AD5204 AD5206 AD5204 AD5206 RDAC1 4 RDAC2 4 RDAC 4 6 f Figure 18 Equivalent Input Control Logic The target RDAC latch is loaded with the last eight bits of the serial data word completing one DAC update Four separate 8 bit data words must be clocked in to change all four VR settings Figure 19 Detail SDO Output Schematic of the AD5204 All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 20 Applies to digital pins CS SDI SDO PR SHDN CLK 340kOQ Figure 20 ESD Protection of Digital Pins A B W Vss Figure 21 ESD Protection of Resistor Terminals V Von 1LSB V 256 Figure 22 Potentiometer Divider Nonlinearity Error Test Circuit INL DNL NO CONNECT Figure 23 Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL 10 ly iV RNowNAL V Vpp Vwe Vwi lw RAwll Rgw Ry a lw WHERE Vun Vms WHEN ly 0 AND Vw Vms WHEN ly 1 R V Vpp 10 Aye PSRR dB 20 LOG AVpp AVus PSS S 2 AVpp Figure 25 Power Supply Sensitivity Test Circuit PSS PSRR OFFSET GND OFFSET BIAS Y Figure 27 Noninverting Programmable Gain Test Circuit Figure 28 Gain vs Frequency Test Circuit Re DAN DUT SW IST ae CODE Ou Figure 29 Incremental ON Resistance Test Circuit REV 0 REV 0 OUTLINE DIMENSIONS Dim
9. cess lot dependent having a 30 variation The change in Bo with temperature has a 700 ppm C temperature coefficient PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal For example connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than 5 V Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 position resolution of the potentiometer divider The general equation defining the output voltage with respect to ground for any given input voltage applied to termi nals AB is Vy Dx Dx 256 x Han Vg 3 Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature Here the output voltage is dependent on the ratio of the internal resistors not the absolute value therefore the drift improves to 15 ppm C AD5204 ONLY AD5204 ONLY GND PR AD5204 ONLY Figure 17 Block Diagram DIGITAL INTERFACING The AD5204 AD5206 contain a standard three wire serial input control interface The three inputs are clock CLK CS and serial data input SDI The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families w
10. ensions shown in inches and mm 24 Lead Narrow Body PDIP N 24 1 275 32 30 P 1 125 28 60 Ge 24 130 280 7 11 ei 12 0 240 6 10 k 0 325 8 25 PIN 1 0 300 Ge 0 060 1 52 e 0 015 0 38 0 195 4 95 max Al UHHUHHUDH UD 0 150 0 115 2 93 0 200 5 05 TLLA f oo 0 125 3 18 le si be 0 015 0 381 0 022 0 558 0 100 0 070 1 77 SEATING 0 008 0 204 0 014 0 386 se 0 045 1 15 24 Lead SOIC R 24 SOL 24 0 6141 15 60 0 5985 15 20 24 13 0 2992 7 60 0 2914 7 40 0 4193 10 65 S 12 0 3937 10 00 PIN 1 0 1043 2 65 0 0291 0 74 0 0926 2 35 0 0098 0 25 49 0 0098 0 25 ARTE a wi je elke 8 el je 0 0118 0 30 0 0500 0 0192 0 49 SEATING 0 0 0500 1 27 7010 10 1 27 0 0138 0 35 PLANE 0 0125 0 32 en 0 0040 0 10 WEP 0 0138 0 35 0 0091 0 23 0 0157 0 40 24 Lead Thin Shrink SO Package TSSOP RU 24 0 311 7 90 l 0 303 7 70 0 177 4 50 0 169 4 30 0 256 6 50 0 246 6 25 0 006 0 15 0 0433 1 10 0 002 0 05 MAX M a gt je gt e S gt je SEATING 0 0256 0 65 ene 0 0079 0 20 0 0 028 0 70 PLANE 0 19 5 0035 0 090 0 090 0 020 0 50 11 AD5204 AD5206 C3677 8 9 99 PRINTED IN U S A
11. le II D DEC Rws 2 Output State 255 10006 Full Scale 128 5045 Midscale PR 0 Condition 1 84 1 LSB 0 45 Zero Scale Wiper Contact Resistance Note that in the zero scale condition a finite wiper resistance of 45 Q is present Care should be taken to limit the current flow between W and B in this state to a maximum value of 20 mA to avoid degradation or possible destruction of the internal switch contact Like the mechanical potentiometer the RDAC replaces it is totally symmetrical The resistance between the Wiper W and Terminal A produces a digitally controlled resistance Rwa When these terminals are used the B terminal should be tied to the wiper Setting the resistance value for Rwa starts at a maxi mum value of resistance and decreases as the data loaded in the latch is increased in value The general transfer equation for this operation is Rwa Dx 256 Dx 256 x Rg4 Ry 2 where Dx is the data contained in the 8 bit RDACXx latch and Rpa is the nominal end to end resistance For example when Va 0 V and B terminal is tied to the Wiper W the following output resistance values will be set for the following RDAC latch codes Table III D DEC Rwa O Output State 255 84 FullScale 128 5045 Midscale PR 0 Condition 1 10006 1 LSB 0 10045 Zero Scale REV 0 AD5204 AD5206 The typical distribution of Rg4 from channel to channel matches within 1 However device to device matching is pro
12. mat provided in Table I if two AD5204 four channel RDACS are daisy chained During shutdown SHDN the SDO output pin is forced to the off logic high state to disable power dissipation in the pull up resistor See Figure 19 for equivalent SDO output circuit schematic Table IV Input Logic Control Truth Table CLK CS PR SHDN Register Activity L L H JH No SR effect enables SDO pin P L H JH Shift one bit in from the SDI pin The eleventh previously entered bit is shifted out of the SDO pin Load SR data into RDAC latch based on A2 A1 A0 decode Table V ps wi D T X H H IH No Operation X X IL H Sets all RDAC latches to midscale wiper centered and SDO latch cleared X H P H Latches all RDAC latches to 80y X H IH JIL Open circuits all Resistor A termi nals connects W to B turns off SDO output transistor NOTE P positive edge X don t care SR shift register Table V Address Decode Table A2 A1 A0 Latch Decoded 0 0 0 RDACZI 0 0 1 RDAC 2 0 1 0 RDAC 3 0 1 1 RDAC 4 1 0 0 RDAC 5 AD5206 Only 1 0 1 RDAC 6 AD5206 Only The data setup and data hold times in the specification table determine the data valid time requirements The last 11 bits of the data word entered into the serial register are held when CS returns high At the same time CS goes high it gates the address decoder enabling one of four or six positive edge triggered RDAC latches see Figure 18 det
13. n discharge without detection Although the AD5204 AD5206 features proprietary ESD protection circuitry permanent dam age may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING spe aac ESD SENSITIVE DEVICE REV 0 3 AD5204 AD5206 1 soi Lelalale jos Jos ios jos oz jo be 0 1 0 1 RDAC LATCH LOAD cs al 0 Figure 1 Timing Diagram spi DATA IN Ax OR Dx Ax OR Dx 0 ips toH 1 para S 0 CLK tpp_max Figure 2 Detail Timing Diagram Vout ts M 1 LSB ERROR BAND 1 LSB Figure 3 AD5204 Preset Timing Diagram ORDERING GUIDE Model KO Temperature Range Package Descriptions Package Options AD5204BN10 10 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5204BR10 10 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5204BRU10 10 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 AD5204BN50 50 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5204BR50 50 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5204BRU50 50 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 AD5204BN100 100 40 C to 85 C 24 Lead Narrow Body PDIP N 24 AD5204BR100 100 40 C to 85 C 24 Lead Wide Body SOIC R 24 SOL 24 AD5204BRU100 100 40 C to 85 C 24 Lead Thin Shrink SO Package TSSOP RU 24 AD5206BN10
14. nt of 700 ppm C Each VR has its own VR latch which holds its programmed resistance value These VR latches are updated from an internal serial to parallel shift register that is loaded from a standard 3 wire serial input digital interface Eleven data bits make up the data word clocked into the serial input register The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data word when the CS strobe is returned to logic high A serial data output pin at the opposite end of the serial register AD5204 only allows simple daisy chaining in multiple VR applications without additional external decoding logic REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAMS An optional reset PR pin forces all the AD5204 wipers to the midscale position by loading 80g into the VR latch The AD5204 AD5206 is available in both surface mount SOL 24 TSSOP 24 and the 24 lead plastic DIP package All parts are guaranteed to operate over the extended industrial temperature range of 40 C to 85 C For additional single dual and quad channel devices see the AD8400 AD840
15. or VR device Changing the programmed VR settings is accomplished by clocking in a 11 bit serial data word into the SDI Serial Data Input pin The format of this data word is three address bits MSB first fol lowed by eight data bits MSB first Table I provides the serial register data word format Table I Serial Data Word Format ADDR DATA B10 B9 B8 B7 B6 BS B4 B3 B2 B1 BO A2 Al AO D7 D6 D5 D4 D3 D2 DI DO MSB LSB MSB LSB 210 28 27 29 See Table IV for the AD5204 AD5206 address assignments to decode the location of VR latch receiving the serial register data in Bits B7 through BO VR outputs can be changed one at a time in random sequence The AD5204 presets to a midscale by asserting the PR pin simplifying fault condition recovery at power up Both parts have an internal power ON preset that places the wiper in a preset midscale condition at power ON In addition the AD5204 contains a power shutdown SHDN pin which places the RDAC in a zero power consumption state where Terminals Ax are open circuited and the wiper Wx is connected to Bx resulting in only leakage currents being con sumed in the VR structure In shutdown mode the VR latch settings are maintained so that returning to operational mode from power shutdown the VR settings return to their previous resistance values Figure 16 AD5204 AD5206 Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of
16. ork well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means Figure 17 shows more detail of the internal digital circuitry When CS is taken active low the clock loads data into the serial register on each positive clock edge see Table IV When using a positive Vpp and negative Vss supply voltage the logic levels are still referenced to digital ground GND The serial data output SDO pin contains an open drain n channel FET This output requires a pull up resistor in order to REV 0 9 transfer data to the next package s SDI pin The pull up resistor termination voltage may be larger than the Vpp supply of the AD5204 SDO output device e g the AD5204 could operate at Vpp 3 3 V and the pull up for interface to the next device could be set at 5 V This allows for daisy chaining several RDACS from a single processor serial data line Clock period needs to be increased when using a pull up resistor to the SDI pin of the following device in the series Capacitive loading at the daisy chain node SDO SDI between devices must be ac counted for to successfully transfer data When daisy chaining is used the CS should be kept low until all the bits of every pack age are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding loca tion This would require 22 bits of address and data complying to the word for
17. sured using both Vpp 3 V or 5 V lI Propagation delay depends on value of V pp Ry and Cy See Operation section Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS T4 25 C unless otherwise noted Vpp to GND uds p LP eee 0 38 V 7 V Vss to GND ree ce ee ee 0V 7V Non to Vss Eai aD IE RICE EE 7 V Va Vp Vw tO GND ip i Eee EWE Boe Nee Vpp Ax Bx Ax Wx Bx Wx 66 20 mA Digital Input and Output Voltage to GND 0V 7V Operating Temperature Range 40 C to 85 C Maximum Junction Temperature T MAX 150 C Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C CAUTION Package Power Dissipation Ty max TA 0j4 Thermal Resistance Oja P DIP4N 24 ee xa RA ORT 63 C W SOIC SOLI 24 ANERER ERNEST uer m 70 C W TSSOP 24 a dicta a eue eri GO CR 143 C W Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and ca
18. tcsHo 0 ns CLK Fall to CS Rise Hold Time tcsui 0 ns CS Rise to Clock Rise Setup tcsi 10 ns NOTES Typicals represent average readings at 25 C and Vpp 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi tions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic See Figure 23 test circuit Iw Vpp R for both Vpp 3 V or Vpp 5 V Nam Vpp Wiper Vw No connect INL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter V 4 Vpp and Vg 0 V DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions See Figure 22 test circuit 2 REV 0 AD5204 AD5206 gt Resistor Terminals A B W have no limitations on polarity with respect to each other Guaranteed by design and not subject to production test Measured at the Ax terminals All Ax terminals are open circuited in shutdown mode 5Ppiss is calculated from Ipp x Vpp CMOS logic level inputs result in minimum power dissipation All dynamic characteristics use Vpp 5 V V See timing diagrams for location of measured values All input control voltages are specified with tp tp 2 5 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V Switching characteristics are mea
19. the RDAC between Terminals A and B are available with values of 10 kQ 50 kQ and 100 kQ The last digits of the part number determine the nominal resistance value e g 10 KQ 10 100 kQ 100 The nominal resistance Rap of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The eight bit data word in the RDAC latch is decoded to select one of the 256 possible settings The wiper s first connection starts at the B terminal for data 00g This B terminal connection has a wiper contact resis tance of 45 Q The second connection 10 kQ part is the first tap point located at 84 Q Rg4 nominal resistance 256 Rw 84 Q 45 QJ for data Oly The third connection is the next tap point representing 78 45 123 Q for data 024 Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10006 Q The wiper does not directly connect to the A terminal See Figure 16 for a simplified diagram of the equivalent RDAC circuit The general transfer equation determining the digitally pro grammed output resistance between Wx and Bx is Jus Dx Dx 256 x Rpg Ry 1 where Dx is the data contained in the 8 bit RDACXx latch and Rpa is the nominal end to end resistance For example when Vg 0 V and A terminal is open circuit the following output resistance values will be set for the following RDAC latch codes applies to the 10K potentiometer Tab
20. z amp 18A D 5204 AD 5206f hv ES ANALOG DEVICES 4 6 Channel Digital Potentiometers AD5204 AD5206 FEATURES 256 Position Multiple Independently Programmable Channels AD5204 4 Channel AD5206 6 Channel Potentiometer Replacement 10 kQ 50 kQ 100 kQ 3 Wire SPI Compatible Serial Data Input 2 7 V to 5 5 V Single Supply 2 7 V Dual Supply Operation Power ON Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation Gain Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters Delays Time Constants Line Impedance Matching GENERAL DESCRIPTION The AD5204 AD5206 provides four six channel 256 position digitally controlled Variable Resistor VR devices These de vices perform the same electronic adjustment function as a potentiometer or variable resistor Each channel of the AD5204 AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI compatible serial input register The resis tance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch The variable resistor offers a completely program mable value of resistance between the A terminal and the wiper or the B Terminal and the wiper The fixed A to B terminal resistance of 10 kQ 50 kQ or 100 kQ has a nominal tempera ture coefficie
Download Pdf Manuals
Related Search
ANALOG DEVICES 4 /6 Channel Digital Potentiometers AD5204/AD5206 handbook