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ANALOG DEVICES AD5200/AD5201 handbook

1. 500 T TT 6 CODE FFy 450 0 804 400 6 404 350 12 204 lt 300 m 18 10 1 I H 2 250 z 24 los Vpp Vgg 2 5V 3 084 200 30 loo Vpp Vgg 2 5V 044 150 36 02 Ipp Vpp Vss 5V 0V H 100 2 DR Ipp Y 3V 0V Se pp Von Vss As 0 54 10k 100k 1M 10M ik 10k 100k 1M FREQUENCY Hz FREQUENCY Hz TPC 13 AD5200 10 kQ Supply Current vs Clock Frequency TPC 16 AD5200 10 kQ Gain vs Frequency vs Code 500 ES 6 CODE 554 450 0 400 F 804 40 12 H 204 m 18 10 z 24 H lt ao 084 044 36 024 42 014 48 54 10k 100k 1M 10M 1k 10k 100k 1M FREQUENCY Hz FREQUENCY Hz TPC 14 AD5200 10 kQ Supply Current vs Clock Frequency TPC 17 AD5200 50 kQ Gain vs Frequency vs Code 80 e 6 CODE 804 Va Vpp Vg OV 0 104 PSRR Vpp 5V DC 10 p p AC 6 8 12 A Zu g m 18 1 T 24 g 40 T i z 24 o PSRR Von 3V DC 10 p p AC 1 D o 30 H 36 20 PSRR Vpp 3V DC 10 42 DD 10 p p AC 48 0 54 100 1k 10k 100k 1M 1k 10k 100k 1M FREQUENCY Hz FREQUENCY Hz TPC 15 Power Supply Rejection Ratio vs Frequency TPC 18 AD5201 10 kQ Gain vs Frequency vs Code 8 REV B AD5200 AD5201 GAIN dB D A 1k 10k 100k 1M FREQUENCY Hz TPC 1
2. Table II AD5201 Serial Data Word Format Bar B4 B3 B2 B1 Bo D5 D4 D3 D2 D1 DO MSB LSB 25 2 Six data bits are needed for 33 positions PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminals A and B are available with values of 10 kQ and 50 kQ The final two digits of the part number determine the nominal resistance value e g 10 kQ 10 and 50 kQ 50 The nominal resistance Rag of AD5200 has 256 contact points accessed by the wiper terminal The 8 bit data word in the RDAC latch of AD5200 is decoded to select one of the 256 possible settings In both parts the wiper s first connection starts at the B terminal for data 004 This B terminal connection has a wiper contact resistance of 50 Q as long as valid Vpp Vss is applied regardless of the nominal resistance For a 10 kQ part the second connection of AD5200 is the first tap point with 89 Q Ry Rag 255 Rw 39 Q 50 Q for data 0114 The third connection is the next tap point representing 78 50 128 Q for data 024 Due to its unique internal structure AD5201 has 5 bit 1 resolution but needs a 6 bit data word to achieve the full 33 steps resolution The 6 bit data word in the RDAC latch is decoded to select one of the 33 possible settings Data 34 to 63 will automatically be equal to Position 33 The wiper 004 connection of AD5201 gives 50 Q Similarly for a 10 kQ part t
3. AD5200 AD5201 Tek RYN LJ FE 3500 3000 e g g s 2500 1 OUTPUT 9 ewowy Eich E dl E EE g 2000 x H 1500 Q O 1000 INPUT E 5V DIV lt P amp 500 DI I S G LEGGE b e Gre a pet a SSE SE SELG ME er ee E Se g 0 dE Et ON i zi i sil d 500 M 40 0us A Chi 2 64 Y 0 32 64 96 128 160 192 224 256 gt 0 00000 s CODE Decimal TPC 25 Large Signal Settling Time TPC 28 AD5200 AR yg AT Rheostat Mode Temperature Coefficient 3000 o E 2500 2 2 J 8 2000 a H Vour 1500 20mV DIV Q 1000 w d 3 500 H o o t Pai a 20 0mV iv 18 5400ps 0 4 8 12 16 20 24 28 32 CODE Decimal TPC 26 Digital Feedthrough vs Time TPC 29 AD5201 Potentiometer Mode Temperature Coefficient 4000 3500 o o o 3000 E 40 Oo Qa o I amp 2500 8 30 HI a ty 2000 a 8 F 20 1500 D m E 1000 e 10 w lu E 500 e po 5 10 500 a 32 64 96 128 160 192 224 256 Gar 20 CODE Decimal 0 4 8 12 16 20 2 2 32 CODE Decimal TPC 27 AD5200 AV yyg AT Potentiometer Mode TPC 30 AD5201 AVwg AT Potentiometer Mode Tempco Temperature Coefficient 10 REV B AD5200 AD5201 100 0
4. 2 7V Vgg 2 7V 0 015 lt Vpp 5 5V Vss ON R 0 010 5 S D 9 5 o 1 0 005 z fe D 0 000 5 I N lt s 0 005 Vpp 2 7V Vss OV 0 010 DD SS 0 4 8 12 16 20 24 28 32 CODE Decimal TPC 8 AD5201 10 kQ INL vs Code 10 1 0 4 E a I I o 0 1 z hr 2 0 01 0 001 0 0 1 0 2 0 3 0 4 0 5 0 Vum V TPC 9 Supply Current vs Logic Input Voltage REV B Vu Vss Vin VoD Vpp 5 5V Vpp 2 7V 0 20 40 TEMPERATURE C 60 80 100 TPC 10 Supply Current vs Temperature 20 0 20 40 TEMPERATURE C 60 80 100 TPC 11 Shutdown Current vs Temperature 160 SEE TEST CIRCUIT 13 Ta 25 C 140 120 Vop 2 7V 100 ras Vpp BEN 3 Vsuppcy N TPC 12 Wiper ON Resistance vs V supr y AD5200 AD5201
5. Rag Ry 128 5070 Midscale 1 89 1 LSB 0 50 Zero Scale Wiper Contact Resistance AD5201 Wiper to B Resistance D Rws DEC 0 Output State 32 10050 Full Scale Rag Rw 16 5050 Midscale 1 363 1 LSB 0 50 Zero Scale Wiper Contact Resistance Note that in the zero scale condition a finite wiper resistance of 50 Q is present Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switch contact Like the mechanical potentiometer the RDAC replaces it is totally symmetrical The resistance between the wiper W and Terminal A also produces a digitally controlled resistance Rwa When these terminals are used the B terminal should be tied to the wiper Setting the resistance value for Rw Starts at a maxi mum value of resistance and decreases as the data loaded in the latch is increased in value The general equation for this operation is 255 D Rwa D a Es 50Q for AD5200 3 32 D Rya D Ras 502 for AD5201 4 Similarly D in AD5200 is between 0 to 255 whereas D in AD5201 is between 0 to 32 For Rag 10 kQ and B terminal is opened or tied to the wiper W the following output resistance between W and A will be set for the following RDAC latch codes REV B AD5200 AD5201 AD5200 Wiper to A Resistance D Rwa DEC Q Output State 255 50 Full Scale Rw
6. THEORETICAL Imax MA 0 32 64 96 128 160 192 224 256 CODE Decimal TPC 31 AD5200 I ax vs Code 100 0 lt E I 10 0 x a S Rap 10k0 Q AB m g Q 1 0 I E Rag 50kQ 0 1 0 4 8 12 16 20 24 28 32 CODE Decimal TPC 32 AD5201 Imax vs Code OPERATION The AD5200 AD5201 provide 255 and 33 positions digitally controlled variable resistor VR devices Changing the programmed VR settings is accomplished by clocking in an 8 bit serial data word for AD5200 and a 6 bit serial data word for AD5201 into the SDI Serial Data Input pins Table I provides the serial register data word format The AD5200 AD5201 are preset to a midscale internally during power on condition In addition the AD5200 AD5201 contain power shutdown SHDN pins that place the RDAC in a zero power consump tion state where the immediate switches next to Terminals A and B are open circuited Meanwhile the wiper W is connected to B terminal resulting in only leakage current consumption in the VR structure During shutdown the VR latch contents are maintained when the RDAC is inactive When the part is returned from shutdown the stored VR setting will be applied to the RDAC REV B Table I AD5200 Serial Data Word Format B7 B6 B5 B4 B3 B2 B1 Bo D7 D6 D5 D4 D3 D2 D1 DO MSB LSB
7. 80 y 45 pF Capacitance W Cw f 1 MHz Measured to GND Code 80 y 60 pF Shutdown Supply Current 7 Ipp sp Vpp 5 5 V 0 01 5 uA Common Mode Leakage Tem Va Vz Vpp 2 1 nA DIGITALINPUTS AND OUTPUTS Input Logic High Vin 2 4 V Input Logic Low Vg 0 8 V Input Logic High Vin Vpp 3 V Vss 0 V 2 1 V Input Logic Low Vit Vpp 3 V Vss 0 V 0 6 V Input Current LL Vn 0Vor5 V 1 uA Input Capacitance 6 Cy 5 pF POWER SUPPLIES Logic Supply Viocic 2 7 5 5 V Power Single Supply Range VDD RANGE Vss 0 V 0 3 5 5 NA Power Dual Supply Range Vppiss RANGE 2 3 a IV Positive Supply Current Ipp Vig 5 Vor Vy 0 V 15 40 uA Negative Supply Current Iss Vss 5 V 15 40 uA Power Dissipation Poss Vi 5 Vor Vi 0 V Vpp 5 V Vgg 0 V 0 2 mW Power Supply Sensitivity PSS AVpp 5 V 10 Code Midscale 0 01 0 001 0 01 DYNAMIC CHARACTERISTICS ni Bandwidth 3 dB BW_10 KQ Rag 10 kQ Code 80 y 600 kHz BW 50 kQ Rap 50 kQ Code 80 y 100 kHz Total Harmonic Distortion THD y Va 1 V rms Vp 0 V f I kHz Rag 10 kQ 0 003 Vy Settling Time 10 kQ 50 kQ ts Va 5 V Vg 0 V 1 LSB Error Band 2 9 us Resistor Noise Voltage Density EN WB Rws 5 kQ RS 0 9 nVVHz NOTES Typicals represent average readings at 25 C and Vpp 5 V Vss 0 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi tions R DNL measures the r
8. lt 50 ppm C AD5203 4 5 5 V 3 Wire 10 100 64 5 uA PDIP SOL 24 Full AC specs nA TSSOP 24 Shutdown Current AD5233 4 3 V 5 5 V 3 Wire 10 50 100 64 10 uA TSSOP 16 Nonvolatile Memory Direct Program I D 6 dB Settability AD5204 4 3 V 5 5 V 3 Wire 10 50 100 256 5 uA PDIP SOL 24 Full AC Specs Dual Supply TSSOP 24 Pwr On Reset AD8403 4 5 5 V 3 Wire 1 10 50 100 256 5 uA PDIP SOL 24 Full AC Specs nA TSSOP 24 Shutdown Current AD5206 6 3 V 5 5 V 3 Wire 10 50 100 256 5 uA PDIP SOL 24 Full AC Specs Dual Supply TSSOP 24 Pwr On Reset Future product consult factory for latest status REV B 15 AD5200 AD5201 OUTLINE DIMENSIONS Dimensions shown in inches and mm 10 Lead pSOIC RM 10 0 124 3 15 er Gab I 0 124 3 15 0 199 5 05 0 112 2 84 0 187 4 75 Nu PIN 1 0 0197 0 50 BSC 0 122 3 10 0 120 3 05 KOLE 79 agesat 0 038 0 97 0 043 1 09 0 030 0 76 tp fo 037 0 94 y 0 006 d 15 0 016 o 41 SEATING lt V B 0 002 0 05 0 006 0 15 z o ve a gt 0051 0 53 Revision History Location Page Data Sheet changed from REV A to REV B Eder ORDERING GUIDE pa ep ee A ee a letta 5 02 01 Data Sheet changed from REV O to REV A Edits t ORDERING GUIDE s rasa A ke be Se SN ET Te ed EE a hele BES 5 Edits to ABSOLUTE MAXIMUM RATINGS vvvvav rv v var ne nee ne eee nee ee ene een E 5 TPGs
9. or 3 V 10 Vss 0V V Vpp V 0 V 40 C lt T lt 85 C ELECTRICAL CHARACTERISTICS unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit INTERFACE TIMING CHARACTERISTICS Applies to All Parts Notes 2 3 Input Clock Pulsewidth tc tar Clock Level High or Low 20 ns Data Setup Time tps 5 ns Data Hold Time toy 5 ns CS Setup Time tess 15 ns CS High Pulsewidth tcsw 40 ns CLK Fall to CS Fall Hold Time tesmo 0 ns CLK Fall to CS Rise Hold Time tes 0 ns CS Rise to Clock Rise Setup tcs 10 ns NOTES Typicals represent average readings at 25 C and Vpp 5 V Vss 0 V Guaranteed by design and not subject to production test 3See timing diagram for location of measured values All input control voltages are specified with tr tp 2 ns 10 to 90 of 3 V and timed from a voltage level of 1 5 V Switching characteristics are measured using Vy ocic 5 V Specifications subject to change without notice 1 cae te DO EE ts DAC REGISTER 0 1 VOUT 0 Figure 1a AD5200 Timing Diagram 1 O E E E Ce 0 1 0 1 T5 DAC REGISTER A 0 1LSB Figure 1c Detail Timing Diagram 4 REV B AD5200 AD5201 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted PIN FUNCTION DESCRIPTIONS Pin Name Description Vpp to Vss DAA IAS A Se RRR RR 7V VEI t GND EE 0 3 7V 1 B B Terminal KE RR REENEN 0V 7V 2 Vss Ne
10. voltage across E any two of the A B and W terminals at a given resistance Please refer to TPC 31 and TPC 32 for detail PIN CONFIGURATION TOP VIEW Not to Scale ORDERING GUIDE Temperature Package Package Full Branding Model RES kQ Range Description Option Reel Qty Information AD5200BRM10 REEL7 256 10 40 C 85 C USOIC 10 RM 10 5000 DLA AD5200BRM50 REEL7 256 50 40 C 85 C uSOIC 10 RM 10 5000 DLB AD5201BRM10 REEL7 33 10 40 C 85 C uSOIC 10 RM 10 5000 DMA AD5201BRM50 REEL7 33 50 40 C 85 C uSOIC 10 RM 10 5000 DMB CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD5200 AD5201 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING TAa ESD SENSITIVE DEVICE REV B 5 AD5200 AD5201 Typical Performance Characteristics 0 20 Vpp 2 7V Ven ON 0 15 RDNL LSB o o E Von 2 7V Vss lt 2 7V Vpp 5 5V Vss ON 0 20 l I 0 32 64 96 128 160 192 224 256 CODE Decimal TPC 1 AD5200 10 kQ RDNL vs Code 0 03 Vpp 5 5V Vgg OV 0 02 0 01 RDNL L
11. 00 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 6 Bits Differential Nonlinearity gt DNL 0 5 0 01 0 5 LSB Integral Nonlinearity INL 1 0 02 I LSB Voltage Divider Temperature Coefficient AVy AT Code 104 5 ppm C Full Scale Error WwESE Code 20 y 1 2 1 4 0 LSB Zero Scale Error WwzSE Code 00 y 0 1 4 1 2 LSB RESISTORTERMINALS Voltage Range Va ne Vss Von V Capacitance A B CA B f 1 MHz Measured to GND Code 10 y 45 pF Capacitance W Cw f 1 MHz Measured to GND Code 10 y 60 pF Shutdown Supply Current Ipp sp Vpp 5 5 V 0 01 5 uA Common Mode Leakage Tem Va Vz Vpp 2 1 nA DIGITALINPUTS AND OUTPUTS Input Logic High Vin 2 4 V Input Logic Low Vg 0 8 V Input Logic High Vin Vpp 3 V Vss 0 V 2 1 V Input Logic Low Vy Vop 3V Vss 0V 0 6 V Input Current I Vin 0Vor5 V 1 uA Input Capacitance Cy 5 pF POWER SUPPLIES Logic Supply Viocic 2 7 5 5 V Power Single Supply Range Vpp RANGE Vss 0 V 0 3 5 5 V Power Dual Supply Range Vpp ss RANGE 2 3 27 V Positive Supply Current Ipp Vig 5 Vor Vy 0 V 15 40 uA Negative Supply Current Iss Vss 5V 15 40 uA Power Dissipation Pbiss Vin 5 Vor V 0 V Vpp 5 V Vgg 5 V 0 2 mW Power Supply Sensitivity PSS AVpp 5 V 10 0 01 0 001 0 01 DYNAMIC CHARACTERISTICS 710 Bandwidth 3 dB BW 10 KQ Rag 10 kQ Code 10 y 600 kHz BW 50 kQ Rag 50 kQ Code 10 y 100 kHz Total Harmonic Distortion THD y Va 1
12. 128 5030 Midscale 1 10011 1 LSB 0 10050 Zero Scale Rag Rw AD5201 Wiper to A Resistance D Rwa DEC Q Output State 32 50 Full Scale Rw 16 5050 Midscale 1 9738 1 LSB 0 10050 Zero Scale Rag Rw The tolerance of the nominal resistance can be 30 due to process lot dependance If users apply the RDAC in rheostat variable resistance mode they should be aware of such specifi cation of tolerance The change in Rag with temperature has a 500 ppm C temperature coefficient PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper to B and wiper to A to be proportional to the input volt age at A to B Unlike the polarity of Vpp Vss which must be positive volt age across A B W A and W B can be at either polarity If ignoring the effects of the wiper resistance for an approxima tion connecting terminal to 5 V and B terminal to ground produces an output voltage at the wiper which can be any value starting at almost zero to almost full scale with the minor devia tion contributed by the wiper resistance Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 2N 1 and 2N position resolution of the potentiometer divider for AD5200 and AD5201 respectively The general equation defin ing the output voltage with respect to ground for any valid input voltage applied to Terminals A and is D V
13. 3 Land 32 added ME 11 16 REV B C02188 0 8 01 B PRINTED IN U S A
14. 9 AD5201 50 kQ Gain vs Frequency vs Code s I z 4 O ik 10k 100k 1M FREQUENCY Hz TPC 20 AD5200 3 dB Bandwidth 12 6 10k0 0 6 50kQ m 12 Tv z 18 4 O 24 30 Vin 100mV rms 36 Vpp 5V R 1MO 42 a a a El 48 1k 10k 100k 1M FREQUENCY Hz TPC 21 AD5201 3 dB Bandwidth REV B 20mV DIV 12 T TT TT T TT TT SEE TEST CIRCUIT 10 pr CODE 804 a Vop 5V 2 OF TA 25C 10k0 I 6 N H 50kQ 12 q D 18 z qu 3 24 W 30 z 36 S Q 42 48 10 100 1k 10k 100k 1M FREQUENCY Hz TPC 22 Normalized Gain Flatness vs Frequency 12 TITI TITT SEE TEST CIRCUIT 10 6 CODE 104 Vpp 5V Or Ta 25 C 50kQ NORMALIZED GAIN FLATNESS 0 1dB DIV gt 10 100 1k 10k FREQUENCY Hz 100k 1M TPC 23 AD5201 Normalized Gain Flatness vs Frequency Vw E E CS 5V DIV tha I 3 40V Gv 400 400ns TPC 24 One Position Step Change at Half Scale
15. HA D 5200H F ANALOG DEVICES 256 Position and 33 Position Digital Potentiometers AD5200 AD5201 FEATURES AD5200 256 Position AD5201 33 Position 10 kQ 50 kQ 3 Wire SPI Compatible Serial Data Input Single Supply 2 7 V to 5 5 V or Dual Supply 2 7 V for AC or Bipolar Operations Internal Power On Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation Gain Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters Delays Time Constants Line Impedance Matching GENERAL DESCRIPTION The AD5200 and AD5201 are programmable resistor devices with 256 positions and 33 positions respectively that can be digi tally controlled through a 3 wire SPI serial interface The terms programmable resistor variable resistor VR and RDAC are commonly used interchangeably to refer to digital potentiometers These devices perform the same electronic adjustment function as a potentiometer or variable resistor Both AD5200 AD5201 contain a single variable resistor in the compact USOIC 10 package Each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code The code is loaded in the serial input register The resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the VR latch Each variable resistor offers a comp
16. SB o o o 0 01 Vop 2 7V Vgg 2 0 02 0 03 0 4 8 12 16 20 24 28 32 CODE Decimal TPC 2 AD5201 10 kQ RDNL vs Code RINL LSB Vop 2 7V Vgs 2 7V 0 32 64 96 128 160 192 224 256 CODE Decimal TPC 3 AD5200 10 kQ RINL vs Code 0 12 0 10 Vop 5 5V Vss OV 0 08 R Vop 2 7V 0 06 Vag 2 7V I z e 0 04 0 02 Vop 2 7V Vgs OV 0 00 0 02 0 4 8 12 16 20 24 28 32 DNL LSB CODE Decimal TPC 4 AD5201 10 kQ RINL vs Code Vop 2 7V Vss 2 7V 0 30 32 64 96 128 160 192 224 256 CODE Decimal TPC 5 AD5200 10 kQ DNL vs Code 0 020 0 015 0 010 Vpop 5 5V Vss OV J m o 1 0 005 al z A 0 000 0 005 0 010 0 4 8 12 16 20 24 28 32 CODE Decimal TPC 6 AD5201 10 kQ DNL vs Code REV B AD5200 AD5201 0 3 0 2 Vpp 5 5V Vgg OV 0 1 T I 0 0 Zz m E k ra 5 1 01 o z gt 0 2 2 N 0 3 8 Vpp 2 7V Vgg 2 7V 0 4 Vpp 2 7V Vss 0V 0 5 L 1 0 32 64 96 128 160 192 224 256 CODE Decimal TPC 7 AD5200 10 kQ INL vs Code 0 020 i e i Von
17. Vrms Vp 0 V f I kHz Rag 10 kQ 0 003 Vy Settling Time 10 kQ 50 kQ ts Va 5 V Vg 0 V 1 LSB Error Band 2 9 us Resistor Noise Voltage Density EN WB Ryg 5 kQ RS 0 9 nV VHz NOTES Typicals represent average readings at 25 C and Vpp 5 V Vss OV Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi tions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic Iw Vpp R for both Vpp 2 7 V Vss 2 7 V 3 Vag Nr Wiper Vw No connect 4 Six bits are needed for 33 positions even though it is not a 64 position device INL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Va Vpp and Vz 0 V DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions 6 Resistor Terminals A B W have no limitations on polarity with respect to each other 7 Guaranteed by design and not subject to production test Measured at the A terminal A terminal is open circuited in shutdown mode Ppiss is calculated from Ipp X Vpp CMOS logic level inputs result in minimum power dissipation 10 All dynamic characteristics use Vpp 5 V Vss 0 V Specifications subject to change without notice REV B AD5200 AD5201 SPEGIFIGATIONS Din 5V lt 10
18. atch X H H No operation X H IL Open circuit on A terminal and short circuit between W to B terminals NOTE P positive edge X don t care SR shift register All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 4 Applies to digital input pins CS SDI SHDN CLK 3400 LOGIC Ves Figure 4 ESD Protection of Digital Pins Figure 5 ESD Protection of Resistor Terminals 13 AD5200 AD5201 TEST CIRCUITS Figures 6 to 14 define the test conditions used in the product specification table V Vpp 1 LSB V 2N Figure 6 Potentiometer Divider Nonlinearity Error Test Circuit INL DNL NO CONNECT Figure 7 Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL DUT Iw Vpp RNominat Vusz O Rw Visi Vusallw Figure 8 Wiper Resistance Test Circuit V Vpp 10 AVus PSRR dB 20 LOG v AVys AVpp PSS Figure 9 Power Supply Sensitivity Test Circuit PSS PSRR V OFFSET BIAS Figure 10 Inverting Gain Test Circuit 14 OFFSET BIAS v Figure 11 Noninverting Gain Test Circuit DUT Von DUT Vss GND O V ne NC NO CONNECT Figure 14 Common Mode Leakage Current Test Circuit REV B AD5200 AD5201 DIGITAL POTENTIOMETER SELECTION GUIDE Number Resolution Powe
19. dur ing shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown All parts are guaranteed to operate over the extended industrial temperature range of 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 O Analog Devices Inc 2001 AD5200 AD5201 SPEGIFIGATIONS Voo 5 V 10 or 3 V 10 Vss 0 V Va Vpp Vg 0 V AD5200 ELECTRICAL CHARACTERISTICS Apr lt T lt 85 unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTATMODE Resistor Differential Nonlinearity R DNL Bop Va No Connect 1 0 25 1 LSB Resistor Integral Nonlinearity R INL Bop Va No Connect 2 05 2 LSB Nominal Resistor Tolerance 3 ARAB Ta 25 C 30 30 Resistance Temperature Coefficient Rap AT Vaz Vpp Wiper No Connect 500 ppm C Wiper Resistance Ry Vop 5V 50 100 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 1 4 1 LSB Integral Nonlinearity INL 2 1 2 2 LSB Voltage Divider Temperature Coefficient AVy AT Code 80 y 5 ppm C Full Scale Error VWESE Code FF y 1 5 05 0 LSB Zero Scale Error VwzsE Code 00 y 0 0 5 1 5 LSB RESISTORTERMINALS Voltage Range Va B w Vss Von V Capacitance A B CA B f 1 MHz Measured to GND Code
20. elative step change from ideal between successive tap positions Parts are guaranteed monotonic Iw Vpp R for both Vpp 2 7 V Vss 2 7 V 3Vap Vpp Wiper Vw No connect 4INL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter V a Vpp and Vg 0 V DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions Resistor Terminals A B W have no limitations on polarity with respect to each other Guaranteed by design and not subject to productio n test 7Measured at the A terminal A terminal is open circuited in shutdown mode 8Ppyisg is calculated from Ipp X Vpp CMOS logic level inputs result in minimum power dissipation DAD dynamic characteristics use Vpp 5 V Vss 0 Specifications subject to change without notice V REV B AD5201 ELECTRICAL CHARACTERISTICS 40 lt T lt 85 unless otherwise noted AD5200 AD5201 Von 5 V 10 or 3 V 10 Vss 0 V Va Alan Ve O V Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTATMODE Resistor Differential Nonlinearity R DNL Rywg Va No Connect 0 5 0 05 0 5 LSB Resistor Integral Nonlinearity R INL Rep Va No Connect 1 0 1 1 LSB Nominal Resistor Tolerance 3 ARAB Ta 25 C 30 30 Resistance Temperature Coefficient Rag AT Vaz Vpp Wiper No Connect 500 ppm C Wiper Resistance Ry Vop 5V 50 1
21. gative Power Supply specified for opera Va Vp Vy to GND e Vss Vpp tion from 0 V to 2 7 V Imax SE R S ER ORKAR RA R K B RRR URI K 20 mA 3 GND Ground Digital Inputs and Output Voltage to GND G 0 V EN A CS Chip Select Input Active Low When TS Operating Temperature Range 40 C to 85 C returns high data will be loaded into the Maximum Junction Temperature Tj Max 150 C DAC register Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C 3 SPI ae Data Input be Thermal Resistance Dr USOIC 10 200 C W 6 CLK Serial Clock Input positive edge triggered Package Power Dissipation Ty Max T4 ja 7 SHDN Active Low Input Terminal A open circuit NOTES Shutdown controls Variable Resistors of Stresses above those listed under Absolute Maximum Ratings may cause perma RDAC to temporary infinite nent damage to the device This is a stress rating functional operation of the device 8 Vop Positive Power Supply Sum of Vpp Vss atthese or any other conditions above those listed in the operational sections of this lt 5 5V specification is not implied Exposure to absolute maximum rating conditions for S extended periods may affect device reliability 9 W Wiper Terminal Max current is bounded by the maximum current handling of the switches 10 A A Terminal maximum power dissipation of the package and maximum applied
22. he first tap point of AD5201 yields 363 Q for data Oly 675 Q for data 0254 For both AD5200 and AD5201 each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached Figures 2a and 2b show the simplified diagrams of the equivalent RDAC circuits 11 AD5200 AD5201 O B DIGITAL CIRCUITRY OMITTED FOR CLARITY Figure 2a AD5200 Equivalent RDAC Circuit 255 positions can be achieved up to Switch SW AN B DIGITAL CIRCUITRY OMITTED FOR CLARITY Figure 2b AD5201 Equivalent RDAC Circuit Unlike AD5200 33 positions can be achieved all the way to Switch SW 2 The general equation determining the digitally programmed output resistance between W and B is D Bes D 255 Pa 50Q for AD5200 1 Rws D Ru 50 Q for AD5201 2 where D is the decimal equivalent of the data contained in RDAC latch Rap is the nominal end to end resistance Rw is the wiper resistance contributed by the on resistance of the internal switch a 2 Note D in AD5200 is between 0 to 255 for 256 positions On the other hand D in AD5201 is between 0 to 32 so that 33 positions can be achieved due to the slight internal structure difference Figure 2b Again if Rap 10 kQ and A terminal can be opened or tied to W the following output resistance between W to B will be set for the following RDAC latch codes AD5200 Wiper to B Resistance D Ryg DEC 0 Output State 255 10050 Full Scale
23. letely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper The fixed A to B terminal resistance of 10 kQ or 50 kQ REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM AD5200 AD5201 PWR ON PRESET has a nominal temperature coefficient of 500 ppm C The VR has a VR latch that holds its programmed resistance value The VR latch is updated from an SPI compatible serial to parallel shift register that is loaded from a standard 3 wire serial input digital interface Eight data bits for the AD5200 and six data bits for the AD5201 make up the data word that is clocked into the serial input register The internal preset forces the wiper to the midscale position by loading 804 and 104 into AD5200 and AD5201 VR latches respectively The SHDN pin forces the resistor to an end to end open circuit condition on the A terminal and shorts the wiper to the B terminal achieving a microwatt power shutdown state When SHDN is returned to logic high the previous latch setting puts the wiper in the same resistance setting prior to shutdown The digital interface is still active
24. r of VRs Terminal Interface Nominal Number Supply Part per Voltage Data Resistance Of Wiper Current Number Package Range Control kQ Positions Ipp Packages Comments AD5201 1 3 V 5 5 V 3 Wire 10 50 33 60 uA USOIC 10 Full AC Specs Dual Supply Pwr On Reset Low Cost AD5220 1 5 5 V Up Down 10 50 100 128 40 pA PDIP SO 8 uSOIC 8 No Rollover Pwr On Reset AD7376 1 15 V 28 V 3 Wire 10 50 100 1000 128 100 uA PDIP 14 SOL 16 Single 28 V or Dual 15 V TSSOP 14 Supply Operation AD5200 1 3 V 5 5 V 3 Wire 10 50 256 60 uA USOIC 10 Full AC Specs Dual Supply Pwr On Reset AD8400 1 5 5 V 3 Wire 1 10 50 100 256 5 uA SO 8 Full AC specs AD5241 1 3 V 5 5 V 2 Wire 10 100 1000 256 5 uA SO 14 TSSOP 14 PC Compatible TC lt 50 ppm C AD5231 1 3 V 5 5 V 3 Wire 10 50 100 1024 10 pA TSSOP 16 Nonvolatile Memory Direct Program I D 6 dB Settability AD5222 2 3 V 5 5 V Up Down 10 50 100 1000 128 80 uA SO 14 TSSOP 14 No Rollover Stereo Pwr On Reset TC lt 50 ppm C AD8402 2 5 5 V 3 Wire 1 10 50 100 256 5 uA PDIP SO 14 Full AC Specs nA TSSOP 14 Shutdown Current AD5232 2 3 V 5 5 V 3 Wire 10 50 100 256 10 uA TSSOP 16 Nonvolatile Memory Direct Program I D 6 dB Settability AD5242 2 3 V 5 5 V 2 Wire 10 100 1000 256 5 uA SO 16 TSSOP 16 I C Compatible TC lt 50 ppm C AD5262 2 5 V 12 V 3 Wire 10 50 100 256 60 uA TSSOP 16 Medium Voltage Operation TC
25. y D Se Vag Va for AD5200 5 Vw D 2 Van Vg for AD5201 6 where D in AD5200 is between 0 to 255 and D in AD5201 is between 0 to 32 For more accurate calculation including the effects of wiper resistance Vw can be found as vy p Reel Va Beal Vg 7 AB Raz where Ryg D and Rw4 D can be obtained from Equations 1 to 4 REV B Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature Here the output voltage is dependent on the ratio of the internal resistors and not the absolute values therefore the drift reduces to 15 ppm C DIGITAL INTERFACING The AD5200 AD5201 contain a standard three wire serial input control interface The three inputs are clock CLK CS and serial data input SDI The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families work well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means Figure 3 shows more detail of the internal digital circuitry When CS is low the clock loads data into the serial register on each positive clock edge see Table IID Figure 3 Block Diagram Table III Input Logic Control Truth Table CLK CS SHDN Register Activity L L H No SR effect P L H Shift one bit in from the SDI pin X P H Load SR data into RDAC l

ANALOG DEVICES AD5200/AD5201 handbook

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