ANALOG DEVICES AD5160 256-Position SPI Compatible Digital Potentiometer handbook
Contents
1. CODE Decimal Figure 8 DNL vs Code vs Supply Voltages RHEOSTAT MODE INL LSB RHEOSTAT MODE DNL LSB FSE FULL SCALE ERROR LSB 32 64 96 128 160 192 CODE Decimal Figure 9 R INL vs Code Vpp 5 224 256 2 5 m o CODE Decimal Figure 10 R DNL vs Code Voo 5 V ad a 0 40 80 TEMPERATURE C Figure 11 Full Scale Error vs Temperature 120 Rev 0 Page 7 of 16 ZSE ZERO SCALE ERROR uA lA SHUTDOWN CURRENT nA Ippj9UPPLY CURRENT uA AD5160 40 0 40 80 120 TEMPERATURE C Figure 12 Zero Scale Error vs Temperature TEMPERATURE C Figure 13 Supply Current vs Temperature TEMPERATURE C Figure 14 Shutdown Current vs Temperature AD5160 200 150 50 RHEOSTAT MODE TEMPCO ppm C CODE Decimal Figure 15 Rheostat Mode Tempco ARws AT vs Code 160 140 120 100 POTENTIOMETER MODE TEMPCO 0 32 64 96 128 160 CODE Decimal 192 224 256 Figure 16 Potentiometer Mode Tempco AVwe AT vs Code REF LEVEL IDIV MARKER 1 000 000 000Hz 0 000dB 6 000dB MAG 8 918dB 0 1k 10k START2. ss 13 REVISION HISTORY Revision 0 Initial Version ESD Protection 13 Terminal Voltage Operating Range 13 Power Up Sequence seen 13 Layout and Power Supply Bypassing 14 Pin Configuration and Function 15 Pin Configuration eii E EERE 15 Pin Function Descriptions 15 Outlin Dimensions rentre ere eite eite 16 Ordering Guide ei t nete 16 ESD Caution iiia 16 ww BDTI com ADI Rev 0 Page 2 of 16 ELECTRICAL CHARACTERISTICS 5 VERSION Voo 5 V 10 or 10 Va Von Vs 0 40 C lt Ta lt 125 C unless otherwise noted AD5160 Table 1 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe Va no connect 1 5 0 1 1 5 LSB Resistor Integral Nonlinearity R INL Va no connect 4 0 75 4 LSB Nominal Resistor Tolerance ARas Ta 25 C 30 30 Resistance Temperature Coefficient ARas AT Vas Wiper no connect 45 ppm C Wiper Resistance Rw 50 120 Q DC CHARACTERISTICS DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 5 0 1 1 5 LSB Integral Nonlineari
3. Figure 24 Digital Feedthrough 10M START 1 000 000Hz STOP 1 000 000 000Hz Figure 21 3 dB Bandwidth Code 0x80 III CODE 0x80 Va Vpp Vg 100mV 5 00 200 A CH17152mV 100 m k 100k 1M Figure 25 Midscale Glitch Code 0 80 0 7 FREQUENCY Hz Figure 22 PSRR vs Frequency 900 Vpp 5V 800 700 600 500 a CODE 0x55 300 CODE 0xFF 200 100 5 007 2 5 00 200 5 A CH173 00 0 i i ing Ti T k 100k a Figure 26 Large Signal Settling Time Code OxFF Ox00 FREQUENCY Hz Figure 23 vs Frequency Rev 0 Page 9 of 16 AD5160 TEST CIRCUITS Figure 27 to Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables V 1LSB V 2N Figure 27 Test Circuit for Potentiometer Divider Nonlinearity Error INL DNL NO CONNECT Figure 28 Test Circuit for Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL OFFSET GND V Vpp 10 PSRR dB 20 LOG AV ms AV po Wop PSS OFFSET GND Figure 31 Test Circuit for Inverting Gain Rev 0 Page 10 of 16 Vem NC NC NO CON
4. Table 2 Parameter Symbol Conditions Min Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe Va no connect 1 0 1 1 LSB Resistor Integral Nonlinearity R INL Rws Va no connect 2 0 25 2 LSB Nominal Resistor Tolerance ARas 25 30 30 Resistance Temperature Coefficient Vas 45 ppm C Wiper no connect Wiper Resistance Rw 5 50 120 Q DC CHARACTERISTICS DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity DNL 1 0 1 1 LSB Integral Nonlinearity INL 1 0 3 1 LSB Voltage Divider Temperature Coefficient AVw AT Code 0x80 15 ppm C Full Scale Error Vwese Code OxFF 3 1 0 LSB Zero Scale Error Vwzse Code 0x00 0 1 3 LSB RESISTOR TERMINALS Voltage Range GND V Capacitance A B Cap f 1 MHz measured to 45 pF GND Code 0x80 Capacitance W f 1 MHz measured to 60 pF GN de 0x80 Shutdown Suppl t Vi 0 0 Common Mo Vs 2 1 nA DIGITAL INPUTS AND Input Logic High Vin 2 4 V Input Logic Low Vit 0 8 V Input Logic High Vin 21 V Input Logic Low Vit Voo 3V 0 6 V Input Current li Vin OVor5V 1 Input Capacitance Ci 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2 7 5 5 V Supply Current 5 0 3 8 Power Dissipation Poiss Vn 5VorVi OV 0 2 mW Voo 5V Power Supply Sensi
5. 1 000 000Hz 100k STOP 1 000 000 000Hz 1M Figure 17 Gain vs Frequency vs Code Ras 5 Rev 0 Page 8 of 16 REF LEVEL 0 000dB 0 IDIV 6 000dB MARKER 510 634 725Hz A R 9 049dB 6 0x80 0x40 12 0 20 0 10 0 08 0x04 0x02 0x01 1k 10k START 1 000 000Hz 100k 1M STOP 1 000 000 000Hz Figure 18 Gain vs Frequency vs Code Ras 10 REF LEVEL 0 000dB 6 000dB MARKER 100 885 289Hz A R 9 014dB 1k 10k START 1 000 000Hz 100k 1M STOP 1 000 000 000Hz Figure 19 Gain vs Frequency vs Code Ras 50 kQ REF LEVEL 0 000dB 0 IDIV 6 000dB MARKER 54 089 173Hz 9 052dB 0 80 12 1k 10k START 1 000 000Hz 100k 1M STOP 1 000 000 000Hz Figure 20 Gain vs Frequency vs Code Ras 100 REF LEVEL IDIV 5 000dB 0 500dB 5 5 5 1 10kQ 50kQ 100kQ 54 MHz AD5160 026 MHz 511 MHz 101 MHz 50kQ 5 0 1 CLK 100kQ R 10kQ 10 0 10 5 Ipp HA 10k 100k 1M Ch 1 200mV ByjCh2 5 00 V By M 100ns CH273 00
6. into the serial register on each positive clock edge see Figure 36 The data setup and data hold times in the specification table determine the valid timing requirements The AD5160 uses an 8 bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high Extra MSB bits are ignored ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 39 and Figure 40 This applies to the digital input pins SDI CLK and CS 3400 LOGIC N Vss Figure 39 ESD Protection of Digital Pins Vss Figure 40 ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5160 Vpp and GND power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation Supply signals present on terminals A B and W that exceed Vp GND will be clamped by the internal forward biased diodes see Figure 41 Vpp C i Vss Figure 41 Maximum Terminal Voltages Set by Vpp and Vss POWER UP SEQUENCE Since the ESD protection diodes limit the voltage compliance at terminals A B and W see Figure 41 it is important to power before applying any voltage to terminals A B and W otherwise the diode will be forward biased such that will be powered unintentionally and may affect the rest of the user s circuit The ideal power up sequence is in the followin
7. minimum of 60 Q resistance between terminals W and B The second connection is the first tap point which corresponds to 99 Rws Ras 256 Rw 39 60 for data 0x01 The third connection is the next tap point representing 177 2 x 39 60 for data 0x02 and so on pach yalu increase moves the istor ladd ast ta point is reached 9 Ry shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed therefore there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance Figure 38 AD5160 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between W and B is D Ryg D x Rag R 1 wa 256 AB W where Dis the decimal equivalent of the binary code loaded in the 8 bit register Razis the end to end resistance and Rwis the wiper resistance contributed by the on resistance of the internal switch In summary if Ras 10 and the A terminal is open circuited the following output resistance Rws will be set for the indicated RDAC latch codes Table 6 Codes and Corresponding Rws Resistance D Dec Output State 255 9 961 Full Scale Ras 1158 Rw 128 5 060 Midscale 1 99 1 LSB 0 60 Zero Scale Wiper Contact Resistance Note that in the zero scale condition a finite wiper resistance of 60 15 present Care
8. transistors Die size 30 7 mil x 76 8 mil 2 358 sq mil ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance WARNING eamm aa ESD SENSITIVE DEVICE degradation or loss of functionality ANALOG DEVICES Rev 0 Page 16 of 16 2003 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective companies C03434 0 5 03 0 www analog com
9. 4 CLK Serial Clock Input Positive edge triggered 5 SDI Serial Data Input 6 cs Chip Select Input Active Low When CS returns high data will be loaded into the DAC register 7 B B Terminal 8 A A Terminal ww BDTI com ADI Rev 0 15 of 16 AD5160 OUTLINE DIMENSIONS rrr 2 80 BSC 0 65 BSC 1 95 1 30 BSC 145 0 90 mE 145MAX 022 Y i 008 0 60 5 038 TIE uda 048 0 22 SEATING 0 30 PLANE 0 COMPLIANT TO JEDEC STANDARDS MO 178BA Figure 44 8 Lead Small Outline Transistor Package 507 23 RJ 8 Dimensions shown in millimeters ORDERING GUIDE Model Q re Package De cripti e randing AD5160BRJ5 R2 5 125 23 8 08 AD5160BRJ5 RL7 5k 40 C to 125 C SOT 23 8 RJ 008 AD5160BRJ10 R2 10k 40 to 125 C SOT 23 8 RJ 8 009 AD5160BRJ10 RL7 10k 40 to 125 C SOT 23 8 RJ 8 009 AD5160BRJ50 R2 50k 40 to 125 C SOT 23 8 RJ 8 DOA AD5160BRJ50 RL7 50k 40 to 125 C SOT 23 8 RJ 8 DOA AD5160BRJ100 R2 100k 40 to 125 C SOT 23 8 RJ 8 DOB AD5160BRJ100 RL7 100k 40 to 125 C SOT 23 8 RJ 8 DOB AD5160EVAL See Note 1 Evaluation Board evaluation board is shipped with the 10 Ras resistor option however the board is compatible with all available resistor value options The AD5160 contains 2532
10. ANALOG DEVICES FEATURES 256 position End to end resistance 5 10 50 100 Compact SOT 23 8 2 9 mm x 3 mm package SPI compatible interface Power on preset to midscale Single supply 2 7 V to 5 5 V Low temperature coefficient 45 ppm C Low power 8 pA Wide operating temperature 40 C to 125 C Evaluation board available APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure temperature position chemical and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment WA BDT I ce E The AD5160 provides a compact 2 9 mm x 3 mm packaged solution for 256 position adjustment applications These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution solid state reliability and superior low temperature coefficient performance The wiper settings are controllable through an SPI compatible digital interface The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch Operating from a 2 7 V to 5 5 V power supply and consuming less than 5 uA allows for usage in portable battery operated applications Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is as
11. NECT Figure 35 Test Circuit for Common Mode Leakage current SPI INTERFACE Table 5 AD5160 Serial Data Word Format B7 B6 B5 B4 B3 B2 B1 BO D7 D6 D5 D4 D3 D2 D1 DO MSB LSB 2 2 AD5160 X oo oo RDAC REGISTER LOAD p Figure 36 AD5160 SPI Interface Timing Diagram Va 5 V Ve 0 V Vw 1 0 1 0 1 0 1 0 1LSB Figure 37 SPI Interface Detailed Timing Diagram Va 5 V Ve 0 V Vw Rev 0 Page 11 of 16 AD5160 OPERATION The AD5160 is a 256 position digitally controlled variable resistor VR device An internal power on preset places the wiper at midscale during power on which simplifies the fault condition recovery at power up PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 5 10 50 and 100 The final two or three digits of the part number determine the nominal resistance value e g 10 10 50 50 The nominal resistance Ras of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The 8 bit data in the RDAC latch is decoded to select one of the 256 possible settings Assume a 10 part is used the wiper s first connection starts at the B terminal for data 0x00 Since there is a 60 wiper contact resistance such connection yields a
12. cross A B W A and W B can be at either polarity If ignoring the effect of the wiper resistance for approximation connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B starting at 0 V up to 1 LSB less than 5 V Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider The general equation defining the output voltage at Vw with respect to ground for any valid input voltage applied to terminals A and B is D 256 D 3 w D 256 256 For a more accurate calculation which includes the effect of wiper resistance Vw can be found as Rs D y RwalD 256 256 m Operation of t results in a ation o the rheostat the ratio of the internal resistors Rwa and Rws and not the absolute values Therefore the temperature drift reduces to 15 ppm C SPI COMPATIBLE 3 WIRE SERIAL BUS The AD5160 contains a 3 wire SPI compatible digital interface SDI CS and CLK The 8 bit serial word must be loaded MSB first The format of the word is shown in Table 5 The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register Standard logic families work well If mechanical switches are used for product evaluation they should be debounced by a flip flop or other suitable means When CS is low the clock loads data
13. g order GND digital inputs and then The relative order of powering Va Vs Vw and the digital inputs is not important as long as they are powered after Vop GND Rev 0 Page 13 of 16 AD5160 LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to employ compact minimum lead length layout design The leads to the inputs should be as direct as possible with a minimum conductor length Ground paths should have low resistance and low inductance Similarly it is also a good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0 01 uF to 0 1 uF Low ESR 1 uF to 10 tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 42 Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce AD5160 ea ete ES d Figure 42 Power Supply Bypassing ww BDTI com ADI Rev 0 Page 14 of 16 AD5160 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Bn Table 8 Voo EZ B Pin Name Description SND 3 topview 5 65 1 Ww W Terminal CLK 4 Not to Scale 5 501 2 Positive Power Supply 3 GND Digital Ground Figure 43
14. orage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C Thermal Resistance MSOP 10 230 C W NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance Package power dissipation Tmax Rev 0 Page 5 of 16 AD5160 TYPICAL PERFORMANCE CHARACTERISTICS RHEOSTAT MODE INL LSB RHEOSTAT MODE DNL LSB POTENTIOMETER MODE INL LSB 0 8 0 6 0 4 0 2 0 fdl 5V 3V 32 Figure 3 R INL vs Code vs Supply Voltages 64 96 128 160 192 CODE Decimal 224 256 32 64 96 128 160 192 224 256 CODE Decimal Figure 4 R DNL vs Code vs Supply Voltages 40 C 25 C 85 C 125 32 64 96 128 160 192 224 256 CODE Decimal Figure 5 INL vs Code 5 V Rev 0 Page 6 of 16 POTENTIOMETER MODE INL LSB POTENTIOMETER MODE DNL LSB POTENTIOMETER MODE DNL LSB 0 32 64 96 128 160 192 224 256 CODE Decimal Figure 6 DNL vs Code Vpp 5 CODE Decimal Figure 7 INL vs Code vs Supply Voltages
15. should be taken to limit the current flow etween W and B in this state tg a maximum pulse current of no more 20 de at destruction of he Similar to the mechanical p tentiometer the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance Rwa When these terminals are used the B terminal can be opened Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is 256 D Rya D x Rag Ry Q For Ras 10 and the B terminal open circuited the following output resistance Rwa will be set for the indicated RDAC latch codes Table 7 Codes and Corresponding Rwa Resistance D Dec Rwa Q Output State 255 99 Full Scale 128 5 060 Midscale 1 9 961 1158 0 10 060 Zero Scale Typical device to device matching is process lot dependent and may vary by up to 30 Since the resistance element is processed in thin film technology the change in Ras with temperature has a very low 45 ppm C temperature coefficient Rev 0 Page 12 of 16 AD5160 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage at A to B Unlike the polarity of to GND which must be positive voltage a
16. sumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies 256 Position SPI Compatible Digital Potentiometer AD5160 FUNCTIONAL BLOCK DIAGRAM WIPER REGISTER GND Figure 1 PIN CONFIGURATION Figure 2 Note The terms digital potentiometer VR and RDAC are used interchangeably One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD5160 TABLE OF CONTENTS Electrical Characteristics 5 Version 3 Electrical Characteristics 10 50 100 Versions 4 Timing Characteristics 5 10 50 100 Versions 5 Absolute Maximum Ratings eerte 5 Typical Performance Characteristics 6 Test CIT CUILS e eee ete ei eq adeat 10 SPI Interface ote t 11 CPST ALON E 12 Programming the Variable Resistor 12 Programming the Potentiometer Divider 13 SPI Compatible 3 Wire Serial Bus
17. tions Parts are guaranteed monotonic 3 Vas Von Wiper Vw no connect 51 and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter VA Voo and Vs 0 V DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions 5 Resistor terminals A B W have no limitations on polarity with respect to each other Guaranteed by design and not subject to production test 7 Measured at the A terminal The A terminal is uite n mo tin mi um power put control Voltagesvare specified With ta 0900 9096 V a voltage ABSOLUTE MAXIMUM RATINGS All dynamic Ta 25 C unless otherwise noted 10 See timing d asured level of 1 5 V Table 4 Stresses above those listed under Absolute Maximum Ratings Parameter Value may cause permanent damage to the device This is a stress to GND 0 3 V to 7 V rating only and functional operation of the device at these or Va Vs Vw to GND any other conditions above those indicated in the operational Imax 20 mA section of this specification is not implied Exposure to absolute Digital Inputs and Output Voltage to GND OV to 7 maximum rating conditions for extended periods may affect Operating Temperature Range 40 to 125 device reliability Maximum Junction Temperature Tmax 150 C St
18. tivity PSS 5 V 10 0 02 0 05 Code Midscale DYNAMIC CHARACTERISTICS Bandwidth 3dB BW Ras 10 kO 50 kO 100 kO 600 100 40 kHz Code 0x80 Total Harmonic Distortion THDw Va 1 V rms 0 05 f 1 kHz Ras 10 Vw Settling Time 10 50 100 ts 5 0 2 Hs 1 LSB error band Resistor Noise Voltage Density Rwe 5 RS 0 9 nV 4Hz Rev 0 Page 4 of 16 AD5160 TIMING CHARACTERISTICS 5 10 50 100 VERSIONS Voo 5V 10 or 3V 10 Va Voo Vs 0 Vi 40 C lt Ta lt 125 C unless otherwise noted Table 3 Parameter Symbol Conditions Min Typ Max Unit SPI INTERFACE TIMING CHARACTERISTICS 10 Specifications Apply to All Parts Clock Frequency fax 25 MHz Input Clock Pulsewidth tcu ter Clock level high or low 20 ns Data Setup Time tos 5 ns Data Hold Time 5 ns CS Setup Time tcss 15 ns cS High Pulsewidth tcsw 40 ns CLK Fall to CS Fall Hold Time tcsuo 0 ns CLK Fall to CS Rise Hold Time tcsui 0 ns CS Rise to Clock Rise Setup test 10 ns NOTES 1 Typical specifications represent average readings at 25 C and 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap posi
19. ty INL 1 5 0 6 415 LSB Voltage Divider Temperature Coefficient AVw AT Code 0x80 15 ppm C Full Scale Error Code OxFF 6 2 5 0 LSB Zero Scale Error Vwzse Code 0x00 0 2 6 LSB RESISTOR TERMINALS Voltage Range VABW GND V Capacitance A B f 1 MHz measured to GND 45 pF Code 0x80 Capacitance W Cw f 1 MHz measured to GND 60 pF Code 0x80 Shutdown Supply Current x 55V 1 A Vs nA DIGITAL IN Input Logic Hi IH 2 V Input Logic Low Vit 0 8 Input Logic High Vin 21 V Input Logic Low Vit 0 6 V Input Current lii Vin OVor5V 1 Input Capacitance Ci 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2 7 55 V Supply Current Ipp Vn 5VorVi 0V 3 8 Power Dissipation Poiss 5 V or Vu O V Voo 5 V 0 2 mW Power Supply Sensitivity PSS 5 V 10 0 02 0 05 Code Midscale DYNAMIC CHARACTERISTICS Bandwidth 3dB BW_5K Ras 5 kO Code 0x80 1 2 MHz Total Harmonic Distortion THDw Va 1 V rms Vs 0 V f 1 kHz 0 05 Vw Settling Time ts 5 V 1 LSB error 1 Us band Resistor Noise Voltage Density Rwe 2 5 RS 0 6 nV VHz Rev 0 3 of 16 AD5160 ELECTRICAL CHARACTERISTICS 10 50 100 VERSIONS Voo 5 V 1096 or V 1096 Va Von Vs 0 V 40 C lt Ta lt 125 C unless otherwise noted
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ANALOG DEVICES AD5160 256 Position SPI Compatible Digital Potentiometer handbook