ATMEL AT49BV512 handbook
Contents
1. continued Pin Configurations DIP Top View Pin Name Function NOAA solus NCH 2 31 D WE A15 Addresses age 13 30 NC RFE A12 0 4 29 0 A14 CE Chip Enable 28H 13 um A6 0 6 270 A8 OE Output Enable A507 26 A9 4 8 25 1A11 WE Write Enable a309 2410 OE A2 10 23 A10 1 00 1 07 Data Inputs Outputs agi 2211 CE AOL 12 21 O 1 07 NC No Connect 100 O 13 20 O 1 06 101 O 14 19 0 1 05 VO2 O 15 18 1 1 04 VSOP Top View 8 x 14 mm or GND die i Bio TSOP Top View 8 x 20 mm Type 1 Ac o s sa or PLCC Top View A9 2 31 A10 8 13 30 1 X2o08 A134 291 07 SUME eo ie e macs 28 1 06 fone eee NC 6 27 105 7 15 o 5g D A14 WE 7 26 1 04 A6 0 6 28 O A13 VCC 8 25 1 03 A507 270 A8 NC 9 24 GND A408 26 1A9 NC 10 23 1 02 A309 25 1A11 11 22 1 01 A2 0 10 24 OE A12 12 21 1 00 11 23L1A10 A7 13 20 A0 A0 O 12 22 j CE A6 14 19 A1 1 00 13 TO TE ES EA 1 07 5 15 A2 e A4 16 17 A3 T A 512K 64K x 8 Single 2 7 volt Battery Voltage Flash Memory AT49BV512 Rev 1026C 09 98 AIMEL typical byte programming time is a fast 30 us The end ofa program cycle can be optionally2. 0 6V to Voc 0 6V Voltage on OE with Respect to 0 6 to 13 5V NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability AIMEL AIMEL DC and AC Operating Range AT49BV512 12 AT49BV512 15 Com 0 C 70 C 0 C 70 C Operating Temperature Case Ind 40 C 85 C 40 C 85 C Voc Power Supply 2 7V to 3 6V 2 7V to 3 6V Operating Modes Mode CE OE WE Ai 1 0 Read M Vis Ai Bor Program Vi Vin Vi Ai Dn Standby Write Inhibit Vin x X X High Z Program Inhibit X X Viu Program Inhibit X Vi X Output Disable X Viu X High Z Product Identification Hardware Vi Vin A1 A15 V4 A9 V4 Manufacturer Code Vi A1 A15 V4 A9 V4 Device Code AO Vi Software A0 Vy A1 A15 Vy Manufacturer Code AO Vi A15 V Device Code Notes 1 X can be V or Vi 2 Refer to AC Programming Waveforms 3 V4 2 12 0V 0 5V 4 Manufacturer Code 1FH Device Code 03H 5 See
3. details under Software Product Identification Entry Exit DC Characteristics Symbol Parameter Condition Min Max Units li Input Load Current Vin OV to Voc 10 uA lio Output Leakage Current Vio OV to Voc 10 uA legi Voc Standby Current CMOS CE Vec 0 3V to Voc 50 uA lope Voc Standby Current TTL CE 2 0V to Voc 1 mA leg Voc Active Current f 5 MHz lour 0 mA 25 mA Viu Input Low Voltage 0 6 V Vin Input High Voltage 2 0 V VoL Output Low Voltage lop 2 1 mA 0 45 V VoH Output High Voltage lou 100 pA Vec 3 0V 2 4 V Note 1 Inthe erase mode lcc is 50 mA AC Read Characteristics AT49BV512 12 AT49BV512 15 Symbol Parameter Min Max Min Max Units tacc Address to Output Delay 120 150 ns tee CE to Output Delay 120 150 ns toe 5 OE to Output Delay 50 0 70 ns tpp 53 CE or OE to Output Float 0 30 0 40 ns tou Output Hold from OE CE or Address whichever occurred first 0 0 ns AC Read Waveforms ADDRESS ADDRESS VALID I tACC OUTPUT HIGH ZK OUTPUT VALID Notes 1 CE may be delayed up to tace tce after the address transition without impact on tacc 2 OE may be delayed up to tc tog after the falling edge of CE without impact on tee or by tace tog after an address change without impact on t4cc 3 is specified from OE or CE whichever occurs frist CL 5 pF 4 This parameter is characterized and
4. detected by the DATA poll ing feature Once the end of a byte program cycle has been detected a new access for a read or program can begin The typical number of program and erase cycles is in excess of 10 000 cycles The optional 8K bytes boot block section includes a repro gramming write lock out feature to provide data integrity The boot sector is designed to contain user secure code and when the feature is enabled the boot sector is perma nently protected from being reprogrammed Block Diagram DATA INPUTS OUTPUTS 1 00 1 07 DATA LATCH INPUT OUTPUT BUFFERS Y GATING MAIN MEMORY 56K BYTES Ra X DECODER ADDRESS INPUTS FFFFH 2000H 1FFFH OPTIONAL BOOT BLOCK 8K BYTES 0000H Device Operation READ The AT49BV512 is accessed like an EPROM When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs The outputs are put in the high impedance state whenever CE or OE is high This dual line control gives designers flexibility in preventing bus con tention ERASURE Before a byte can be reprogrammed the 64K bytes memory array or 56K bytes if the boot block featured is used must be erased The erased state of the memory bits is a logical 1 The entire device can be erased at one time by using a 6 byte software code The software chip erase code consists of 6 byte load commands to specific addr
5. 12 15PC 32P6 0 C 70 C AT49BV512 15TC 32T AT49BV512 15VC 32V 25 0 05 AT49BV512 15Jl 32J Industrial AT49BV512 15PI 32P6 40 C 85 C AT49BV512 15TI 32T AT49BV512 15VI 32V Note 1 The AT49BV512 has as optional boot block feature The part number shown in the Ordering Information table is for devices with the boot block in the lower address range i e 0000H to 1FFFH Users requiring boot block protection to be in the higher address range should contact Atmel Package Type 32J 32 Lead Plastic J Leaded Chip Carrier Package PLCC 32P6 32 Lead 0 600 Wide Plastic Dual Inline Package PDIP 32T 32 Lead Thin Small Outline Package TSOP 8 x 20 mm 32V 32 Lead Thin Small Outline Package VSOP 8 x 14 mm Packaging Information 32J 32 Lead Plastic J Leaded Chip Carrier PLCC Dimensions in Inches and Millimeters 045 1 14 X 45 PINNO 1 025 635 X 30 45 AT CONTACT E POINTS zl y 0220559 X 45 MAX 3X po SS IDENTEY H 553 14 0 032 8 211 L 547 13 9 026 660 0 yE 595 15 1 q 585 14 9 Fl i 050 1 27 TYP 430 10 9 EE 390 9 90 32P6 32 Lead 0 600 Wide Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters _ 1 67 42 4 1 64 41 7 P
6. 218A T49BV 5120 hv Features Single Supply Voltage Range 2 7V to 3 6V Single Supply for Read and Write Fast Read Access Time 120 ns Internal Program Control and Timer 8K bytes Boot Block With Lockout Fast Erase Cycle Time 10 seconds Byte By Byte Programming 30 us Byte typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation 25 mA Active Current 50 pA CMOS Standby Current Typical 10 000 Write Cycles Description The AT49BV512 is a 3 volt only 512K Flash memories organized as 65 536 words of 8 bits each Manufactured with Atmel s advanced nonvolatile CMOS technology the devices offer access times to 120 ns with power dissipation of just 90 mW over the commercial temperature range When the devices are deselected the CMOS standby current is less than 50 pA To allow for simple in system reprogrammability the AT49BV512 does not require high input voltages for programming Three volt only commands determine the read and programming operation of the device Reading data out of the device is similar to reading from an EPROM Reprogramming the AT49BV512 is performed by erasing the entire 1 megabit of memory and then programming on a byte by byte basis The
7. DRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE 5 Software Product LOAD DATA 55 Identification Exit ADDRESS 2 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA FO TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second LOAD DATA FO TO ADDRESS 5555 Notes 1 Data Format 7 l OO Hex Address Format A14 AO Hex 2 Boot block lockout feature enabled EXIT PRODUCT IDENTIFICATION MODE Notes 1 Data Format 7 1 00 Hex Address Format A14 AO Hex 2 A1 A15 2V Manufacture Code is read for A0 V Device Code is read for AO Vj 3 The device does note remain in identification mode if powered down 4 The device returns to standard operation mode 5 Manufacturers Code 1FH Device Code 03H AMEL Ordering Information AIMEL tace Icc mA ns Active Standby Ordering Code Package Operation Range 120 25 0 05 AT49BV512 12JC 32J Commercial AT49BV512 12PC 32P6 0 C 70 C AT49BV512 12TC 32T AT49BV512 12VC 32V 25 0 05 AT49BV512 12JI 32J Industrial AT49BV512 12PI 32P6 40 C 85 C AT49BV512 12TI 32T AT49BV512 12VI 32V 150 25 0 05 AT49BV512 15JC 32J Commercial AT49BV5
8. IN 1 Ah Hiina AH 566 14 4 i V 530 13 5 ui NA A LI 090 2 29 1 500 38 10 REF MAX 220 5 59 005 127 MAX J seating uL KAHE PLANE i igi MI o6s 1 65 161 4 09 TOES 015 381 125 3 18 022 559 065 1 65 014 356 110 2 79 041 1 04 090 2 29 630060 590015 0 7 690 17 5 L7 1055 327 32 Lead Plastic Thin Small Outline Package TSOP Dimensions in Millimeters and Inches JEDEC OUTLINE MO 142 BD 1100222000001 i INDEX MARK 18 5 728 20 2 795 78 3 720 19 8 780 MM 0 50 020 __ 0 25 010 BSC 750 295 015008 REF 8 20 323 780 307 E 1 20 047 MAX 0 15006 0 05 002 REF 0 20 008 04 A 0 70 028 0 50 020 m Controlling dimensions millimeters 32V 32 Lead Plastic Thin Small Outline Package VSOP Dimensions in Millimeters Inches 12 5 492 14 2 559 12 3484 13 8 543 Y 050020 L o25 010 7 50 295 0 15 006 REF 8 10 319 7 790 311 1 20 047 MAX 0 15 006 1 i 0 05 002 REF 0 20 008 0 10 004 ps 0 70 028 0 50 020 i AIMEL 11
9. accessed by hardware or software operation The hardware operation mode can be used by an external pro grammer to identify the correct programming algorithm for the Atmel product For details see Operating Modes for hardware operation or Software Product Identification The manufacturer and device code is the same for both modes DATA POLLING The AT49BV512 features DATA polling to indicate the end of a program cycle During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I O7 Once the pro gram cycle has been completed true data is valid on all outputs and the next cycle may begin DATA polling may begin at any time during the program cycle TOGGLE BIT In addition to DATA polling the AT49BV512 provides another method for determining the end of a pro gram or erase cycle During a program or erase operation successive attempts to read data from the device will result in 06 toggling between one and zero Once the program cycle has completed 1 06 will stop toggling and valid data will be read Examining the toggle bit may begin at any time during a program cycle Command Definition in Hex HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT49BV512 in the following ways a Voc sense if Vec is below 1 8V typical the program function is inhibited b Program inhibit holding any one of OE low CE high or WE high inhi
10. bits program cycles c Noise filter Pulses of less than 15 ns typical on the WE or CE inputs will not initiate a pro gram cycle INPUT LEVELS While operating with a 2 7V to 3 6V power supply the address inputs and control inputs OE CE and WE may be driven from 0 to 5 5V without adversely affecting the operation of the device The I O lines can only be driven from 0 to 0 6V 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus command Bus Cycle Cycle Cycle Cycle Cycle Cycle Sequence Cycles Adar Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr Dout Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte 4 5555 AA 2AAA 55 5555 AO Addr Din Program Boot Block 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Lockout Product ID 3 5555 AA 2AAA 55 5555 90 Entry Product ID 3 5555 AA 2AAA 55 5555 FO Exit Product ID 1 XXXX FO Exit Notes 1 The 8K byte boot sector has the address range 0000H to 1FFFH 2 Either one of the Product ID exit commands can be used Absolute Maximum Ratings Temperature Under 85 55 C to 12550 Storage 65 C to 150 C All Input Voltages including NC Pins with Respect to 0 6V to 6 25V All Output Voltages with Respect to Ground
11. ess locations with a specific data pattern please refer to the Chip Erase Cycle Waveforms After the software chip erase has been initiated the device will internally time the erase operation so that no external clocks are required The maximum time needed to erase the whole chip is tec If the boot block lockout feature has been enabled the data in the boot sector will not be erased BYTE PROGRAMMING Once the memory array is erased the device is programmed to a logical O ona byte by byte basis Please note that a data 0 cannot be programmed back to a 1 only erase operations can con vert O s to 1 s Programming is accomplished via the internal device command register and is a 4 bus cycle oper ation please refer to the Command Definitions table The device will automatically generate the required internal pro gram pulses The program cycle has addresses latched on the falling edge of WE or CE whichever occurs last and the data latched on the rising edge of WE or CE whichever occurs first Programming is completed after the specified tgp cycle time The DATA polling feature may also be used to indicate the end of a program cycle BOOT BLOCK PROGRAMMING LOCKOUT The device has one designated block that has a programming lockout feature This feature prevents programming of data in the designated block once the feature has been enabled The size of the block is 8K bytes This block referred to as the b
12. is not 10096 tested Input Test Waveforms and Output Test Load Measurement Level 3 0V AC 2 4 DRIVING 1 5V MEASUREMENT OUTPUT LEVELS av LEVEL BIN tR tF lt 5 ns 1 3K pF Pin Capacitance f 1 MHz T 25 C Typ Max Units Conditions Cn 4 6 pF Vin OV Cour 8 12 pF Vout OV Note 1 This parameter is characterized and is not 100 tested AIMEL B AIMEL AC Byte Load Characteristics Symbol Parameter Min Max Units tas toes Address OE Set up Time 0 ns Address Hold Time 100 ns tes Chip Select Set up Time 0 ns tcu Chip Select Hold Time 0 ns twp Write Pulse Width WE or CE 200 ns tos Data Set up Time 100 ns Iis oes Data OE Hold Time 0 ns twpu Write Pulse Width High 200 ns AC Byte Load Waveforms WE Controlled lt gt OES tOEH ADDRESS Ed tAS 5 1 tCH t esso Ru tOES tOEH tAS tAH tCH E Controlled tCS 5 tDS tDH DATA IN Program Cycle Characteristics Symbol Parameter Min Typ Max Units tgp Byte Programming Time 30 us tas Address Set up Time 0 ns Address Hold Time 100 ns tos Data Set up Time 100 ns tou Data Hold Time 0 ns twp Write Pulse Width 200 ns twpH Write Pulse Width High 200 ns tec Erase Cycle Time 10 seconds Program Cycle Waveforms j PROGRAM CYCLE g
13. oot block can contain secure code that is used to bring up the system Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated This feature does not have to be acti vated the boot block s usage as a write protected region is optional to the user The address range of the boot block is 0000H to 1FFFH Once the feature is enabled the data in the boot block can no longer be erased or programmed Data in the main memory block can still be changed through the regular pro gramming method To activate the lockout feature a series of six program commands to specific addresses with spe cific data must be performed Please refer to the Com mand Definitions table BOOT BLOCK LOCKOUT DETECTION A software method is available to determine if programming of the boot block section is locked out When the device is in the soft ware product identification mode see Software Product Identification Entry and Exit sections a read from address location 00002H will show if programming the boot block is locked out If the data on I O0 is low the boot block can be programmed if the data on I O0 is high the program lock out feature has been activated and the block cannot be programmed The software product identification code should be used to return to standard operation PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel It may be
14. t OE A0 A15 DATA Chip Erase Cycle Waveforms OE A0 A15 DATA BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 Note must be high only when WE and CE are both low AIMEL AIMEL Data Polling Characteristics Symbol Parameter Min Typ Max Units toy Data Hold Time 0 ns OE Hold Time 10 ns toe OE to Output Delay ns twn Write Recovery Time 0 ns Notes 1 These parameters are characterized and not 10095 tested 2 See tog spec in AC Read Characteristics Data Polling Waveforms WE 4 CE tOEH tDH tOE tWR 1 07 A0 A15 An An An An An Toggle Bit Characteristics Symbol Parameter Min Typ Max Units tox Data Hold Time 0 ns Hold Time 10 ns log OE to Output Delay ns togup OE High Pulse 150 ns twn Write Recovery Time 0 ns Notes 1 These parameters are characterized and not 100 tested 2 See tog spec in AC Read Characteristics Toggle Bit Waveforms 99 Notes 1 1 06 Toggling either OE or CE or both OE and CE will operate toggle bit The togpp specification must be met by the toggling input s Beginning and ending state of will vary Any address location may be used but the address should not vary Boot Block Lockout Feature Enable Algorithm LOAD DATA AA TO ADDRESS 5555 Software Product Identification Entry LOAD DATA AA TO AD
Download Pdf Manuals
Related Search
ATMEL AT49BV512 handbook