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ANALOG DEVICES AD600/AD602* handbook

1. 1uV 10uV 100V 1mV 10mV 100mV 1V 10V INPUT SIGNAL V RMS Figure 28 Adding the 2 dB Offsets Improves the Linearization The maximum gain of this circuit is 120 dB If no filtering were used the noise spectral density of the AD600 1 4 nVAHZ would amount to an input noise of 8 28 uV rms in the full band width 35 MHz At a gain of one million the output noise would dominate Consequently some reduction of bandwidth is mandatory and in the circuit of Figure 25 it is due mostly to a single pole low pass filter R5 C3 which provides a 3 dB fre quency of 458 kHz which reduces the worst case output noise at Vago to about 100 mV rms at a gain of 100 dB Of course the bandwidth and hence output noise could be easily reduced further for example in audio applications merely by increasing C3 The value chosen for this application is optimal in minimiz ing the error in the Vr og output for small input signals The AD600 is dc coupled but even miniscule offset voltages at the input would overload the output at high gains so high pass filtering is also needed To provide operation at low frequencies two simple zeros at about 12 Hz are provided by R1 C1 and R4 C2 op amp sections U3A and U3B AD713 are used to provide impedance buffering since the input resistance of the AD600 is only 100 Q A further zero at 12 Hz is provided by C4 and the 6 7 kQ input
2. a cs I W 9 z lt f o 5 Y o 3dB o g A 0 1 1 10 100 FREQUENCY MHz Figure 16 AC Response at the Stabilized Output Level of 1 3V RMS B 102 I 5 100kHz Ro 3 1MHz E 02 E 10MHz q ae H 0 4 0 001 0 01 0 1 1 INPUT AMPLITUDE Volts RMS Figure 17 Output Stabilization vs RMS Input for Sine Wave Inputs at 100 kHz 1 MHz and 10 MHz While the bandgap principle used here sets the output ampli tude to 1 2 V for the square wave case the stabilization point can be set to any higher amplitude up to the maximum output of t Vs 2 V which the AD600 can support It is only neces sary to split R2 into two components of appropriate ratio whose parallel sum remains close to the zero TC value of 806 Q This is illustrated in Figure 18 which shows how the output can be raised without altering the temperature stability REV A TO AD600 PIN 16 TO AD600 PIN 11 Figure 18 Modification in Detector to Raise Output to 2VRMS A Wide Range RMS Linear dB Measurement System 2 MHz AGC Amplifier with RMS Detector Monolithic rms dc converters provide an inexpensive means to measure the rms value of a signal of arbitrary waveform and they also may provide a low accuracy logarithmic decibel scaled output However they have certain shortcomings The first of these is their restricted dy
3. 16 9 PIN gt 0 310 7 87 0 220 5 59 ei 8 0 320 8 13 4 0 840 21 34 MAX 0 290 7 37 ae pice i 0 200 0 015 0 38 5 08 MAX 0 150 0 200 5 08 ry ry 3 81 0 015 0 38 0 125 3 18 Y MIN 0 008 0 20 15 gt e gt gt e ay a 0 023 0 58 0 100 0 070 1 78 SEATING 0 0 014 0 36 2 54 0 030 0 76 PLANE BSC 20 REV A C1664 24 4 92 PRINTED IN U S A
4. tector This circuit can handle inputs from 100 uV to 1 V rms with a constant measurement bandwidth of 20 Hz to 2 MHz limited primarily by the AD636 rms converter Its logarithmic output is a loadable voltage accurately calibrated to 100 mV dB or 2 V per decade which simplifies the interpretation of the reading when using a DVM and is arranged to be 4 V for an input of 100 uV rms input zero for 10 mV and 4 V fora 1 V rms input In terms of Equation 4 Vggr is 10 mV and VscaLE is 2 V 11 AD600 AD602 INPUT 1V RMS MA NW CAL 0dB 6V DEC POWER SUPPLY DECOUPLING NETWORK Vour 100mV dB OV OdB AT 10mV RMS NC NO CONNECT Figure 19 The Output of This Three IC Circuit Is Proportional to the Decibel Value of the RMS Input Note that the peak log output of 4 V requires the use of 6 V supplies for the dual op amp U3 AD712 although lower supplies would suffice for the AD600 and AD636 If only 5 V supplies are available it will be either necessary to use a reduced value for Vscarg say 1 V in which case the peak output would be only 2 V or restrict the dynamic range of the signal to about 60 dB As in the previous case the two amplifiers of the AD600 are used in cascade However the 6 dB attenuator and low pass fil ter found in Figure 1 are replaced by a unity gain buffer ampli fier U3A whose 4 MHz bandwidth eliminates the risk of instability at the highest gains The buffer also
5. 0 5 dB Maximum Output Offset Voltage Vg 625 mV to 625 mV 10 50 10 65 mV Output Offset Variation Vg 625 mV to 625 mV 10 50 10 65 mV AD602 Gain Error 10 dB to 7 dB Gain 0 0 5 1 0 5 0 5 1 5 dB 7 dB to 27 dB Gain 0 5 0 2 0 5 0 1 0 2 1 0 dB 27 dB to 30 dB Gain 1 0 5 0 1 5 0 5 0 5 dB Maximum Output Offset Voltage Vg 625 mV to 625 mV 5 30 10 45 mV Output Offset Variation Vg 625 mV to 625 mV 5 30 10 45 mV GAIN CONTROL INTERFACE Gain Scaling Factor 3 dB to 37 dB AD600 7 dB to 27 dB AD602 31 7 32 32 3 30 5 32 33 5 dB V Common Mode Range 0 75 2 5 0 75 2 5 V Input Bias Current 0 35 1 0 35 1 uA Input Offset Current 10 50 10 50 nA Differential Input Resistance Pins I to 16 Pins 8 to 9 15 15 50 MQ Response Rate Full 40 dB Gain Change 40 40 dB us SIGNAL GATING INTERFACE Logic Input LO Output ON 0 8 0 8 V Logic Input HI Output OFF 2 4 2 4 V Response Time ON to OFF OFF to ON 0 3 0 3 us Input Resistance Pins 4 to 3 Pins 5 to 6 30 30 kQ Output Gated OFF Output Offset Voltage 10 100 10 400 mV Output Noise Spectral Density 65 65 nV VHz Signal Feedthrough 1 MHz AD600 80 80 dB AD602 70 70 dB POWER SUPPLY Specified Operating Range t4 75 t5 25 4 75 5 25 V Quiescent Current 11 12 5 11 14 mA NOTES Typical open or short circuited input noise is lower when system is set to maximum gain and input is short circuited This figure includes the effects of both voltage and curre
6. 28 8 4 gt E 3 0 8 2 S 32 ul 8 0 34 07 05 03 01 01 03 05 07 0 50 100 200 500 1000 2000 GAIN CONTROL VOLTAGE Volts LOAD RESISTANCE Q Figure 38 AD600 and AD602 Figure 39 Third Order Intermodula Figure 40 Typical Output Voltage Typical Group Delay vs Vc tion Distortion Vout 2 V p p vs Load Resistance Negative Out R 5000 put Swing Limits First GAIN 40dB ierat INPUT IMPEDANCE Q OUTPUT OFFSET VOLTAGE mV 100k 1M 10M 100M 0 7 05 03 01 01 03 05 07 FREQUENCY Hz GAIN CONTROL VOLTAGE Volts Figure 41 Input Impedance vs Figure 42 Output Offset vs Gain Figure 43 Gain Control Channel Frequency Control Voltage Control Channel Response Time Top Output Volt Feedthrough age 2 V max Bottom Gain Con trol Voltage Vc 625 mV 18 REV A AD600 AD602 OUTPUT Figure 44 Gating Feedthrough to Output Gating Off to On Figure 47 Input Stage Overload Recovery Time AD600 G 20dB AD602 G 10dB BOTH Voy 100mV RMS 0 1k 10k 100k 1M 10M 100M FREQUENCY Hz Figure 50 CMRR vs Frequency REV A Figure 45 Gating Feedthrough to Output Gating On to Off TES iem ES ENENE NN Figure 48 Output Stage Overload Recovery Time AD600 AD602 PSRR dB amp eo 50 AD600 G 40dB
7. AD600 can be connected as an AGC amplifier Al and A2 are cascaded with 6 dB of attenuation introduced by the 100 Q resistor R1 while a time constant of 5 ns is formed by C1 and the 50 Q of net resistance at the input of A2 This has the dual effect of a lowering the overall gain range from 0 dB to 80 dB to 6 dB to 74 dB and b introducing a single pole low pass filter with a 3 dB frequency of about 32 MHz This ensures stability at the maximum gain for a slight reduction in the over all bandwidth The capacitor C4 blocks the small dc offset volt age at the output of Al which might otherwise saturate A2 at its maximum gain and introduces a high pass corner at about 8 kHz useful in eliminating low frequency noise and spurious signals which may be present at the input AD600 AD602 IS i Ea x RT i b 300A 5V at 300K O0 1uF 45V DEC 5V DEC POWER SUPPLY DECOUPLING NETWORK Figure 15 This Accurate HF AGC Amplifier Uses Just Three Active Components A simple half wave detector is used based on Q1 and R2 The average current into capacitor C2 is just the difference between the current provided by the AD590 300 uA at 300 K 27 C and the collector current of Q1 In turn the control voltage VG is the time integral of this error current When Vg and thus the gain is stable the rectified current in Q1 must on average ex actly balance the current in the AD590 If the output of A2
8. AD602 G 30dB 60 BOTH R 5002 7 Vin 0V Rg 500 80 100k 1M 10M 100M FREQUENCY Hz Figure 51 PSRR vs Frequency 19 Figure 46 Transient Response Medium and High Gain Pf S stom TT tT Pet TT Figure 49 Transient Response Minimum Gain AD600 CH1 G 40dB Vy 0 0 CH2 G 20dB Vy 100mV AD602 CH1 G 30dB Vy 0 10 CH2 G 10dB Vy 316mV 20 BOTH Vour 1V RMS Rs 509 AD600 R 5000 CH1 Vout CROSSTALK 20log env Vin CROSSTALK dB L eo a AD602 80 90 100k 1M 10M 100M FREQUENCY Hz Figure 52 Crosstalk Between A1 and A2 vs Frequency AD600 AD602 OUTLINE DIMENSIONS Dimensions shown in inches and mm 16 Pin Plastic DIP N 16 Package 16 e 4 i 0 25 0 31 6 35 7 87 1 8 Y i PP SPSS SS T e 0 87 22 1 MAX gt uu 0 035 n 89 ied i 0 18 0 125 0 011 4 57 Ug 3 18 0 28 n e Ea e ms gt 0 3 7 62 l 0 018 0 46 0 033 0 84 pt 2 E 16 Pin SOIC R 16 Package dis 0 012 un 50 0030 Y uri 3 0 mA j een He ee oo 1 27 0 019 0 LE 042 REF 0 49 0 32 1 07 16 Pin Cerdip Q 16 Package 0 005 0 13 MIN 0 080 2 03 MAX gt e
9. arising directly from the fundamental and exact exponential attenuation of the ladder networks in the AD600 Typical results are presented for a sine wave input at 100 kHz Figure 20 shows that the output is held very close to the setpoint of 316 mV rms over an input range in excess of 80 dB REV A AD600 AD602 This system can of course be used as an AGC amplifier in which the rms value of the input is leveled Figure 21 shows the decibel output voltage More revealing is Figure 22 which shows that the deviation from the ideal output predicted by Equation 1 over the input range 80 uV to 500 mV rms is within 450 425 400 375 350 325 300 275 250 225 200 175 150 10uV 100uV 1mV 10mV 100mv 1V 10V INPUT SIGNAL V RMS Vout mV Figure 20 The RMS Output of A2 Is Held Close to the Setpoint 316 mV for an Input Range of Over 80 dB 5 4 3 Vout Volts 10uV 100uV 1mV 10mV 100mv 1V 10V INPUT SIGNAL V RMS Figure 21 The dB Output of Figure 19 s Circuit Is Linear Over an 80 dB Range 2 5 2 0 OUTPUT ERROR dB 10uV 100uV 1mV 10mV 100mv 1V 10V INPUT SIGNAL V RMS Figure 22 Data from Figure 20 Pres
10. network usually just a capacitor that rejects the dc offset The nominal gain range is now 2 dB to 82 dB for the AD600 or 22 dB to 62 dB for the AD602 There are several options in connecting the gain control inputs The choice depends on the desired signal to noise ratio SNR and gain error output ripple The following examples feature the AD600 the arguments generally apply to the AD602 with appropriate changes to the gain values Sequential Mode Maximum S N Ratio In the sequential mode of operation the SNR is maintained at its highest level for as much of the gain control range possible as shown in Figure 2 Note here that the gain range is 0 dB to 80 dB Figure 3 shows the general connections to accomplish this Both gain control inputs C1HI and C2HI are driven in parallel by a positive only ground referenced source with a range of 0 V to 2 5 V 85 S N RATIO dB a a Figure 2 S N Ratio vs Control Voltage Sequential Control 1 MHz Bandwidth AD600 AD602 lt lt Ai p l 40 00dB 41 07dB OUTPUT INPUT 40 00dB AT07dB 42 14dB onde Aj 0dB C1HI C1LO C1HI C1LO PE Vea Ve2 Vo1 0 592V Vo2 1 908V Vo 20V m 0 51dB 1 07dB OUTPUT INPUT 41 07dB 40 56dB H 63dB 41 07dB dnd 0dB C1HI CiLlO 5 Ve2 Vo2 1 908V Vc 1 25V b 0dB 38 93dB OUTPUT INPUT 41 07dB 41
11. 40 C to 85 C R 16 Pin 13 VPOS Positive Supply for Both Amplifiers AD602AQ 10 dB to 30 dB 40 C to 85 C Q 16 Pin 14 A1OP CHI Output 40 85 AD602AR BOERS ROSE lege ots 853C RFLG Pin 15 AICM CHI Common Usually Taken to CH1 AD600JR 0 dB to 40 dB 0 C to 70 C R 16 Pin 16 C1HI CH1 Gain Control Input HI Positive AD602 N 10 dB to 30 dB 0 C to 70 C N 16 Voltage Increases CH1 Gain AD602JR 10 dB to 30 dB 0 C to 70 C R 16 AD600SQ 883B 0 dB to 40 dB 55 C to 150 C Q 16 CONNECTION DIAGRAM 3 o o AD602SQ 883B 10 dB to 30 dB 55 C to 150 C Q 16 16 Pin Plastic DIP N Package NOTES 16 Pin Plastic SOIC R Package Plastic DIP Q Cerdip R Small Outline IC SOIC Refer to AD600 AD602 Military data sheet Also available as 5962 9457201 MPA Refer to AD600 AD602 Military data sheet Also available as 5962 9457202MPA CAUTION A1HI ame A1LO SEA A10P GAT1 pi GAT2 om ic A2LO rake A2HI ols Fe C2LO C2HI om AD600 AD602 16 Pin Cerdip Q Package ESD electrostatic discharge sensitive device Permanent damage may occur on unconnected devices subject to high energy electrostatic fields Unused devices must be stored in conductive foam or shunts The protective foam should be discharged to the destination socket before devices are removed WARNING WA NRT ate ESD SENSITIVE DEVICE REV A AD600 AD602 THEORY OF OPERATION The AD6
12. The polarity of the gain control voltage may be reversed and the control voltage inputs C1HI and C1LO reversed to achieve the same effect The gain control voltage can be supplied by a voltage output DAC such as the AD7242 which contains two complete DACs operates from 5 V supplies has an internal reference of 3 V and provides 3 V of output swing As such it is well suited for use with the AD600 AD602 needing only a few resistors to scale the output voltage of the DACs to the levels needed by the AD600 AD602 CONTROL VOLTAGE VOLTAGE OUTPUT DAC 625mV Figure 11 The Simplest Application of the X AMP Is as a TGC or TVG Amplifier in Ultrasound or Sonar Only the A1 Connections Are Shown for Simplicity Increasing Output Drive The AD600 AD602 s output stage has limited capability for negative load driving capability For driving loads less than 500 Q the load drive may be increased by about 5 mA by con necting a 1 kQ pull down resistor from the output to the nega tive supply Figure 12 Driving Capacitive Loads For driving capacitive loads of greater than 5 pF insert a 10 Q resistor between the output and the load This lowers the possi bility of oscillation GAIN CONTROL VOLTAGE PULL DOWN RESISTOR Figure 12 Adding a 1 kQPull Down Resistor Increases the X AMP s Output Drive by About 5 mA Only the A1 Con nections Are Shown for Simplicity Realizing Other Gain Ranges Larger gain ranges can
13. allows the use of a high impedance coupling network C1 R3 which introduces a high pass corner at about 12 Hz An input attenuator of 10 dB X0 316 is now provided by R1 R2 operating in conjunction with the AD600 s input resistance of 100 Q The adjustment provides exact calibration of the logarithmic intercept Vggr in critical applications but R1 and R2 may be replaced by a fixed resistor of 215 Q if very close calibration is not needed since the input resistance of the AD600 and all other key parameters of it and the AD636 are already laser trimmed for accurate opera tion This attenuator allows inputs as large as 4 V to be ac cepted that is signals with an rms value of 1 V combined with a crest factor of up to 4 The output of A2 is ac coupled via another 12 Hz high pass fil ter formed by C2 and the 6 7 kQ input resistance of the AD636 The averaging time constant for the rms dc converter is deter mined by C4 The unbuffered output of the AD636 at Pin 8 is compared with a fixed voltage of 316 mV set by the positive supply voltage of 6 V and resistors R6 and R7 Vggg is pro portional to this voltage and systems requiring greater calibra tion accuracy should replace the supply dependent reference with a more stable source AT2 Any difference in these voltages is integrated by the op amp U3B with a time constant of 3 ms formed by the parallel sum of R6 R7 and C3 Now if the output of the AD600 is too high V rms will
14. are available in a 16 pin cerdip Q pack age and are MIL STD 883 compliant The AD600S and AD602S are also available under DESC SMD 5962 94572 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD600 AD602 SPEC FI CATI 0 NS Each amplifier section at T 25 C V 5 V 625 mV lt Veg lt 625 mV R 500 and 5 pF unless otherwise noted Specifications for AD600 and AD602 are identical unless otherwise noted AD600J AD602J AD600A AD602A Parameter Conditions Min Typ Max Min Typ Max Units INPUT CHARACTERISTICS Input Resistance Pins 2 to 3 Pins 6 to 7 98 100 102 95 100 105 Q Input Capacitance 2 2 pF Input Noise Spectral Density 1 4 1 4 nV VHz Noise Figure Rs 50 Q Maximum Gain 5 3 5 3 dB Rs 200 Q Maximum Gain 2 2 dB Common Mode Rejection Ratio f 100 kHz 30 30 dB OUTPUT CHARACTERISTICS 3 dB Bandwidth Vout 100 mV rms 35 35 MHz Slew Rate 275 275 V us Peak Output Ry 2 500 Q t25 3 t2 5 t3 V Output Impedance f lt 10 MHz 2 2 Q Output Short Circuit Current 50 50 mA Group Delay Change vs Gain f 3 MHz Full Gain Range 2 2 ns Group Delay Change vs Frequency Ve 0 V f 1 MHz to 10 MHz 2 2 ns Total Harmonic Distortion Rj 200 Q Vour 1 V Peak Rpd 1 kQ 60 60 dBc ACCURACY AD600 Gain Error 0 dB to 3 dB Gain 0 0 5 1 0 5 0 5 0 5 dB 3 dB to 37 dB Gain 0 5 0 2 0 5 0 1 0 2 1 0 dB 37 dB to 40 dB Gain 1 0 5 0 1 5 0 5
15. be greater than the setpoint of 316 mV causing the output of U3B that is Voyr to ramp up note that the inte grator is noninverting A fraction of Vopr is connected to the inverting gain control inputs of the AD600 so causing the gain to be reduced as required until V rms is exactly equal to 316 mV at which time the ac voltage at the output of A2 is forced to be exactly 316 mV rms This fraction is set by R4 and R5 such that a 15 625 mV change in the control voltages of Al and A2 which would change the gain of the cascaded amplifi ers by 1 dB requires a change of 100 mV at Vour Notice here that since A2 is forced to operate at an output level well below its capacity waveforms of high crest factor can be tolerated throughout the amplifier To check the operation assume an input of 10 mV rms is ap plied to the input which results in a voltage of 3 16 mV rms at the input to A1 due to the 10 dB loss in the attenuator If the system operates as claimed Voyr and hence Vg should be zero This being the case the gain of both Al and A2 will be 20 dB and the output of the AD600 will therefore be 100 times 40 dB greater than its input which evaluates to 316 mV rms the input required at the AD636 to balance the loop Finally note that unlike most AGC circuits needing strong temperature compensation for the internal kT q scaling these voltages and thus the output of this measurement system are tempera ture stable
16. defined by an internal voltage reference The response time of this interface is less than 1 us Each channel also has an independent gating facility that optionally blocks sig nal transmission and sets the dc output level to within a few mil livolts of the output ground The gating control input is TTL and CMOS compatible The maximum gain of the AD600 is 41 07 dB and that of the AD602 is 31 07 dB the 3 dB bandwidth of both models is nominally 35 MHz essentially independent of the gain The signal to noise ratio SNR for a 1 V rms output and a 1 MHz noise bandwidth is typically 76 dB for the AD600 and 86 dB for the AD602 The amplitude response is flat within 0 5 dB from 100 kHz to 10 MHz over this frequency range the group delay varies by less than 2 ns at all gain settings Each amplifier channel can drive 100 Q load impedances with low distortion For example the peak specified output is t 2 5 V minimum into a 500 Q load or 1 V into a 100 Q load For a 200 Q load in shunt with 5 pF the total harmonic distortion for a t1 V sinusoidal output at 10 MHz is typically 60 dBc The AD600J and AD602 are specified for operation from 0 C to 70 C and are available in both 16 pin plastic DIP N and 16 pin SOIC R The AD600A and AD602A are specified for operation from 40 C to 85 C and are available in both 16 pin cerdip Q and 16 pin SOIC R The AD600S and AD602S are specified for operation from 55 C to 125 C and
17. of U1B and the S N ratio pro 200 1uV 10uV 100uiV 1mV 10mV 100mV 1V 10V gressively decreases INPUT SIGNAL V RMS Once UIB reaches its maximum gain of 41 07 dB its output Figure 32 Vagc Remains Nose to Its Setpoint of also becomes a gain independent noise source this noise is pre 316 mV RMS Over the Full 120 dB Range sented to U2A As the control voltage is further increased the gains of both U1A and UIB remain fixed at their maximum 90 value of 41 07 dB and the S N ratio continues to decrease Fig ure 34 clearly shows this because the maximum S N ratio of 90 dB is extended for the first 40 dB of input signal before it 70 starts to roll off a 0 This arrangement of staggered gains can be easily implemented B because when the control inputs of the AD600 are overdriven g the gain limits to its maximum or minimum values without side 40 effects This eliminates the need for awkward nonlinear shaping 5 circuits that have previously been used to break up the gain range of multistage AGC amplifiers It is the precise values of 20 the AD600 s maximum and minimum gain not 0 dB and 7 40 dB but 1 07 dB and 41 07 dB that explain the rather odd values of the offset values that are used 33 2 625 0 416 6 208 3 0 208 3 416 6 625 0 833 2 The optimization of the output S N ratio is of obviou
18. resistance of the AD636 rms converter REV A The rms value of Vi og is generated at Pin 8 of the AD636 the averaging time for this process is determined by C5 and the value shown results in less than 1 rms error at 20 Hz The slowly varying V rms is compared with a fixed reference of 316 mV derived from the positive supply by R10 R11 Any dif ference between these two voltages is integrated in C6 in con junction with op amp U3C the output of which is Vrog A fraction of this voltage determined by R12 and R13 is returned to the gain control inputs of all AD600 sections An increase in Vioc lowers the gain because this voltage is connected to the inverting polarity control inputs Now in this case the gains of all three VCA sections are being varied simultaneously so the scaling is not 32 dB V but 96 dB V or 10 42 mV dB The fraction of Vi oq required to set its scaling to 50 mV dB is therefore 10 42 50 or 0 208 The result ing full scale range of Vi oa is nominally 2 5 V This scaling was chosen to allow the circuit to operate from 5 V supplies Optionally the scaling could be altered to 100 mV dB which would be more easily interpreted when V og is displayed on a DVM by increasing R12 to 25 5 kQ The full scale output of 5 V then requires the use of supply voltages of at least t 7 5 V A simple attenuator of 16 6 1 25 dB is formed by R2 R3 and the 100 Q input resistance of the AD600 This allows the refer ence lev
19. to 1 V for maximum gain This prevents Q1 from going into heavy saturation at low gains and leaves suffi cient headroom of 4 V for the AD590 to operate correctly at high gains when using a 5 V supply In fact the 6 dB interstage attenuator means that the overall gain of this AGC system actually runs from 6 dB to 74 dB Thus an input of 2 V rms would be required to produce a 1 V rms output at the minimum gain which exceeds the 1 V rms maximum input specification of the AD600 The available gain range is therefore 0 dB to 74 dB or X1 to X5000 Since the gain scaling is 15 625 mV dB because of the cascaded stages the minimum value of Vg is actually increased by 6 x 15 625 mV or about 94 mV to 156 mV so the risk of saturation in Q1 is reduced REV A AD600 AD602 The emitter circuit of Q1 is somewhat inductive due its finite f and base resistance Consequently the effective value of R2 in creases with frequency This would result in an increase in the stabilized output amplitude at high frequencies but for the ad dition of C3 determined experimentally to be 15 pF for the 2N3904 for maximum response flatness Alternatively a faster transistor can be used here to reduce HF peaking Figure 16 shows the ac response at the stabilized output level of about 1 3 V rms Figure 17 demonstrates the output stabilization for sine wave inputs of 1 mV to 1 V rms at frequencies of 100 kHz 1 MHz and 10 MHz
20. 00 and AD602 have the same general design and fea tures They comprise two fixed gain amplifiers each preceded by a voltage controlled attenuator of 0 dB to 42 14 dB with in dependent control interfaces each having a scaling factor of 32 dB per volt The gain of each amplifier in the AD600 is laser trimmed to 41 07 dB X113 thus providing a control range of 1 07 dB to 41 07 dB 0 dB to 40 dB with overlap while the AD602 amplifiers have a gain of 31 07 dB X35 8 and provide an overall gain of 11 07 dB to 31 07 dB 10 dB to 30 dB with overlap The advantage of this topology is that the amplifier can use negative feedback to increase the accuracy of its gain also since the amplifier never has to handle large signals at its input the distortion can be very low A further feature of this approach is that the small signal gain and phase response and thus the pulse response are essentially independent of gain The following discussion describes the AD600 Figure 1 is a simplified schematic of one channel The input attenuator is a seven section R 2R ladder network using untrimmed resistors of nominally R 62 5 Q which results in a characteristic resis tance of 125 Q 20 A shunt resistor is included at the input and laser trimmed to establish a more exact input resistance of 100 Q 2 which ensures accurate operation gain and HP corner frequency when used in conjunction with external resis tors or capacitors ant PREC
21. 02 75 70 S N RATIO dB OVERALL GAIN dB 35 30 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 Figure 5 Plot of Separate and Overall Gains in Sequential Figure 8 SNR for Cascaded Stages Parallel Control Control 1 2 1 0 0 8 0 6 0 4 0 2 0 0 02 0 4 0 6 1 6 0 8 ES d 1 0 oO N WO A CO GAIN ERROR dB N GAIN ERROR dB 8 1 2 0 5 0 0 0 5 1 0 1 5 2 0 2 5 3 0 0 0 0 1 0 2 0 3 0 4 0 5 06 0 7 08 0 9 1 0 1 1 1 2 1 3 Vc Vc Figure 6 Gain Error for Cascaded Stages Sequential Figure 9 Gain Error for Cascaded Stages Low Ripple Control Mode GAIN ERROR dB L S N RATIO dB 35 01 0 0 2 0 4 0 6 0 8 1 0 1 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 Vc Vc Figure 7 Gain Error for Cascaded Stages Parallel Figure 10 ISNR vs Control Voltage Low Ripple Mode Control REV A 7 AD600 AD602 APPLICATIONS The full potential of any high performance amplifier can only be realized by careful attention to details in its applications The following pages describe fully tested circuits in which many such details have already been considered However as is always tru
22. 07dB 2 14dB 41 07dB 80dB 0dB C1HI C1LO C1HI CiLO r Vea Ve2 Vo1 0 592V Vo2 1 908V Vo 25V c Figure 3 AD600 Gain Control Input Calculations for Sequential Control Operation The gains are offset Figure 4 such that A2 s gain is increased only after Al s gain has reached its maximum value Note that for a differential input of 700 mV or less the gain of a single amplifier A1 or A2 will be at its minimum value of 1 07 dB for a differential input of 700 mV or more the gain will be at its maximum value of 41 07 dB Control inputs beyond these limits will not affect the gain and can be tolerated without dam age or foldover in the response See the Specifications Section of this data sheet for more details on the allowable voltage range The gain is now Gain dB 32 Vo where Vc is the applied control voltage 3 41 07dB 38 93dB 1 07dB 0 592 0 0 625 20 1 25 40 25 80 Vc V 82 14 GAIN OFFSET OF 1 07dB OR 33 44mV Figure 4 Explanation of Offset Calibration for Sequential Control When Vc is set to zero Va 0 592 V and the gain of Al is 1 07 dB recall that the gain of each amplifier section is 0 dB for Vg 625 mV meanwhile VG 1 908 V so the gain of A2 is 1 07 dB The overall gain is thus 0 dB see Figure 3a When Vc 1 25 V Vg 1 25 V 0 592 V 0 658 V which sets the gain of Al to 40 56 dB while Vg 1 25 V 1 908 V 0 658 V which s
23. D 0 Abeod O ANALOG DEVICES Dual Low Noise Wideband Variable Gain Amplifiers AD600 AD602 FEATURES Two Channels with Independent Gain Control Linear in dB Gain Response Two Gain Ranges AD600 0 dB to 40 dB AD602 10 dB to 30 dB Accurate Absolute Gain 0 3 dB Low Input Noise 1 4 nV VHz Low Distortion 60 dBc THD at 1 V Output High Bandwidth DC to 35 MHz 3 dB Stable Group Delay 2 ns Low Power 125 mW max per Amplifier Signal Gating Function for Each Amplifier Drives High Speed A D Converters MIL STD 883 Compliant and DESC Versions Available APPLICATIONS Ultrasound and Sonar Time Gain Control High Performance Audio and RF AGC Systems Signal Measurement PRODUCT DESCRIPTION The AD600 and AD602 dual channel low noise variable gain amplifiers are optimized for use in ultrasound imaging systems but are applicable to any application requiring very precise gain low noise and distortion and wide bandwidth Each indepen dent channel provides a gain of 0 dB to 40 dB in the AD600 and 10 dB to 30 dB in the AD602 The lower gain of the AD602 results in an improved signal to noise ratio at the out put However both products have the same 1 4 nVNHz input noise spectral density The decibel gain is directly proportional to the control voltage is accurately calibrated and is supply and temperature stable To achieve the difficult performance objectives a proprietary circuit form the K AMP h
24. ISION PASSIVE EA INPUT ATTENUATOR HA SCALING REFERENCE Q A10P GAIN CONTROL INTERFACE MA 2 24kO AD600 6940 AD602 FIXED GAIN AMPLIFIER 41 07dB AD600 31 07dB AD602 Figure 1 Simplified Block Diagram of Single Channel of the AD600 and AD602 The nominal maximum signal at input AIHI is 1 V rms 41 4 V peak when using the recommended 5 V supplies although operation to 2 V peak is permissible with some increase in HF distortion and feedthrough Each attenuator is provided with a separate signal LO connection for use in rejecting common mode the voltage between input and output grounds Circuitry is included to provide rejection of up to 100 mV The signal applied at the input of the ladder network is attenu ated by 6 02 dB by each section thus the attenuation to each of the taps is progressively 0 6 02 12 04 18 06 24 08 30 1 36 12 and 42 14 dB A unique circuit technique is employed to inter polate between these tap points indicated by the slider in Fig ure 1 providing continuous attenuation from 0 dB to 42 14 dB It will help in understanding the AD600 to think in terms of a mechanical means for moving this slider from left to right in fact it is voltage controlled The details of the control interface are discussed later Note that the gain is at all times exactly de termined and a linear decibel relationship is automatically guar anteed between the gain and the control parameter wh
25. antly The reduction in noise and spurious signal feedthrough is useful in ultrasound beam forming applications where many amplifier outputs are summed REV A Common Mode Rejection A special circuit technique is used to provide rejection of volt ages appearing between input grounds A1LO and A2LO and output grounds AICM and A2CM This is necessary because of the op amp form of the amplifier as shown in Figure 1 The feedback voltage is developed across the resistor RF1 which to achieve low noise has a value of only 20 O The voltage developed across this resistor is referenced to the input common so the output voltage is also referred to that node To provide rejection of this common voltage an auxiliary ampli fier not shown is included which senses the voltage difference between input and output commons and cancels this error component Thus for zero differential signal input between A1HI and A1LO the output A1OP simply follows the voltage at A1CM Note that the range of voltage differences which can ex ist between AILO and AICM or A2LO and A2CM is limited to about 100 mV Figure 50 one of the typical performance curves at the end of this data sheet shows typical common mode rejection ratio versus frequency ACHIEVING 80 dB GAIN RANGE The two amplifier sections of the X AMP can be connected in series to achieve higher gain In this mode the output of A1 A1OP and A1 CM drives the input of A2 via a high pass
26. as been developed Each channel of the X AMP comprises a variable attenuator of 0 dB to 42 14 dB followed by a high speed fixed gain amplifier In this way the amplifier never has to cope with large inputs and can benefit from the use of negative feedback to precisely define the gain and dynamics The attenuator is realized as a seven stage R 2R ladder network having an input resistance of 100 Q laser trimmed to 2 The attenuation between tap points is 6 02 dB the gain control circuit provides continuous interpolation be tween these taps The resulting control function is linear in dB X AMP is a registered trademark of Analog Devices Inc Patented REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM on PRECISION PASSIVE INPUT ATTENUATOR EL EL SCALING REFERENCE A10P GAIN CONTROL INTERFACE E 2 24k0 AD600 6940 AD602 RF1 A1HI O me AILO R 2R LADDER NETWORK FIXED GAIN AMPLIFIER 41 07dB AD600 31 07dB AD602 The gain control interfaces are fully differential providing an input resistance of 15 MQ and a scale factor of 32 dB V that is 31 25 mV dB
27. be accommodated by cascading amplifi ers Combinations built by cascading two amplifiers include 20 dB to 60 dB using one AD602 10 dB to 70 dB 1 2 of an AD602 followed by 1 2 of an AD600 and 0 dB to 80 dB one AD600 In multiple channel applications extra protection against oscillations can be provided by using amplifier sections from different packages An Ultralow Noise VCA The two channels of the AD600 or AD602 may be operated in parallel to achieve a 3 dB improvement in noise level providing 1 nV VHz without any loss of gain accuracy or bandwidth In the simplest case as shown in Figure 13 the signal inputs A1HI and A2HI are tied directly together the outputs AlOP and A2OP are summed via R1 and R2 100 Q each and the control inputs CIHI C2HI and C1LO C2LO operate in paral lel Using these connections both the input and output resis tances are 50 Q Thus when driven from a 50 Q source and terminated in a 50 Q load the gain is reduced by 12 dB so the gain range becomes 12 dB to 28 dB for the AD600 and 22 dB to 18 dB for the AD602 The peak input capability remains unaffected 1 V rms at the IC pins or 2 V rms from an unloaded 50 Q source The loading on each output with a 50 Q load is effectively 200 Q because the load current is shared between the two channels so the overall amplifier still meets its specified maximum output and distortion levels for a 200 Q load This amplifier can deliver a maximum s
28. ded to extend the nominal conversion range to 120 dB with the inclusion of simple LP filters of the type shown in Fig ure 15 Very low errors can then be maintained over a 100 dB range OUTPUT ERROR dB 10uV 100uV 1mV 10mV 100mv 1V 10V INPUT SIGNAL V RMS Figure 24 Using the 3 dB Offset Network the Ripple Is Reduced 13 AD600 AD602 INPUT 1V RMS MAX SINE WAVE 0 1uF 45V DEC FB 5V DEC Js 0 14F FB 5v POWER SUPPLY DECOUPLING NETWORK 5V DEC Q R15 19 6k2 R16 Q1 6 65k2 2N3906 mia V 4 301kQ hia R12 spiko 11 3kQ R7 R8 R9 1270 1270 10kQ V 45V DEC 4JyuF MED Qs x 1 4 316 2mV AD713 V NC NO CONNECT Figure 25 RMS Responding AGC Circuit with 100 dB Dynamic Range 100 dB to 120 dB RMS Responding Constant Bandwidth AGC Systems with High Accuracy dB Outputs The next two applications double as both AGC amplifiers and measurement systems In both precise gain offsets are used to achieve either 1 a very high gain linearity of 0 1 dB over the full 100 dB range or 2 the optimal signal to noise ratio at any gain A 100 dB RMS AGC System with Minimal Gain Error Parallel Gain with Offset Figure 25 shows an rms responding AGC circuit which can equally well be used as an accurate measurement system It accepts inputs of 10 uV to 1 V rms 100 dBV to 0 dBV with generous
29. e of high accuracy high speed analog circuits the schematic is only part of the story this is no less true for the AD600 and AD602 Appropriate choices in the overall board layout and the type and placement of power supply decoupling components are very important As explained previously the input grounds A1LO and A2LO must use the shortest possible connections The following circuits show examples of time gain control for ultrasound and for sonar methods for increasing the output drive and AGC amplifiers for audio and RF IF signal process ing using both peak and rms detectors These circuits also illus trate methods of cascading X AMPs for either maintaining the optimal S N ratio or maximizing the accuracy of the gain control voltage for use in signal measurement These AGC cir cuits may be modified for use as voltage controlled amplifiers for use in sonar and ultrasound applications by removing the detector and substituting a DAC or other voltage source for supplying the control voltage Time Gain Control TGC and Time Variable Gain TVG Ultrasound and sonar systems share a similar requirement both need to provide an exponential increase in gain in response to a linear control voltage that is a gain control that is linear in dB Figure 11 shows the AD600 AD602 configured for a con trol voltage ramp starting at 625 mV and ending at 625 mV for a gain control range of 40 dB For simplicity only the Al connections are shown
30. e AD600 were preceded for example by a 900 Q resistor to allow operation from inputs up to 10 V rms However in most cases the low impedance of the source will limit the maximum noise resistance It will be apparent from the foregoing that it is essential to use a low resistance in the design of the ladder network to achieve low noise In some applications this may be inconvenient requiring the use of an external buffer or preamplifier However very few amplifiers combine the needed low noise with low distortion at maximum input levels and the power consumption needed to achieve this performance is fundamentally required to be quite high due to the need to maintain very low resistance values while also coping with large inputs On the other hand there is little value in providing a buffer with high input impedance since the usual reason for this the minimization of loading of a high resistance source is not compatible with low noise Apart from the small variations just discussed the signal to noise S N ratio at the output is essentially independent of the attenuator setting since the maximum undistorted output is 1 V rms and the NSD at the output of the AD600 is fixed at 113 times 1 4 nV VHz or 158 nV VHz Thus in a 1 MHz band width the output S N ratio would be 76 dB The input NSD of the AD600 and AD602 are the same but because of the 10 dB lower gain in the AD602 s fixed amplifier its output S N ratio is 10 dB be
31. e and in Figure 34 decreases for more positive values of the gain control voltage REV A AD600 AD602 20 In contrast the S N ratio for the sequential mode is shown in 7 Figure 34 U1A always acts as a fixed noise source varying its gain has no influence on the output noise This is a feature of 1 0 the X AMP technique Thus for the first 40 dB of control a range actually slightly more as explained below when only 3 23 this VCA section has its gain varied the S N ratio remains con 9 T stant During this time the gains of U1B and U2A are at their T 0 2 minimum value of 1 07 dB z a 0 5 o 90 1 0 80 1 5 70 2 0 60 iuV 10V 100V 1mV 10mV 100mV iV 10v m INPUT SIGNAL V RMS 5 E Figure 31 The Error Ripple Due to the Individual Gain E 40 Functions 30 400 20 10 0 350 1 183 0 558 0 067 0 692 1 317 1 942 2 567 3 192 3 817 z CONTROL VOLTAGE Vc 31 25mV dB Volts 1 tc amp 300 Figure 34 S N Ratio vs Control Voltage for Sequential E Gain Control Figure 29 3 For the next 40 dB of control range the gain of U1A remains 250 fixed at its maximum value of 41 07 dB and only the gain of UIB is varied while that of U2A remains at its minimum value of 1 07 dB In this interval the fixed output noise of U1A is amplified by the increasing gain
32. el of the decibel output to be precisely set to zero for an input of 2 16 mV rms and thus center the 100 dB range be tween 10 uV and 1 V In many applications R2 R3 may be re placed by a fixed resistor of 590 Q For example in AGC applications neither the slope nor the intercept of the logarith mic output is important A few additional components R14 R16 and Q1 improve the accuracy of Vi og at the top end of the signal range that is for small gains The gain starts rolling off when the input to the first amplifier U1A reaches 0 dB To compensate for this non linearity Q1 turns on at Vi oG 1 5 V and increases the feed back to the control inputs of the AD600s thereby needing a smaller voltage at Vr oc to maintain the input to the AD636 to the setpoint of 316 mV rms A 120 dB RMS AGC System with Optimal S N Ratio Sequential Gain In the last case all gains were adjusted simultaneously resulting in an output signal to noise ratio S N ratio which is always less than optimal The use of sequential gain control results in a ma jor improvement in S N ratio with only a slight penalty in the accuracy of Vi og and no penalty in the stabilization accuracy of Vacc Ihe idea is simply to increase the gain of the earlier stages first as the signal level decreases and thus maintain the highest S N ratio throughout the amplifier chain This can be easily achieved with the AD600 because its gain is accurate even when the control inpu
33. ented as the Deviation from the Ideal Output Given in Equation 4 REV A 0 5 dB and within 1 dB for the 80 dB range from 80 uV to 800 mV By suitable choice of the input attenuator R1 R2 this could be centered to cover any range from 25 mV to 250 mV to say 1 mV to 10 V with appropriate correction to the value of Vggr Note that Vscarz is not affected by the changes in the range The gain ripple of 0 2 dB seen in this curve is the re sult of the finite interpolation error of the X AMP Note that it occurs with a periodicity of 12 dB twice the separation be tween the tap points because of the two cascaded stages This ripple can be canceled whenever the X AMP stages are cascaded by introducing a 3 dB offset between the two pairs of control voltages A simple means to achieve this is shown in Figure 23 the voltages at C1HI and C2HI are split by 46 875 mV or t 1 5 dB Alternatively either one of these pins can be individually offset by 3 dB and a 1 5 dB gain adjustment made at the input attenuator R1 R2 J 3dB OFFSET MODIFICATION NC NO CONNECT Figure 23 Reducing the Gain Error Ripple The error curve shown in Figure 24 demonstrates that over the central portion of the range the output voltage can be main tained very close to the ideal value The penalty for this modifi cation is the higher errors at the extremities of the range The next two applications show how three amplifier sections can be casca
34. ets A2 s gain at 0 56 dB The overall gain is now 40 dB see Figure 3b When Vc 2 5 V the gain of Al is 41 07 dB and that of A2 is 38 93 dB resulting in an overall gain of 80 dB see Figure 3c This mode of operation is further clarified by Figure 5 which is a plot of the separate gains of Al and A2 and the overall gain versus the control voltage Figure 6 is a plot of the gain error of the cascaded amplifiers versus the control voltage Parallel Mode Simplest Gain Control Interface In this mode the gain control voltage is applied to both inputs in parallel C1HI and C2HI are connected to the control volt age and CILO and C2LO are optionally connected to an offset voltage of 0 625 V The gain scaling is then doubled to 64 dB V requiring only 1 25 V for an 80 dB change of gain The am plitude of the gain ripple in this case is also doubled as shown in Figure 7 and the instantaneous signal to noise ratio at the output of A2 decreases linearly as the gain is increased Figure 8 Low Ripple Mode Minimum Gain Error As can be seen in Figures 6 and 7 the output ripple is periodic By offsetting the gains of Al and A2 by half the period of the ripple or 3 dB the residual gain errors of the two amplifiers can be made to cancel Figure 9 shows the much lower gain rip ple when configured in this manner Figure 10 plots the S N ratio as a function of gain it is very similar to that in the Par allel Mode REV A AD600 AD6
35. ference principle in thinly veiled disguise When we choose R2 such that the sum of the voltage across it and the Vgg of Q1 is close to the bandgap voltage of about 1 2 V Vour will be stable over a wide range of temperatures provided of course that Q1 and the AD590 share the same thermal environment 10 Since the average emitter current is 600 uA during each half cycle of the square wave a resistor of 833 Q would add a PTAT voltage of 500 mV at 300 K increasing by 1 66 mV C In prac tice the optimum value of R2 will depend on the transistor used and to a lesser extent on the waveform for which the tem perature stability is to be optimized for the devices shown and sine wave signals the recommended value is 806 Q This resistor also serves to lower the peak current in Q1 and the 200 Hz LP filter it forms with C2 helps to minimize distortion due to ripple in Vg Note that the output amplitude under sine wave condi tions will be higher than for a square wave since the average value of the current for an ideal rectifer would be 0 637 times as large causing the output amplitude to be 1 88 1 2 0 637 V or 1 33 V rms In practice the somewhat nonideal rectifier results in the sine wave output being regulated to about 1 275 V rms An offset of 375 mV is applied to the inverting gain control inputs CILO and C2LO Thus the nominal 625 mV to 625 mV range for Vg is translated upwards at Vg to 0 25 V for minimum gain
36. ge S 55 C to 125 C Pin 4 GATI CHI Gating Input A Logic HI Shuts Off Storage Temperature Range 65 C to 150 C CHI Signal Path Lead Temperature Range Soldering 60 sec 300 C Pin5 GAT2 CH2 Gating Input A Logic HI Shuts Off NOTES CH2 Signal Path Stresses above those listed under Absolute Maximum Ratings may cause Pin 6 A2LO CH2 Signal Input LO Usually Taken to permanent damage to the device This is a stress rating only and functional CH2 Input Ground operation of the device at these or any other conditions above those indicated in the ap E operational section of this specification is not implied Exposure to absolute Pin7 A2HI CH2 Signal Input HI Positive Voltage maximum rating conditions for extended periods may affect device reliability Increases CH2 Output Thermal Characteristics 16 Pin Plastic Package 054 85 C Watt i p di dee 16 Pin SOIC Package 6j 100 C Watt Pin 8 C2LO CH2 Gain Control Input LO Positive 16 Pin Cerdip Package 6j4 120 C Watt Voltage Reduces CH2 Gain Pin 9 C2HI CH2 Gain Control Input HI Positive ORDERING GUIDE Voltage Increases CH2 Gain Pin 10 A2CM CH2 Common Usually Taken to CH2 Gain Temperatue Package Output Ground Mods Range Range Option pin 1 A20P CH2 Output AD600AQ 0 dB to 40 dB 40 C to 85 C Q 16 Pin 12 VNEG Negative Supply for Both Amplifiers AD600AR 0 dB to 40 dB
37. ich determines the position of the slider In practice the gain devi ates from the ideal law by about 0 2 dB peak see for ex ample Figure 6 Note that the signal inputs are not fully differential AILO and A1CM for CH1 and A2LO and A2CM for CH2 provide separate access to the input and output grounds This recog nizes the practical fact that even when using a ground plane small differences will arise in the voltages at these nodes It is important that AILO and A2LO be connected directly to the input ground s significant impedance in these connections will reduce the gain accuracy AICM and A2CM should be con nected to the load ground s Noise Performance An important reason for using this approach is the superior noise performance that can be achieved The nominal resistance seen at the inner tap points of the attenuator is 41 7 Q one third of 125 Q which exhibits a Johnson noise spectral density NSD of 0 84 nV VHz that is VAKTR at 27 C which is a large fraction of the total input noise The first stage of the am plifier contributes a further 1 12 nV VHz for a total input noise of 1 4 nV VHz The noise at the 0 dB tap depends on whether the input is short circuited or open circuited when shorted the minimum NSD of 1 12 nV VHz is achieved when open the resistance of 100 Q at the first tap generates 1 29 nV VHz so the noise in creases to a total of 1 71 nV VHz This last calculation would be important if th
38. ifier As Vy increases in a positive di rection Q1 conducts more heavily and its r becomes lower while that of Q2 increases Conversely more negative values of Vin result in the r Of Q2 decreasing while that of Q1 increases The design is chosen such that the net emitter resistance is es sentially independent of the instantaneous value of Vw result ing in moderately low distortion Low values of resistance and moderately high bias currents are important in achieving the low noise wide bandwidth and low distortion of this preamplifier Heavy decoupling prevents noise on the power supply lines from being conveyed to the input of the X AMP Table I Measured Preamplifier Performance VH then the input noise of a X2 preamplifier must be X 3 4 times as large that is 1 2 nVAHz 45V GROUND 1000 Ry OF X AMP OUTPUT GROUND Figure 14 A Low Noise Preamplifier for the AD600 and AD602 REV A Measurement Value Unit Gain f 30 MHz 6 dB Bandwidth 3 dB 250 MHz Input Signal for 1 dB Compression 1 V p p Distortion Vin 200 mV p p HD2 0 27 HD3 0 14 Vin 500 mV p p HD2 0 44 HD3 0 58 System Input Noise 1 03 nV VHz Spectral Density NSD Preamp plus X AMP Input Resistance 1 4 kQ Input Capacitance 15 pF Input Bias Current 150 uA Power Supply Voltage 5 V Quiescent Current 15 mA A Low Noise AGC Amplifier with 80 dB Gain Range Figure 15 provides an example of the ease with which the
39. ine wave power of 10 dBm to the load REV A AD600 AD602 GAIN CONTROL VOLTAGE AD600 or AD602 Figure 13 An Ultralow Noise VCA Using the AD600 or AD602 A Low Noise 6 dB Preamplifier In some ultrasound applications the user may wish to use a high input impedance preamplifier to avoid the signal attenua tion that would result from loading the transducer by the 100 Q input resistance of the X AMP High gain cannot be tolerated because the peak transducer signal is typically 0 5 V while the peak input capability of the AD600 or AD602 is only slightly more than 1 V A gain of two is a suitable choice It can be shown that if the preamplifier s overall referred to input RTT noise is to be the same as that due to the X AMP alone 1 4 nV An inexpensive circuit using complementary transistor types chosen for their low rep is shown in Figure 14 The gain is de termined by the ratio of the net collector load resistance to the net emitter resistance that is it is an open loop amplifier The gain will be X2 6 dB only into a 100 Q load assumed to be provided by the input resistance of the X AMP R2 and R7 are in shunt with this load and their value is important in defining the gain For small signal inputs both transistors contribute an equal transconductance which is rendered less sensitive to sig nal level by the emitter resistors R4 and R5 which also play a dominant role in setting the gain This is a Class AB ampl
40. is too small to do this Vg will ramp up causing the gain to in crease until Q1 conducts sufficiently The operation of this control system will now be described in detail First consider the particular case where R2 is zero and the out put voltage Vour is a square wave at say 100 kHz that is well above the corner frequency of the control loop During the time Vovr is negative Q1 conducts when Vout is positive it is cut off Since the average collector current is forced to be 300 WA and the square wave has a 50 duty cycle the current when con ducting must be 600 uA With R2 omitted the peak value of Vour would be just the Vgg of Q1 at 600 pA typically about 700 mV or 2 Vgg peak to peak This voltage hence the ampli tude at which the output stabilizes has a strong negative tem perature coefficient TC typically 1 7 mV C While this may not be troublesome in some applications the correct value of R2 will render the output stable with temperature To understand this first note that the current in the AD590 is closely proportional to absolute temperature PTAT In fact this IC is intended for use as a thermometer For the moment continue to assume that the signal is a square wave When Q1 is conducting Vopr is the now the sum of Vgg and a voltage which is PTAT and which can be chosen to have an equal but opposite TC to that of the base to emitter voltage This is actually noth ing more than the bandgap voltage re
41. namic range typically only 50 dB More troublesome is that the bandwidth is roughly pro portional to the signal level for example the AD636 provides a 3 dB bandwidth of 900 kHz for an input of 100 mV rms but has a bandwidth of only 100 kHz for a 10 mV rms input Its logarithmic output is unbuffered uncalibrated and not stable over temperature considerable support circuitry including at least two adjustments and a special high TC resistor is required to provide a useful output All of these problems can be eliminated using an AD636 as merely the detector element in an AGC loop in which the differ ence between the rms output of the amplifier and a fixed dc ref erence are nulled in a loop integrator The dynamic range and the accuracy with which the signal can be determined are now entirely dependent on the amplifier used in the AGC system Since the input to the rms dc converter is forced to a constant amplitude close to its maximum input capability the band width is no longer signal dependent If the amplifier has an ex actly exponential linear dB gain control law its control voltage VG is forced by the AGC loop to be have the general form VIN RMS REF Vour Vscare log 10 4 Figure 19 shows a practical wide dynamic range rms responding measurement system using the AD600 Note that the signal out put of this system is available at A2OP and the circuit can be used as a wideband AGC amplifier with an rms responding de
42. nt noise sources Using resistive loads of 500 Q or greater or with the addition of a 1 KQ pull down resistor when driving lower loads 3The dc gain of the main amplifier in the AD600 is X113 thus an input offset of only 100 uV becomes an 11 3 mV output offset In the AD602 the amplifier s gain is X35 7 thus an input offset of 100 uV becomes a 3 57 mV output offset Specifications shown in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels All min and max specifications guaranteed although only those shown in boldface are tested on all production units Specifications subject to change without notice REV A AD600 AD602 ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Supply Voltage Vs sss 7 5 V Input Voltages Pin Function Description i a 2 A z A dM EE FECHA Eo Pinl CILO CHI Gain Control Input LO Positive 5193 05 MUS tte ant e tp RE ENS Ee t Voltage Reduces CH1 Gain ET tV for 10 ms EM m Pins A tbe ah suos coste sd se ooi cashes V Pin2 AIHI CHI Signal Input HI Positive Voltage Internal Power Dissipation 0005 600 mW Increases CH1 Output Operating Temperature Range J 0 C to 70 C_ Pin3 AILO CHI Signal Input LO Usually Taken to Operating Temperature Range A 40 C to 85 C CHI Input Ground Operating Temperature Ran
43. overrange Figure 26 shows the logarithmic output Vtoc Which is accurately scaled 1 V per decade that is 50 mV dB with an intercept Vrog 0 at 3 16 mV rms 50 dBV Gain offsets of 2 dB have been introduced between the amplifiers provided by the 62 5 mV introduced by R6 R9 These offsets cancel a small gain ripple which arises in the X AMP from its finite interpolation error which has a period of 18 dB in the individual VCA sections The gain ripple of all three amplifier sections without this offset in which case the gain errors simply add is shown in Figure 27 it is still a 14 remarkably low 0 25 dB over the 108 dB range from 6 uV to 1 5 V rms However with the gain offsets connected the gain linearity remains under 0 1 dB over the specified 100 dB range Figure 28 5 4 3 LOGARITHMIC OUTPUT Volts 1uV 10uV 100uV 1mV 10mV 100mV 1V 10V INPUT SIGNAL V RMS Figure 26 Vioc Plotted vs Vi for Figure 25 s Circuit Showing 120 dB AGC Range REV A AD600 AD602 GAIN ERROR dB b iuV 10uV 100V 1mV 10mV INPUT SIGNAL V RMS 100mv 1V 10V Figure 27 Gain Error for Figure 25 Without the 2 dB Offset Modification GAIN ERROR dB b
44. r over a full 120 dB range Figure 31 shows the error ripple due to the individual gain func tions which is bounded by 0 2 dB dotted lines from 6 uV to 2 V The small perturbations at about 200 uV and 20 mV caused by the impracticality of matching the gain functions per fectly are the only sign that the gains are now sequential Fig ure 32 is a plot of Vagc which remains very close to its set value of 316 mV rms over the full 120 dB range To more directly compare the signal to noise ratios in the simultaneous and sequential modes of operation all inter stage attenuation was eliminated R2 and R3 in Figure 25 R2 in Figure 29 the input of U1A was shorted R5 was selected to provide a 20 kHz bandwidth R5 7 87 kQ and only the gain control was varied using an external source The rms value of the noise was then measured at Vour and expressed as an S N 16 5 4 3 LOGARITHMIC OUTPUT Volts 1uV 10uV 100uV 1mV 10mV 100mV 1V 10V INPUT SIGNAL V RMS Figure 30 V og Is Essentially Linear Over the Full 120 dB Range ratio relative to 0 dBV this being almost the maximum output capability of the AD600 Results for the simultaneous mode can be seen in Figure 33 The S N ratio degreades uniformly as the gain is increased Note that since the inverting gain control was used the gain in this curv
45. s value in CONTROL VOLTAGE Vc 10 417mV dB mV AGC systems However in applications where these circuit are considered for their wide range logarithmic measurements capa Figure 33 S N Ratio vs Control Voltage for Parallel Gain bilities the inevitable degradation of the S N ratio at high gains Control Figure 25 need not seriously impair their utility In fact the bandwidth of the circuit shown in Figure 25 was specifically chosen so as to improve measurement accuracy by altering the shape of the log error curve Figure 31 at low signal levels REV A 17 AD600 AD602 Typical Performance Characteristics 0 45 0 35 0 25 10dB s 0 15 7dB S 005 tc o fi 0 05 e 45 amp 0 15 o 90 0 25 0 35 0 45 0 7 0 5 0 3 01 01 03 05 07 100k 1M 10M 100M 100k 1M 10M 100M GAIN CONTROL VOLTAGE Volts FREQUENCY Hz FREQUENCY Hz Figure 35 Gain Error vs Gain Figure 36 AD600 Frequency and Figure 37 AD602 Frequency and Control Voltage Phase Response vs Gain Phase Response vs Gain 10 0 a 1 0 9 8 Vg 0V 9 12 1OdB DIV L 14 9 6 CENTER e 2 94 FREQ 1MHz 23 77 I 1OkHz DIV 5 18 x92 m 3 5 2 0 ul 9 0 Q 2 2 5 8 8 5 24 E 2 6 86 5 2 6 o
46. t is overdriven that is each gaincontrol win dow of 1 25 V is used fully before moving to the next amplifier to the right Figure 29 shows the circuit for the sequential control scheme R6 to R9 with R16 provide offsets of 42 14 dB between the individual amplifiers to ensure smooth transitions between the gain of each successive X AMP with the sequence of gain increase being UIA first then U1B and lastly U2A The adjust able attenuator provided by R3 R17 and the 100 Q input 15 AD600 AD602 S odB ADJUST R14 R13 R12 7 32kQ 8660 1kQ R Us C1HI R7 R8 R9 R16 1kQ 2940 1kQ 2870 6V 6V DEC FB 0 1uF 6V DEC 6V DEC R11 56 2kQ FB d C6 4 7uF 6V POWER SUPPLY DECOUPLING NETWORK Y Qv 4316 2mV AD713 V NC NO CONNECT Figure 29 120 dB Dynamic Range RMS Responding Circuit Optimized for S N Ratio resistance of U1A as well as the fixed 6 dB attenuation provided by R2 and the input resistance of U1B are included both to set Voc to read 0 dB when Vy is 3 16 mV rms and to center the 100 dB range between 10 uV rms and 1 V rms input R5 and C3 provide a 3 dB noise bandwidth of 30 kHz R12 to R15 change the scaling from 625 mV decade at the control inputs to 1 V decade at the output and at the same time center the dy namic range at 60 dB which occurs if the Vg of U1B is equal to zero These arrangements ensure that the Vr og will still fit within the 6 V supplies Figure 30 shows Vi og to be linea
47. the appropriate signal levels and polarities for various control schemes For example the gain control input can be fed differentially to the inputs or single ended by simply grounding the unused in put In another example if the gain is to be controlled by a DAC providing a positive only ground referenced output the Gain Control LO pin either CILO or C2LO should be bi ased to a fixed offset of 625 mV to set the gain to 0 dB when Gain Control HI C1HI or C2HI is at zero and to 40 dB when at 1 25 V It is a simple matter to include a voltage divider to achieve other scaling factors When using an 8 bit DAC having a FS output of 2 55 V 10 mV bit a divider ratio of 1 6 generating 6 25 mV bit would result in a gain setting resolution of 0 2 dB bit Later we will discuss how the two sections of an AD600 or AD602 may be cascaded when various options exist for gain control Signal Gating Inputs Each amplifier section of the AD600 and AD602 is equipped with a signal gating function controlled by a TTL or CMOS logic input GAT1 or GAT2 The ground references for these inputs are the signal input grounds A1LO and A2LO respec tively Operation of the channel is unaffected when this input is LO or left open circuited Signal transmission is blocked when this input is HI The dc output level of the channel is set to within a few millivolts of the output ground AICM or A2CM and simultaneously the noise level drops signific
48. tter or 86 dB in a 1 MHz bandwidth REV A AD600 AD602 The Gain Control Interface The attenuation is controlled through a differential high imped ance 15 MQ input with a scaling factor which is laser trimmed to 32 dB per volt that is 31 25 mV dB Each of the two amplifiers has its own control interface An internal band gap reference ensures stability of the scaling with respect to supply and temperature variations and is the only circuitry common to both channels When the differential input voltage Vg 0 V the attenuator slider is centered providing an attenuation of 21 07 dB thus resulting in an overall gain of 20 dB 21 07 dB 41 07 dB When the control input is 625 mV the gain is lowered by 20 dB 0 625 x 32 to 0 dB when set to 625 mV the gain is increased by 20 dB to 40 dB When this interface is over driven in either direction the gain approaches either 1 07 dB 42 14 dB 41 07 dB or 41 07 dB 0 41 07 dB respectively The gain of the AD600 can thus be calculated using the follow ing simple expression Gain dB 32 Vg 20 1 where Vg is in volts For the AD602 the expression is Gain dB 32 Vg 10 2 Operation is specified for Va in the range from 625 mV dc to 625 mV dc The high impedance gain control input ensures minimal loading when driving many amplifiers in multiple channel applications The differential input configuration pro vides flexibility in choosing

ANALOG DEVICES AD600/AD602* handbook

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