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ANALOG DEVICES AD5231/AD5232/AD5233 handbook

1. Parameter Symbol Conditions Min Typ Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs Resistor Differential Nonlinearity R DNL Rvp Va NC 1 1 4 1 LSB Resistor Nonlinearity R INL Rwsg Va NC 1 1 2 1 FS Nominal resistor tolerance AR Ta 25 C Vas Von Wiper Vw No connect 30 30 Resistance Temperature Coefficent Rag AT VAB Vpp Wiper Vw No Connect 500 ppm C Wiper Resistance Rw lw 1 VIR Vpp 5V 50 100 Q Wiper Resistance Rw lw 1 VIR Vpp 3V 200 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N AD5231 AD5232 AD5233 10 8 6 Bits Integral Nonlinearity INL 1 1 2 1 FS Differential Nonlinearity DNL 1 1 4 1 LSB Voltage Divider Temperature Coefficent AVwAT Code Half scale 15 ppm C Full Scale Error VWFSE Code Full scale 3 0 FS Zero Scale Error Vwzse Code Zero scale 0 3 HFS RESISTOR TERMINALS Voltage Range Vasw Vss Vop V Capacitance Ax Bx Cap f 1 MHz measured to GND Code Half scale 45 pF Capacitance gt Wx Cw f 1 MHz measured to GND Code Half scale 60 pF Common mode Leakage Current lcm Va Vg Vpp 2 0 01 1 pA DIGITAL INPUTS amp OUTPUTS Input Logic High Vin with respect to GND VDD 5V 24 V Input Logic Low Vit with respect to GND VDD 5V 0 8 V Input Logic High Vin with respect to GND VDD 3V 2 1 V Input Logic Low Vit with respect to GND VDD 3V 0 6 V Output Logic High Vou Reu up 2 2KQ to
2. oif 16 02 CLK 2 15 RDY spi 3 14 tS SDO 4 13 PR GND 5 12 WP Vss 6 11 Voo T 7 10 A1 Bi 8 9 w1 AD5231 PIN FUNCTION DESCRIPTION Name Description 1 13 14 15 16 Ol CLK SDI SDO GND RDY 02 REV PrF Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Non Volatile Digital Output 1 ADDR O1 1H data bit position DO Serial Input Register clock pin Shifts in one bit at a time on positive clock CLK edges Serial Data Input Pin Serial Data Output Pin Open Drain Output requires external pull up resistor Commands 9 amp 10 activate the SDO output See Instruction operation Truth Table Other commands shift out the previously loaded bit pattern delayed by 24 clock pulses This allows daisy chain operation of multiple packages Ground pin logic ground reference Negative Supply Connect to zero volts for single supply applications Used as digital input during factory test mode Leave pin floating or connect to Vpp or Vss B terminal of RDAC1 Wiper terminal of RDAC1 ADDR RDAC1 04 A terminal of RDAC1 Positive Power Supply Pin Should b
3. 1 The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy chain operation Exception following Instruction 9 or 10 the selected internal register data will be present in data byte 0 amp 1 Instructions following 9 amp 10 must be a full 24 bit data word to completely clock out the contents of the serial register 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non volatile EEMEM register 2 The increment decrement and shift commands ignore the contents of the shift register Data Byte 0 4 Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high REV PrF 9 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 Table 4 AD5232 Instruction Operation Truth Table Instruction Byte 1 Data Byte 0 Operation B15 eeeeeeeeeeeeeeee BB B7 eeeeeeeeeeeeeeeee BO C3 C2 C1 CO A3 A2 Al AO D7 D6 D5 D4 D3 D2 D1 DO X X XXX X XX Write contents of EEMEM ADDR to RDAC ADDR Register X X X XX X X X SAVE WIPER SETTING Write conten
4. Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 NO CONNECT Figure X8 Resistor Position Nonlinearity Error Rheostat Operation R INL R DNL Voo DUT Vss GND Figure X15 Common Mode Leakage current test circuit V Vop 10 AVus PSAR dB 20 LOG AVpp AV PSS ms TYPICAL PERFORMANCE GRAPHS AVpp TBD Figure X10 Power supply sensitivity test circuit PSS PSSR A DUT B Vout OFFSET GND z OFFSET BIAS V Figure X11 Inverting Gain test Circuit OFFSET GND o BIAS Figure X12 Non Inverting Gain test circuit Figure X13 Gain Vs Frequency test circuit REV PrF 13 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 OUTLINE DIMENSIONS Dimensions shown in
5. 5V 49 V Output Logic High Von lon 40HA Viogic t5V 4 V Output Logic Low VoL loL 1 6mMA VLogic 5V 0 4 V Input Current li Vin OV or Voo 1 HA Input Capacitance Ci 5 pF POWER SUPPLIES Single Supply Power Range Vpp Vss OV 2 7 5 5 V Dual Supply Power Range Voo Vss 2 25 2 75 V Positive Supply Current lbp Vin Voo or Vi GND 2 20 pA Programming Mode Current lope Vin Voo or Vi GND 35 mA Read Mode Current s lpp ReAD Vin Voo or Vi GND 0 9 9 mA Negative Supply Current Isg Vin Voo or Vi GND Von 2 5V Vss 2 5V 10 yA Power Dissipation Poiss Vin Voo or Viy GND 0 1 mW Power Supply Sensitivity PSS AVpp 5V 10 0 002 0 01 l DYNAMIC CHARACTERISTICS 8 Bandwidth 3dB BW_10K R 10KQ 600 KHz Total Harmonic Distortion THDy Va 1Vrms Vg OV fE1KHz 0 003 Vw Settling Time ts Va Voo Vg 0V 50 of final value For Ras 10K 50K 100K 1 3 6 us Resistor Noise Voltage en we Rys 5KQ f 1KHz 9 nVVHz Crosstalk Cw1 Cw2 Cr Va Vpn Vs OV Measure Vw with adjacent VR making full scale change 65 dB NOTES See bottom of table next page REV PrF 2 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com AD5231
6. edges Serial Data Output Pin Open Drain Output requires external pull up resistor Commands 9 amp 10 activate the SDO output See Instruction operation Truth Table Other commands shift out the previously loaded bit pattern delayed by 16 clock pulses This allows daisy chain operation of multiple packages Ground pin logic ground reference Negative Supply Connect to zero volts for single supply applications Wiper terminal of RDAC1 ADDR RDAC1 04 Wiper terminal of RDAC2 ADDR RDAC2 14 Wiper terminal of RDAC3 ADDR RDAC3 24 Wiper terminal of RDAC4 ADDR RDAC4 34 Positive Power Supply Pin Should be the input logic HIGH voltage Write Protect Pin When active low WP prevents any changes to the present contents except retrieving EEMEM content Hardware over ride preset pin Refreshes the scratch pad register with current contents of the EEMEM register Factory default loads midscale 20y until EEMEM loaded with a new value by the user PR is activated at the logic high Serial Register chip select active low Serial register operation takes place when CS returns to logic high Ready Active high open drain output Identifies completion of commands 2 3 8 9 10 Non Volatile Digital Output 2 ADDR O2 4y data bit position D1 Name Description 1 O1 2 CLK 3 SDI Serial Data Input Pin 4 SDO 5 GND 6 Vss 7 Al A terminal of RDAC1 8 wil 9 Bl B terminal of RDAC1 10 A2 A terminal of RDAC2 11 W2 12 B2 B
7. pattern delayed by 16 clock pulses This allows daisy chain operation of multiple packages Ground pin logic ground reference Negative Supply Connect to zero volts for single supply applications A terminal of RDAC1 Wiper terminal of RDAC1 ADDR RDAC1 0 B terminal of RDAC1 B terminal of RDAC2 Wiper terminal of RDAC2 ADDR RDAC2 ly A terminal of RDAC2 Positive Power Supply Pin Should be the input logic HIGH voltage Write Protect Pin When active low WP prevents any changes to the present contents except retrieving EEMEM content and RESET Hardware over ride preset pin Refreshes the scratch pad register with current contents of the EEMEM register Factory default loads midscale 80 until EEMEM loaded with a new value by the user PR is activated at the logic high transition Serial Register chip select active low Serial register operation takes place when CS returns to logic high Ready Active high open drain output Identifies completion of commands 2 3 8 9 10 22 MAR 01 Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 AD5233 PIN CONFIGURATION 02 RDY 33a Voo A4 w4 B4 A3 w3 B3 AD5233 PIN FUNCTION DESCRIPTION Non Volatile Digital Output 1 ADDR O1 4y data bit position DO Serial Input Register clock pin Shifts in one bit at a time on positive clock CLK
8. terminal of RDAC2 13 B3 B terminal of RDAC3 14 w3 15 A3 A terminal of RDAC3 16 B4 B terminal of RDAC4 17 W4 18 A4 A terminal of RDAC4 19 Vpp 20 WP and RESET 21 PR transition 22 S 23 RDY 24 02 REV PrF 6 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 OPERATIONAL OVERVIEW The AD5231 32 33 digital potentiometer family is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of Vss lt VtERM lt Vpp The basic voltage range is limited to a Vpp Vogl lt 5 5V Control of the digital potentiometer allows both scratch pad register RDAC register changes to be made as well as 100 000 nonvolatile electrically erasable memory EEMEM register operations The EEMEM update process takes approximately 20 2ms during this time the shift register is locked preventing any changes from taking place The RDY pin flags the completion of this EEMEM save The EEMEM retention is designed to last 15 years at 85 C which is equivalent to 90 years at 55 C without refresh The scratch pad
9. 0 0 ADS2310 0 0 ANALOG Nonvolatile Memory DEVICES Digital Potentiometers AD5231 AD5232 AD5233 FEATURES Nonvolatile Memory Preset Maintains Wiper Settings FUNCTIONAL BLOCK DIAGRAMS AD5231 Single 1024 Position Resolution aS AD5231 AD5232 Dual 256 Position Resolution O Yon AD5233 Quad 64 Position Resolution cLK 2 pecone denen poe 10K 50K 100K Ohm Terminal Resistance SDI SDi L at p A Linear or Log taper Settings SERIAL w Increment Decrement Commands Push Button Command GND INTERFACE RENEI B SPI Compatible Serial Data Input with Readback Function 3 to 5V Single Supply or 2 5V Dual Supply Operation SDO H SDO DIGITAL 2 a a User EEMEM nonvolatile memory for constant storage WP OH Etmem REGISTER I2 Surpu APRLICATIONS RDY Q CONTROL AY 4 purrer O EEMEM2 Mechanical Potentiometer Replacement PR O Usen EENEN Mss Instrumentation Gain Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters Delays Time Constants cs AD5232 7 Line Impedance Matching Power Supply Adjustment DIP Switch Setting GENERAL DESCRIPTION The AD5231 AD5232 AD5233 family provides a single dual quad channel digitally controlled variable resistor VR with resolutions of 1024 256 64 positions respectively These devices perform the same elect
10. 10 REEL7 X1 10 40 85 C TSSOP 16 RU 16 1 000 AD5231BRUS0 X1 50 40 85 C TSSOP 16 RU 16 AD5231BRUS50 REEL7 X1 50 40 85 C TSSOP 16 RU 16 1 000 AD5231BRU100 X1 100 40 85 C TSSOP 16 RU 16 AD5231BRU100 REEL7 X1 100 40 85 C TSSOP 16 RU 16 1 000 ADS5232BRU10 X2 10 40 85 C TSSOP 16 RU 16 ADS5232BRU10 REEL7 X2 10 40 85 C TSSOP 16 RU 16 1 000 ADS5232BRUS0 X2 50 40 85 C TSSOP 16 RU 16 ADS5232BRUS50 REEL7 X2 50 40 85 C TSSOP 16 RU 16 1 000 AD5232BRU100 X2 100 40 85 C TSSOP 16 RU 16 AD5232BRU100 REEL7 X2 100 40 85 C TSSOP 16 RU 16 1 000 ADS5233BRU10 X4 10 40 85 C TSSOP 24 RU 24 AD5233BRU10 REEL7 X4 10 40 85 C TSSOP 24 RU 24 AD5233BRUS0 X4 50 40 85 C TSSOP 24 RU 24 AD5233BRUS50 REEL7 X4 50 40 85 C TSSOP 24 RU 24 AD5233BRU100 X4 100 40 85 C TSSOP 24 RU 24 AD5233BRU100 REEL7 X4 100 40 85 C TSSOP 24 RU 24 The AD5231 AD5232 AD5233 contains 9 646 transistors Die size 69 mil x 115 mil 7 993 sq mil REV PrF 4 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 PIN CONFIGURATION
11. 232 and the quad AD5233 digital potentiometer devices The AD5232 and AD5233 use a 16 bit serial data word loaded MSB first while the AD5231 uses a 24 bit serial word loaded MSB first The format of the SPI compatible word is shown in Table 1 and 2 The Command Bits Cx control the operation of the digital potentiometer according to the command instructions shown in Table 3 4 and 5 The Address Bits Ax determine which register is activated The Data Bits Dx are the values that are loaded into the decoded register The last instruction executed prior to a period of no programming activity should be the No OPeration NOP instruction This will place the internal logic circuitry in a minimum power dissipation state PR O VALID COMMAND COMMAND sy PROCESSOR A COUNTER gt amp ADDRESS DECODE R purLuP CLK SERIAL REGISTER e CS GND SDI V Figure 2 Equivalent Digital Input Output Logic The equivalent serial data input and output logic is shown in figure 2 The open drain output SDO is disabled whenever chip select CS is logic high The SPI interface can be used in two slave modes CPHA 1 CPOL 1 and CPHA 0 CPOL 0 CPHA and CPOL refer to the control bits which dictate SPI timing in the following microprocessors Micro Converters ADuC812 824 M68HC11 and MC68HC16R1 916R1 22 MAR 01 Information contained in this Preliminary data sheet describes a produ
12. 3 Table 3 AD5231 Instruction Operation Truth Table Instruction Byte 1 Data Byte 1 B15 eeecccccccccccce BS B15 eooo BS B7 eee BO C3 C2 C1 CO A3 A2 Al AO X eee DI D8 D7 eee DO Data Byte 0 N jo jo H m i a oe 0 1 H H jt H N H j jo w H Ww a ical NOTES anna al pope Operation No Operation NOP Do nothing Write contents of EEMEM ADDR to RDAC ADDR Register SAVE WIPER SETTING Write contents of RDAC ADDR to EEMEM ADDR Write contents of Serial Register Data Byte 0 amp 1 to EEMEM ADDR Decrement 6dB Right Shift contents of RDAC ADDR stops at all Zeros Decrement All 6dB Right Shift contents of all RDAC Registers stops at all Zeros Decrement contents of RDAC ADDR by One stops at all Zeros Decrement contents of RDAC Register by One stops at all Zeros RESET Load all RDACs with their corresponding EEMEM previously saved values Write contents of EEMEM ADDR to Serial Register Data Byte 0 amp 1 Write contents of RDAC ADDR to Serial Register Data Byte 0 amp 1 Write contents of Serial Register Data Byte 0 amp 1 to RDAC ADDR Increment 6dB Left Shift contents of RDAC ADDR stops at all Ones Increment All 6dB Left Shift contents of all RDAC Registers stops at all Ones Increment contents of RDAC ADDR by One stops at all Ones Increment contents of RDAC Register by One stops at all Ones
13. 64 positions that correspond to the lower 6 bits of register data 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non volatile EEMEM register The increment decrement and shift commands ignore the contents of the shift register Data Byte 0 4 Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high O N jo je jo H jo H e jo o m m o o H o o m A A is z ii H H N BH H jo D REV PrF 11 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 Latched Digital Outputs A pair of digital outputs O1 amp O2 is available on the AD5231 and the AD5233 parts that provide a nonvolatile logic 0 or logic 1 setting O1 amp O2 are standard CMOS logic outputs shown in figure 2A These outputs are ideal to replace functions often provided by DIP switches In addition they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change Vop OUTPUTS O01 amp 02
14. AD5232 AD5233 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10K 50K 100K OHM VERSIONS V 3V 10 to 5V 10 and V 0V V V 5 V OV 40 C lt T lt 85 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INTERFACE TIMING CHARACTERISTICS applies to all parts Notes 5 9 Clock Cycle Time ty 20 ns Input Clock Pulse Width t2 t3 Clock level high or low 10 ns CS Setup Time t4 10 ns Data Setup Time ts From Positive CLK transition 5 ns Data Hold Time te From Positive CLK transition 5 ns CLK Shutdown Time t7 0 ns CS Rise to Clock Rise Setup te 10 ns CS High Pulse Width ty 10 ns CLK to SDO Propagation Delay t40 Rp 1KQ C lt 20pF 1 25 ns Store to Nonvolatile EEMEM Save Time t 12 Applies to Command 2n 3x 9H 25 ms CS to SDO SPI line acquire t13 ns CS to SDO SPI line release t14 ns RDY Rise to CS Fall tts ns Startup Time tie ms CLK Setup Time ti7 For 1 CLK period ts ts 1 CLK period ns Preset Pulse Width Asynchronous ter 50 ns Preset Response Time terese PR pulsed low then high 70 us NOTES 1 Typicals represent average readings at 25 C and Vpp 5V 2 Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic Iw Vop R for both Vop 3V or Vop 5V 3 I
15. NL and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Va Von and Vs Vss DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions 4 Resistor terminals A B W have no limitations on polarity with respect to each other 5 Guaranteed by design and not subject to production test 6 Common mode leakage current is a measure of the DC leakage from any terminal A B W to a common mode bias level of Von 2 7 Poiss is calculated from lop x Voo Iss X Vss 8 All dynamic characteristics use Vpp 5V 9 See timing diagram for location of measured values All input control voltages are specified with ta tr 2 5ns 10 to 90 of 3V and timed from a voltage level of 1 5V Switching characteristics are measured using both Voo 3V or 5V 10 Propagation delay depends on value of Von Reuut_up and C see applications text 11 Low only for instruction commands 8 9 10 2 3 CMD_8 1ms CMD_9 10 0 12ms CMD_2 3 20ms 12 Dual Supply Operation primarily affects the POT terminals 13 Read Mode current is not continuous Timing Diagram CLK i lt gt kK i t Pet gt 8 42 tL gt lt t lt gt 4 cs Et i a8 ie spl MSB X rh X LSB t t aji SDO X MsB Xa A LSB X 16 tis gt gt t RDY SDO CLK IDLES LOW SDO CLK IDLES HIGH Figure 1 Timing Diagra
16. PINS GND Figure 2A Logic Outputs Ol amp 02 Using Additional internal Nonvolatile EEMEM The AD523x family of devices contains additional internal user storage registers EEMEM for saving constants and other 8 bit data Table 6 provides an address map of the internal storage registers shown in the functional block diagrams as EEMEM1 EEMEM2 EEMEMnh and bytes of USER EEMEM Table 6 EEMEM Address Map EEMEM EEMEM Contents of each device Address EEMEM ADDR ADDR AD5231 16B AD5232 AD5233 8B 8B 0000 RDAC RDACI RDAC1 0001 O1 amp 02 RDAC2 RDAC2 0010 USER 1 USER 1 RDAC3 0011 USER 2 USER 2 RDAC4 0100 USER 3 USER 3 Ol amp 02 0101 USER 4 USER 4 USER 1 1111 USER 14 USER 14 USER 11 NOTES 1 RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at Power ON or when the following instructions are executed Inst 1 and Inst 8 2 O1 amp O2 data stored in EEMEM locations are transferred to their corresponding DIGITAL REGISTER at Power ON or when the following instructions are executed Inst 1 and Inst 8 3 USER data are internal nonvolatile EEMEM registers available to store and retrieve constants using Inst 3 and Inst 9 respectively 4 AD5231 EEMEM locations are 2 bytes each 16 bits of data while the AD5232 amp AD5233 are 1 byte each 8 bits REV PrF Detail Programmable Potentiometer Operation The a
17. ct in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 Table 1 AD5232 amp AD5233 16 bit Serial Data Word MSB LSB AD5232 C3 C2 C1 CO A8 A2 A1_ AO D7 D6 DS D4 D3 D2 D1 DO AD5233 C3 C2 C1 CO A3 A2 A1 AO X X D5 D4 D3 D2 D1 DO Table 2 AD5231 24 bit Serial Data Word M L S S B B AD5231 C C C C A3J A2 A1 A0IX X X X X X D D D D D D D D D D 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Command bits are identified as Cx address bits are Ax and data bits are Dx Command instruction codes are defined in tables 3 4 amp 5 REV PrF 8 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD523
18. ctual structure of the RDAC is designed to emulate the performance of a mechanical potentiometer The RDAC contains a string of connected resistor segments with an array of analog switches that act as the wiper connection to several points along the resistor array The number of points is the resolution of the device For example the AD5232 has 256 connection points allowing it to provide better than 0 5 set ability resolution Figure 3 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC The SW and SW will always be ON while one of the switches SW 0 to SW 24 1 will be ON one at a time depending upon the resistance step decoded from the Data Bits Note there are two 50 ohm wiper resistances Rw The resistance contributed by Rw must be accounted for in the output resistance At terminals A to wiper Rw is the sum of the resistances of SW and SWx Similarly Rw is the sum of the resistances SW and SW at terminals B to Wiper SW 2 1 RDAC WIPER R Wx sw 2 2 f O REGISTER s amp e e e DECODER e Rs sw 1 Rs sw 0 R R N S DIGITAL CIRCUITRY SW B OMITTED FOR S CLARITY Figure 3 Equivalent RDAC structure TEST CIRCUITS Figures X7 to X15 define the test conditions used in the product specification s table V Voo 1LSB V 2N Figure X7 Potentiometer Divider Nonlinearity error test circuit INL DNL 22 MAR 01
19. e the input logic HIGH voltage Write Protect Pin When active low WP prevents any changes to the present contents except retrieving EEMEM contents and RESET Hardware over ride preset pin Refreshes the scratch pad register with current contents of the EEMEM register Factory default loads midscale 200 until EEMEM loaded with a new value by the user PR is activated at the rising logic high transition Serial Register chip select active low Serial register operation takes place when CS returns to logic high Ready Active high open drain output Identifies completion of commands 2 3 8 9 10 Non Volatile Digital Output 2 ADDR O2 1H data bit position D1 AD5231 AD5232 AD5233 AD5232 PIN CONFIGURATION CLK 1 16 RDY spi 2 15 tS SDO 3 14 PR GND 4 13 WP Vss 5 12 Vop Ai 6 11 a2 wi 7 10 w2 B1 8 9 B2 AD5232 PIN FUNCTION DESCRIPTION Name Description 1 14 15 16 CLK SDI SDO RDY Serial Input Register clock pin Shifts in one bit at a time on positive clock edges Serial Data Input Pin Shifts in one bit at a time on positive clock CLK edges Serial Data Output Pin Open Drain Output requires external pull up resistor Commands 9 amp 10 activate the SDO output See Instruction operation Truth Table Other commands shift out the previously loaded bit
20. following 9 amp 10 must be a full 16 bit data word to completely clock out the contents of the serial register 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non volatile EEMEM register The increment decrement and shift commands ignore the contents of the shift register Data Byte 0 4 Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high HB jo jo H A A UO O H je pi je BR H H N H j jo 2 REV PrF 10 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 Table 5 AD5233 Instruction Operation Truth Table Instruction Byte 1 Data Byte 0 Operation B15 eeeeeeeeeeeeeeee BB B7 eeeeeeeeeeeeeceeee BO C3 C2 C1 CO A3 A2 Al AO D7 D6 D5 D4 D3 D2 D1 DO xX K X X R RKI XK X Write contents of EEMEM ADDR to RDAC ADDR Register X X X X X X XK X SAVE WIPER SETTING Write contents of RDAC ADDR to EEMEM ADDR D7 D D5 D4 D3 D2 D1 DO Write contents of Serial Register Data Byte 0 to EEMEM ADDR A X X XXX XXX Decreme
21. hanges of current content in the scratch pad register regardless of the commands except that EEMEM setting can be retrieved using commands 1 and 9 Therefore write protect WP pin provides hardware EEMEM protection feature DIGITAL INPUT OUTPUT CONFIGURATION All digital inputs are ESD protected high input impedance that can be driven directly from most digital sources For PR and WP which are active at logic low can be tied directly to Vpp if they are not being used The SDO and RDY pins are open drain digital outputs where pull up resistors are needed only if using these functions A resistor value in the range of 1k to 10k ohm optimizes the power and switching speed trade off REV PrF 7 SERIAL DATA INTERFACE The AD523X family contains a four wire SPI compatible digital interface SDI SDO CS and CLK Key features of this interface include e Independently Programmable Read amp Write to all registers e Direct parallel refresh of all RDAC wiper registers from corresponding internal EEMEM registers e Increment amp Decrement instructions for each RDAC wiper register e Left amp right Bit Shift of all RDAC wiper registers to achieve 6dB level changes e Nonvolatile storage of the present scratch pad RDAC register values into the corresponding EEMEM register e Fxtra bytes of user addressable electrical erasable memory The serial interface contains three different word formats to support the single AD5231 dual AD5
22. inches and mm 16 Lead TSSOP RU 16 0 201 5 10 0 193 4 90 f HHH Le ff a 0 177 4 50 0 169 4 30 pe 0 256 6 50 0 246 6 25 PIN1 0 006 0 15 0 002 0 05 0 0433 C SE S gt He gt e MAX T 8e 0 028 0 70 pja SEATING 00256 0 0118 0 30 PLANE 9 85 0 0075 0 19 BSC 0 0079 0 20 0 020 0 50 0 0035 0 090 24 Lead Thin Surface Mount TSSOP Package RU 24 0 311 7 90 i 0 303 7 70 T 0 256 6 50 0 246 6 25 0 177 4 50 0 169 4 30 E HN i be Ps max AR 8 0 028 0 70 J 0118 0 30 0 0 0256 0 65 9 0 30 0 0079 0 20 0 020 0 50 SEATING ___ BSC 0 0075 0 19 o PLANE 0 19 0 0035 0 090 REV PrF 14 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com
23. m REV PrF 3 22 MAR 01 Information contained in this Preliminary data sheet describes a product in the early definition stage There is no guarantee that the information contained here will become a final product in its present form For latest information contact Walt Heinzer Analog Devices Santa Clara CA TEL 408 382 3107 FAX 408 382 2708 walt heinzer analog com Nonvolatile Memory Digital Potentiometers AD5231 AD5232 AD5233 Absolute Maximum Rating T 25 C unless Digital Inputs amp Output Voltage to GND 006 OV 7V otherwise noted Operating Temperature Range 0c 40 C to 85 C Vpp to GND Maximum Junction Temperature Ty MAX 0 0 150 C Vise to GND iniaa a ana eataatioae Storage Temperature sssseseeeeeeeeeeeees 65 C to 150 C Vopn to Sexes dopa con easton n cada aul Lead Temperature Soldering 10 sec ssseeee 300 C Vas Vp Vw to GND cece o RS En RS Vss Vpp Package Power Dissipation cesee Tmax Ta Oya Ax By Ax Wx Bx Wx Thermal Resistance 9 Intermittent Aans nn n EEV SR 20mA TSS OPAl Gest cet EE TET AAA 150 C W Continuous TSSOP 2A rn edi aene eer E cesses 128 C W OVO GND iieri a dienes Ordering Guide Number of End to End Temp Package Package Devices Top Mark Model Channels R k Ohm Range Description Option per Container AD5231BRU10 X1 10 40 85 C TSSOP 16 RU 16 AD5231BRU
24. nt 6dB Right Shift contents of RDAC ADDR stops at all Zeros X X xX X X X XXX XXX Decrement All 6dB Right Shift contents of all RDAC Registers stops at all Zeros lt lt ADDR gt gt X X X XX X X X Decrement contents of RDAC ADDR by One stops at all Zeros X X XX X X X KX X KX XK X Decrement contents of all RDAC Registers by One stops at all Zeros X X XXX XXX RESET Load all RDACs with their corresponding EEMEM previously saved values X X XXX XXX Write contents of EEMEM ADDR to Serial Register Data Byte 0 xX X X X X RL XK X Write contents of RDAC ADDR to Serial Register Data Byte 0 D7 D6 D5 D4 D3 D2 D1 DO Write contents of Serial Register Data Byte 0 to RDAC ADDR A X X X X X XXX Increment 6dB Left Shift contents of RDAC ADDR stops at all Ones X X X X X X X X X X X X Increment All 6dB Left Shift contents of all RDAC Registers stops at all Ones lt lt ADDR gt gt X X X X XK XXX Increment contents of RDAC ADDR by One stops at all Ones X X X X X X XXX XXX Increment contents of all RDAC Registers by One stops at all Ones NOTES 1 The SDO output shifts out the last 8 bits of data clocked into the serial register for daisy chain operation Exception following Instruction 9 or 10 the selected internal register data will be present in data byte 0 Instructions following 9 amp 10 must be a full 16 bit data word to completely clock out the contents of the serial register The wiper only has
25. register can be changed incrementally by using the software controlled Increment Decrement instruction or the Shift Left Right instruction command Once an Increment Decrement or Shift command has been loaded into the shift register subsequent CS strobes will repeat this command This is useful for push button control applications Alternately the scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the representative data word The scratch pad register can be loaded with the current contents of the nonvolatile EEMEM register under program control At system power ON the default value of the scratch pad memory is the value previously saved in the EEMEM register The factory EEMEM preset value is midscale The scratch pad wiper register can be loaded with the current contents of the nonvolatile EEMEM register under hardware control by pulsing the PR pin Beware that the PR pulse first sets the wiper at midscale when brought to logic zero and then on the positive transition to logic high it reloads the DAC wiper register with the contents of EEMEM Similarly the saved EEMEM value will automatically be retrieved to the scratch pad register during system power ON A serial data output pin is available for daisy chaining and for readout of the internal register contents The serial input data register uses a 16 or 24 bit instruction address data WORD Write protect WP disables any c
26. ronic adjustment function as a potentiometer or variable resistor The AD523X s versatile programming via a Micro Controller allows multiple modes of operation and adjustment In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the micro controller Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register When changes are made to the RDAC register to establish a new wiper position the value of the setting can be saved into the EEMEM by executing an EEMEM save operation Once the settings are saved in the EEMEM register these values will be transferred automatically to the RDAC register to set the wiper position at system power ON Such operation is enabled by the internal preset strobe and the preset can also be accessed externally The basic mode of adjustment is the increment and decrement command controlling the present setting of the Wiper position setting RDAC register An internal scratch pad RDAC register can be moved UP or DOWN one step of the nominal terminal resistance between terminals A and B This linearly changes the wiper to B terminal resistance Rwg by one position segment of the device s end to end resistance Rag For exponential logarithmic changes in wiper setting a left right shift command adjusts levels in 6dB steps which can be useful for sound and light alarm applications The AD523X are a
27. ts of RDAC ADDR to EEMEM ADDR N D7 D D5 D4 D3 D2 D1 DO Write contents of Serial Register Data Byte 0 to EEMEM ADDR X X X XX X X X Decrement 6dB Right Shift contents of RDAC ADDR stops at all Zeros X X X X X X X XX XXX Decrement All 6dB Right Shift contents of all RDAC Registers stops at all Zeros lt lt ADDR gt gt X X XXX XXX Decrement contents of RDAC ADDR by One stops at all Zeros X X X X X X XXX XXX Decrement contents of all RDAC Registers by One stops at all Zeros X X X XX XXX RESET Load all RDACs with their corresponding EEMEM previously saved values X X XXX XXX Write contents of EEMEM ADDR to Serial Register Data Byte 0 X X X XX XXX Write contents of RDAC ADDR to Serial Register Data Byte 0 D7 D D5 D4 D3 D2 D1 DO Write contents of Serial Register Data Byte 0 to RDAC ADDR A X X X XX XXX Increment 6dB Left Shift contents of RDAC ADDR stops at all Ones X X xX X X X XXX XXX Increment All 6dB Left Shift contents of all RDAC Registers stops at all Ones lt lt ADDR gt gt xX X X X X KX XX Increment contents of RDAC ADDR by One stops at all Ones X X XX X X X XX XXX Increment contents of all RDAC Registers One stops at all Ones NOTES 1 The SDO output shifts out the last 8 bits of data clocked into the serial register for daisy chain operation Exception following Instruction 9 or 10 the selected internal register data will be present in data byte 0 Instructions
28. vailable in the thin TSSOP package All parts are guaranteed to operate over the extended industrial temperature range of 40 C to 85 C REV PrF 22 MAR 01 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ADDR DECODE SERIAL INTERFACE SDI EEMEM CONTROL RDAC1 REGISTER U RDAC2 REGISTER A EEMEM2 ADDR DECODE SDI SERIAL INTERFACE 11 BYTES USER EEMEM DIGITAL OUTPUT BUFFER RDAC1 REGISTER EEMEM1 RDAC2 REGISTER EEMEM2 RDAC3 I REGISTER EEMEM3 DIGITAL 5 REGISTER A RDAC4 REGISTER AD5233 V EEMEMS EEMEM4 RDAC1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A World Wide Web Site http www analog com Analog Devices Inc 1999 Tel 781 329 4700 Fax 617 326 8703 AD5231 AD5232 AD5233 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10K 50K 100K OHM VERSIONS Vop 3V 10 or 5V 10 and Vss 0V Va Vpp Ve OV 40 C lt Ta lt 85 C unless otherwise noted

ANALOG DEVICES AD5231/AD5232/AD5233 handbook

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