Home

freescale MC9328MXL handbook

Contents

1. weim data in a Read Data e Read Data Figure 24 WSC 2 OEA 2 CNC 3 BCM 0 A HALF E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 39 p Specifications hak YA icu a e J hsel weim cs 4 A wi A htrans Nonseaf Idle JNonseqJ hwrite A Read Write haddr IX V1 Y Y V8 A hready UT am SA A hwdata Last Valid Data Write Data A weim hrdata Last Valid Data A Read Data weim hready AL weim_bclk weim addr Last Valid Addk Address V1 Y Address V8 ei cnc gt weim cs i l weim_r w Redd Write a weim lba l weim oe weim eb EBC 0 jo weim eb EBC 1 weim data in Read Data weim data out Last Valid Data X Write Data Figure 25 WSC 2 OEA 2 WEA 1 WEN 2 CNC 3 A HALF E HALF MC9328MXL Advance Information Rev 5 40 Freescale Semiconductor hclk hsel weim cs 2 htrans hwrite haddr hready weim hrdata weim hready weim bclk weim addr weim cs 2 weim r w weim iba weim oe weim eb EBC 0 weim eb EBC 1 weim ecb weim data in Specifications Pe A x Y Idle A Pol qx nal T ia
2. Chip select na m kK Read Write OE rising edge OE falling edge EB rising edge EB falling edge LBA negated falling edge LBA negated rising edge Burst Clock rising edge Burst Clock falling edge Read Data Write Data negated falling Write Data negated rising Dm ek re Figure 5 EIM Bus Timing Diagram MC9328MXL Advance Information Rev 5 Freescale Semiconductor 19 Specifications Table 12 EIM Bus Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Min Typical Max Min Typical Max la Clock fall to address valid 2 48 3 31 9 11 2 4 3 2 8 8 ns 1b Clock fall to address invalid 1 55 2 48 5 69 1 5 2 4 5 5 ns 2a Clock fall to chip select valid 2 69 3 31 7 87 2 6 3 2 7 6 ns 2b Clock fall to chip select invalid 1 55 2 48 6 31 1 5 2 4 6 1 ns 3a Clock fall to Read Write Valid 1 35 2 79 6 52 1 3 2 7 6 3 ns 3b Clock fall to Read Write Invalid 1 86 2 59 6 11 1 8 2 5 5 9 ns 4a Clock rise to Output Enable Valid 2 32 2 62 6 85 2 3 2 6 6 8 ns 4b Clock rise to Output Enable Invalid 2 11 2 52 6 55 24 2 5 6 5 ns 4c Clock fall to Output Enable Valid 2 38 2 69 7 04 23 2 6 6 8 ns 4d Clock fall to Output Enable Invalid 2 17 2 59 6 73 2 1
3. Monsea X Sea Y y Idle N Read Read Dv y x es JEN og e NALE Last Valid Y Address V1 X Address V2 EN NL i eu viva Y V1 2 2 EN Kan v222 f l Figure 28 WSC 2 SYNC 1 DOL 1 0 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 43 Specifications hclk X A e SP PCI SNA ded e e qe el hsel weim cs 2 A AN AN htrans Non Seq Hi ldle hwrite Rea Read haddr vi X y v2 hready weim_hrdata Last Valid Data OO EE v2 Wor welm_hready NE cin him bik EAN ICI EL J weim_addr Last Y Address V1 weim cs 2 weim r w Read weim Iba V weim oe weim eb EBC 0 weim eb EBC 1 weim data in A A vite vize ver vz Figure 29 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 2 A WORD E HALF MC9328MXL Advance Information Rev 5 44 Freescale Semiconductor hclk hsel weim cs 2 htrans hwrite haddr hreadv weim hrdata weim hreadv weim bclk weim addr weim_cs 2 weim r w Specifications EPA e AA JA JA
4. N t vMo_ROE 4 gt tROE VMO e tPERIOD Y NM GY H gt li HOR Figure 52 USB Device Timing Diagram for Data Transfer to USB Transceiver TX Table 26 USB Device Timing Parameter Table for Data Transfer to USB Transceiver TX 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 1 troe_vpo USBD_ROE active to 83 14 83 47 83 14 83 47 ns USBD_VPO low 2 troE vmo USBD_ROE active to 81 55 81 98 81 55 81 98 ns USBD_VMO high 3 typo Rog USBD_VPO high to 83 54 83 80 83 54 83 80 ns USBD_ROE deactivated MC9328MXL Advance Information Rev 5 66 Freescale Semiconductor Specifications Table 26 USB Device Timing Parameter Table for Data Transfer to USB Transceiver TX 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 4 tvmo Roe USBD_VMO low to 248 90 249 13 248 90 249 13 ns USBD_ROE deactivated includes SEO 5 treopr SEO interval of EOP 160 00 175 00 160 00 175 00 ns 6 tpeRiop Data transfer rate 11 97 12 03 11 97 12 03 Mb s USBD_AFE Output N USBD ROE YA Output USBD VPO Output USBD VMO Output USBD SUSPND Output 1 N A USBD RCV X N Input gt treoPR USBD VP PARE E a Input USBD_VM
5. weim bclk weim addr Last Valid Addr Address V1 X Address V1 2 weim cs 2 weim r w Read weim ba b a weim_oe weim eb EBC 0 weim eb EBC 1 weim data in 2 Half Word 2 2 Half Word Lp Figure 17 WSC 3 OEA 2 OEN 2 A WORD E HALF MC9328MXL Advance Information Rev 5 32 Freescale Semiconductor hclk hsel weim cs 2 htrans hwrite haddr hreadv hwdata weim hrdata weim hready weim bclk weim addr weim cs 2 weim r w weim Iba weim oe weim eb weim data out Specifications IN SENT FI Y Nonseq Write JP I Y VI PIN EE Write Data V1 Word Y Unknown Last Valid Data A Last Valid Adar y Address V1 X Address V1 2 Write 11 Last Valid Data 1 2 Half Word A 2 2 Half Word Figure 18 WSC 2 WWS 1 WEA 1 WEN 2 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 33 Specifications BERTA o ieu ee E hsel weim cs 2 Pm A htrans Nonseq Y hwrite p Write haddr X vi mea FT nu a hwdata Last Vali Data Write Data V1 Word Unknown weim_hrdata Last Valid Data weim_hready NI weim bclk weim add
6. J Figure 7 DTACK Timing WSC 111111 DTACK sel 1 Table 14 Access Cycle Timing Parameters Rei 1 8V 0 10V 3 0V 0 30V No Characteristic kr uni Min Max Min Max 1 External DTACK input setup from CS5 0 0 ns asserted Note 1 nis the number of wait states in the current memory access cycle The max n is 1022 2 T is the system clock period system clock is 96 MHz 3 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state MC9328MXL Advance Information Rev 5 22 Freescale Semiconductor Po Specifications 3 9 3 EIM External Bus Timing The timing diagrams in this section show the timing of accesses to memory or a peripheral hsel weim cs 0 EE htrans Y Seq Nonseq Y hwrite Read haddr X vi A hready f f f V weim hrdata Last Valid Data EM VI weim_hready I PA weim bclk weim addr Last Valid Address X vi weim cs weim r w Read weim ba weim oe weim eb EBC 0 i weim_eb EBC 1 weim_data_in aU V1 Figure 8 WSC 1 A HALF E HALF Lo MC9328MXL Advance Information Rev 5 Freescale Semiconductor 23 POO Specifications helk GE JAN hsel weim cs 0 NW htrans X Nonseq hwrite Wirite haddr y vi hready NW hwdata La
7. z L sjueuiuBissy uid VOBdVIN 957 TXNSZEGJW EE eigen egexoed VDAAVW utd 9cz ou 107 syuounuBisse urd a3exoed ayi SOJLJISNJJI ce ALL uoneuojuj abeyoeg pue 1nQ uld y MC9328MXL Advance Information Rev 5 79 Freescale Semiconductor Pin Out and Package Information yoo o 1sunq LOGAY amas Svo ewod ga val va 1oas ov za 30 zga 193 Lia av 4S13S34 ONTO I34OdS svu LNOa LLVIN OLVIN sa 9d LV ev ev LA Sv vid ISHI ALVISIHI 03995 owoa zwoa oa LWd oso eso ga 6a 0g3 eta IN 8v IN9LIVIX3 NIL3S3H zagno 1008 SSAN MY prog LSO vSO LOGAN 43 ora ela sia 91a MZETVLXI WOLTVIX SSAO HOd SSAN SSAN 493 za sso LOGAN LOGAN gia La 6v OLY Ino NVIGNA AZETVLX 713534 ola Idi z1008 La SSAN LOGAN SSAD SSAN LOGAN 610 289 LLY ELV X19 sa 01008 1LOOS OGL MOL Oel 9d ISO SSAN LaGAD SSAN SSAN LOGAN oza Lea ev LAN MIOXId ONASA SNL VIVA Oel isa Iso aiso ZAGAN SSAN SSAN SSAN SSAN zza ved eza 9LV SLV Sd ISO ONASH ISO Za ISO Ed ISO OWMd SSAD SSAN SSAN YAaGAN SSAN LOGAN sza aza 81V LIV IVOXL NIOXH SLO va Iso ed 189 stan vidi eddAo s10 70ISS 0ISS ziuvn LOGAN LOGAN zza sza 61V ozy XION aov OSIW SLO axy sit TISO 0d ISO NLL oral 740 Las TLLHVA TLLHVA e1uvn SSAD LOGAN eza oea zzy Law ISOW axl IVOXL etan ZINOL La 1a1 ONASH Llas AGAN eluvn vAdAO dA aasn LOGAN LISS Liva vov Ezy sit SA4XL axy OdA S XL S4XH ZQQAN zai 6017 gal ONA
8. Figure 53 USB Device Timing Diagram for Data Transfer from USB Transceiver RX Table 27 USB Device Timing Parameter Table for Data Transfer from USB Transceiver RX MC9328MXL Advance Information Rev 5 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 1 treopr Receiver SEO interval of EOP 82 82 ns Freescale Semiconductor 67 Specifications 3 17 IC Module The C communication protocol consists of seven elements START Data Source Recipient Data Direction Slave Acknowledge Data Data Acknowledge and STOP SCL Figure 54 Definition of Bus Timing for lc Table 28 1 C Bus Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 1 Hold time repeated START condition 182 160 ns 2 Data hold time 0 171 0 150 ns 3 Data setup time 11 4 10 ns 4 HIGH period of the SCL clock 80 120 ns 5 LOW period of the SCL clock 480 320 ns 6 Setup time for STOP condition 182 4 160 ns 3 18 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous In synchronous mode the transmitter and the receiver use a common clock and frame synchronization signal In asynchronous mode the transmitter and receiver each have their own clock and frame synchronization signals
9. NI 9n Seq X Idle Rea Read jem v PA P Last Valid Data EE vi Word V2 Word Last weim Iba weim oe weim eb EBC 0 weim eb EBC 1 weim ecb weim data in Read l sj bere SSS V1 1 2 y V1 2 2 Y V2 1 2 Y V2 2 2 Figure 30 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 1 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 45 Specifications 3 10 SPI Timing Diagrams To utilize the internal transmit TX and receive RX data FIFOs when the SPI 1 module is configured as a master two control signals are used for data transfer rate control the SS signal output and the SPI RDY signal input The SPI 1 Sample Period Control Register PERIODREG1 and the SPI 2 Sample Period Control Register PERIODREG2 can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2 When the SPI 1 module is configured as a slave the user can configure the SPI 1 Control Register CONTROLREGI to match the external SPI master s timing In this configuration SS becomes an input signal and is used to latch data into or load data out to the internal data shift registers as well as to increment the data FIFO Figure 31 through Figure 35 show the timing relationship of the master SPI using different trig
10. 3 SDRAM clock cycle time 11 4 10 ns 4 Address setup time 3 42 3 ns 5 Address hold time 2 28 2 ns 6 Precharge cycle period tap tgp ns 7 Auto precharge command period tro tro ns 1 tgp and tac SDRAM clock cycle time These settings can be found in the MC9328MXL reference manual SDCLK Figure 51 SDRAM Self Refresh Cvcle Timing Diagram MC9328MXL Advance Information Rev 5 Freescale Semiconductor Specifications 3 16 USB Device Port Four types of data transfer modes exist for the USB module control transfers bulk transfers isochronous transfers and interrupt transfers From the perspective of the USB module the interrupt transfer type is identical to the bulk data transfer mode and no additional hardware is supplied to support it This section covers the transfer modes and how they work from the ground up Data moves across the USB in packets Groups of packets are combined to form data transfers The same packet transfer mechanism applies to bulk interrupt and control transfers Isochronous data is also moved in the form of packets however because isochronous pipes are given a fixed portion of the USB bandwidth at all times there is no end of transfer USBD AFE Output USBD ROE Output USBD VPO Output USBD VMO Output USBD SUSPND Output USBD RCV Input USBD VP Input USBD VM Input m 1 tRoE veo S
11. loH Output high current 4 0 mA Voy 0 8Vpp Vpp 1 8V lou Output low current 4 0 mA VoL 0 4V Vpp 1 8V loz Output leakage current 5 HA Vout Vpp output is tri stated Gi Input capacitance 5 pF Co Output capacitance x 5 pF 3 5 AC Electrical Characteristics The AC characteristics consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of other signals All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz core operating frequency 150 MHz with an operating supply voltage from Vespa Yop max under an operating temperature from Ty to Ty All timing is measured at 30 pF loading Table 7 Tristate Signal Timing Pin Parameter Minimum Maximum Unit TRISTATE Time from TRISTATE activate until I O becomes Hi Z 20 8 ns Table 8 32k 16M Oscillator Signal Timing Parameter Minimum RMS Maximum Unit EXTAL32k input jitter peak to peak 5 20 ns MC9328MXL Advance Information Rev 5 Freescale Semiconductor 13 Specifications Table 8 32k 16M Oscillator Signal Timing Continued Parameter Minimum RMS Maximum Unit EXTAL32k startup time 800 ms EXTAL16M input jitter peak to peak TBD TBD EXTAL16M startup time TBD 3 6 Embedded Trace Macrocell All registers in the
12. period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time 1ns setup time 1ns positive duty cycle 10 2 5ns gt max rise time allowed 5 1 4ns MC9328MXL Advance Information Rev 5 76 Freescale Semiconductor Specifications negative duty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time max rise time allowed positive duty cycle setup time 3 19 2 Non Gated Clock Mode Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 62 on page 78 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 32 on page 78 i Se l I I PIXCLK d I I kI I 1 I L I DATA 7 0 y Valid Data 1 Valid Data Valid Data A 4 9 Figure 61 Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge MC9328MXL Advance Information Rev 5 Freescale Semiconductor 77 Specifications 1 VSYNC gt _ gt PIXCLK L e We 4 I DATA 7 0 Valid Data x Valid Data Valid Data IAA COSTS Figure 62 Sensor Output Data on Pixel Clock Rising Edge CSI
13. Continuous or gated clock mode can be selected In continuous mode the clock runs continuously In gated clock mode the clock functions only during transmission The internal and external clock timing diagrams are shown in Figure 56 through Figure 58 on page 70 Normal or network mode can also be selected In normal mode the SSI functions with one data word of I O per frame In network mode a frame can contain between 2 and 32 data words Network mode is typically used in star or ring time division multiplex networks with other processors or codecs allowing interface to time division multiplexed networks without additional logic Use of the gated clock is not allowed in network mode These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices MC9328MXL Advance Information Rev 5 68 Freescale Semiconductor Specifications 1 STCK Output KAN s STFS bl Output OE qe E ode Ed e SRXD Input Note SRXD input in synchronous mode only Figure 55 SSI Transmitter Internal Clock Timing Diagram SRFS bl Output T AA SRXD Input SRCK Output RA Figure 56 SSI Receiver Internal Clock Timing Diagram MC9328MXL Advance Information Rev 5 Freescale Semiconductor 69 Specifications STCK Input STFS bl Input STFS wl Input STXD Output SRXD Input Note SRXD Input in Sync
14. cli Last Vali sa Write Da ta V1 Word Last Valid Data IO a Last Valid Addr Address V1 Address V1 Write E weim eb weim data out i dd f Last Valid Data X 1 2 Half Word A 2 2 Half Word Figure 13 WSC 3 WEA 1 WEN 3 A WORD E HALF MC9328MXL Advance Information Rev 5 28 Freescale Semiconductor Specifications hclk hsel_weim_cs 2 htrans hwrite haddr hreadv weim hrdata weim hready weim bclk weim addr quje mese MEME 1 Last Valid Data FU n vi FU Last Valid Addr Address V1 Address V1 2 weim cs 2 weim r w weim Iba weim oe weim eb EBC 0 weim eb EBC 1 weim data in Read 9 73 e Half Word Figure 14 WSC 3 OEA 4 A WORD E HALF MC9328MXL Advance Information Rev 5 O 2 2 Half Word Freescale Semiconductor 29 Specifications hclk hsel weim cs 2 htrans hwrite haddr hreadv hwdata weim_hrdata weim_hready weim bclk weim addr weim cs 2 weim r w weim Iba weim oe Neg ag ke Ly A J VA Y Nonseq X p Write A ZR SON Last
15. 10 ns 4a Output delay time 5 7 5 ns 4b Output setup time 5 7 5 ns 1 C of PWMO 30 pF 3 15 SDRAM Controller A write to an address within the memory region initiates the program sequence The first command issued to the SyncFlash 1s Load Command Register The value in A 7 0 determines which operation the command performs For this write setup operation an address of 0x40 is hardware generated The bank and other address lines are driven with the address to be programmed The next command is Active which registers the row address and confirms the bank address The third command supplies the column address re confirms the bank address and supplies the data to be written SyncFlash does not support burst writes therefore a Burst Terminate command is not required A read to the memory region initiates the status read sequence The first command issued to the SyncFlash is the Load Command Register with A 7 0 set to 0x70 which corresponds to the Read Status Register operation The bank and other address lines are driven to the selected address The second command is MC9328MXL Advance Information Rev 5 60 Freescale Semiconductor CE O OO Specifications Active which sets up the status register read The bank and row addresses are driven during this command The third command of the triplet is Read Bank and column addresses are driven on the address bus during this command Data is returned f
16. 2 5 6 5 ns 5a Clock rise to Enable Bytes Valid 1 91 2 52 5 54 1 9 2 5 5 5 ns 5b Clock rise to Enable Bytes Invalid 1 81 2 42 5 24 1 8 2 4 5 2 ns 5c Clock fall to Enable Bytes Valid 1 97 2 59 5 69 1 9 2 5 5 5 ns 5d Clock fall to Enable Bytes Invalid 1 76 2 48 5 38 1 7 2 4 5 2 ns 6a Clock fall to Load Burst Address Valid 2 07 2 79 6 73 2 0 2 7 6 5 ns 6b Clock fall to Load Burst Address Invalid 1 97 2 79 6 83 1 9 2 7 6 6 ns 6c Clock rise to Load Burst Address Invalid 1 91 2 62 6 45 1 9 2 6 6 4 ns 7a Clock rise to Burst Clock rise 1 61 2 62 5 64 1 6 2 6 5 6 ns 7b Clock rise to Burst Clock fall 1 61 2 62 5 84 1 6 2 6 5 8 ns 7C Clock fall to Burst Clock rise 1 55 2 48 5 59 1 5 24 5 4 ns 7d Clock fall to Burst Clock fall 1 55 2 59 5 80 1 5 25 5 6 ns 8a Read Data setup time 5 54 5 5 ns 8b Read Data hold time 0 0 ns 9a Clock rise to Write Data Valid 1 81 2 72 6 85 1 8 2 7 6 8 ns 9b Clock fall to Write Data Invalid 1 45 2 48 5 69 1 4 2 4 5 5 ns 9c Clock rise to Write Data Invalid 1 63 1 62 ns 10a DTACK setup time 2 52 2 5 ns 1 Clock refers to the system clock signal HCLK generated from the System PLL MC9328MXL Advance Information Rev 5 20 Freescale Semiconductor Specifications 3 9 1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal When using the extemal DTACK signal as
17. 8 ns 12 STCK high to STXD high impedance 12 88 13 57 11 3 11 9 ns 13 SRXD setup time before SRCK low 21 1 18 5 ns 14 SRXD hold time after SRCK low 0 0 ns External Clock Operation Port C Primary Function 15 STCK SRCK clock period 92 8 81 4 ns 16 STCK SRCK clock high period 27 1 40 7 ns 17 STCK SRCK clock low period 61 1 40 7 ns 18 STCK high to STFS bl high 92 8 0 81 4 ns 19 SRCK high to SRFS bl high 92 8 0 81 4 ns 20 STCK high to STFS bl low 92 8 0 81 4 ns 21 SRCK high to SRFS bl low 92 8 0 81 4 ns 22 STCK high to STFS wl high 92 8 0 81 4 ns 23 SRCK high to SRFS wl high 92 8 0 81 4 ns 24 STCK high to STFS wl low 92 8 0 81 4 ns 25 SRCK high to SRFS wl low 92 8 0 81 4 ns 26 STCK high to STXD valid from high 18 01 28 16 15 8 24 7 ns impedance 27a STCK high to STXD high 8 98 18 13 7 0 15 9 ns 27b STCK high to STXD low 9 12 18 24 8 0 16 0 ns MC9328MXL Advance Information Rev 5 Freescale Semiconductor 71 Specifications Table 29 SSI Port C Primary Function Timing Parameter Table Continued 1 8V x 0 10V 3 0V x 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 28 STCK high to STXD high impedance 18 47 28 5 16 2 25 0 ns 29 SRXD setup time before SRCK low 1 14 1 0 ns 30 SRXD hole time after SRCK low 0 0 ns Synchronous Internal Clock Operation Port C Primary Function 31 SRXD setup before ST
18. STCK SRCK clock period 95 83 3 ns 2 STCK high to STFS bl high 1 7 4 8 1 5 4 2 ns 3 SRCK high to SRFS bl high 0 1 1 0 0 1 1 0 ns 4 STCK high to STFS bl low 3 08 5 24 2 7 4 6 ns 5 SRCK high to SRFS bl low 1 25 2 28 1 1 2 0 ns 6 STCK high to STFS wl high 1 71 4 79 1 5 4 2 ns 7 SRCK high to SRFS wl high 0 1 1 0 0 1 1 0 ns 8 STCK high to STFS wl low 3 08 5 24 2 7 4 6 ns MC9328MXL Advance Information Rev 5 72 Freescale Semiconductor Table 30 SSI Port B Alternate Function Timing Parameter Table Continued Specifications Be 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum 9 SRCK high to SRFS wl low 1 25 2 28 1 1 2 0 ns 10 STCK high to STXD valid from high 14 93 16 19 13 1 14 2 ns impedance 11a STCK high to STXD high 1 25 3 42 1 1 3 0 ns 11b STCK high to STXD low 2 51 3 99 2 2 3 5 ns 12 STCK high to STXD high impedance 12 43 14 59 10 9 12 8 ns 13 SRXD setup time before SRCK low 20 17 5 ns 14 SRXD hold time after SRCK low 0 0 ns External Clock Operation Port B Alternate Function 15 STCK SRCK clock period 92 8 81 4 ns 16 STCK SRCK clock high period 27 1 40 7 ns 17 STCK SRCK clock low period 61 1 40 7 ns 18 STCK high to STFS bl high 92 8 0 81 4 ns 19 SRCK high to SRFS bl hi
19. Valic Data A Write Data V1 Word Last Valid Data 1 Last Valid Addr X Address V1 Address Vi 2 ki Write A n weim eb weim data out i y Last Valid Data Y 1 2 Half Word A 2 2 Half Word Figure 15 WSC 3 WEA 2 WEN 3 A WORD E HALF MC9328MXL Advance Information Rev 5 30 Freescale Semiconductor hclk hsel weim cs 2 htrans hwrite haddr hready weim hrdata weim hready weim bclk weim addr weim cs 2 weim r w Specifications jeu edd CAN E ifs Y Nonseq f A Read JE 4 n Last Valid Data Last Valid Addr Y Address V1 Address V1 2 weim Iba weim oe weim eb EBC 0 weim eb EBC 1 weim data in Read 1 2 Half Word uU 2 2 Half Word I Figure 16 WSC 3 OEN 2 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 31 p Specifications ee pure X NER RD j hsel weim cs 2 4 1 E htrans Nonseq Y hwrite A Read haddr Y vi A hready fo sil weim hrdata Last Valid Data V1 Word weim hreadv A Tu
20. a data acknowledge signal the bus time out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only CS5 group is designed to support DTACK signal function when using the external DTACK signal for data acknowledgement 3 9 2 DTACK Signal Timing Figure 6 shows the access cycle timing used by chip select 5 The signal values and units of measure for this figure are found in Table 13 I4 ENTRE TESTE SE EXT DTACK 4 O INT_DTACK Figure 6 DTACK Timing WSC 111111 DTACK_sel 0 Table 13 Access Cycle Timing Parameters H t 1 8V 0 10V 3 0V 0 30V No Characteristic Unit l Min Max Min Max 1 CS5 asserted to OE asserted T T ns 2 External DTACK input setup from CS5 0 0 ns asserted 3 CS5 pulse widih 3T 3T ns 4 External DTACK input hold after CS5 is 0 1 5T 0 1 5T ns negated 5 OE negated after CS5 is negated 0 4 5 0 4 ns Note 1 n is the number of wait states in the current memory access cycle The max n is 1022 2 T is the system clock period system clock is 96 MHz 3 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state MC9328MXL Advance Information Rev 5 Freescale Semiconductor 21 Specifications iku TRETE TETE ATA TE me _ST Ff ao ik e MIN gt EXT_DTACK WAIT INT_DTACK
21. and timing diagrams for the MC9328MXL processor 3 1 Maximum Ratings Table 4 provides information on maximum ratings Table 4 Maximum Ratings Rating Symbol Minimum Maximum Unit Supply voltage Vidd 0 3 3 3 V Maximum operating temperature range TA 0 70 C MC9328MXLVH20 MC9328MXLVM20 MC9328MXLVF20 MC9328MXLVP20 Maximum operating temperature range Ta 30 70 C MC9328MXLDVH20 MC9328MXLDVM20 MC9328MXLDVF20 MC9328MXLDVP20 Maximum operating temperature range TA 40 85 C MC9328MXLCVH15 MC9328MXLCVM15 MC9328MXLCVF15 MC9328MXLCVP15 ESD at human body model HBM VESD_HBM d 2000 ESD at machine model MM VESD MM 100 Latch up current ILatchup 200 mA Storage temperature Test 55 150 C Power Consumption Pmax 800 1300 mw 1 Atypical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core that is 7x GPIO 15x Data bus and 8x Address bus 2 A worst case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core that is 32x GPIO 30x Data bus 8x Address bus These calculations are based on the core running its heaviest OS application at 200MHz and where the whole image is running out of SDRAM QVDD at 2 0V NVDD and AVDD at 3 3V therefore 180mA is the worst measurement recorded in the factory environment max 5mA is consumed for OSC pads with each toggl
22. bit 1 23 ns 16 MS SDIO input hold time for MS SCLKO falling edge RED bit 1 0 ns 1 Loading capacitor condition is less than or equal to 30pF 2 An external resistor 100 200 ohm should be inserted in series to provide current control on the MS SDIO pin because of a possibility of signal conflict between the MS SDIO pin and Memory Stick SDIO pin when the pin direction changes 3 If the MSC2 RED bit 0 MSHC samples MS SDIO input data at MS SCLKO rising edge 4 If the MSC2 RED bit 1 MSHC samples MS SDIO input data at MS SCLKO falling edge MC9328MXL Advance Information Rev 5 Freescale Semiconductor 59 Specifications 3 14 Pulse Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency The selected clock signal is passed through a divider and a prescaler before being input to the counter The output is available at the pulse width modulator output PWMO external pin Its timing diagram is shown in Figure 47 and the parameters are listed in Table 22 System Clock PWM Output Figure 47 PWM Output Timing Diagram Table 22 PWM Output Timing Parameter Table Ref 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 1 System CLK frequency 0 87 0 100 MHz 2a Clock high time 3 3 5 10 ii ns 2b Clock low time 7 5 5 10 ns 3a Clock fall time 5 5 10 ns 3b Clock rise time 6 67 5
23. el ede PA Last Valid Addy Address V1 Address V5 ip Read GENES v wona Yo word IK vs word We word Figure 26 WSC 3 SYNC 1 A HALF E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 41 Specifications hclk hsel_weim_cs 2 htrans hwrite haddr hreadv weim hrdata weim hready weim bclk weim addr weim cs 2 weim r w weim Iba weim oe weim eb EBC 0 weim eb EBC 1 weim ecb weim data in JA PA ZA ei Sm Xm C Xm XX He Read Read 77 Read V Read CY CX OCC OO mi gie Last Valid Data Y V1 Word Y V2 Word Y V3 Word Y V4 Word m JA 4 cm Last Valid Addk Address V1 iet E V1 Word X V2 Word X V3 Word X V4 Word Figure 27 WSC 2 SYNC 1 DOL 1 0 A WORD E WORD MC9328MXL Advance Information Rev 5 42 Freescale Semiconductor hclk hsel weim cs 2 htrans hwrite haddr hready weim hrdata weim hready weim bclk weim addr weim cs 2 weim r w weim Iba weim oe weim eb EBC 0 weim eb EBC 1 weim ecb weim data in Specifications ap d A
24. od prog val sa sa vso Lv 83 za3 AZETVIX vivaTozi 119 Oel ISHI 01008 1008 L3xoas enoa ga za goa 9a s9 oga 6a ev MIOXId ino IG SWL 1d Iso Iso z1009 13534 dS 13534 LWDQ La L1Vd va ov a old 193 vv ONASH NV Sd ISO 9d ISO ONASA ISO Iso vd Iso IGN3 Dia NI 13S3H Svu OLVW MH LSSAN 10as 9v La zia sv ed Iso 2d iso La Iso od ISO 19W ISO OWMd NIL MOL Svo LSSAN LOGAN via sia eta IN 8v stan ZLNOL rian stan zan otan ZAGAN ZAGAN LOGAN ISSAN LSSAN LOGAN zia 6v gta ouv ESSAD ECONO La 801 zan 907 ZSSAN ZSSAN LOGAN LSSAN LOGAN LOGAN ela sia LIV zv gan 601 san vai zai 001 Sd LaaGAD ISSAD LSSAN LOGAN LOGAN oza viv zza ely ISOW SLO MIOXL IVOXL tan ONASA ONASH GOV 30 ISVHLNOO s19 ON Las TLLHVA LISS LISS Laa eza vza LIV SLY OSIN SAXL axi SA4XL udS dS 11981 ON ON A38 ON ON Las 0ISS ziyvn USS 91V 61v sza zed 8Lv IVOXL sit ON ON ON ON ON ON ON SS las BUS zitvn WA aasn z1va gza sza Lay ozy Age ldS 1vax4 OWA OdA anasns ON ON ON ON ON ON ON ds BUS aasn aasn aasn SAX HSS 6za osa zev axl Siki axe SLO AOU ON ON ON ON ON ON ON TLLHVA 0ISS ziuvn ziuvn aasn MIOXY LISS OLva Lea ev NIOS MIOXL NIOXH 308 ON ON ON SSAD ON ON ON Las ois 0ISS dA aasn aasn 1vaxy ss ama kiwa vev axu sit 34V ON ON ON raaAo ON ON SAGAN TLLHVA TLLHVA ESSAN YAGAN qasn YSSAN 19 elva LSSAN 9L SL bl L Al LI 0L 6 8 L 9 S v
25. programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 31 on page 76 NO M RO e HSYNC A 8 40 ii I I pp n xul MU a 1 l LI i i i Valid Dat Valid Dat lt lt l 70 06 Figure 59 Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge MC9328MXL Advance Information Rev 5 Freescale Semiconductor 75 Specifications VSYNC HSYNC I I I PIXCLK ue s om e I 1 I X Valid Data X Valid Data Valid Data I i I DATA 7 0 5 910 Figure 60 Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 31 Gated Clock Mode Timing Parameters Ref No Parameter Min Max Unit 1 csi vsync to csi hsync 180 ns 2 csi hsync to csi pixclk 1 ns 3 csi_d setup time 1 ns 4 csi d hold time 1 ns 5 csi pixcik high time 10 42 ns 6 csi pixclk low time 10 42 ns 7 csi pixclk frequency 0 48 MHz The limitation on pixel clock rise time fall time are not specified It should be calculated from the hold time and setup time according to Rising edge latch data max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time
26. the registered trademark of ARM Limited ARM9 ARM920T and ARM9TDMI are the trademarks of ARM Limited O Freescale Semiconductor Inc 2004 All rights reserved e 2 freescale semiconductor
27. 2 PBGA 225 Package Dimensions Figure 64 illustrates the 225 PBGA 13 mm x 13 mm x 0 8 mm package Case Outline 1304B B T 13 4 C 225x OJo Apr A 1 INDEX AREA A i PA 0 2 A A PLANE 13 b D 0 15 i RP Pooooooo oooooooo N 996o60600600060606090 M 4 490 9009000940040 14x 0 8 L AA AA AA AA AA AA AA AA AA AAA K oo6o ooooooooooo J PROSS 1 2 nl e e e e e e 000009006 D C 499 dd Fl o 6o696o06oo0o0ooo0690909 El oo6o6ooo00oooooo020 D OHLOVOGQOPGOGGGOB c ooo6oo9o9o0o09009090909O B ooo6999909o0o90909 zc a 1 16 ALe6e9e6ee0e0e0e6e0oe6e06o0e069o0o0 mall 040 1234567 89101112131415 225X 99 45 A i NM SPE A1 INDEX AREA BOTTOM VIEW a G o Le A BIC SIDE VIEW NOTES MALL DIMENSIONS ARE IN MILLIMETERS DIMENSIONS AND TOLERANCES PER ASME V14 5M 1994 MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A A DATUM A THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE Figure 64 MC9328MXL 225 PBGA Mechanical Drawing MC9328MXL Advance Information Rev 5 82 Freescale Semiconductor NOTES MC9328MXL Advance Information Rev 5 Freescale Semiconductor 83 How to Reach Us
28. 2 Width of internal POWER ON RESET 300 300 300 300 ms CLK32 at 32 kHz 3 7K to 32K cycle stretcher for SDRAM reset 7 7 7 7 Cycles of CLK32 4 14K to 32K cycle stretcher for internal system reset 14 14 14 14 Cycles of HRESERT and output reset at pin RESET OUT CLK32 5 Width of external hard reset RESET IN 4 4 Cvcles of CLK32 6 AK to 32K cvcle qualifier 4 4 4 4 Cvcles of CLK32 POR width is dependent on the 32 or 32 768 kHz crvstal oscillator start up time Design margin should allow for crvstal tolerance i MX chip variations temperature impact and supplv voltage influence Through the process of supplving crvstals for use with CMOS oscillators crvstal manufacturers have developed a working knowledge of start up time of their crvstals Tvpicallv start up times range from 400 ms to 1 2 seconds for this tvpe of crvstal If an external stable clock source alreadv running is used instead of a crvstal the width of POR should be ignored in calculating timing for the start up process MC9328MXL Advance Information Rev 5 18 Freescale Semiconductor pu Specifications 3 9 External Interface Module The External Interface Module EIM handles the interface to devices external to the MC9328MXL including the generation of chip selects for external peripherals and memory The timing diagram for the EIM is shown in Figure 5 and Table 12 on page 20 defines the parameters of signals HCLK Bus Clock A A c BE
29. 7 0 ETM packet signals which are multiplexed with ECB LBA BCLK burst clock PA17 A 19 16 ETMTRACEPKT 7 0 are selected in ETM mode CMOS Sensor Interface CSI D 7 0 Sensor port data CSI MCLK Sensor port master clock CSI VSYNC Sensor port vertical sync CSI HSYNC Sensor port horizontal sync CSI PIXCLK Sensor port data latch clock LCD Controller LD 15 0 LCD Data Bus All LCD signals are driven low after reset and when LCD is off FLM VSYNC Frame Sync or Vsync T his signal also serves as the clock signal output for the gate driver dedicated signal SPS for Sharp panel HR TFT LP HSYNC Line pulse or H sync LSCLK Shift clock ACD OE Alternate crystal direction output enable CONTRAST This signal is used to control the LCD bias voltage as contrast control SPL SPR Program horizontal scan direction Sharp panel dedicated signal PS Control signal output for source driver Sharp panel dedicated signal CLS Start signal output for gate driver This signal is an inverted version of PS Sharp panel dedicated signal REV Signal for common electrode driving signal preparation Sharp panel dedicated signal SPI 1 and 2 SPI1 MOSI Master Out Slave In SPI1_MISO Slave In Master Out SPH SS Slave Select Selectable polarity SPI1 SCLK Serial Clock SPI1_SPI_RDY Serial Data Ready SPI2 TXD SPI2 Master TxData Output This signal is multiplexed with a GPI O pin yet shows up as a primary or alternative signal in the signal multip
30. CK falling 15 4 13 5 ns 32 SRXD hold after STCK falling 0 0 ns Synchronous External Clock Operation Port C Primary Function 33 SRXD setup before STCK falling 1 14 1 0 ns 34 SRXD hold after STCK falling 0 0 ns 1 All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame svnc STFS SRFS shown in the tables and in the figures 2 There are 2 sets of I O signals for the SSI module They are from Port C primary function pad 257 to pad 261 and Port B alternate function pad 283 to pad 288 When SSI signals are configured as outputs they can be viewed both at Port C primary function and Port B alternate function When SSI signals are configured as input the SSI module selects the input based on status of the FMCR register bits in the Clock controller module CRM By default the input are selected from Port C primary function 3 bl bitlength wl word length Table 30 SSI Port B Alternate Function Timing Parameter Table 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation Port B Alternate Function 1
31. E3 a LI ARM O Freescale Semiconductor Inc 2004 All rights reserved m La This document contains information on a new product Specifications and information herein are i gt x subject to change without notice ze freescale semiconductor Introduction System Control Standard Power CGM System 1 0 ello Connectivity MC9328MXL PWM CPU Complex ARMSTDMI Watchdog Multimedia Interitipt Accelerator AIPI 1 VMMU COR i DMAC Bus AIPI 2 11 Chnl Human Interface EIM 8 LCD Controller SDRAMC Figure 1 MC9328MXL Functional Block Diagram 1 1 Conventions This document uses the following conventions OVERBAR is used to indicate a signal that is active when pulled low for example RESET Logic level one is a voltage that corresponds to Boolean true 1 state Logic level zero is a voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one To clear a bit or bits means to establish logic level zero A signal is an electronic construct whose state conveys or changes in state convey information A pin is an external physical connection The same pin can be used to connect a number of signals Asserted means that a discrete signal is in active logic state Active low signals change from logic level one to logic level zero Active high signals change from logic level zero to logic level one Negated means that an asserted discrete signal chan
32. ETM are programmed through a JTAG interface The interface is an extension of the ARM920T processor s TAP controller and is assigned scan chain 6 The scan chain consists of a 40 bit shift register comprised of the following e 32 bit data field e 7 bit address field e A read write bit The data to be written is scanned into the 32 bit data field the address of the register into the 7 bit address field and a 1 into the read write bit A register is read by scanning its address into the address field and a 0 into the read write bit The 32 bit data field is ignored A read or a write takes place when the TAP controller enters the UPDATE DR state The timing diagram for the ETMO is shown in Figure 2 See Table 9 for the ETM9 timing parameters used in Figure 2 a Valid Data EE Valid Data 42 lt gt ab Figure 2 Trace Port Timing Diagram TRACECLK TRACECLK Half Rate Clocking Mode Output Trace Port Table 9 Trace Port Timing Diagram Parameter Table MC9328MXL Advance Information Rev 5 DE 1 8V 0 10V 3 0V 0 30V UN Parameter Unit i Minimum Maximum Minimum Maximum 1 CLK frequency 0 85 0 100 MHz 2a Clock high time 1 3 2 ns 2b Clock low time 3 2 ns Freescale Semiconductor Specifications Table 9 Trace Port Timing Diagram Parameter Table Continued 1 8V 0 10V 3 0V x 0 30V Ref f No Parameter Unit Minimum Maximum Min
33. FIM CO328MXLCV EL StH hig Freescale Semiconductor MC9328MXL D Advance Information Rev 5 08 2004 MC9328MXL Package Information Plastic Package M C9328 MX L MAPBGA 225 or 256 Ordering Information See Table 2 on page 5 1 Introduction Contents 1 Introduction 1 TI family builds on the DragonBall family of 2 Signals and Connections 6 application processors which have demonstrated leadership A in the portable handheld market Continuing this legacy the 4 Pin Out and Package Information 2 BEES Ee sions Hee provides e leap m Contact Information Last Page performance with an ARMOTM microprocessor core and highly integrated system functions The i MX products specifically address the requirements of the personal portable product market by providing intelligent integrated peripherals an advanced processor core and power management capabilities The new MC9328MXL features the advanced and power efficient ARM920T M core that operates at speeds up to 200 MHz Integrated modules which include an LCD controller USB support and an MMC SD host controller support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience It is packaged in either a 256 pin Mold Array Process Ball Grid Array MAPBGA or 225 pin PBGA package Figure 1 shows the functional block diagram of the MC9328MXL a L a Li
34. Latches Data on Pixel Clock Falling Edge Table 32 Non Gated Clock Mode Parameters Ref No Parameter Min Max Unit 1 csi_vsync to csi_pixclk 180 ns 2 csi d setup time 1 ns 3 csi d hold time 1 ns 4 csi pixclk high time 10 42 ns 5 csi pixclk low time 10 42 ns 6 csi pixclk frequency 0 48 MHz The limitation on pixel clock rise time fall time are not specified It should be calculated from the hold time and setup time according to max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time 1ns setup time Ins positive duty cycle 10 2 5ns gt max rise time allowed 5 1 4ns negative duty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time max rise time allowed positive duty cycle setup time MC9328MXL Advance Information Rev 5 78 Freescale Semiconductor Pin Out and Package Information yoojo JsINQ ZSSAO IN9LTIVLX W9LIVIXA 3lvISIBL LAGAY ONTO amas zwod LLVIN oso 1s9 zso sso 30 av LSSAN NZETVLXA 2ZadAo OGL L1008 HOd oFyoas owoa
35. SA LSVHLNOO LLEVAN 0ISS eluvn aasn ziva LISS LISS olya Lead HdS axl Lvaxe OWA adv vax zan 907 gan 001 ds NIOS1 SS Las LLEVAN 0ISS aasn Aou aasn aasn LISS m0 elva 10S MIOXL S4XH aNasns 304 MIOXL 1oxu san vai zai Sd A3H Las AQH Las 0ISS 0ISS WA aasn aasn aasn HSS LISS QNO st bl L ZL LI OL 6 8 L 9 S r z L sjueuiuBissy uid VOEAd SZZ 1XINSCE6OW VE 9Iqer egexoed YD Ed utd czc ou 103 SJUMMUSISSE urd a3exoed ayi SOJLJISNJJI pe o qe MC9328MXL Advance Information Rev 5 Freescale Semiconductor 80 Pin Out and Package Information 4 1 MAPBGA 256 Package Dimensions Figure 63 illustrates the 256 MAPBGA 14 mm x 14 mm x 1 30 mm package which has 0 8 mm spacing between the pads The device designator for the MAPBGA package is VH Case Outline 1367 T R P N M L K J G F E A 833 gt 1 12 i 12345578910 12 14 16 si 11 13 15 1 25 A1 INDEX 258x a84 A E SIDE VIEW ig 015 A5IC BOTTOM VIEW DEBEN NOTES 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 A MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A DATUM A THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS Figure 63 MC9328MXL 256 MAPBGA Mechanical Drawing MC9328MXL Advance Information Rev 5 Freescale Semiconductor 81 Pin Out and Package Information 4
36. USA Europe Locations Not Listed Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 Asia Pacific Freescale Semiconductor Hong Kong Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Home Page www freescale com MC9328MXL D Rev 5 08 2004 Information in this document is provided solelv to enable svstem and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate anv integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to anv products herein Freescale Semiconductor makes no warrantv representation or guarantee regarding the suitabilitv of its products for anv particular purpose nor does Freescale Semiconductor assume anv liabilitv arising out of the application or use of anv product or circuit and specificallv disclaims anv and all liabilitv including without limitation consequential or incidental damages Tvpical parameters that mav be provided in Freescale Semiconductor data sheets and or specifications can and do varv in different applications and actual performan
37. able 6 contains both maximum and minimum DC characteristics of the MC9328MXL Table 6 Maximum and Minimum DC Characteristics Number or Symbol Parameter Min Typical Max Unit lop Full running operating current at 1 8V for QVDD 3 3V for QVDD at mA NVDD AVDD Core 96 MHz System 96 MHz MPEG4 1 8v 120mA decoding playback from external memory card to both NVDD AVDD at external SSI audio decoder and TFT display panel and OS 3 0v 30mA with MMU enabled memory system is running on external SDRAM Sidd Standby current 25 E LA Core 150 MHz QVDD 1 8V temp 25 C Sidd Standby current 45 LA Core 150 MHz QVDD 1 8V temp 55 C Sidds Standby current 35 pA Core 150 MHz QVDD 2 0V temp 25 C MC9328MXL Advance Information Rev 5 12 Freescale Semiconductor Table 6 Maximum and Minimum DC Characteristics Continued Specifications Number or Symbol Parameter Min Typical Max Unit Sidd4 Standby current 60 LA Core 150 MHz QVDD 2 0V temp 55 C VIH Input high voltage 0 7Vpp Vdd 0 2 V ViL Input low voltage 0 4 V VoH Output high voltage lop 2 0 mA 0 7Vpp Vdd V VOL Output low voltage lo 2 5 mA 0 4 V liL Input low leakage current 1 HA Vin GND no pull up or pull down liy Input high leakage current 1 LA Vin Vpp no pull up or pull down
38. al Descriptions Continued Signal Name Function Notes UART1 RTS Request to Send UART1 CTS Clear to Send UART2 RXD Receive Data UART2 TXD Transmit Data UART2 RTS Request to Send UART2 CTS Clear to Send UART2 DSR Data Set Readv UART2 RI Ring Indicator UART2 DCD Data Carrier Detect UART2 DTR Data Terminal Readv Serial Audio Port SSI configurable to I S protocol SSI TXDAT Transmit Data SSI RXDAT Receive Data SSI TXCLK Transmit Serial Clock SSI RXCLK Receive Serial Clock SSI TXFS Transmit Frame Sync SSI RXFS Receive Frame Sync PC I2C SCL I C Clock I2C SDA I C Data PWM PWMO PWM Output Digital Supplv Pins NVDD Digital Supplv for the I O pins NVSS Digital Ground for the I O pins Supply Pins Analog Modules AVDD Supply for analog blocks AVSS Quiet ground for analog blocks Internal Power Supply QVDD Power supply pins for silicon internal circuitry QVSS Ground pins for silicon internal circuitry MC9328MXL Advance Information Rev 5 10 Freescale Semiconductor Specifications Table 3 MC9328MXL Signal Descriptions Continued Signal Name Function Notes Substrate Supply Pins SVDD Supply routed through substrate of package not to be bonded SGND Ground routed through substrate of package not to be bonded 3 Specifications This section contains the electrical specifications
39. ata Last Valid Data y Write Data weim_hrdata Last Valid Data X Read Data weim hready 1 weim bclk weim addr Last Valid Addr Address V Address V8 weim cs 2 V weim r w Read Write weim ba weim oe V weim eb EBC 0 ES AE AT ATA AR 73 weim eb EBC 1 weim_data_in Read Data Last Valid Data Y weim_data_out Write Data Figure 21 WSC 2 WWS 1 WEA 1 WEN 2 EDC 1 A HALF E HALF MC9328MXL Advance Information Rev 5 36 Freescale Semiconductor hclk hsel weim cs 4 htrans hwrite haddr hready hwdata weim hrdata weim hready weim bclk weim addr weim cs Specifications je palm aay eg Y Write y yi YE E Last Valid Data gt lt Write Data Word Last Valid Data Last Valid Addr Address V1 Address V1 2 weim r w weim Iba weim oe weim eb weim data out hec y Write of L EA Last Valid Data X Write Data 1 2 Half Word A Write Data 2 2 Half Word Figure 22 WSC 2 CSA 1 WWS 1 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 37 Specificati
40. ce may varv over time All operating parameters including Tvpicals must be validated for each customer application bv customer s technical experts Freescale Semiconductor does not convev anv license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in svstems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directiv or indirectiv any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the propertv of their respective owners The ARM POWERED logo is
41. d in the open drain mode The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 39 The symbols for Figure 39 through Figure 43 are defined in Table 19 Table 19 State Signal Parameters for Figure 39 through Figure 43 After a card receives its RCA it switches to data transfer mode As shown on the first diagram in Figure 40 SD CMD lines in this mode are driven with push pull drivers The command is followed by a period of two Z bits allowing time for direction switching on the bus and then by P bits pushed up by the Card Active Host Active Symbol Definition Symbol Definition Z High impedance state S Start bit 0 D Data bits T Transmitter bit Host 1 Card 0 Repetition P One cvcle pull up 1 CRC Cvclic redundancv check bits 7 bits E End bit 1 Nip cvcles Host Command CID OCR ovo BT wa Tcp EHI en ER Identification Timing Nor cycles Host Command gt gt CID OCR ovo BT wa pe EHI eme ERR SET RCA Timing Figure 39 Timing Diagrams at Identification Mode responding card The other two diagrams show the separating periods Ngc and Nec MC9328MXL Advance Information Rev 5 Specifications Freescale Semiconductor 51 Specifications Ncp cycles Host Command gt Response ovo feji O jena Epp Command response timing data transfer mode Nec cycles Response Host C
42. e GPIO consuming 4mA MC9328MXL Advance Information Rev 5 Freescale Semiconductor 11 Specifications 3 2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages The MC9328MXL has multiple pairs of VDD and VSS power supply and return pins QVDD and QVSS pins are used for internal logic All other VDD and VSS pins are for the I O pads voltage supply and each pair of VDD and VSS provides power to the enclosed I O pads This design allows different peripheral supply voltage levels in a system Because AVDD pins are supply voltages to the analog pads it is recommended to isolate and noise filter the AVDD pins from other VDD pins For more information about I O pads grouping per VDD please refer to Table 3 on page 6 Table 5 Recommended Operating Range Rating Svmbol Minimum Maximum Unit O supply voltage if using MSHC SPI BTA USBd LCD and CSI NVDD 2 70 3 30 V which are oniv 3 V interfaces I O supply voltage if not using the peripherals listed above NVDD 1 70 3 30 V Internal supplv voltage Core 150 MHz QVDD 1 70 1 90 V Internal supply voltage Core 200 MHz QVDD 1 80 2 00 V Analog supply voltage AVDD 1 70 3 30 V 3 3 Power Sequence Requirements For required power up and power down sequencing please refer to the Power Up Sequence section of application note AN2537 on the i MX website page 3 4 DC Electrical Characteristics T
43. el6oud Asnq seuio2eq pied 4o0 q ejep SEJ Jeye pA UOISSILISUEJ dois zeze Guluwel60 d Asnq seowoveq pied 490 q ejep 1se Jaye peAreooi UOISSIWSUBL dois pJeo ay Wouj Josue SNIS JHO Buunp uoissiusuej dois SOU OU WOUJ JejsueJ eyep Buunp uolssiwsue dois di elejjejjojjejjejjejjejjejejjejjejja oo e TE PUEWWIOI JSOH oom fl z z a a ouo wewo per ppp esuodsay pied mi sejoAo HON z z z a E a a PPPEPP vva puewwo ISOH Figure 43 Stop Transmission During Different Scenarios MC9328MXL Advance Information Rev 5 55 Freescale Semiconductor Specifications Table 20 Timing Values for Figure 39 through Figure 43 Parameter Symbol Minimum Maximum Unit Parameter MMC SD bus clock CLK All values are referred to minimum VIH and maximum MMC SD bus clock CLK VIL All values are referred to minimum VIH and maximum VIL Command response cycle NCR 2 64 Clock Command response cycle cycles Identification response cycle NID 5 5 Clock Identification response cycles cycle Access time delay cycle NAC 2 TAAC NSAC Clock Access time delay cycle cycles Command read cycle NRC 8 Clock Command read cycle cycles Command command cycle NCC 8 Clock Command command cycle cycles Command write cycle NWR 2 Clock Command write cycle cycles Stop transmission cycle NST 2 2 Clock Stop transmissio
44. er DDI O157E MC9328MXL Product Brief order number MC9328MXLP D MC9328MXL Reference Manual order number MC9328MXLRM D The Motorola manuals are available on the Motorola Semiconductors Web site at http www motorola com semiconductors These documents may be downloaded directly from the Motorola Web site or printed versions may be ordered The ARM Ltd documentation is available from http www arm com MC9328MXL Advance Information Rev 5 4 Freescale Semiconductor 1 6 Ordering Information Introduction Table 2 provides ordering information for both the 256 lead mold array process ball grid array MAPBGA package and the 225 lead BGA package Table 2 MC9328MXL Ordering Information Package Type Frequency Temperature Solderball Type Order Number 256 lead MAPBGA 150 MHz 40 C to 85 C Standard MC9328MXLCVH15 R2 Pb free MC9328MXLCVM15 R2 200 MHz 0 C to 70 C Standard MC9328MXLVH20 R2 Pb free MC9328MXLVM20 R2 30 C to 70 C Standard MC9328MXLDVH20 R2 Pb free MC9328MXLDVM20 R2 225 lead MAPBGA 150 MHz 40 C to 85 C Standard MC9328MXLCVF15 R2 Pb free MC9328MXLCVP15 R2 200 MHz 0 C to 70 C Standard MC9328MXLVF20 R2 Pb free MC9328MXLVP20 R2 30 C to 70 C Standard MC9328MXLDVF20 R2 Pb free MC9328MXLDVP20 R2 MC9328MXL Advance Information Rev 5 Freescale Semiconductor Signals and Connections 2 Signals and Connections Table 3 identifies and d
45. escribes the MC9328MXL signals that are assigned to package pins The signals are grouped by the internal module that they are connected to Table 3 MC9328MXL Signal Descriptions Signal Name Function Notes External Bus Chip Select EIM A 24 0 Address bus signals D 31 0 Data bus signals EBO MSB Byte Strobe Active low external enable byte signal that controls D 31 24 EB1 Byte Strobe Active low external enable byte signal that controls D 23 16 EB2 Byte Strobe Active low external enable byte signal that controls D 15 8 EB3 LSB Byte Strobe Active low external enable byte signal that controls D 7 0 OE Memory Output Enable Active low output enables external data bus CS 5 0 Chip Select The chip select signals CS 3 2 are multiplexed with CSD 1 0 and are selected by the Function Multiplexing Control Register FMCR By default CSD 1 0 is selected ECB Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on going burst sequence and initiate a new long first access burst sequence LBA Active low signal sent by a flash device causing the external burst device to latch the starting burst address BCLK burst clock Clock signal sent to external synchronous memories such as burst flash during burst mode RW RW signal Indicates whether external access is a read high or write
46. gering mechanisms ka B ene sono uO Figure 31 Master SPI Timing Diagram Using SPI RDY Edge Trigger SPIRDY A m Figure 32 Master SPI Timing Diagram Using SPI_RDY Level Trigger SS output Figure 33 Master SPI Timing Diagram Ignore SPI RDY Level Trigger SS input Figure 34 Slave SPI Timing Diagram FIFO Advanced by BIT COUNT MC9328MXL Advance Information Rev 5 46 Freescale Semiconductor Specifications S input SCLK MOSI MISO Figure 35 Slave SPI Timing Diagram FIFO Advanced bv SS Rising Edge Table 15 Timing Parameter Table for Figure 31 through Figure 35 1 8V 0 10V 3 0V 0 30V Ref Parameter Unit No Minimum Maximum Minimum Maximum 1 SPI RDY to SS output low oT oT ns 2 SS output low to first SCLK 3 e Tsclk 2 3 Tsclk ns edge 3 Last SCLK edge to SS output 2 e Tsclk 2 e Tsclk ns high 4 SS output high to SPI RDY 0 0 ns low 5 SS output pulse width Tsclk Tsclk ns WAIT WAIT 6 SS input low to first SCLK T T ns edge 7 SS input pulse width T T ns T CSPI system clock period PERCLK2 2 Tsclk Period of SCLK WAIT Number of bit clocks SCLK or 32 768 kHz clocks per Sample Period Control Register e 3 11 LCD Controller This section includes timing diagrams for the LCD controller For detailed timing diagrams of the LCD controller with various display config
47. ges logic state Active low signals change from logic level zero to logic level one Active high signals change from logic level one to logic level zero LSB means least significant bit or bits and MSB means most significant bit or bits References to low and high bytes or words are spelled out Numbers preceded by a percent sign Yo are binary Numbers preceded by a dollar sign or 0x are hexadecimal MC9328MXL Advance Information Rev 5 Freescale Semiconductor Introduction 1 2 Features To support a wide variety of applications the MC9328MXL offers a robust array of features including the following e ARM920T Microprocessor Core e AHB to IP Bus Interfaces AIPIs External Interface Module EIM SDRAM Controller SDRAMC DPLL Clock and Power Control Module e Two Universal Asynchronous Receiver Transmitters UART 1 and UART 2 e Two Serial Peripheral Interfaces SPI1 and SPI2 Two General Purpose 32 bit Counters Timers e Watchdog Timer e Real Time Clock Sampling Timer RTC LCD Controller LCDC e Pulse Width Modulation PWM Module e Universal Serial Bus USB Device Multimedia Card and Secure Digital MMC SD Host Controller Module Memory Stick Host Controller MSHC Direct Memory Access Controller DMAC Synchronous Serial Interface and Inter IC Sound SSI I S Module Inter IC C Bus Module Video Port e General Purpose I O GPIO Ports Bootstrap Mode e Multimedia Accele
48. gh 92 8 0 81 4 ns 20 STCK high to STFS bl low 92 8 0 81 4 ns 21 SRCK high to SRFS bl low 92 8 0 81 4 ns 22 STCK high to STFS wl high ii 92 8 0 81 4 ns 23 SRCK high to SRFS wl high 92 8 0 81 4 ns 24 STCK high to STFS wl low 92 8 0 81 4 ns 25 SRCK high to SRFS wl low 92 8 0 81 4 ns 26 STCK high to STXD valid from high 18 9 29 07 16 6 25 5 ns impedance 27a STCK high to STXD high 9 23 20 75 8 1 18 2 ns 27b STCK high to STXD low 10 60 21 32 9 3 18 7 ns 28 STCK high to STXD high impedance 17 90 29 75 15 7 26 1 ns 29 SRXD setup time before SRCK low 1 14 1 0 Z ns 30 SRXD hold time after SRCK low 0 0 T ns MC9328MXL Advance Information Rev 5 Freescale Semiconductor 73 Specifications Table 30 SSI Port B Alternate Function Timing Parameter Table Continued SE 1 8V 0 10V 3 0V 0 30V NG Parameter Unit a Minimum Maximum Minimum Maximum Synchronous Internal Clock Operation Port B Alternate Function 31 SRXD setup before STCK falling 18 81 16 5 ns 32 SRXD hold after STCK falling 0 0 ns Synchronous External Clock Operation Port B Alternate Function 33 SRXD setup before STCK falling 1 14 x 1 0 x ns 34 SRXD hold after STCK falling 0 0 ns 1 All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted fra
49. he MMC SD module inner system and the application user programming Bus Clock CMD DAT Input CMD DAT Output Figure 38 Chip Select Read Cycle Timing Diagram Table 18 SDHC Bus Timing Parameter Table Ref 1 8V 0 10V 3 0 0 30V N Parameter Unit Minimum Maximum Minimum Maximum 1 CLK frequency at Data transfer Mode 0 25 5 0 25 5 MHz PP 10 30 cards 2 CLK frequency at Identification Mode 0 400 0 400 kHz 3a Clock high time 10 30 cards 6 33 10 50 fa ns 3b Clock low time 10 30 cards 15 75 i 10 50 i ns 4a Clock fall time 10 30 cards gt 10 50 10 50 ns 5 00 3 4b Clock rise time 10 30 cards 14 67 10 50 ns 6 67 ba Input hold time3 10 30 cards 5 7 5 7 5 5 ns 5b Input setup time 10 30 cards 5 7 5 7 5 5 ns 6a Output hold time 10 80 cards 5 7 5 7 5 5 ns 6b Output setup time 10 30 cards 5 7 5 7 5 5 ns 7 Output delay time 0 16 0 14 ns 1 C 100 pF 250 pF 10 30 cards 2 C 250 pF 21 cards 3 C lt 25 pF 1 card MC9328MXL Advance Information Rev 5 50 Freescale Semiconductor 3 12 1 Command Response Timing on MMC SD Bus The card identification and card operation conditions timing are processed in open drain mode The card response to the host command starts after exactly Nip clock cycles For the card address assignment SET_RCA is also processe
50. hronous mode only Figure 57 SSI Transmitter External Clock Timing Diagram SRCK Input di O Ar SRFS bl Input XN amp SRFS wl Input D SRXD Input Figure 58 SSI Receiver External Clock Timing Diagram Table 29 SSI Port C Primary Function Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation Port C Primary Function 1 STCK SRCK clock period 95 A 83 3 ns 2 STCK high to STFS bl high 1 5 4 5 1 8 3 9 ns 3 SRCK high to SRFS bl high 1 2 1 7 1 1 1 5 ns MC9328MXL Advance Information Rev 5 70 Freescale Semiconductor Table 29 SSI Port C Primary Function Timing Parameter Table Continued Specifications 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 4 STCK high to STFS bl low 2 5 4 3 2 2 3 8 ns 5 SRCK high to SRFS bl low 0 1 0 8 0 1 0 8 ns 6 STCK high to STFS wl high 1 48 4 45 1 3 3 9 ns 7 SRCK high to SRFS wl high 1 1 1 5 1 1 1 5 ns 8 STCK high to STFS wl low 2 51 4 33 2 2 3 8 ns 9 SRCK high to SRFS wl low 0 1 0 8 0 1 0 8 ns 10 STCK high to STXD valid from high 14 25 15 73 12 5 13 8 ns impedance 11a STCK high to STXD high 0 91 3 08 0 8 2 7 ns 11b STCK high to STXD low 0 57 3 19 0 5 2
51. ied to both timers simultaneousiv TMR20UT Timer 2 Output USB Device USBD_VMO USB Minus Output USBD_VPO USB Plus Output USBD_VM USB Minus Input USBD_VP USB Plus Input USBD_SUSPND USB Suspend Output USBD_RCV USB Receive Data USBD_OE USB OE USBD_AFE USB Analog Front End Enable Secure Digital Interface SD_CMD SD Command If the system designer does not wish to make use of the internal pull up via the Pull up enable register a 4 7K 69K external pull up resistor must be added SD_CLK MMC Output Clock SD DAT 3 0 Data lf the system designer does not wish to make use of the internal pull up via the Pull up enable register a 50K 69K external pull up resistor must be added Memorv Stick Interface MS BS Memorv Stick Bus State Output Serial bus control signal MS SDIO Memorv Stick Serial Data Input Output MS SCLKO Memorv Stick Serial Clock Input Serial protocol clock source for SCLK Divider MS SCLKI Memory Stick External Clock Output Test clock input pin for SCLK divider This pin is only for test purposes not for use in application mode MS PIO General purpose InputO Can be used for Memory Stick Insertion Extraction detect MS PI General purpose Inputi Can be used for Memorv Stick Insertion Extraction detect UARTs IrDA Auto Bauding UART1 RXD Receive Data UART1 TXD Transmit Data MC9328MXL Advance Information Rev 5 Freescale Semiconductor 9 Signals and Connections Table 3 MC9328MXL Sign
52. imum Maximum 3a Clock rise time 4 3 ns 3b Clock fall time 3 3 ns 4a Output hold time 2 28 2 ns 4b Output setup time 3 42 3 ns MC9328MXL Advance Information Rev 5 Freescale Semiconductor 15 Specifications 3 7 DPLL Timing Specifications Parameters of the DPLL are given in Table 10 In this table T f is a reference clock period after the pre divider and Tq is the output double clock period Table 10 DPLL Specifications Parameter Test Conditions Minimum Typical Maximum Unit Reference clock freq range Vcc 1 8V 5 100 MHZ Pre divider output clock Vcc 1 8V 5 30 MHZ freq range Double clock freq range Vcc 1 8V 80 220 MHz Pre divider factor PD 1 16 Total multiplication factor MF Includes both integer 5 15 and fractional parts MF integer part 5 15 MF numerator Should be less than the 0 1022 denominator MF denominator 1 1023 Pre multiplier lock in time E 312 5 usec Freq lock in time after FOL mode for non integer MF 250 280 300 Tref full reset does not include pre multi lock in 56 us time Freq lock in time after FOL mode for non integer MF 220 250 270 Tref partial reset does not include pre multi lock in 50 us time Phase lock in time after FPL mode and integer MF does 300 350 400 Tref full reset not include pre multi lock in time 70 us Pha
53. is another feature in SDIO that allows the user to submit commands during the data transfer In this mode the block temporarily pauses the data transfer operation counter and related status yet keeps the clock running and allows the user to submit commands as normal After all commands are submitted the user can switch back to the data transfer operation and all counter and status values are resumed as access continues Jn Jun ao A Reese E DAT 1 Block Data Eizizit H Block Data For 4 bit For 4 bit Figure 45 SDIO ReadWait Timing Diagram 3 13 Memory Stick Host Controller The Memory Stick protocol requires three interface signal line connections for data transfers MS_BS MS_SDIO and MS_SCLKO Communication is always initiated by the MSHC and operates the bus in either four state or two state access mode The MS_BS signal classifies data on the SDIO into one of four states BSO BS1 BS2 or BS3 according to its attribute and transfer direction BSO is the INT transfer state and during this state no packet transmissions occur During the BS1 BS2 and BS3 states packet communications are executed The BS1 BS2 and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length in four state access mode The Memory Stick usually operates in four state access mode and in BS1 BS2 and BS3 bus states When an error occurs during packet communication the mode is shif
54. lex scheme table Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin SPI2 RXD SPI2 Master RxData Input This signal is multiplexed with a GPI O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin MC9328MXL Advance Information Rev 5 Freescale Semiconductor Signals and Connections Table 3 MC9328MXL Signal Descriptions Continued Signal Name Function Notes SPI2 SS SPI2 Slave Select This signal is multiplexed with a GPI O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin SPI2 SCLK SPI2 Serial Clock This signal is multiplexed with a GPI O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin General Purpose Timers TIN Timer Input Capture or Timer Input Clock The signal on this input is appl
55. low cycle Used as a WE input signal by external DRAM DTACK DTACK signal The external input data acknowledge signal When using the external DTACK signal as a data acknowledge signal the bus time out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed Bootstrap BOOT 3 0 System Boot Mode Select The operational system boot mode of the MC9328MXL upon system reset is determined by the settings of these pins SDRAM Controller SDBA 4 0 SDRAM SyncFlash non interleave mode bank address multiplexed with address signals A 15 11 These signals are logically equivalent to core address p addr 25 21 in SDRAM SvncFlash cycles SDIBA 3 0 SDRAM SyncFlash interleave addressing mode bank address multiplexed with address signals A 19 16 These signals are logically equivalent to core address p_addr 12 9 in SDRAM SyncFlash cycles MA 11 10 SDRAM address signals MA 9 0 SDRAM address signals which are multiplexed with address signals A 10 1 MA 9 0 are selected on SDRAM SyncFlash cycles DQM 3 0 SDRAM data enable CSDO SDRAM SyncFlash Chip select signal which is multiplexed with the CS2 signal These two signals are selectable by programming the system control register MC9328MXL Advance Information Rev 5 Freescale Semiconductor Signals and Connections Table 3 MC9328MXL Signal Descriptions Continued Signal Name Function Note
56. me sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures 2 There are 2 set of I O signals for the SSI module They are from Port C primary function pad 257 to pad 261 and Port B alternate function pad 283 to pad 288 When SSI signals are configured as outputs they can be viewed both at Port C primary function and Port B alternate function When SSI signals are configured as inputs the SSI module selects the input based on FMCR register bits in the Clock controller module CRM By default the input are selected from Port C primary function 3 bl bit length wl word length MC9328MXL Advance Information Rev 5 74 Freescale Semiconductor 3 19 CMOS Sensor Interface Specifications The CMOS Sensor Interface CSI module consists of a control register to configure the interface timing a control register for statistic data generation a status register interface logic a 32 x 32 image data receive FIFO and a 16 x 32 statistic data FIFO 3 19 1 Gated Clock Mode Figure 59 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 60 on page 76 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is
57. miconductor Table 17 4 8 16 Bit Pixel TFT Color Mode Panel Timing Continued Specifications Symbol Description Minimum Corresponding Register Value Unit T7 End of OE to beginning of HSYN 1 HWAIT1 1 Ts T8 SCLK to valid LD data 3 3 ns T9 End of HSYN idle2 to VSVN edge 2 2 Ts for non displav region T9 End of HSYN idle2 to VSVN edge 1 1 Ts for Displav region T10 VSYN to OE active Sharp 0 1 1 Ts when VWAIT2 0 T10 VSYN to OE active Sharp 1 2 2 Ts when VWAIT2 0 Note e Tsisthe SCLK period which equals LCDC CLK PCD 1 Normally LCDC CLK 15ns e VSYN HSYN and OE can be programmed as active high or active low In Figure 37 all 3 signals are active low e The polarity of SCLK and LD 15 0 can also be programmed e SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period In Figure 37 SCLK is always active e For T9 non display region VSYN is non active It is used as an reference e XMAX is defined in pixels MC9328MXL Advance Information Rev 5 Freescale Semiconductor 49 Specifications 3 12 Multimedia Card Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus DMA access internal MMC SD module data bus and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content empty or full FIFO address and byte block counters for t
58. n cycle cycles TAAC Data read access time 1 defined in CSD register bit 119 112 TAAC Data read access NSAC Data read access time 2 in CLK cvcles NSAC 100 defined in CSD register time 1 defined in CSD bit 111 104 register bit 119 112 NSAC Data read access time 2 in CLK cycles NSAC 100 defined in CSD register bit 111 104 3 12 2 SDIO IRQ and ReadWait Service Handling In SDIO there is a l bit or 4 bit interrupt response from the SDIO peripheral card In l bit mode the interrupt response is simply that the SD DATI line is held low The SD DATT 1 line is not used as data in this mode The memorv controller generates an interrupt according to this low and the svstem interrupt continues until the source is removed SD DATT 1 returns to its high level In 4 bit mode the interrupt is less simple The interrupt triggers at a particular period called the Interrupt Period during the data access and the controller must sample SD DAT 1 during this short period to determine the IRQ status of the attached card The interrupt period only happens at the boundary of each block 512 bytes MC9328MXL Advance Information Rev 5 56 Freescale Semiconductor Specifications JULLULLULLLLULULUUULT JOU ur omo sii Content Jonojefzjzjojaj Response Epa E DATI1 Interrupt Period Block Data IRQ Block Data E IRQ For 4 bit We 4 DATI1 Interrupt Period For 1 bit Figure 44 SDIO IRQ Timing Diagram ReadWait
59. nsfer mode Figure 41 Timing Diagrams at Data Read Figure 42 shows the basic write operation timing As with the read operation after the card response the data transfer starts after Nwp cycles The data is suffixed with CRC check bits to allow the card to check for transmission errors The card sends back the CRC check result as a CC status token on the data line If there was a transmission error the card sends a negative CRC status 101 otherwise a positive CRC status 010 is returned The card expects a continuous flow of data blocks if it is configured to multiple block mode with the flow terminated by a stop transmission command MC9328MXL Advance Information Rev 5 Freescale Semiconductor 53 Specifications pugwwoo ejum y90 q ajdizinui eui jo Buru L sejoko YMN sejoKo YMN lt SM SES sniels DUO Asng C 0 ejeq UM ejeq UM BB veo 5182009390022 o meo FREE sve A s Pee Po eo PARA s Fees vero FRE i eS San sejoAo YMN gt i pugwwoo anm J90Jq eui jo Buru L snjejs 949 Asng lt gt geed SUM AARNA seo BR e es iba es RI e ua Peewee eepo wawa jifli pgpp oso memo fip ano esuodsey puewwop 1SOH sajo o YIN Figure 42 Timing Diagrams at Data Write MC9328MXL Advance Information Rev 5 Freescale Semiconductor 54 Specifications The stop transmission command may occur when the card is in different states Figure 43 shows the different scenarios on the bus Guluw
60. ommand omo efi Comert fenci E Timing response end to next CMD start data transfer mode Ncc cycles Host Command Host Command omo feji coment Jeni E Timing of command sequences all modes Figure 40 Timing Diagrams at Data Transfer Mode Figure 41 on page 53 shows basic read operation timing In a read operation the sequence starts with a single block read command which specifies the start address in the argument field The response is sent on the SD CMD lines as usual Data transmission from the card starts after the access time delay Nac beginning from the last bit of the read command If the system is in multiple block read mode the card sends a continuous flow of data blocks with distance Nyc until the card sees a stop transmission command The data stops two clock cycles after the end bit of the stop command MC9328MXL Advance Information Rev 5 52 Freescale Semiconductor Specifications Nor cycles Host Command __ Response ovo ff ee Tec ET FREI n T8 1 pat zz zo Pas Read Data Nac cycles Timing of single block read Ncp cycles Host Command Response ovo Ef a ji amz fpe ji sd ss Jean __ Read Data I Read Data Nac cycles Nac cycles Timing of multiple block read Ncg cycles Host Command lt gt Response cmp sr Content Jonojejzjzjoj rr fejs Content oro Ej Nsr gt DAT fo ooo Valid Read Data Timing of stop command CMD12 data tra
61. ons hclk hsel weim cs 4 htrans hwrite haddr hready hwdata weim hrdata weim hready Sre i EE y m AN XNonseq Nonseq Y A Read Write n X vs YO JA Last Valid Data Wirite Data Last Valid Data gt lt Read Data weim bclk weim addr Last Valid Addr Address V1 ji Address V8 weim cs 4 TA weim_r w Read Write weim Iba a weim_oe weim_eb EBC 0 JE weim eb EBC 1 T Read Data weim data in weim data out Last Valid Data A Wirite Data Figure 23 WSC 3 CSA 1 A HALF E HALF MC9328MXL Advance Information Rev 5 38 Freescale Semiconductor XX Specifications a de E SRELE J hsel weim cs 4 A htrans Nonseq bi Idle y Seq A hwite Read Read A hadar Y vT Y va ww MON F weim hrdata Last Valid Data Y Read Data V1 Read Data V2 si ee mud eie YA INI FN INI NU NN NND weim addr Last Valid Y Address V1 Address V2 CNC weim_cs 4 r weim Iba weim oe weim_eb EBC 0 fa weim eb EBC 1 l
62. r Last Valid Addr Address V1 ji Address V1 2 weim_cs 2 V weim r w Write 11 weim iba V weim oe weim eb V weim_data_out Last Valid Data n 1 2 Half Word Y 2 2 Half Word Figure 19 WSC 1 WWS 2 WEA 1 WEN 2 A WORD E HALF MC9328MXL Advance Information Rev 5 34 Freescale Semiconductor Specifications hak FA Zg AT e e mel wem es FN htrans XNonseq XNonseq f hwrite Read J Write V resse DC Y C Y mea f na FM A hwdata Last Valid Data Write Data Y weim_hrdata Last Valid Data Y Read Data weim_hready n a weim_bclk weim_addr Last Valid Addr Address V1 Y Address V8 weim cs 2 weim r w Read Write o weim_lba 5 weim oe i weim_eb EBC 0 ki TA A weim eb EBC 1 V weim data in e Read Data weim data out Last Valid Data Y Write Data Figure 20 WSC 2 WWS 2 WEA 1 WEN 2 A HALF E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 35 Specifications helk hsel weim cs 2 a aide r Write gt RIA ie dm htrans f Nonseq X Nonseqj hwrite Read J Write V w Dove y CA hready A j 3x JE Ade hwd
63. r up event JTAG TRST Test Reset Pin External active low signal used to asynchronously initialize the JTAG controller TDO Serial Output for test instructions and data Changes on the falling edge of TCK TDI Serial Input for test instructions and data Sampled on the rising edge of TCK TCK Test Clock to synchronize test logic and control register access through the JTAG port TMS Test Mode Select to sequence the JTAG test controller s state machine Sampled on the rising edge of TCK DMA BIG ENDIAN Big Endian Input signal that determines the configuration of the external chip select space If it is driven logic high at reset the external chip select space will be configured to little endian If it is driven logic low at reset the external chip select space will be configured to big endian DMA REQ External DMA request pin ETM ETMTRACESYNC ETM sync signal which is multiplexed with A24 ETMTRACESYNC is selected in ETM mode MC9328MXL Advance Information Rev 5 Freescale Semiconductor 7 Signals and Connections Table 3 MC9328MXL Signal Descriptions Continued Signal Name Function Notes ETMTRACECLK ETM clock signal which is multiplexed with A23 ETMTRACECLK is selected in ETM mode ETMPIPESTAT 2 0 ETM status signals which are multiplexed with A 22 20 ETMPIPESTAT 2 0 are selected in ETM mode ETMTRACEPKT
64. rator MMA Power Management Features Operating Voltage Range 1 7 V to 1 98 V core 1 7 V to 3 3V I O e 256 pin MAPBGA Package e 225 pin MAPBGA Package 1 3 Target Applications The MC9328MXL is targeted for advanced information appliances smart phones Web browsers digital MP3 audio players handheld computers and messaging applications MC9328MXL Advance Information Rev 5 Freescale Semiconductor 3 Introduction 1 4 Revision History Table 1 provides revision history for this release This history includes technical content revisions only and not stylistic or grammatical changes Table 1 MC9328MXL Data Sheet Revision History Rev 5 Revision Location Revision Throughout Clarified instances where BCLK signal is burst clock Section 3 3 Power Sequence Added reference to AN2537 Requirements on page 12 1 5 Product Documentation The following documents are required for a complete description of the MC9328MXL and are necessary to design properly with the device Especially for those not familiar with the ARM920T processor or previous DragonBall products the following documents are helpful when used in conjunction with this document ARM Architecture Reference Manual ARM Ltd order number ARM DDI 0100 ARMODTI Data Sheet Manual ARM Ltd order number ARM DDI 0029 ARM Technical Reference Manual ARM Ltd order number ARM DDI 0151C EMT9 Technical Reference Manual ARM Ltd order numb
65. reference manual MC9328MXL Advance Information Rev 5 62 Freescale Semiconductor Specifications SDCLK ADDR an 77 Figure 49 SDRAM SyncFlash Write Cycle Timing Diagram Table 24 SDRAM Write Timing Parameter Table Ref 1 8V 0 10V 3 0V 0 30V l No Parame ter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 2 67 4 2 SDRAM clock low level width 6 4 3 SDRAM clock cycle time 11 4 10 4 Address setup time 3 42 3 5 Address hold time 2 28 2 6 Precharge cycle period tap trp 7 Active to read write command delay taco tre MC9328MXL Advance Information Rev 5 Freescale Semiconductor A ae Table 24 SDRAM Write Timing Parameter Table Continued 3 0V 0 30V nit Specifications Rof 1 8V 0 10V Na Parameter U j Minimum Maximum Minimum Maximum 8 Data setup time 4 0 2 ns Data hold time 2 28 2 ns 9 Precharge cvcle timing is included in the write timing diagram tgp and taco SDRAM clock cycle time These settings can be found in the MC9328MXL reference manual Des Specifications Table 25 SDRAM Refresh Timing Parameter Table Continued S 1 8V 0 10V 3 0V 0 30V NS Parameter Unit f Minimum Maximum Minimum Maximum
66. rom memory on the low order 8 data bits following the CAS latency gt GH Note CKE is high during the read write cycle Figure 48 SDRAM SyncFlash Read Cycle Timing Diagram Table 23 SDRAM Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit i Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 2 67 4 5 ns 2 SDRAM clock low level width 6 4 ns 3 SDRAM clock cycle time 11 4 10 ns 3S CS RAS CAS WE DOM setup time 3 42 3 ns MC9328MXL Advance Information Rev 5 61 Freescale Semiconductor Specifications Table 23 SDRAM Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum 3H CS RAS CAS WE DQM hold time 2 28 2 ns 4S Address setup time 3 42 3 ns 4H Address hold time 2 28 2 ns 5 SDRAM access time CL 3 6 84 6 ns 5 SDRAM access time CL 2 6 84 6 ns 5 SDRAM access time CL 1 22 22 ns 6 Data out hold time 2 85 2 5 ns 7 Data out high impedance time CL 3 6 84 6 ns 7 Data out high impedance time CL 2 6 84 6 ns 7 Data out high impedance time CL 1 a 22 22 ns 8 Active to read write command period RC 1 trop trop ns 1 tacp SDRAM clock cycle time This settings can be found in the MC9328MXL
67. s CSD1 SDRAM SyncFlash Chip select signal which is multiplexed with CS3 signal These two signals are selectable by programming the system control register By default CSD1 is selected so it can be used as SyncFlash boot chip select by properly configuring BOOT 3 0 input pins RAS SDRAM SyncFlash Row Address Select signal CAS SDRAM SyncFlash Column Address Select signal SDWE SDRAM SyncFlash Write Enable signal SDCKEO SDRAM SyncFlash Clock Enable O SDCKE1 SDRAM SyncFlash Clock Enable 1 SDCLK SDRAM SyncFlash Clock RESET_SF SyncFlash Reset Clocks and Resets EXTAL16M Crystal input 4 MHz to 16 MHz or a 16 MHz oscillator input when the internal oscillator circuit is shut down XTAL16M Crystal output EXTAL32K 32 kHz crystal input XTAL32K 32 kHz crystal output CLKO Clock Out signal selected from internal clock signals RESET IN Master Reset External active low Schmitt trigger input signal When this signal goes active all modules except the reset module and the clock control module are reset RESET OUT Reset Out Internal active low output signal from the Watchdog Timer module and is asserted from the following sources Power on reset External reset RESET IN and Watchdog time out POR Power On Reset Internal active high Schmitt trigger input signal The POR signal is normally generated by an external RC circuit designed to detect a powe
68. se lock in time after FPL mode and integer MF does 270 320 370 Tref partial reset not include pre multi lock in time 64 us Freq jitter p p 0 005 0 01 2 T dck 0 01 Phase jitter p p Integer MF FPL mode Vcc 1 8V 1 0 1 5 ns 10 Power supply voltage 1 7 B 2 5 V Power dissipation FOL mode integer MF 4 mW fuck 200 MHz Vcc 1 8V MC9328MXL Advance Information Rev 5 16 Freescale Semiconductor Specifications 3 8 Reset Module The timing relationships of the Reset module with the POR and RESET IN are shown in Figure 3 and Figure 4 NOTE Be aware that NVDD must ramp up to at least 1 8V before QVDD is powered up to prevent forward biasing 90 AVDD B O 10 AVDD POR lt 4 Exact 300ms lt gt 7 cycles CLK32 RESET_DRAM HRESET 14 cycles CLK32 RESET_OUT RESET_POR CLK32 HCLK ee Figure 3 Timing Relationship with POR MC9328MXL Advance Information Rev 5 Freescale Semiconductor 17 Specifications RESET IN HRESET RESET OUT lig 6 AS NM 14 cycles 9 CLK32 e NN MINNN E Figure 4 Timing Relationship with RESET IN Table 11 Reset Module Timing Parameter Table M t 1 8V 0 10V 3 0V x 0 30V No Parameter Unit l Min Max Min Max 1 Width of input POWER ON RESET note E note E
69. st Valid Data Write Data V1 Y Unknown a E e E weim_hrdata Last Valid Data weim_hready J weim_bclk weim_addr Last Valid Address V1 weim cs 0 weim r w Write ET pm gt lt TA weim_lba weim oe weim eb y j weim data out Last Valid Data n Write Data V1 Figure 9 WSC 1 WEA 1 WEN 1 A HALF E HALF MC9328MXL Advance Information Rev 5 24 Freescale Semiconductor IT Specifications E NA a NV hclk NE hsel weim cs 0 htrans X Nonseq hwrite EN Read haddr X vi hready is aa weim hrdata Last Valid Data TAX V1 Word BL ii e L3 weim_hready weim bclk weim addr Last Valid Addr X Address V1 Y Address V1 2 weim cs 0 J weim_r w Read weim iba weim oe V 3 3 f po UN weim eb EBC 0 weim_eb EBC 1 weim_data_in O 1 2 Half Word 74 2 2 Half Word jon Figure 10 WSC z 1 OEA 1 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 25 Specifications hclk hsel weim cs 0 htrans hwrite haddr hreadv hwdata weim_hrdata weim_hready weim bclk weim addr pe Ta pea p
70. ted to two state access mode and the BSO and BSI bus states are automatically repeated to avoid a bus collision on the SDIO MC9328MXL Advance Information Rev 5 Freescale Semiconductor 57 Specifications eO exse OX VAGA MS SCLKO MS BS MS SDIO output d x MS SDIO input RED bit 0 MS SDIO input xl RED bit 1 Figure 46 MSHC Signal Timing Diagram Table 21 MSHC Signal Timing Parameter Table Ref 3 0 0 3V l No Parameter Unit Minimum Maximum 1 MS_SCLKI frequency 25 MHZ 2 MS SCLKI high pulse width 20 ns 3 MS_SCLKI low pulse width 20 ns 4 MS SCLKI rise time 3 ns 5 MS SCLKI fall time 3 ns 6 MS SCLKO frequency 25 MHz 7 MS SCLKO high pulse width 20 i ns 8 MS SCLKO low pulse width 15 ns 9 MS_SCLKOrisetime 5 ns 10 MS SCLKO fall time 5 ns MC9328MXL Advance Information Rev 5 58 Freescale Semiconductor Specifications Table 21 MSHC Signal Timing Parameter Table Continued Ref 3 0 0 3V l No Parameter Unit Minimum Maximum 11 MS BS delay time 3 ns 12 MS SDIO output delay time 3 ns 13 MS SDIO input setup time for MS SCLKO rising edge RED bit 0 18 i ns 14 MS SDIO input hold time for MS SCLKO rising edge RED bit 0 0 ns 15 MS_SDIO input setup time for MS_SCLKO falling edge RED
71. u Last Valid Data gt lt Write Data V1 Word Last Valid Data Bau Last Valid Addr Address V1 Address V1 2 weim_cs 0 weim_r w Write weim_lba weim oe weim eb weim data out per A TAN pep Ve aa 1 2 Half Word X 2 2 Half Word Figure 11 WSC z 1 WEA 1 WEN 2 A WORD E HALF MC9328MXL Advance Information Rev 5 26 Freescale Semiconductor hclk hsel weim cs 3 htrans hwrite haddr hreadv weim hrdata weim hready weim bclk weim addr weim_cs 3 weim r w weim Iba A di ye Specifications Last Valid Data Bet Co lt lt f NIL Last Valid Add rh Address V1 Address V1 2 Read a weim oe weim eb EBC 0 weim eb EBC 1 weim data in Se LA LA Gy t2hatwoo A 22 Hatt word jis Figure 12 WSC 3 OEA 2 A WORD E HALF MC9328MXL Advance Information Rev 5 Freescale Semiconductor 27 Specifications hclk hsel weim cs 3 htrans hwrite haddr hready hwdata weim hrdata weim hready weim bclk weim addr weim cs 3 weim_r w weim ba weim oe LINA Nu Ad A PA j TI XNonseqj Write X vi
72. urations refer to the LCD controller chapter of the MC9328MXL Reference Manual LSCLK da an e LD 15 0 ya X l O Figure 36 SCLK to LD Timing Diagram MC9328MXL Advance Information Rev 5 Freescale Semiconductor 47 Specifications Table 16 LCDC SCLK Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Minimum Maximum Minimum Maximum Unit 1 SCLK to LD valid 2 2 ns gt lt Non display region gt Display region Ti T3 TA lt ma gt a P VSYN T2 lt gt HSYN gU Tp LU ru d Mn 4p OE Lj MIEL LD 15 0 Joey ii m x Sa md ii T5 T6 XMAX T7 e A gt lt HSYN EE i d de ke a Tjj SCLK BA ii OE E LD 15 0 VSYN i T9 Figure 37 4 8 16 Bit Pixel TFT Color Mode Panel Timing Table 17 4 8 16 Bit Pixel TFT Color Mode Panel Timing Svmbol Description Minimum Corresponding Register Value Unit T1 End of OE to beginning of VSYN T5 T6 VWAIT1 T2 T5 T6 T7 T9 Ts T7 T9 T2 HSYN period XMAX 5 XMAX T5 T6 T7 T9 T10 Ts T3 VSYN pulse width T2 VWIDTH T2 Ts T4 End of VSVN to beginning of OE 2 VWAIT2 T2 Ts T5 HSYN pulse width 1 HWIDTH 41 Ts T6 End of HSYN to beginning to T9 1 HWAIT2 1 Ts MC9328MXL Advance Information Rev 5 48 Freescale Se

Download Pdf Manuals

Related Search

freescale MC9328MXL handbook

Related Contents

        Panasonic TC-P55VT30 TC-P65VT30 user manual  ANALOG DEVICES AD5172/AD5173 256-Position One-Time Programmable Dual-Channel I 2 C Digital Potentiometers handbook      Refrigerator Manual(1)    

Copyright © All rights reserved.