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freescale MC9328MX21 handbook(1)(1)

1. weim hready BCLK A 24 0 Last Valid Adar y Address V1 Y Address V1 2 CS 3 m RW Read LBA 3 T E i EB EBC 0 EB EBC 1 Eu DATA IN Ui weswos MM 22Hatwoa Figure 58 WSC 3 OEA 2 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 74 Freescale Semiconductor Specifications hak P gop Spig AR M hselm weim cs 3 ON 3 htrans M Nonseq Y hwrite Write n haddr M V1 I FN iuga en Valg Write Data V1 Word Y weim_hrdata Last Valid Data weim_hready pet BCLK A 24 0 Last Valid Addry Address V1 Y Address V1 2 CS 3 R W Write lb ES i A D 31 0 Last Valid Data Y 1 2 Half Word Y 2 2 Half Word Figure 59 WSC 3 WEA 1 WEN 3 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 75 Specifications hak La Rep a ar den J hselm_weim_cs 2 an M htrans Y Nonseq y hwrite IN Read haddr Y V1 we B weim hrdata Last Valid Data NENNEN vives weim hready ao BCLK A 24 0 Last Valid Addr Address V1 X Address V1 2 CS 2 RW Read EB E
2. Bel 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation SSI2 Ports 1 Tx Rx CK clock period 90 91 90 91 ns 2 Tx CK high to FS bl high 0 01 0 15 0 01 0 15 ns 3 Rx CK high to FS bl high 0 21 0 05 0 21 0 05 ns 4 Tx CK high to FS bl low 0 01 0 15 0 01 0 15 ns 5 Rx CK high to FS bl low 0 21 0 05 0 21 0 05 ns 6 Tx CK high to FS wl high 0 01 0 15 0 01 0 15 ns 7 Rx CK high to FS wl high 0 21 0 05 0 21 0 05 ns 8 Tx CK high to FS wl low 0 01 0 15 0 01 0 15 ns 9 Rx CK high to FS wl low 0 21 0 05 0 21 0 05 ns 10 Tx CK high to STXD valid from high impedance 0 34 0 72 0 34 0 72 ns 11a Tx CK high to STXD high 0 34 0 72 0 34 0 72 ns 11b Tx CK high to STXD low 0 34 0 72 0 34 0 72 ns 12 Tx CK high to STXD high impedance 0 34 0 48 0 34 0 48 ns 13 SRXD setup time before Rx CK low 21 50 21 50 ns 14 SRXD hold time after Rx CK low 0 0 ns MC9328MX21 Product Preview Rev 1 1 58 Freescale Semiconductor Table 34 SSI to SSI2 Ports Timing Parameter Table Continued Specifications Ret 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum External Clock Operation SSI2 Ports 15 Tx Rx CK clock period 90 91 i 90 91 ns 16 Tx Rx CK clock hi
3. BMI_CLK CS BMI READ REQ A Ec xe n BMI D 15 0 gt E yee ett i Tdh BMI_WRITE NET BMlwrite BMI write BMI READ BMI write A 1 is written to READ bit of control reg1 DMA or CPU write data to TxFIFO On the next Int_Clk BMI issues a write cycle BMI_READ_REQ is still logic high BMI issues next write cycle Figure 11 Memory Interface Master Mode BMI Read Write to External Slave Device Timing without Wait Signal MMD_MODE_SEL 0 MASTER_MODE_SEL 1 3 8 8 2 Memory Interface Master Mode with WAIT Signal When the WAIT control bit is set the BMI_WAIT signal is used and the CS cycle is terminated upon sampling a logic high BMI WAIT signal Figure 12 shows the BMI write timing when the WAIT bit is set When the BMI WRITE is asserted the BMI will detect the BMI WAIT signal on every falling edge of the Int CIk When it detected the high level of the BMI WAIT the BMI WRITE will be negated after 1 WS Int Clik period If the BMI WAIT is always high or already high before BMI WRITE is asserted this timing will same as without WAIT signal So the BMI WRITE will be asserted at least for 1 WS Int_Clk period MC9328MX21 Product Preview Rev 1 1 28 Freescale Semiconductor Specifications 0 1 ws ds Int_Clk reference only B
4. Table 7 32k 26M Oscillator Signal Timing Parameter Minimum RMS Maximum Unit EXTAL32k input jitter peak to peak for both System PLL and MCUPLL 5 20 ns EXTAL32k input jitter peak to peak for MCUPLL only 5 100 ns EXTAL32k startup time 800 ms Table 8 CLKO Rise Fall Time at 30pF Loaded Best Case Typical Worst Case Units Rise Time 0 80 1 00 1 40 ns Fall Time 0 74 1 08 1 67 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 17 Specifications 3 5 DPLL Timing Specifications Parameters of the DPLL are given in Table 9 In this table T efis a reference clock period after the predivider and Tq is the output double clock period Table 9 DPLL Specifications Parameter Test Conditions Minimum Typical Maximum Unit Reference clock frequency range Voc 1 5V 16 320 MHz Pre divider output clock frequency Vcc 1 5V 16 32 MHz range Double clock frequency range Vcc 1 5V 160 560 MHz Pre divider factor PD 7 1 16 Total multiplication factor MF Includes both integer 5 15 and fractional parts MF integer part 5 15 MF numerator Should be less than the denominator 0 1022 MF denominator 1 1023 Frequency lock in time after FOL mode for non integer MF 350 400 450 Tret full reset does not include pre multi lock in time Frequency lock in ti
5. FS bl Input FS wl Input STXD Output SRXD Input Note SRXD Input in Synchronous mode only Figure 44 SSI Transmitter External Clock Timing Diagram CK Input FS bl Input NN FS wl Input 80 m cem uh Figure 45 SSI Receiver External Clock Timing Diagram SRXD Input Table 32 SSI to SAP Ports Timing Parameter Table Ret 1 8V 0 10V 3 0V 0 30V No Parameter Unit i Minimum Maximum Minimum Maximum Internal Clock Operation SAP Ports 1 Tx Rx CK clock period 90 91 90 91 ns 2 Tx CK high to FS bl high 3 30 1 16 2 98 1 10 ns 3 Rx CK high to FS bl high 3 93 1 34 4 18 1 43 ns MC9328MX21 Product Preview Rev 1 1 54 Freescale Semiconductor Table 32 SSI to SAP Ports Timing Parameter Table Continued Specifications Ref 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 4 Tx CK high to FS bl low 3 30 1 16 2 98 1 10 ns 5 Rx CK high to FS bl low 3 93 1 34 4 18 1 43 ns 6 Tx CK high to FS wl high 3 30 1 16 2 98 1 10 ns 7 Rx CK high to FS wl high 3 93 1 34 4 18 1 43 ns 8 Tx CK high to FS wl low 3 30 1 16 2 98 1 10 ns 9 Rx CK high to FS wl low 3 93 1 34 4 18 1 43 ns 10 Tx CK high to STXD valid from high impeda
6. l T5 r T6 PS lt gt i T7 T7 j REV a a Figure 21 Sharp TFT Panel Timing Table 20 Sharp TFT Panel Timing Symbol Description Minimum Value Unit T1 SPL SPR pulse width 1 Ts T2 End of LD of line to beginning of HSYN 1 HWAIT1 1 Ts T3 End of HSYN to beginning of LD of line 4 HWAIT2 4 Ts T4 CLS rise delay from end of LD of line 3 CLS_RISE_DELAY 1 Ts T5 CLS pulse width 1 CLS_HI_WIDTH 1 Ts T6 PS rise delay from CLS negation 0 PS_RISE_DELAY Ts T7 REV toggle delay from last LD of line 1 REV_TOGGLE_DELAY 1 Ts Note e Falling of SPL SPR aligns with first LD of line e Falling of PS aligns with rising edge of CLS e REV toggles in every HSYN period MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 33 Specifications VSYN LD 15 0 T1 XMAX Figure 22 Non TFT Mode Panel Timing Table 21 Non TFT Mode Panel Timing Symbol Description Minimum Value Unit T1 HSYN to VSYN delay 2 HWAIT2 2 Tpix T2 HSYN pulse width 1 HWIDTH 1 Tpix T3 VSYN to SCLK 0 lt T3 lt Ts T4 SCLK to HSYN 1 HWAIT1 1 Tpix Note Ts is the SCLK period while Tpix is the pixel clock period VSYN HSYN and SCLK can be programmed as active high or active low In Figure 67 on page 83 all these 3 signals are active high When it is in CSTN mode or monochrome mod
7. ns 16 Tx Rx CK clock high period 36 36 36 36 ns 17 Tx Rx CK clock low period 36 36 36 36 T ns 18 Tx CK high to FS bl high 9 62 17 10 7 90 15 61 ns 19 Rx CK high to FS bl high 10 30 19 54 8 58 18 05 ns 20 Tx CK high to FS bl low 9 62 17 10 7 90 15 61 ns 21 Rx CK high to FS bl low 10 30 19 54 8 58 18 05 ns 22 Tx CK high to FS wl high 9 62 17 10 7 90 15 61 ns 23 Rx CK high to FS wl high 10 30 19 54 8 58 18 05 ns MC9328MX21 Product Preview Rev 1 1 60 Freescale Semiconductor Specifications Table 35 SSI to SSI3 Ports Timing Parameter Table Continued Rel 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 24 Tx CK high to FS wl low 9 62 17 10 7 90 15 61 ns 25 Rx CK high to FS wl low 10 30 19 54 8 58 18 05 ns 26 Tx CK high to STXD valid from high impedance 9 02 16 46 7 29 14 97 ns 27a Tx CK high to STXD high 8 48 15 32 6 75 13 83 ns 27b Tx CK high to STXD low 8 48 15 32 6 75 13 83 ns 28 Tx CK high to STXD high impedance 9 02 16 46 7 29 14 97 ns 29 SRXD setup time before Rx CK low 1 49 1 49 m ns 30 SRXD hole time after Rx CK low 0 0 ns Synchronous Internal Clock Operation SSI3 Ports 31 SRXD setup before Tx CK falling 21 99 21 99 ns 32 SRXD hold after Tx CK falling 0 0 ns Synchronous External Clock Operation SSI3 Ports
8. 0 27 0 96 0 27 ns 8 Tx CK high to FS wl low 0 68 0 15 0 68 0 15 ns 9 Rx CK high to FS wl low 0 96 0 27 0 96 0 27 ns MC9328MX21 Product Preview Rev 1 1 56 Freescale Semiconductor Table 33 SSI to SSI1 Ports Timing Parameter Table Continued Specifications Bel 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 10 Tx CK high to STXD valid from high impedance 1 68 0 36 1 68 0 36 ns 11a Tx CK high to STXD high 1 68 0 36 1 68 0 36 ns 11b Tx CK high to STXD low 1 68 0 36 1 68 0 36 ns 12 Tx CK high to STXD high impedance 1 58 0 31 1 58 0 31 ns 13 SRXD setup time before Rx CK low 20 41 20 41 ns 14 SRXD hold time after Rx CK low 0 0 ns External Clock Operation SSI1 Ports 15 Tx Rx CK clock period 90 91 90 91 ns 16 Tx Rx CK clock high period 36 36 36 36 ns 17 Tx Rx CK clock low period 36 36 36 36 E ns 18 Tx CK high to FS bl high 10 22 17 63 8 82 16 24 ns 19 Rx CK high to FS bl high 10 79 19 67 9 39 18 28 ns 20 Tx CK high to FS bl low 10 22 17 63 8 82 16 24 ns 21 Rx CK high to FS bl low 10 79 19 67 9 39 18 28 ns 22 Tx CK high to FS wl high 10 22 17 63 8 82 16 24 ns 23 Rx CK high to FS wl high 10 79 19 67 9 39 18 28 ns 24 Tx CK high to FS wl low 1
9. Non Gated Clock Mode Parameters Number Parameter Minimum Maximum Unit 1 csi vsync to csi pixclk 9 TucLk ns 2 csi_d setup time 1 ns 3 csi_d hold time 1 7 ns 4 csi_pixclk high time THcLK ns MC9328MX21 Product Preview Rev 1 1 100 Freescale Semiconductor Specifications Table 44 Non Gated Clock Mode Parameters Continued Number Parameter Minimum Maximum Unit 5 csi pixclk low time THcLK ns 6 csi_pixclk frequency 0 HCLK 2 MHz HCLK AHB System Clock THcLk Period of HCLK 3 22 3 Calculation of Pixel Clock Rise Fall Time The limitation on pixel clock rise time fall time is not specified It should be calculated from the hold time and setup time based on the following assumptions Rising edge latch data max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time Ins setup time Ins positive duty cycle 10 2 5ns 2 max rise time allowed 5 1 4ns negative duty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time max rise time allowed positive duty cycle setup time
10. 33 SRXD setup before Tx CK falling 3 80 3 80 ns 34 SRXD hold after Tx CK falling 0 0 ns All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures 3 17 1 Wire Interface Timing 3 17 1 Reset Sequence with Reset Pulse Presence Pulse To begin any communications with the DS2502 it is required that an initialization procedure be issued A reset pulse must be generated and then a presence pulse must be detected The minimum reset pulse length is 480 us The bus master one wire will generate this pulse then after the DS2502 detects a rising edge on the one wire bus it will wait 15 60 us before it will transmit back a presence pulse The presence pulse will exist for 60 240 us The timing diagram for this sequence is shown in Figure 46 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 61 Specifications Reset and Presence Pulses AutoClear RPP Set RPP 7 Control Bit walts Sidus MAIS DS2502Tx pla presence pulse P 60 240us gt j one wire BUS di 512us lt 1 l One Wire samples set PST 68us Figure 46 1 Wire Initialization The reset pulse begi
11. COO Specifications hok NR E EE c hselm weim cs 2 M pel htrans ji Nonseq Y Seq Y Y Idle X hwrite Read Read X haddr Y V1 cC Kanne ai ES o o Q UE nll Oe as ce po CD I Q hready M NI weim hrdata Last Valid Data Y V1 Word X V2 Word y V3 Word Y V4 Word weim_hready TE BCLK ri f P Xe esr ns Nes CEA A 24 0 ast Valid Addr Address V1 CS o R W Read wet V OE 11 EB EBC 0 EB EBC 1 DATA_IN a V1 Word X V2Word f V3Word X V4Word y J Figure 73 WSC 2 SYNC 1 DOL 1 0 A WORD E WORD MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 89 Specifications ei VN EJA 2 p hselm weim cs 2 eT htrans JNonsea I Y Seq Y Y Idle hwrite M Read gt lt DS gt lt L Zz o e en haddr X V1 A Breed E ami weim hrdata Last Vaid Data Vi Word NH V2 Word weim_hready ED Nx BCLK PONE Cae ah Cu ce i NG ee A 24 0 Last Valid Addr Y Address V1 Y Address V2 CS 2 RIW Read me LY m SUBE EB EBC 0 EB EBC 1 c ay AMEN V DATA IN mem V1 12 Jj V1 2 2 EE v2 1 2 Y V2 2 2 Y Lr Figu
12. Chip Select Control Register and EIM Configuration Register EW bit set WSC set to gt 1 and CSN set to lt 3 in the Chip Select Control Register BCD DCT set to desired insensitivity time in the Chip Select Control Register The insensitivity time is dictated by the external device s timing requirements e AGE bit cleared in the EIM Configuration Register Other bits such as DSZ OEA OEN and so on may be set according to system and timing requirements of the external device The waveforms in the following section provide examples of the DTACK signal operation MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 93 Specifications 3 20 1 DTACK Example Waveforms Internal ARM AHB Word Accesses to Word Width 32 bit Memory AE BSRSRESITISR NATASQUE eee ADDR 5 f vi y CS m aw Read LBA p OE EB EBC 0 A EB EBC 1 Figure 77 DTACK Edge Triggered Read Access WSC 3F OEA 8 OEN 5 AGE 1 MC9328MX21 Product Preview Rev 1 1 94 Freescale Semiconductor CES Specifications HCLK Pad eae oe a A A ee ee ee oO 2 BCLK E g ADDR Last Valid Addr Address V1 V1 4 V148 CS 0 RW Read IBA OE EB EBC 0 E EB EBC 1 DCT j DATA_IN GD vwo X V144 Word Y vi 8 Word Figure 78 DTACK Level Sensit
13. Revision History 105 ARMa OWERED e This document contains information on a product under development Freescale reserves the right to change or discontinue this product without notice Freescale Semiconductor Inc 2004 All rights reserved Z freescale semiconductor Introduction multimedia experience In addition the 1 MX21 provides optional hardware enabled security features including high assurance boot mode unique processor IDs secret key support secure RAM and a security monitor These optional features enable secure e commerce digital rights management DRM information encryption and secure software downloads For cost sensitive applications the NAND Flash controller allows the use of low cost NAND Flash devices to be used as primary or secondary non volatile storage The on chip error correction code ECC and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks WLAN Bluetooth and expansion options are provided through PCMCIA CF USB and MMC SD host controllers The i MX21 is packaged in a 289 pin MAPBGA Figure 1 i MX21 Functional Block Diagram MC9328MX21 Product Preview Rev 1 1 2 Freescale Semiconductor Introduction 1 1 Conventions This document uses the following conventions e OVERBAR is used to indicate a signal that is active when pulled low for example RESET Logic level one is a voltage that corresponds to Boolean true 1
14. Sensor Interface CSI_D 7 0 Sensor port data CSI_MCLK Sensor port master clock CSI VSYNC Sensor port vertical sync CSI HSYNC Sensor port horizontal sync CSI PIXCLK Sensor port data latch clock LCD Controller LD 17 0 LCD Data Bus All LCD signals are driven low after reset and when LCD is off LD 15 0 signals are multiplexed with SLCDC1_DAT 15 0 from SLCDC1 and BMI_D 15 0 LD 17 signal is multiplexed with BMI WRITE of BMI LD 16 signal is multiplexed with BMI READ REQ of BMI and EXT DMAGRANT signals FLM VSYNC Frame Sync or Vsync This signal also serves as the clock signal output for gate or simply referred driver dedicated signal SPS for Sharp panel HR TFT This signal is multiplexed with to as VSYNC BMI RXF FULL and BMI WAIT of the BMI LP HSYNC or simply referred to as HSYNC Line Pulse or HSync LSCLK Shift Clock This signal is multiplexed with the BMI CLK CS from BMI OE ACD Alternate Crystal Direction Output Enable CONTRAST This signal is used to control the LCD bias voltage as contrast control This signal is multiplexed with the BMI READ from BMI SPL SPR Sampling start signal for left and right scanning This signal is multiplexed with the SLCDC1_CLK PS Control signal output for source driver Sharp panel dedicated signal This signal is multiplexed with the SLCDC1 CS CLS Start signal output for gate driver This sig
15. clock period 42 962 ns T2 Chip select setup time 5 ns T3 Chip select hold time 5 ns T4 Data setup time 5 zz ns T4 Data hold time 5 ns T6 Register select setup time 5 ns T7 Register select hold time 5 ns coo EET LT LT IT LI LI UU LCD RS LCD CS LCD DATA 15 0 command data X display data CSPOL 0 LCD CLK i 7 7 le T4 ple T5 t LCD RS LCD_CS A T2995 T2 command data X display data LCD DATA 15 0 CSPOL 1 Figure 24 SLCDC Parallel Transfers Timing MC9328MX21 Product Preview Rev 1 1 36 Freescale Semiconductor Specifications Table 23 SLCDC Parallel Transfers Timing Symbol Description Minimum Maximum Unit T1 Pixel clock period 23 962 ns T2 Data setup time 5 7 ns T3 Data hold time 5 x ns T4 Register select setup time 5 ns T5 Register select hold time 5 ns 3 12 Multimedia Card Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus DMA access internal MMC SD module data bus and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content empty or full FIFO address and byte block counters for the MMC SD module inner system and the application user programming Bus Clock C
16. device Especially for those not familiar with the ARM926EJ S processor or previous DragonBall products the following documents are helpful when used in conjunction with this manual ARM Architecture Reference Manual ARM Ltd order number ARM DDI 0100 ARM 7TDMI Data Sheet ARM Ltd order number ARM DDI 0029 ARM920T Technical Reference Manual ARM Ltd order number ARM DDI 0151C MC9328MX21 Product Brief order number MC9328MX21P D MC9328MX21 Reference Manual order number MC9328MX21RM D MC9328MX1 Product Brief order number MC9328MX1P D MC9328MX1 Data Sheet order number MC9328MX1 D MC9328MX1 Reference Manual order number MC9328MX1RM D The Freescale manuals are available on the Freescale Semiconductor Web site at http www freescale com These documents may be downloaded directly from the Freescale Web site or printed versions may be ordered The ARM Ltd documentation is available from http www arm com MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 3 Introduction 1 4 Ordering Information Table 1 provides ordering information for the i MX21 Table 1 i MX21 Ordering Information Marking Package Size Package Type Operating range MC9328MX21VG 289 lead MAPBGA Lead 0 C 70 C 0 65mm 14mm x 14mm MC9328MX21VK 289 lead MAPBGA Lead free 0 C 70 C 0 65mm 14mm x 14mm MC9328MX21VH 289 lead MAPBGA Lead 0 C 70 C 0 8mm 17mm x 17mm MC9328MX21VM 289 lead MAPB
17. multiplexed with USBH1_TXDM UART4_RTS Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP UART4_CTS Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM Serial Audio Port SSI configurable to IS protocol and AC97 SSH CLK Serial clock signal which is output in master or input in slave SSH TXD Transmit serial data SSI1 RXD Receive serial data SSH FS Frame Sync signal which is output in master and input in slave SSH MCLK SSH master clock Multiplexed with TOUT SSI2 CLK Serial clock signal which is output in master or input in slave SSI2 TXD Transmit serial data signal SSI2 RXD Receive serial data MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 13 Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes SSI2 FS Frame Sync signal which is output in master and input in slave SSI2 MCLK SSI2 master clock Multiplexed with TOUT SSI3_CLK Serial clock signal which is output in master or input in slave This signal is multiplexed with SLCDC2_CLK SSI3_TXD Transmit serial data signal which is multiplexed with SLCDC2_CS SSI3_RXD Receive serial data which is multiplexed with SLCDC2 RS SSI3_FS Frame Sync signal which is output in master and input in slave This signal is multiplexed with SLCDC2 DO SAP CLK Serial clock signal
18. positive duty cycle 10 2 5ns gt max rise time allowed 5 1 4ns negative duty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time Ins max rise time allowed positive duty cycle setup time 3 22 2 Non Gated Clock Mode Figure 83 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 84 on page 100 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 44 on page 100 The formula for calculating the pixel clock rise and fall time is located in Section 3 22 3 Calculation of Pixel Clock Rise Fall Time on page 101 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 99 Specifications I I l POLK a CO NE AS Xm c I DATA 7 0 x Valid Data X Valid Data Valid Data 2 l 3 I l l mre Figure 83 Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge P I I I I PIXCLK DATA 7 0 Valid Data Valid Data I 2 I 3 I I l i Figure 84 Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 44
19. setup time Tds 2 8 ns transfer data hold time Tdh 2 8 ns read_req hold time Trh 2 18 ns Note In this mode the max frequency of the BMI_CLK CS can be up to 36Mhz double as max data pad speed Note The BMI_CLK CS can only be divided by 2 4 8 16 from HCLK 3 8 1 4 MMD Write BMI Timing Figure on page 26 shows the MMD write BMI timing when BMI drives BMI_CLK CS When the BMI WRITE signal is asserted the BMI can write a 1 to READ bit of control register to issue a WRITE cycle This bit is cleared automatically when the WRITE operation is completed In a WRITE burst the MMD will write COUNT 1 data to the BMI The user can issue another WRITE operation if the MMD still has data to write after the first operation completed The BMI can latch the data either at falling edge or the next rising edge of the BMI CLK CS according to the DATA LATCH bit When the DATA LATCH bit is set the BMI latch data at the next rising edge and latch the last data using the internal clock BMI WRITE signal can not be negated when the WRITE operation is proceeding MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 25 Specifications lt _ Total has COUNT 1 clocks in one burst p BMI_CLK CS A m BMI_READ_REQ Cah be asserted any time Can be asserted any m _ BMI_D 15 0 N RxD1 Tm RxD2 i ZU E y ka gt fasi P Taste Bii WRITE A 1 is written to
20. signals are available on some of the USB OTG and USBH1 signals SLCDC2 CLK SLCDC Clock input signal for pass through to SLCD device This signal is multiplexed with SSI3 CLK signal from SSI3 SLCDC2 CS SLCDC Chip Select input signal for pass through to SLCD device This signal is multiplexed with SSI3 TXD signal from SSI3 SLCDC2 RS SLCDC Register Select input signal for pass through to SLCD device This signal is multiplexed with SSI3_RXD signal from SSI3 SLCDC2 DO SLCD Data input signal for pass through to SLCD device This signal is multiplexed with SSI3 FS signal from SSI3 Bus Master Interface BMI BMI_D 15 0 BMI bidirectional data bus Bus width is programmable between 8 bit or 16 bit These signals are multiplexed with LD 15 0 and SLCDC DAT 15 0 BMI_CLK_CS BMI bidirectional clock or chip select signal This signal is multiplexed with LSCLK of LCDC BMI_WRITE BMI bidirectional signal to indicate read or write access This is an input signal when the BMI is a slave and an output signal when BMI is the master of the interface BMI WRITE is asserted for write and negated for read This signal is muxed with LD 17 of LCDC BMI_READ BMI output signal to enable data read from external slave device This signal is not used and driven high when BMI is slave This signal is multiplexed with CONTRAST signal of LCDC BMI_READ_REQ BMI Read request output signal to external bus master This signal is active when
21. there is no end of transfer MC9328MX21 Product Preview Rev 1 1 64 Freescale Semiconductor Specifications USB ON L1 N Output t OEB_TXDP t rxpw oE amp 4 gt lt gt gt USB OE pm Output N ERIOD gt P tTXDP OEB USB_TXDP i Output USB TXDM Output e La La SERERE irFEoPT USB_VP Input USB_VM Input Figure 50 USB Timing Diagram for Data Transfer to USB Transceiver TX Table 38 USB Timing Parameter Table for Data Transfer to USB Transceiver TX Ref 3 0 0 3V l No Parameter Unit Minimum Maximum 1 toes rxpp USBD_OE active to USBD_TXDP low 83 14 83 47 ns 2 toes rxpw USBD OE active to USBD_TXDM high 81 55 81 98 ns 3 trxpP oes USBD TXDP high to USBD_OE deactivated 83 54 83 8 ns 4 trxpy oce USBD TXDM low to USBD OE deactivated includes SEO 248 9 249 13 ns 5 trgopr SEO interval of EOP 160 175 ns 6 tperiop Data transfer rate 11 97 12 08 Mb s MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 65 Specifications USB_ON Output USB_OE a N Output USB TXDP Output USB TXDM Output trEoPR e USB RXDP jc pu F Input USB_RXDM m Input Figure 51 USB Timing Diagram for Data Transfer from USB Transceiver RX Table 39 USB Timing Parameter Table for Da
22. which is output in master or input in slave SAP TXD Transmit serial data SAP RXD Receive serial data SAP FS Frame Sync signal which is output in master and input in slave Pc I2C CLK I2C Clock I2C DATA IC Data 1 Wire OWIRE One wire input and output signal This signal is multiplexed with JTAG RTCK PWM PWMO PWM Output This signal is multiplexed with PC SPKOUT of PCMCIA as well as TOUT2 and TOUTS of the General Purpose Timer module Keypad KP COL 7 0 Keypad Column selection signals KP COL 7 6 are multiplexed with UART2_CTS and UART2 TXD respectively Alternatively KP COL6 is also available on the internal factory test signal TEST WB2 The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing to select the alternate signal multiplexing to choose which signal KP COL6 is available KP ROW 7 0 Keypad Row selection signals KP ROW 7 6 are multiplexed with UART2 RTS and UART2 RXD signals respectively Alternatively KP ROW7 and KP ROWS are available on the internal factory test signals TEST WBO and TEST WB1 respectively The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing to select the alternate signal multiplexing to choose which signals KP ROW6 and KP ROWT7 are available Noisy Supply Pins NVDD Noisy Supply for the I O pins There are six 6 I O voltage rin
23. 0 22 17 63 8 82 16 24 ns 25 Rx CK high to FS wl low 10 79 19 67 9 39 18 28 ns 26 Tx CK high to STXD valid from high impedance 10 05 15 75 8 66 14 36 ns 27a Tx CK high to STXD high 10 00 15 63 8 61 14 24 ns 27b Tx CK high to STXD low 10 00 15 63 8 61 14 24 ns 28 Tx CK high to STXD high impedance 10 05 15 75 8 66 14 36 ns 29 SRXD setup time before Rx CK low 0 78 0 47 ns 30 SRXD hole time after Rx CK low 0 0 a ns Synchronous Internal Clock Operation SSI1 Ports 31 SRXD setup before Tx CK falling 19 90 19 90 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 57 Specifications Table 33 SSI to SSI Ports Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V a Parameter Unit Minimum Maximum Minimum Maximum 32 SRXD hold after Tx CK falling 0 0 ns Synchronous External Clock Operation SSI1 Ports 33 SRXD setup before Tx CK falling 2 59 2 28 ns 34 SRXD hold after Tx CK falling 0 0 Ex ns All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures Table 34 SSI to SSI2 Ports Timing Parameter Table
24. 22 CMOS Sensor interface The CSI module consists of a control register to configure the interface timing a control register for statistic data generation a status register interface logic a 32 x 32 image data receive FIFO and a 16 x 32 statistic data FIFO 3 22 1 Gated Clock Mode Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 82 on page 98 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 43 on page 98 The formula for calculating the pixel clock rise and fall time is located in Section 3 22 3 Calculation of Pixel Clock Rise Fall Time on page 101 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 97 Specifications 1 I I I I VSYNC I I I I I I 4 1 I I L r I I HSYNC A I 5 6 1 na 4 i l i l 1 PIXCLK i I L I i i 1 I 1 I H l Valid Dat i i I I 3 i 4 1 I I I I 99 Figure 81 Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 1 1 1 4 I I I I VSYNC 1 1 1 7 I ___ _ __ 1 I I I I I HSYN
25. 32 MULUT SEDI ME LULU TU MONDOD N Figure 3 Timing Relationship with RESET IN Table 10 Reset Module Timing Parameter Table Ref 1 8V 0 10V 3 0V 0 30V N Parameter Unit Min Max Min Max 1 Width of input POWER_ON_RESET 800 800 ms 2 Width of internal POWER ON RESET 300 300 300 300 ms CLK32 at 32 KHz 3 7K to 32K cycle stretcher for SDRAM reset 7 7 7 7 Cycles of CLK32 4 14K to 32K cycle stretcher for internal system reset 14 14 14 14 Cycles of HRESERT and output reset at pin RESET OUT CLK32 5 Width of external hard reset RESET IN 4 4 Cycles of CLK32 6 4K to 32K cycle qualifier 4 4 4 4 Cycles of CLK32 MC9328MX21 Product Preview Rev 1 1 20 Freescale Semiconductor Specifications 3 7 External DMA Request and Grant The External DMA request is an active low signal to be used by devices external to 1 MX21 processor to request the DMAC for data transfer After assertion of External DMA request the DMA burst will start when the channel on which the External request is the source as per the RSSR settings becomes the current highest priority channel The external device using the External DMA request should keep its request asserted until it is serviced by the DMAC One External DMA request will initiate one DMA burst The output External Grant signal from the DMAC is an active low signal When the following conditions are true the External DM
26. A Grant signal is asserted with the initiation of the DMA burst The DMA channel for which the DMA burst is ongoing has request source as external DMA Request as per source select register setting e REN and CEN bit of this channel are set External DMA Request is asserted After the grant is asserted the External DMA request will not be sampled until completion of the DMA burst As the external request is synchronized the request synchronization will not be done during this period The priority of the external request becomes low for the next consecutive burst if another DMA request signal is asserted Worst case that is the smallest burst 1 byte read write timing diagrams are shown in Figure 4 and Figure 5 on page 21 Minimum and maximum timings for the External request and External grant signals are present in Table 11 on page 22 Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External DMA request 1s de asserted immediately after sensing grant signal active Ext DMAReq Ext DMAGrant K tmin_assert Figure 4 Assertion of DMA External Grant Signal Figure 5 shows the safe maximum time for which External DMA request can be kept asserted after sensing grant signal active such that a new burst is not initiated Ext DMAReq Ext DMAGrant lmax req assert Data read from External device tmax_read 39 Data written to tma
27. BC 0 H F DATA IN XI Half Word a2 Half Word Figure 60 WSC 3 OEA 4 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 76 Freescale Semiconductor helk hselm_weim_cs 2 Specifications pred S NEM E 3 htrans X Nonseq Y hwrite haddr p Write Xv hready hwdata Last Vali Data X J 3 X Write Data V1 Word weim_hrdata Last Va lid Data weim_hready BCLK A 24 0 Last Valid Addr Y Address V1 Address V1 2 CS 2 R W Write S EB D 31 0 k 7 y Last Valid Data X 1 2 Half Word X 2 2 Half Word Figure 61 WSC 3 WEA 2 WEN 3 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 77 Specifications hak ON um m 2 2 J hselm_weim_cs 2 i e IN htrans Y Nonseq Y hwrite A Read haddr Y V1 Y hready Be weim_hrdata Last Valid Data ee ne V1 Word m weim_hready BCLK A 24 0 Last Valid Addr Address V1 Y Address V1 2 CS 2 m RW Read EB EBC 0 EB EBC 1 DATA IN qu 1 2 Half Word md 2 2 Half Word S Figure 62 WSC 3 OEN 2 A WOR
28. C 5 6 1 S j4 P 4 i i I PIXCLK I I i i i 1 I 1 I L I Valid Dat i i DATA 7 0 Ao yapaa Calig L I I 3 4 I I I I I 9 Figure 82 Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 43 Gated Clock Mode Timing Parameters Number Parameter Minimum Maximum Unit 1 csi vsync to csi hsync 9 TucLk ns 2 csi_hsync to csi_pixclk 3 Tp 2 3 ns 3 csi_d setup time 1 ns 4 csi_d hold time 1 ns MC9328MX21 Product Preview Rev 1 1 98 Freescale Semiconductor Table 43 Gated Clock Mode Timing Parameters Specifications Number Parameter Minimum Maximum Unit 5 csi_pixclk high time Tuck ns 6 csi pixclk low time THcLk ns 7 csi pixclk frequency 0 HCLK 2 MHz HCLK AHB System Clock Tuck Period for HCLK Tp Period of CSI PIXC LK The limitation on pixel clock rise time fall time is not specified It should be calculated from the hold time and setup time based on the following assumptions Rising edge latch data max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time Ins setup time
29. CLKOUT are both set The software must know which mode it is now READ or WRITE When the BMI WRITE is high BMI drives BMI CLK CS out if the TxFIFO is not emptied When BMI WRITE is low user can write a 1 to READ bit of control register to issue a write cycle MMD write BMI 3 8 1 3 MMD Read BMI Timing Figure 13 on page 29 shows the MMD read BMI timing when BMI drives the BMI CLK CS When the BMI WRITE is high the BMI drives BMI CLK CS out if data is written to TxFIFO BMI READ REQ become high BMI puts data into data bus and enable data out on the rising edge of BMI CLK CS The MMD devices can latch the data on each falling edge of BMI CLK CS It is recommended that the MMD do not change the BMI WRITE signal from high to low when the BMI READ REQ is asserted If user writes data to the TxFIFO when the BMI WRITE is low the BMI will drive BMI CLK CS out once the BMI WRITE is changed from low to high MC9328MX21 Product Preview Rev 1 1 24 Freescale Semiconductor Specifications BMI_CLK CS BMI_READ_REQ b ut i Tdh Tra gt S BMI_D 15 0 TxD1 X TxD2 X fans x X Nast T49 BMI WRITE DMA or CPU write data to TxFIFO Figure 8 BMI Drives Clock MMD Read BMI Timing MASTER_MODE_SEL 0 MMD_MODE_SEL 1 MMD_CLKOUT 1 Table 14 MMD Read BMI Timing Table when BMI Drives Clock Item Symbol MIN TYP MAX Unit transfer data
30. Clock rise to Output Enable Invalid 3 70 5 61 9 26 3 46 5 37 8 81 ns 4c Clock fall to Output Enable Valid 3 60 5 48 8 77 3 44 5 30 8 88 ns 4d Clock fall to Output Enable Invalid 3 69 5 62 9 12 3 42 5 36 8 60 ns 5a Clock rise to Enable Bytes Valid 3 69 5 46 8 71 3 46 5 25 8 54 ns 5b Clock rise to Enable Bytes Invalid 4 64 5 47 8 70 3 46 5 25 8 54 ns 5c Clock fall to Enable Bytes Valid 3 52 5 06 8 39 3 41 5 18 8 36 ns 5d Clock fall to Enable Bytes Invalid 3 50 5 05 8 27 3 41 5 18 8 36 ns 6a Clock fall to Load Burst Address Valid 3 65 5 28 8 69 3 30 5 23 8 81 ns 6b Clock fall to Load Burst Address Invalid 3 65 5 67 9 36 3 41 5 43 9 13 ns 6c Clock rise to Load Burst Address Invalid 3 66 5 69 9 48 3 33 5 47 9 25 ns 7a Clock rise to Burst Clock rise 3 50 5 22 8 42 3 26 4 99 8 19 ns 7b Clock rise to Burst Clock fall 3 49 5 19 8 30 3 31 5 03 8 17 ns 7C Clock fall to Burst Clock rise 3 50 5 22 8 39 3 26 4 98 8 15 ns 7d Clock fall to Burst Clock fall 3 49 5 19 8 29 3 31 5 02 8 12 ns 8a Read Data setup time 4 54 4 54 ns 8b Read Data hold time 0 5 0 5 x B ns 9a Clock rise to Write Data Valid 4 13 5 86 9 16 3 95 6 36 10 31 ns 9b Clock fall to Write Data Invalid 4 10 5 79 9 15 4 04 6 27 9 16 ns 9c Clock rise to Write Data Invalid 4 02 5 81 9 37 4 22 5 29 9 24 ns 10a DTACK setup time 2 65 4 63 8 40 2 64 4 61 8 41 ns 1 Clock refers to the system clock signal HCLK generated from the System DPLL 3 19 1 EI
31. D E HALF MC9328MX21 Product Preview Rev 1 1 78 Freescale Semiconductor Specifications Dok fes UR P SD D AEN E j hselm weim cs 2 gee I htrans LX Nonseq hwrite lee Read haddr LX V1 hready weim hready lA A CU Ro a BCLK A 24 0 Last Valid Addr Address V1 Y Address V1 2 CS 2 A RW Read 9E er i EB EBC 0 EB EBC 1 DATA IN 1L Half Word Half Word Figure 63 WSC 3 OEA 2 OEN 2 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 79 Specifications helk hselm weim cs 2 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK A 24 0 CS 2 La quw Y je EP FOR Y Nonseq X Write a LS Last Valid ata X aR X Write Data V1 Word Y Unknown Last Valid Data A Last Valid Addr y Address V1 Address V1 2 R W D 31 0 Write In Last Valid Data 1 2 Half Word 2 2 Half Word Figure 64 WSC 2 WWS 1 WEA 1 WEN 2 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 80 Freescale Semiconductor hclk hs
32. D V VIL Input low voltage 0 0 3NVDD V VoH Output high voltage 0 8NVDD V VoL Output low voltage 0 2NVDD V Vite Positive input threshold voltage V Vin x 2 15 V Vit Negative input threshold voltage V zVii 0 75 V Vhys Hysteresis Vit Vii Vin 0 3 liL Input low leakage current m 1 uA Vin GND no pull up or pull down hw Input high leakage current 1 uA Vin Vpp no pull up or pull down IOH Output high current Slow Pad 6 mA VO VOH Fast Pad 5 loL Output low current Slow Pad 6 mA VO VOL Fast Pad 5 loz Output leakage current 5 uA Vout Vpp Output is tri stated Ci Input capacitance 5 pF Co Output capacitance 5 pF MC9328MX21 Product Preview Rev 1 1 16 Freescale Semiconductor Specifications 3 4 AC Electrical Characteristics The AC characteristics consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of other signals All timing specifications are specified at a system operating frequency from 0 MHz to 133 MHz core operating frequency 266 MHz with an operating supply voltage from V D min 9 VDD max under an operating temperature from T to Ty All timing is measured at 30 pF loading Table 6 Tri State Signal Timing Pin Parameter Minimum Maximum Unit TRISTATE Time from TRISTATE activate until O becomes Hi Z 20 8 ns
33. D high impedance 12 08 19 36 7 71 9 20 ns 29 SRXD setup time before Rx CK low 0 37 0 42 s ns 30 SRXD hole time after Rx CK low 0 0 ns Synchronous Internal Clock Operation SAP Ports 31 SRXD setup before Tx CK falling 23 00 21 41 ns 32 SRXD hold after Tx CK falling 0 0 ns Synchronous External Clock Operation SAP Ports 33 SRXD setup before Tx CK falling 1 20 0 88 ns 34 SRXD hold after Tx CK falling 0 0 ns 1 All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures Table 33 SSI to SSI1 Ports Timing Parameter Table Bst 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation SSI1 Ports 1 Tx Rx CK clock period 90 91 90 91 ns 2 Tx CK high to FS bl high 0 68 0 15 0 68 0 15 ns 3 Rx CK high to FS bl high 0 96 0 27 0 96 0 27 ns 4 Tx CK high to FS bl low 0 68 0 15 0 68 0 15 ns 5 Rx CK high to FS bl low 0 96 0 27 0 96 0 27 ns 6 Tx CK high to FS wl high 0 68 0 15 0 68 0 15 ns 7 Rx CK high to FS wl high 0 96
34. DD4 KP_ KP_ CSPM TEST UART2 KP COL1 KP COLO TEST ROW5 ROW2 MOSI WBO RTS WB1 K A16 A17 D23 D24 NVSS1 NVSS4 QVDDX UART1 TDO QVDD QVSS KP_ KP COL5 KP COLA KP_ RXD COL3 COL2 L A14 A15 D21 D22 NVSS1 NVDD3 QVDD QVSS NFIO2 NFWP UART1 UART2 UART3_ UART3_CTS UART3_ NFIO9 NFIO10 TXD TXD RTS TXD M D19 A13_ D20 D18 NVDD2 NVDD3 NVSS3 QVSS NFIO7 NFRB EXT UART2 UART3_ UART1_RTS UART1_ NFIO8 48M RXD RXD CTS N A11 A12 D17 D16 LBA NVSS3 SDCKEO NVSS1 NVSS1 NVDD1 NVDD1 SD1_ TCK SD1 D1 RTCK DO P A9 A10 D15 D14 SD1 SD1_ TDI TMS D2 CMD R A7 A8 D13 D12 SD1_ EXT_ NVSS2 TRST CLK 266M T A5 A6 EB3 D10 CS3 CS1 BCLK MA11 RAS CAS NFIO5 NFIOS NFWE RESET NFCE BOOT1 SD1 D3 CLKMODE1 CLK IN MODEO U D11 EB1 EB2 OE CS4 D6 ECB D3 MA10 PC_ NFIO4 NFIO1 NFALE NFCLE POR BOOT2 BOOTS XTAL32K PWRON v A4 EBO D9 D8 CS5 D5 CSO RW D1 JTAG_ SDWE CLKO NFIO6 QVSS RESET BOOTO OSC26M_ VDDA EXTAL CTRL OUT TEST 32K w A3 A2 D7 A1 CS2 AO D4 D2 DO SDCLK SDCKE1 NFIOO NFRE QVDD QVSS EXTAL XTAL26M QVDD QVSS 26M uoneuuoJu eBexoeg pue 1nO uld Pin Out and Package Information 4 1 MAPBGA Package Dimensions Figure 85 illustrates the MAPBGA 14 mm x 14 mm x 1 41 mm package which has 0 65 mm spacing between the pads NOTES ALL DIMENSIONS IN MILLIMETERS DIMENSIONING AND TOLERANCING PER ASME Y14 54 1994 MAX MUM SOLDER BALL DIAMETER MEASURED PARALLEL TG DATU
35. DRAM Controller SDBA 4 0 SDRAM non interleave mode bank address signals These signals are multiplexed with address signals A 20 16 SDIBA 3 0 SDRAM interleave addressing mode bank address signals These signals are multiplexed with address signals A 24 21 MA 11 0 SDRAM address signals MA 9 0 are multiplexed with address signals A 10 1 DQM 3 0 SDRAM data qualifier mask multiplexed with EB 3 0 DOMS corresponds to D 31 24 DQM2 corresponds to D 23 16 DQM1 corresponds to D 15 8 and DQMO corresponds to D 7 0 CSDO SDRAM Chip Select signal This signal is multiplexed with the CS2 signal This signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter CSD1 SDRAM Chip Select signal This signal is multiplexed with the CS3 signal This signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter RAS SDRAM Row Address Select signal CAS SDRAM Column Address Select signal SDWE SDRAM Write Enable signal SDCKEO SDRAM Clock Enable 0 SDCKE1 SDRAM Clock Enable 1 SDCLK SDRAM Clock MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes Clocks and Resets EXTAL26M Crystal input 26MHz or a 16 MHz to 32 MHz oscillator or square wave input when internal oscillator circuit i
36. DRAM access time CL 3 5 4 5 4 ns 5 SDRAM access time CL 2 6 0 6 0 ns 5 SDRAM access time CL 1 ns 6 Data out hold time 3 0 3 0 ns 7 Data out high impedance time CL 3 luz taz ns 7 Data out high impedance time CL 2 ie taz ns 7 Data out high impedance time CL 1 x ns 8 Active to read write command period RC 1 trep trep ns 1 tyz SDRAM data out high impedance time external SDRAM memory device dependent parameter 2 tgcp SDRAM clock cycle time The trep setting can be found in the i MX21 reference manual MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 49 Specifications SDCLK WE DQ DQM Figure 39 SDRAM Write Cycle Timing Diagram Table 30 SDRAM Write Timing Parameter Table Ref 1 8V 3 0V 10 l No Parameter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 3 00 m 4 2 SDRAM clock low level width 3 00 4 3 SDRAM clock cycle time 11 1 7 5 4 Address setup time 3 67 3 5 Address hold time 2 95 2 6 Precharge cycle period tap tap 7 Active to read write command delay tren tren 8 Data setup time 3 41 2 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Specifications Table 30 SDRAM Write Timing Parameter Table Continued 1 8V 3 0V 10 Ref No Parame
37. Descriptions Continued Signal Name Function Notes CSPI CSPI1_MOSI Master Out Slave In signal CSPI1_MISO Master In Slave Out signal CSPI1_SS 2 0 Slave Select Selectable polarity signal CSPI1_SS2 is also multiplexed with USBG_RXDAT CSPI1_SCLK Serial Clock signal CSPI1_RDY Serial Data Ready signal Also multiplexed with EXT_DMAREQ CSPI2 MOSI Master Out Slave In signal This signal is multiplexed with USBH2 TXDP signal of USB OTG CSPI2 MISO Master In Slave Out signal This signal is multiplexed with USBH2 TXDM signal of USB OTG CSPI2 SS 2 0 Slave Select Selectable polarity signals These signals are multiplexed with USBH2 FS USBH2 RXDP and USBH2 RXDM signal of USB OTG CSPI2 SCLK Serial Clock signal This signal is multiplexed with USBH2_OE signal of USB OTG CSPI3_MOSI Master Out Slave In signal This signal is multiplexed with SD1_CMD CSPI3_MISO Master In Slave Out signal This signal is multiplexed with SD1_DO CSPI3_SS Slave Select Selectable polarity signal multiplexed with SD1_D3 CSPI3_SCLK Serial Clock signal This signal is multiplexed with SD1_CLK General Purpose Timers TIN Timer Input Capture or Timer Input Clock The signal on this input is applied to all 3 timers simultaneously This signal is muxed with the Walk up Guard Mode WKGD signal in the PLL Clock and Reset Controller module TOUT1 or simply TOUT Timer Output signal from General Purpose Time
38. E NAND Flash Write Enable output signal This signal is multiplexed with and PC_BVD2 of PCMCIA NF_RB NAND Flash Ready Busy input signal This signal is multiplexed with PC_RST of PCMCIA NF IO 15 0 NAND Flash Data input and output signals NF 1O 15 7 signals are multiplexed with A 25 21 and A 15 13 NF IO 7 0 signals are multiplexed with several PCMCIA signals PCMCIA Controller PC A 25 0 PCMCIA Address signals These signals are multiplexed with A 25 0 PC D 15 0 PCMCIA Data input and output signals These signals are multiplexed with D 15 0 PC CD1 PCMCIA Card Detect1 input signal This signal is multiplexed with NFIO 7 signal of NF PC CD2 PCMCIA Card Detect2 input signal This signal is multiplexed with NFIO 6 signal of NF PC WAIT PCMCIA Wait input signal to extend current access This signal is multiplexed with NFIO 5 signal of NF PC READY PCMCIA Ready input signal to indicate card is ready for access This signal is multiplexed with NFIO 4 signal of NF PC RST PCMCIA Reset output signal This signal is multiplexed with NFRB signal of NF PC OE PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles This signal is multiplexed with NFALE signal of NF PC WE PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles This signal is shared with RW of the EIM PC VS1 PCMCIA Voltage Sense1 input signal This signal is multiplexed with NFIO 2 signal of NF
39. Freescale Semiconductor Product Preview MC9328MX21 1 Introduction Freescale s i MX family of microprocessors has demonstrated leadership in the portable handheld market Building on the success of the MX Media Extensions series the i MX21 MC9328MX21 provides a leap in performance with an ARM926EJ S microprocessor core that provides native security and accelerated Java support in addition to highly integrated system functions The i MX products specifically address the needs of the smartphone and portable product markets with their intelligent integrated peripherals advanced processor core and power management capabilities The i MX21 features the advanced and power efficient ARM926EJ S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption On chip modules such as a video accelerator module LCD controller USB On The Go CMOS sensor interface and two synchronous serial interfaces offer designers a rich suite of peripherals that can enhance any product seeking to provide a rich MC9328MX21 D Rev 1 1 09 29 2004 MC9328MX21 Package Information MAPBGA 289 Ordering Information See Table 1 on page 4 Contents 1 Introduction 2 ccc eee 1 2 Signal Descriptions 000ee eee 5 3 Specifications ccc eee ee 15 4 Package Information LLL 102 5 Document
40. GA Lead free 0 C 70 C 0 8mm 17mm x 17mm MC9328MX21DVG 289 lead MAPBGA Lead 30 C 70 C 0 65mm 14mm x 14mm MC9328MX21DVK 289 lead MAPBGA Lead free 30 C 70 C 0 65mm 14mm x 14mm MC9328MX21DVH 289 lead MAPBGA Lead 30 C 70 C 0 8mm 17mm x 17mm MC9328MX21DVM 289 lead MAPBGA Lead free 30 C 70 C 0 8mm 17mm x 17mm MC9328MX21CVG 289 lead MAPBGA Lead 40 C 85 C 0 65mm 14mm x 14mm MC9328MX21CVK 289 lead MAPBGA Lead free 40 C 85 C 0 65mm 14mm x 14mm MC9328MX21CVH 289 lead MAPBGA Lead 40 C 85 C 0 8mm 17mm x 17mm MC9328MX21CVM 289 lead MAPBGA Lead free 40 C 85 C 0 8mm 17mm x 17mm 1 5 Features The 1 MX21 boasts a robust array of features that can support a wide variety of applications Below is a brief description of i MX21 features ARM926EJ S Core Complex enhanced Multimedia Accelerator eMMA Optional Security System Display and Video Modules LCD Controller LCDC Smart LCD Controller SLCDC CMOS Sensor Interface CSI Bus Master Interface BMI MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Signal Descriptions Wireless Connectivity Fast Infra Red Interface Fast IR Wired Connectivity USB On The Go USBOTG Controller Four Universal Asynchronous Receiver Transmitters UART1 UART2 UART3 and UART4 Two Configurable Serial Peripheral Interfaces CSPI1 and CSPI2 for High Speed Data Transfer Inter IC PC Bus Module T
41. IO functionality or for it s other multiplexed function then configure as GPIO input with pull up enabled and leave as a no connect TEST WBJ4 3 These are special factory test signals To ensure proper operation leave these signals as no connects WKGD Battery indicator input used to qualify the walk up process Also multiplexed with TIN JTAG TRST Test Reset Pin External active low signal used to asynchronously initialize the JTAG controller TDO Serial Output for test instructions and data Changes on the falling edge of TCK TDI Serial Input for test instructions and data Sampled on the rising edge of TCK TCK Test Clock to synchronize test logic and control register access through the JTAG port TMS Test Mode Select to sequence the JTAG test controllers state machine Sampled on the rising edge of TCK JTAG CTRL JTAG Controller select signal JTAG CTRL is sampled during the rising edge of TRST Must be pulled to logic high for proper JTAG interface to debugger Pulling JTAG_CRTL low is for internal test purposes only RTCK JTAG Return Clock used to enhance stability of JTAG debug interface devices This signal is multiplexed with OWIRE hence utilizing OWIRE will render RTCK unusable and vice versa MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes CMOS
42. M A DATUM A THE SEATING PLANE IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE ppp TOP VEW 18 0 65 2Hgx B3B IN FPRORPR ABE Er eaeeswe se L25411411241124141241 41 BEA IRE 44o aPR DSAASENS 80 0805 4 Al INDEX AREA BOTTOM VIEW SIBE VIEW Figure 85 i MX21 MAPBGA Mechanical Drawing MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 103 Pin Out and Package Information 4 2 MAPBGA Package Dimensions Figure 86 illustrates the MAPBGA 17 mm x 17 mm x 1 45 mm package which has 0 8 mm spacing between the pads 17 B Al INDEX AREA C 4X 23 015 56 5 4 4 4 6 0 5 4 4 84 65 44 4606 5 4 4 4 6556444544 6i 18x 0 8 abl L4 Ld d serves Ld gt Ld L Ld ILIIJSRIIJSARESSIALI SESCSSCISSSSVESSESSES PUCERIR ER ere Ieee 200x 0045 N ero ABC aC 086 A ei Ftd ite Al INDEX AREA BOTTOM VIEW SIDE VIEW NOTES ALL DIMENSIONS IN MILLIMETERS DIMENSIONING AND TOLERANCING PER ASME Y14 54 1984 MAX MUM SOLDER BALL DIAMETER MEASURED PARALLEL TG DATUM A 1 2 A DATUM A THE SEATING PLANE IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE Figure 86 i MX21 MAPBGA Mechanical Drawing MC9328MX21 Product Previe
43. M External Bus Timing Diagrams The following timing diagrams show the timing of accesses to memory or a peripheral MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 69 P Specifications hclk a RENE A hselm weim cs 0 htrans Y Seq Nonseq hwrite Read p DM haddr Y V4 medy ff NV 1 Of N weim hrdata Last Valid Data GEN v1 weim_hready Jo BCLK A 24 0 Last Valid Address Y v1 CSI0 RW Read TBA OE EB EBC 0 7 EB EBC 1 DATA_IN a Vi Figure 54 WSC 1 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 70 Freescale Semiconductor hclk hselm weim cs 0 htrans hwrite haddr p Specifications ZEE NN ZEE OMM Nonseq Write V1 EIER IS ES hready Write Data V1 Y hwdata Last Valid Data Unknown DA oa ee ss weim hrdata Last Valid Data weim hready BCLK A 24 0 Last Valid Address V1 CS O R W Write LBA EN ee ee OE EB D 31 0 Last Valid Data y T T T T Figure 55 WSC 1 WEA 1 WEN 1 A HALF E HALF Write Data V1 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconducto
44. MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 101 coL JOojonpuooruleg e eoseeJJ LL ASH ver eJd 12npoJjd LZXIASCEGOIN 4 Pin Out and Package Information Table 45 i MX21 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A LD9 LD12 LD14 REV HSYNC OE SD2_D2 CSI CSI CSI USBH1_ USBH1_ USBG TOUT SAP_ SSH SSI2 SSI2 TXDAT SSI3_ ACD DO PIXCLK VSYNC FS OE FS TXDAT CLK RXDAT FS B LD7 LD5 LD11 LD16 PS CON SD2 DO SD2 CSI CSI_D6 USB USBG USBG SAP SSH SSI2 SSI3_ I2C DATA CSPI2_ TRAST CMD D4 PWR SCL TXDM FS FS FS TXDAT SS2 c LD1 LD3 LD6 LD10 LD17 VSYNC SD2 D3 CSI CSI CSI USB USBH1_ USBG_ TIN SSH SSI3_ SSI3_ I2C CLK CSPI2_ D1 MCLK HSYNC OC RXDM RXDM TXDAT RXDAT CLK ssi D LD2 LDO LD13 CLS QVDD QVSS SD2_D1 SD2_ CSI_ CSI_D7 USBH1_ USBH1_ USBG_ USBG_ SAP SSH Ssl2_ CSPI2 SS0 CSPI2_ CLK D2 TXDM RXDP N RXDP RXDAT RXDAT CLK SCLK E LD8 LD4 LD15 SPL_ SAP CSPI2 CSPM SS2 CSPI2_ SPR CLK MISO MOSI F A24 D31 A25_ LSCLK CSPM CSPI1_ KP ROWO CSPI1_ NFIO14 NFIO15 SS1 MISO SSO G A22_ D29 A23_ D30 NVDD6 NVSS6 CSI_D3 USB USBH_ USBG USBG_ KP_ KP_ UART2_CTS KP_ NFIO12 NFIO13 BYP ON SDA TXDP ROW1 ROWS ROW4 H A20 D27 A21_ D28 NVDD1 NVSS5 CSI D5 CSPI1_ CSPI1_ USBH1_ USBG_ TEST_ TEST_ TEST_WB3 PWMO NFIO11 SCLK RDY TXDP OE WB4 WB2 J A19 A18 D25 D26 NVDD1 NVDD5 NV
45. MD DAT Input CMD DAT Output Figure 25 Chip Select Read Cycle Timing Diagram Table 24 SDHC Bus Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Min Max Min Max 1 CLK frequency at Data transfer Mode PP 10 30 cards 0 25 5 0 25 5 MHz 2 CLK frequency at Identification Mode 0 400 0 400 KHz 3a Clock high time 10 30 cards 6 33 10 50 ns 3b Clock low time 10 30 cards 15 75 10 50 ns 4a Clock fall time 10 30 cards E 10 50 5 00 10 50 ns 4b Clock rise time 10 30 cards 14 67 6 67 10 50 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 37 Specifications Table 24 SDHC Bus Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V No Parameter Unit 3 Min Max Min Max 5a Input hold time 10 30 cards 5 7 5 7 5 5 ns 5b Input setup time 10 30 cards 5 7 5 7 5 5 ns 6a Output hold time3 10 30 cards 5 7 5 7 5 5 ns 6b Output setup time 10 30 cards 5 7 5 7 5 5 ns 7 Output delay time 0 16 0 14 ns a Cj lt 100 pF 250 pF 10 30 cards C 250 pF 21 cards C 25 pF 1 card on 3 12 1 The card identification and card operation conditions timing are processed in open drain mode The card response to the host command starts after exactly Nyp clock cycles For the card address
46. MD latch data at falling edge Note If the MMD latch data at next rising edge the ideally max clock can be as much as double but because the BMI data pads are slow pads and it max frequency can only up to 18Mhz the max clock frequency can only up to 36 MHz 3 8 1 1 2 MMD Write BMI Timing Figure 7 on page 24 shows the MMD write BMI timing when MMD drives clock On each falling edge of BMI CLK CS BMI checks the BMI WRITE logic level to determine if the current cycle is a write cycle If the BMI WRITE is logic low it latches data into the RxFIFO on each falling edge of BMI CLK CS signal MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 23 Specifications mows LLL LS BMI_READ_REQ Can be asserted any time Can be asserted any time E t i l BMI_D 15 0 V RxD1 RxD2 astRHxD DE Tas i i BMI_WRITE neda Ts it hy Figure 7 MMD ATI Drives Clock MMD Write BMI Timing MMD_MODE_SEL 1 MASTER_MODE_SEL 0 MMD_CLKOUT 0 Table 13 MMD Write BMI Timing Item Symbol Minimum Typical Maximum Unit write setup time Ts 11 ns write hold time Th 0 ns receive data setup time Tds 5 ns Note All timings assume that the hclk is running at 133 MHz Note At this mode the maximum frequency of the BMI_CLK CS can be up to 36 MHz doubles as maximum data pad speed 3 8 1 2 BMI Drives the BMI CLK CS In this mode MMD MODE SEL and MMD
47. MI_CLK CS i BMI_D 15 0 l s TXD a u TXD b BMI READ BMI WRITE BMI WAIT Figure 12 Memory Interface Master Mode BMI Write to External Slave Device Timing with Wait Signal MMD MODE SEL 0 MASTER MODE SEL 1 WAIT 1 Figure 13 shows the BMI read timing when the WAIT bit is set As write timing when the BMI READ is asserted the BMI will detect the BMI WAIT signal on every falling edge ofthe Int CIk When it detected the high level of the BMI WAIT the BMI READ will be negated after 1 WS Int CIk period If the BMI WAIT is always high or already high before BMI READ is asserted this timing will same as without WAIT signal So the BMI READ will be asserted at least for 1 WS Int CIk period 1s 1 ws Int_Clk relents only BMI_CLK CS BMI_D 15 0 P RXDas i RXD_b BMI_WRITE i i m i BMI_READ mm BMI WAIT Figure 13 Memory Interface Master Mode BMI Read to External Slave Device Timing with Wait Signal MMD MODE SEL z0 MASTER MODE SEL 1 WAIT 1 3 9 SPI Timing Diagrams To use the internal transmit TX and receive RX data FIFOs when the SPI 1 module is configured as a master two control signals are used for data transfer rate control the SS signal output and the SPI RDY signal input The SPI 1 S
48. PC VS2 PCMCIA Voltage Sense2 input signal This signal is multiplexed with NFIO 1 signal of NF PC BVD1 PCMCIA Battery Voltage Detect1 input signal This signal is multiplexed with NFIO O signal of NF PC BVD2 PCMCIA Battery Voltage Detect2 input signal This signal is multiplexed with NF WE signal of NF PC SPKOUT PCMCIA Speaker Out output signal This signal is multiplexed with PWMO signal PC REG PCMCIA Register Select output signal This signal is shared with EB2 of EIM PC CE1 PCMCIA Card Enable1 output signal This signal is multiplexed with NFCE signal of NF PC CE2 PCMCIA Card Enable2 output signal This signal is multiplexed with NFWP signal of NF PC IORD PCMCIA IO Read output signal This signal is shared with EB3 of EIM PC IOWR PCMCIA IO Write output signal This signal is shared with OE signal of EIM PC WP PCMCIA Write Protect input signal This signal is multiplexed with NFIO 3 signal of NF PC POE PCMCIA Output Enable signal to enable voltage translation buffers and transceivers This signal is multiplexed with NFCLE signal of NF PC RW PCMCIA Read Write output signal to control external transceiver direction Asserted high for read access and negated low for write access This signal is multiplexed with NFRE signal of NF PC PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized MC9328MX21 Product Preview Rev 1 1 10 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal
49. READ bit of control register Figure 9 BMI Drives Clock MMD Write BMI Timing MASTER_MODE_SEL 0 MMD_MODE_SEL 1 MMD_CLKOUT 1 Table 15 MMD Write BMI Timing Table when BMI Drives Clock Item Symbol Minimum Typical Maximum Unit receive data setup time1 Tds1 14 ns receive data setup time2 Tds2 14 ns Note The BMI_CLK CS can only be up to 30Mhz if BMI latch data at the falling edge and can be up to 36Mhz double as max data pad speed if BMI latch data at the next rising edge Note Tds1 is the receive data setup time when BMI latch data at the falling edge Note Tds2 is the receive data setup time when BMI latch data at the next rising edge 3 8 2 Connecting BMI to External Bus Master Devices In this mode both MASTER SEL bit and MMD MODE SEL bit are cleared and the MMD CLKOUT bit is no useful BMI WRITE and BMI CLK CS are input signals driving by the external bus master The Output signal BMI READ REQ can be used as an interrupt signal to inform external bus master that data is ready in the BMI TxFIFO for a read access The external bus master can write data to the BMI RxFIFO anytime since the CPU or DMA can move data out from RxFIFO much faster than the BMI interface An overflow interrupt is generated if RxFIFO overflow is detected Once this happens the new coming data is ignored Each falling edge of BMI CLK CS will determine if the current cycle is read or write cycle It drives data and enables dat
50. a out if BMI WRITE is logic high The D EN signal remains active only while BMI CLK CS is logic low and BMI WRITE is logic high Each rising edge of BMI CLK CS will determine if data should be latched to RxFIFO from the data bus MC9328MX21 Product Preview Rev 1 1 26 Freescale Semiconductor Specifications BMI_CLK CS Eoi MEC a CN mh BMI READ REQ RE UE ig Tidh BMI_D 15 0 NDO A RxD a aso Tsien C Ts me i M MS BMI WRITE i i NG m i tA 1 1 1 1 D f i Th i i Read Write Read BMI BMI BMI Figure 10 Memory Interface Slave Mode External Bus Master Read Write to BMI Timing MMD_MODE_SEL 0 MASTER_MODE_SEL 0 Table 16 External Bus Master Read Write to BMI Timing Table Item Symbol Minimum Typical Maximum Unit write setup time Ts 11 ns write hold time Th 0 ns receive data hold time Trdh 3 ns transfer data setup time Ttds 6 14 ns transfer data hold time Ttdh 6 14 ns read_req hold time Trh 6 24 ns Note All the timings are assumed that the hclk is running at 133 MHz 3 8 8 Connecting BMI to External Bus Slave Devices In this mode the BMI WRITE BMI READ and BMI CLK CS are output signals driving by the BMI module The output signal BMI READ REQ is still driving active in on a write cycle but it can be ignored in this case Instead it is used to trigger internal l
51. agrams When enabled the DTACK input signal is used to externally terminate a data transfer For DTACK enabled operations a bus time out monitor generates a bus error when an external bus cycle is not terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed where HCLK is the internal system clock driven from the PLL module For a 133 MHz HCLK setting this time equates to 7 7 us Refer to the Section 3 5 DPLL Timing Specifications on page 18 for more information on how to generate different HCLK frequencies MC9328MX21 Product Preview Rev 1 1 92 Freescale Semiconductor Specifications There are two modes of operation for the DTACK input signal rising edge detection or level sensitive detection with a programmable insensitivity time DTACK is only used during external asynchronous data transfers thus the SYNC bit in the chip select control registers must be cleared During edge detection mode the EIM will terminate an external data transfer following the detection of the DTACK signal s rising edge so long as it occurs within the 1024 HCLK cycle time Edge detection mode is used for devices that follow the PCMCIA standard Note that DTACK rising edge detection mode can only be used for CS 5 operations To configure CS 5 for DTACK rising edge detection the following bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register e WSC bit field set to Ox3F and CSA or CSN set
52. ample Period Control Register PERIODREG1 and the SPI 2 Sample Period Control Register PERIODREG2 can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2 When the SPI 1 module is configured as a slave the user can configure the SPI 1 Control Register CONTROLREGI to match the external SPI master s timing In this configuration SS becomes an input MC9328MX 21 Product Preview Rev 1 1 Freescale Semiconductor 29 Specifications signal and is used to latch data into or load data out to the internal data shift registers as well as to increment the data FIFO 2 GIO pu Figure 14 Master SPI Timing Diagram Using SPI RDY Edge Trigger SPIRDY m Figure 15 Master SPI Timing Diagram Using SPI_RDY Level Trigger SS output Figure 16 Master SPI Timing Diagram Ignore SPI RDY Level Trigger SS input Figure 17 Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS input SCLK MOSI MISO Figure 18 Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge MC9328MX21 Product Preview Rev 1 1 30 Freescale Semiconductor Table 17 Timing Parameter Table for Figure 14 through Figure 18 n Parameter Minimum Maximum Unit 1 SPI RDY to SS output low oT ns 2 SS output low to first SCLK edge 3 Tsclk ns 3 Last SCLK edge to SS output high 2 Tsclk ns 4 SS output high to SPI RDY low 0 ns 5 SS output pul
53. assignment SET RCA is also processed in the open drain mode The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 26 The symbols for Figure 26 through Figure 30 are defined in Table 25 Table 25 State Signal Parameters for Figure 26 through Figure 30 Command Response Timing on MMC SD Bus Card Active Host Active Symbol Definition Symbol Definition Z High impedance state S Start bit 0 D Data bits T Transmitter bit Host 1 Card 0 Repetition P One cycle pull up 1 CRC Cyclic redundancy check bits 7 bits E End bit 1 MC9328MX21 Product Preview Rev 1 1 38 Freescale Semiconductor Specifications Nip cycles Host Command CID OCR ovo ff conen Te ERI eee BER Identification Timing Nor cycles Host Command 2 CID OCR ow Bi comen Jeep Si ee Be SET RCA Timing Figure 26 Timing Diagrams at Identification Mode After a card receives its RCA it switches to data transfer mode As shown on the first diagram in Figure 27 on page 39 SD CMD lines in this mode are driven with push pull drivers The command is followed by a period of two Z bits allowing time for direction switching on the bus and then by P bits pushed up by the responding card The other two diagrams show the separating periods Ngc and Nec Nor cycles Host Command gt Response oo MEE ro HEMNENRUNESETr Command r
54. ata weim_hrdata weim_hready BCLK A 24 0 CS 4 R W OE EB EBC 0 EB EBC 1 DATA_IN D 31 0 NE ME Specifications P n Last Valid Data Write Data Last Valid Data Y Read Data Last Vaid Adar Address V1 Address V8 E Read Write e PT S 3 3 L Last Valid Data X Write Data Figure 69 WSC 3 CSA 1 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 85 P Specifications fy VAN E NALE GN J hselm weim cs 4 MEE IN htrans J Nonseq y j Idle j Seq hwrite i Read Read hadar Y vT Y Yv w S P weim hrdata Last Valid Data N Read Data V1 JRead Data v2 vein ven f ex EN ENIFNFAUVNVINU NN NE NUN p D D c A 24 0 Last Valid Addr Address V1 y Address V2 CNC gt TSA f R W Read EB EBC 0 A EB EBC 1 DATA_IN U dra 0 eh ae Figure 70 WSC 2 OEA 2 CNC 3 BCM 1 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 86 Freescale Semiconductor hclk hselm weim cs 4 htrans hwrite haddr hready hwdata
55. d status yet keeps the clock running and allows the user to submit commands as normal After all commands are submitted the user can switch back to the data transfer operation and all counter and status values are resumed as access continues MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 43 Specifications JTUUUUUUUUUUUUUUUUULA JUL CMD DAT 1 Block Data eizzH Block Data For 4 bit For 4 bit Figure 32 SDIO ReadWait Timing Diagram 3 13 NAND Flash Controller Interface The timing diagrams Figure 33 through Figure 36shows the timing of the NAND Flash controller Table 27 on page 46 provides the relative timing requirement for the different signals of NFC at the i MX21 module level NFCLE te tCLH lt gt K 1pH NFIO7 0 gt K command gt lt As Figure 33 Command Latch Cycle Timing MC9328MX21 Product Preview Rev 1 1 44 Freescale Semiconductor Specifications lt tWP oe EN Lu tALS tALH 1 NFAE MoN eq Ro 1DH i NFIOZ 0 OK Address 9 S SSS Figure 34 Address Latch Cycle Timing lt tWP Wer Ie a tALS tALH lt lt NFALE lt tDS lt gt DH NFIO15 0 Figure 35 Input Data Latch Cycle Timing MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 45 Specifications tREH 2S tRP K NRE l T S IREA tRHZ lt L
56. e delay circuit will hold the data line low to override the 1 generated by the bus master one wire For the Write 1 or Read the control register WR1 RD is set and auto cleared when the sequence has been completed After a Read the control register RDST bit is set to the value of the read MC9328MX21 Product Preview Rev 1 1 62 Freescale Semiconductor Auto Clear WR1 R Y Set WR1 RD Write 1 Slot 117us nd 42 Figure 48 Write 1 Timing Specifications Set WR1 RD Auto Clear WR1 RD Set WR1 RD Auto Clear WR1 R Read Timing Read 0 Slot 117us Read 1 Slot 117us 60us one wire 7 5us 5us One Wire samples One Wire samples mut set RDST izu set RDST us Figure 49 Read Timing The precision of the generated clock is very important to get a proper behavior of the one wire module This module is based on a state machine which undertakes actions at defined times Table 36 System Timing Requirements Times Values Minimum Maximum Absolute Relative Microsec Microsec microsec Precision Precision RSTL 511 480 31 0 0645 PST 68 60 75 7 0 1 RSTH 512 480 32 0 0645 LOWO 100 60 120 20 0 2 LOWR 5 1 15 4 0 8 READ sample 13 15 2 0 15 The most stringent constraint is 0 0645 as a relative time imprecision The time relative precision is directly derived from the frequency of the derivative clock f Time
57. e with bus width 1 T3 Tpix Ts When it is in monochrome mode with bus width 2 4 and 8 T3 1 2 and 4 Tpix respectively MC9328MX21 Product Preview Rev 1 1 34 Freescale Semiconductor Specifications 3 11 Smart LCD Controller T2 gt T3 e LCD_CS EX cedes LCD CLK LCD DATA G 7 7 di T fi i T T4 gt T5 lt T7 le SDATA LCD DATA 7 MSB Y X X X i y LSB lt T6 RS LCD CLK LCD DATA 6 SDATA LCD DATA 7 RS 0 gt command data RS 1 gt display data SCKPOL 0 CSPOL 0 T2 gt TS e LCD CS E T e TEN LCD CLK LCD DATA 6 T T TAa gt T5 lt gt ae es Oe Ee EDU T RS 0 gt command data RS 1 gt display data SDATA LCD DATA 7 UJ CKPOL 1 CSPOL 1 Toe ses T3 e LCD CS m LCD CLK LCD DATA 6 eX X X CX RS 0 gt command data RS 1 gt display data SDATA LCD DATA 7 RS SCKPOL 0 CSPOL 1 Figure 23 SLCDC Serial Transfer Timing MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 35 Specifications Table 22 SLCDC Serial Transfer Timing Symbol Description Minimum Maximum Unit T1 Pixel
58. ead Write OE rising edge OE falling edge B rising edge EB falling edge LBA negated falling edge LBA negated rising edge Burst Clock rising edge Burst Clock falling edge Read Data Write Data negated rising di E CN a Figure 53 EIM Bus Timing Diagram Table 41 EIM Bus Timing Parameters 1 8V 0 1V 3 0V 0 3V Ref No Parameter Unit Min Typical Max Min Typical Max 1a Clock fall to address valid 3 97 6 02 9 89 3 83 5 89 9 79 ns 1b Clock fall to address invalid 3 93 6 00 9 86 3 81 5 86 9 76 ns 2a Clock fall to chip select valid 3 47 5 59 8 62 3 30 5 09 8 45 ns 2b Clock fall to chip select invalid 3 39 5 09 8 27 3 15 4 85 8 03 ns 3a Clock fall to Read Write Valid 3 51 5 56 8 79 3 39 5 39 8 51 ns MC9328MX21 Product Preview Rev 1 1 68 Freescale Semiconductor Table 41 EIM Bus Timing Parameters Continued Specifications 1 8V 0 1V 3 0V 0 3V Ref No Parameter Unit Min Typical Max Min Typical Max 3b Clock fall to Read Write Invalid 3 59 5 37 9 14 3 36 5 20 8 50 ns 4a Clock rise to Output Enable Valid 3 62 5 49 8 98 3 46 5 33 9 02 ns 4b
59. egion T1 T3 T4 m gt lt gt VSYN T2 u ua lt m AIT LD 17 0 Je Jul A p ex L IL TU OE v i j DOCERE es LD 15 0 Figure 20 4 8 12 16 18 Bit Pixel TFT Color Mode Panel Timing Table 19 4 8 12 16 18 Bit Pixel TFT Color Mode Panel Timing Symbol Description Minimum Value Unit T1 End of OE to beginning of VSYN T5 T6 T7 1 VWAIT1 T2 T5 T6 T7 1 Ts T2 HSYN period XMAX T5 1T6 T7 Ts T3 VSYN pulse width T2 VWIDTH T2 Ts T4 End of VSYN to beginning of OE 1 VWAIT2 T2 1 Ts T5 HSYN pulse width 1 HWIDTH 1 Ts T6 End of HSYN to beginning to OE 3 HWAIT2 3 Ts T7 End of OE to beginning of HSYN 1 HWAIT1 1 Ts Note Ts is the SCLK period VSYN HSYN and OE can be programmed as active high or active low In Figure 20 all 3 signals are active low SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period In Figure 20 SCLK is always active XMAX is defined in number of pixels in one line MC9328MX21 Product Preview Rev 1 1 32 Freescale Semiconductor Specifications L DI osi SPL SPR EE Ti E E s s yoz AR T AE WE a ee T2 HSN H e T4 74 CLS n1
60. elm weim cs 2 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK A 24 0 CS 2 Specifications WD IE exp oue i Write Data V1 Word JUnknown Last Valid Data Address V1 Address V1 2 R W Write 11 EB D 31 0 1 2 Half Word 2 2 Half Word Figure 65 WSC 1 WWS 2 WEA 1 WEN 2 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 81 Specifications helk hselm weim cs 2 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK 24 0 CS 2 DATA IN D 31 0 SETTES Last Valid Data Write Data Last Valid Data X Read Data PANN xL Last Valid Addr Address V1 x Address V8 Read n Write 3 3 PM i B Read Data Last Valid Data M Write Data Figure 66 WSC 2 WWS 2 WEA 1 WEN 2 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 82 Freescale Semiconductor hclk hselm weim cs 2 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK 24 0 dcm r Write Specifications r 2p ri a A Y l
61. ency 0 45 0 45 MHz 2a Clock high time 12 29 12 29 ns 2b Clock low time 9 91 a 9 91 ns 3a Clock fall time 0 5 0 5 ns 3b Clock rise time 0 5 0 5 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 47 Specifications Table 28 PWM Output Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V a Parameter Unit Minimum Maximum Minimum Maximum 4a Output delay time 9 37 3 61 ns 4b Output setup time 8 71 i 3 03 ns 1 C of PWMO 30 pF 3 15 SDRAM Memory Controller The following figures Figure 38 through Figure 41 on page 52 and their associated tables specify the timings related to the SDRAMC module in the i MX21 gt Note CKE is high during the read write cycle Figure 38 SDRAM Read Cycle Timing Diagram MC9328MX21 Product Preview Rev 1 1 48 Freescale Semiconductor Specifications Table 29 SDRAM Timing Parameter Table Ref 1 8V 3 0V 10 l No Parameter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 3 00 4 ns 2 SDRAM clock low level width 3 00 4 ns 3 SDRAM clock cycle time 11 1 7 5 ns 3S CS RAS CAS WE DQM setup time 4 78 3 ns 3H CS RAS CAS WE DQM hold time 3 03 2 ns 4S Address setup time 3 67 3 ns 4H Address hold time 2 95 2 m ns 5 S
62. ent states Figure 30 shows the different scenarios on the bus MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 41 Specifications Buiuurej804d sng seuiooeq pieg 4o0 q ejep 1se Jeye peAieoei uoissiLsuen dois HEHERRRRERERRRREH SR dudaddadddddade Buiuurej804d sng seuiooeq pieg 4o0 q ejep 1se Je pA uoissiLusueJ dois PRPRPRPRPEPEPPPPPPRPRPRPPPR em s puea eu WO JejsueJ SNIS 2uo Buunp uolssiwsues dois PRPEPPPPPPPPPPPPPPRPRPPPRPR me DRE orospzppIpRpR a Buruwebod si peg Asng JSOY OU WO4 JejsueJ eyep Buunp uoissiusueJ dois HIRHEHIHERRRHEHH IH E ered IUM PPP EE EEE EE oe wo E goo e BER Bebes ones pueWWOD SOH asuodsey plea puewwoy 190H se oKo HON Figure 30 Stop Transmission During Different Scenarios Table 26 Timing Values for Figure 26 through Figure 30 Unit Clock cycles Clock cycles Maximum 64 Minimum and maximum VIL Symbol NCR NID Parameter MMC SD bus clock CLK All values are referred to minimum VIH Command response cycle Identification response cycle MC9328MX 21 Product Preview Rev 1 1 Freescale Semiconductor 42 Specifications Table 26 Timing Values for Figure 26 through Figure 30 Continued Parameter Symbol Minimum Maximum Unit Access time delay cycle NAC 2 TAAC NSAC Clock cycles Co
63. esponse timing data transfer mode Nnc cycles Response Host Command ovo feji cemenijencjiz ejajn NNESNENN ESO Ep Timing response end to next CMD start data transfer mode Ncc cycles Host Command Host Command ovo feji cemeniijencjiz FINGERS ESO Ep Timing of command sequences all modes Figure 27 Timing Diagrams at Data Transfer Mode Figure 28 on page 40 shows basic read operation timing In a read operation the sequence starts with a single block read command which specifies the start address in the argument field The response is sent on the SD CMD lines as usual Data transmission from the card starts after the access time delay Nac beginning from the last bit of the read command If the system is in multiple block read mode the card sends a continuous flow of data blocks with distance Nc until the card sees a stop transmission command The data stops two clock cycles after the end bit of the stop command MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 39 Specifications Nor cycles Host Command gt Response ovo efi Kearen ene eer Hs een Gao gr e 7 a Read Data Nac cycles Timing of single block read Ncp cycles Host Command lt _ gt Response cmo fua 3 amz fpe sgg cs 7 a a ReadData lt gt Read Data Nac cycles Nac cycles Timing of multiple block read Nor cycles Host Command Response ov
64. gh period 36 36 36 36 ns 17 Tx Rx CK clock low period 36 36 36 36 ns 18 Tx CK high to FS bl high 10 40 17 37 8 67 15 88 ns 19 Rx CK high to FS bl high 11 00 19 70 9 28 18 21 ns 20 Tx CK high to FS bl low 10 40 17 37 8 67 15 88 ns 21 Rx CK high to FS bl low 11 00 19 70 9 28 18 21 ns 22 Tx CK high to FS wl high 10 40 17 37 8 67 15 88 ns 23 Rx CK high to FS wl high 11 00 19 70 9 28 18 21 ns 24 Tx CK high to FS wl low 10 40 17 37 8 67 15 88 ns 25 Rx CK high to FS wl low 11 00 19 70 9 28 18 21 ns 26 Tx CK high to STXD valid from high impedance 9 59 17 08 7 86 15 59 ns 27a Tx CK high to STXD high 9 59 17 08 7 86 15 59 ns 27b Tx CK high to STXD low 9 59 17 08 7 86 15 59 ns 28 Tx CK high to STXD high impedance 9 59 16 84 7 86 15 35 ns 29 SRXD setup time before Rx CK low 2 52 2 52 x ns 30 SRXD hole time after Rx CK low 0 0 ns Synchronous Internal Clock Operation SSI2 Ports 31 SRXD setup before Tx CK falling 20 78 20 78 ns 32 SRXD hold after Tx CK falling 0 0 ns Synchronous External Clock Operation SSI2 Ports 33 SRXD setup before Tx CK falling 4 42 4 42 ns 34 SRXD hold after Tx CK falling 0 0 ns 1 All the timings for the SSI are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remain
65. gs NVDD1 through NVDD6 NVSS Noisy Ground for the I O pins MC9328MX21 Product Preview Rev 1 1 14 Freescale Semiconductor Specifications Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes Supply Pins Analog Modules VDDA Supply for analog blocks formally AVDD QVSS internally Quiet GND for analog blocks QVSS and AVSS are synonymous connected to AVSS Internal Power Supply QVDD Power supply pins for silicon internal circuitry QVSS Quiet GND pins for silicon internal circuitry QVDDX Power supply pin for the ARM core connect directly to QVDD 3 Specifications This section contains the electrical specifications and timing diagrams for the 1 M X21 processor 3 1 Maximum Ratings Table 3 provides information on maximum ratings Table 3 Maximum Ratings Rating Symbol Minimum Maximum Unit Supply voltage Vaa 0 3 3 3 V Maximum operating temperature range of i MX21 TA 40 30 0 70 85 C Storage temperature Test 55 150 C 3 2 Recommended Operating Range Table 4 provides the recommended operating ranges for the supply voltages The i MX21 processor has multiple pairs of VDD and VSS power supply and return pins QVDD QVDDx and QVSS pins are used for internal logic All other VDD and VSS pins are for the I O pads voltage supply and each pair of VDD and VSS provides power to the enclosed I O pads Thi
66. gt lt S nae Lj _j j S tT NFIO15 0 Data from NF tRR l lt gt Figure 36 Output Data Latch Cycle Timing Note The data shown in Figure 36 is generated using the NAND Flash device and sampled with IPP_FLASH_CLK Table 27 Timing Characteristics MC9328MX21 Product Preview Rev 1 1 Number Es Minimum Maximum 1 tCLS 0 2 tCLH 10 3 tCS 0 4 tCH 10 5 tWP 25 6 tALS 0 a 7 tALH 10 8 tDS 20 9 tDH 10 10 tWC 45 11 tWH 15 12 tAR 10 13 tCLR 10 14 tRR 20 15 tRP 25 16 tWB 100 46 Freescale Semiconductor Table 27 Timing Characteristics Continued Number See Minimum Maximum 17 tRC 50 18 tCEA 45 19 tREA 30 20 tRHZ E 30 21 tCHZ 20 22 tOH 15 23 tREH 15 24 tIR 0 25 tWHR 60 3 14 Pulse Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency The selected clock signal is passed through a divider and a prescaler before being input to the counter The output is available at the pulse width modulator output PWMO external pin System Clock PWM Output Figure 37 PWM Output Timing Diagram Table 28 PWM Output Timing Parameter Table Specifications Ref 1 8V 0 10V 3 0V 0 30V sio Parameter Unit Minimum Maximum Minimum Maximum 1 System CLK frequ
67. internal pull up via the Pull up enable register a 50 K 69K external pull up resistor must be added SD1 D 3 is muxed with CSPI3_SS while SD1 D 0 is muxed with CSPI3_MISO SD2 CMD SD Command bidirectional signal This signal is multiplexed with SLCDC1 CS signal from SLCDC1 SD2 CLK SD Output Clock signal This signal is multiplexed with SLCDC1 CLK signal from SLCDC1 SD2_D 3 0 SD Data bidirectional signals SD2_D 3 2 are which are multiplexed with SLCDC1 RS and SLCDC DO signals from SLCDC1 UARTs IrDA Auto Bauding UART1 RXD Receive Data input signal UART1_TXD Transmit Data output signal UART1 RTS Request to Send input signal UART1 CTS Clear to Send output signal UART2 RXD Receive Data input signal This signal is multiplexed with KP ROWSG signal from KPP UART2 TXD Transmit Data output signal This signal is multiplexed with KP COL6 signal from KPP UART2 RTS Request to Send input signal This signal is multiplexed with KP ROWT signal from KPP UART2 CTS Clear to Send output signal This signal is multiplexed with KP COL7 signal from KPP UART3_RXD Receive Data input signal This signal is multiplexed with IR_RXD from FIRI UART3_TXD Transmit Data output signal This signal is multiplexed with IR TXD from FIRI UART3_RTS Request to Send input signal UART3_CTS Clear to Send output signal UART4_RXD Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP UART4_TXD Transmit Data output signal which is
68. ive Sequential Read Accesses WSC 2 EW 1 DCT 1 AGE 0 Example of DTACK staying high MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 95 Specifications ESI du s sce 8 BCOLK 5 2 S ADDR Last Valid Addr Address V1 Y V144 X V148 Y t CS 0 RWA AWN r gt RW Write A EN LBA OE EB DCT vc EN DATA OUT V1 Word X V1 4 Word J vi 8 Figure 79 DTACK Level Sensitive Sequential Write Accesses WSC 2 EW 1 RWA 1 RWN 1 DCT 1 AGE 0 Example of DTACK Asserting MC9328MX21 Product Preview Rev 1 1 96 Freescale Semiconductor 3 21 The PC communication protocol consists of seven elements START Data Source Recipient Data Direction Slave Acknowledge Data Data Acknowledge and STOP I2C Module Specifications SCL Figure 80 Definition of Bus Timing for lc Table 42 1 C Bus Timing Parameter Table Ret 1 8V 0 10V 3 0V 0 30V l No Parameter Unit Minimum Maximum Minimum Maximum SCL Clock Frequency 0 100 0 100 kHz 1 Hold time repeated START condition 114 8 111 1 ns 2 Data hold time 0 69 7 0 72 8 ns 3 Data setup time 3 1 1 76 ns 4 HIGH period of the SCL clock 69 7 68 3 ns 5 LOW period of the SCL clock 336 4 335 1 ns 6 Setup time for STOP condition 110 5 111 1 ns 3
69. me after FOL mode for non integer MF does not 220 280 330 Tref partial reset include pre multi lock in time Phase lock in time after FPL mode and integer MF does not 480 530 580 Tref full reset include pre multi lock in time Phase lock in time after FPL mode and integer MF does not 360 410 460 Tref partial reset include pre multi lock in time Frequency jitter p p 0 02 0 03 2 T ack Phase jitter p p Integer MF FPL mode Vcc 1 5V 1 0 1 5 ns Power dissipation FOL mode integer MF 1 5 mW fuck 560 MHz Vcc 1 5V Avg MC9328MX21 Product Preview Rev 1 1 18 Freescale Semiconductor 3 6 Reset Module Specifications The timing relationships of the Reset module with the POR and RESET IN are shown in Figure 2 and Figure 3 on page 20 Be aware that NVDD must ramp up to at least 1 7V for NVDDI and 2 7V for NVDD2 6 before QVDD is powered up to prevent forward biasing i v D O Can be adjusted depending on the crystal start up time 32KHz or 32 768KHz RESET_POR Exact 300ms RESET_DRAM HRESET RESET_OUT CLK32 HCLK lt 3 gt 7 cycles CLK32 14 cycles CLK32 Figure 2 Timing Relationship with POR MC9328MX21 Product Preview Rev 1 1 Jj g Freescale Semiconductor 19 Specifications gt RESET_IN 14 cycles CLK32 HRESET RESET_OUT cel 9 CLK
70. mmand read cycle NRC 8 Clock cycles Command command cycle NCC 8 Clock cycles Command write cycle NWR 2 Clock cycles Stop transmission cycle NST 2 2 Clock cycles TAAC Data read access time 1 defined in CSD register bit 119 112 NSAC Data read access time 2 in CLK cycles NSAC 100 defined in CSD register bit 111 104 3 12 2 SDIO IRQ and ReadWait Service Handling In SDIO there is a 1 bit or 4 bit interrupt response from the SDIO peripheral card In 1 bit mode the interrupt response is simply that the SD_DATT 1 line is held low The SD DATTI line is not used as data in this mode The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed SD DATTI1 returns to its high level In 4 bit mode the interrupt is less simple The interrupt triggers at a particular period called the Interrupt Period during the data access and the controller must sample SD DATT 1 during this short period to determine the IRQ status of the attached card The interrupt period only happens at the boundary of each block 512 bytes DATT1 Interrupt Period Block Data IRQ Block Data IRQ For 4 bit m 4 DAT 1 Interrupt Period For 1 bit Figure 31 SDIO IRQ Timing Diagram ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer In this mode the block temporarily pauses the data transfer operation counter and relate
71. muxed with SLCDC1_DAT10 USBH1_RXDP USB Host1 Receive Data Plus input signal This signal is multiplexed with VART4_RXD and SLCDC1_DATE6 It also provides an alternative multiplex for UART4 RTS where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter USBH1 RXDM USB Host1 Receive Data Minus input signal This signal is muxed with SLCDC1 DATS It also provides an alternative multiplex for UART4 CTS USBH1_TXDP USBH1_TXDM USB Host1 Transmit Data Plus output signal This signal is multiplexed with UART4 CTS and SLCDC1_DAT4 It also provides an alternative multiplex for UART4 RXD where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter USB Host1 Transmit Data Minus output signal This signal is multiplexed with UART4 TXD and SLCDC1_DATS3 USBH1_RXDAT USB Host1 Transceiver differential data receive signal Multiplexed with USBH1_FS USBH1_OE USB Host1 Output Enable signal This signal is muxed with SLCDC1_DAT2 USBH1_FS USB Host1 Full Speed output signal This signal is multiplexed with UART4_RTS and SLCDC1_DAT1 and USBH1_RXDAT USBH_ON USB Host transceiver ON output signal This signal is muxed with SLCDC1_DATO USBH2_RXDP USB Host2 Receive Data Plus input signal This signal is multiplexed with CSPI2_SS 1 of CSPI2 USBH2_RXDM USB Host2 Receive Data Minus i
72. nal is invert version of PS Sharp panel dedicated signal This signal is multiplexed with the SLCDC1 RS REV Signal for common electrode driving signal preparation Sharp panel dedicated signal This signal is multiplexed with SLCDC1 DO Smart LCD Controller SLCDC1 CLK SLCDC Clock output signal This signal is multiplexed and available at 2 alternate locations These are SPL SPR and SD2 CLK signals of LCDC and SD2 respectively SLCDC1 CS SLCDC Chip Select output signal This signal is multiplexed and available at 2 alternate signal locations These are PS and SD2_CMD signals of LCDC and SD2 respectively SLCDC1 RS SLCDC Register Select output signal This signal is multiplexed and available at 2 alternate signal locations These are CLS and SD2 D3 signals of LCDC and SD2 respectively SLCDC1 DO SLCDC serial data output signal This signal is multiplexed and available at 2 alternate signal locations These are and REV and SD2 D2 signals of LCDC and SD2 respectively This signal is inactive when a parallel data interface is used MC9328MX 21 Product Preview Rev 1 1 8 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes SLCDC1 DAT 15 0 SLCDC Data output signals for connection to a parallel SLCD panel interface These signals are multiplexed with LD 15 0 while an alternate 8 bit SLCD muxing is available on LD 15 8 Further alternate muxing of these
73. nce 2 44 0 60 2 65 0 98 ns 11a Tx CK high to STXD high 2 44 0 60 2 65 0 98 ns 11b Tx CK high to STXD low 2 44 0 60 2 65 0 98 ns 12 Tx CK high to STXD high impedance 2 67 0 99 2 65 0 98 ns 13 SRXD setup time before Rx CK low 23 68 22 09 ns 14 SRXD hold time after Rx CK low 0 0 ns External Clock Operation SAP Ports 15 Tx Rx CK clock period 90 91 90 91 ns 16 Tx Rx CK clock high period 36 36 36 36 ns 17 Tx Rx CK clock low period 36 36 36 36 ns 18 Tx CK high to FS bl high 10 24 19 50 7 16 8 65 ns 19 Rx CK high to FS bl high 10 89 21 27 7 63 9 12 ns 20 Tx CK high to FS bl low 10 24 19 50 7 16 8 65 ns 21 Rx CK high to FS bl low 10 89 21 27 7 63 9 12 ns 22 Tx CK high to FS wl high 10 24 19 50 7 16 8 65 ns 23 Rx CK high to FS wl high 10 89 21 27 7 63 9 12 ns 24 Tx CK high to FS wl low 10 24 19 50 7 16 8 65 ns 25 Rx CK high to FS wl low 10 89 21 27 7 63 9 12 ns 26 Tx CK high to STXD valid from high impedance 12 08 19 36 7 71 9 20 ns 27a Tx CK high to STXD high 10 80 19 36 7 71 9 20 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 55 Specifications Table 32 SSI to SAP Ports Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 27b Tx CK high to STXD low 10 80 19 36 7 71 9 20 ns 28 Tx CK high to STX
74. nput signal This signal is multiplexed with CSPI2_SS 2 of CSPI2 USBH2_TXDP USB Host2 Transmit Data Plus output signal This signal is multiplexed with CSPI2_MOSI of CSPI2 USBH2 TXDM USB Host2 Transmit Data Minus output signal This signal is multiplexed with CSPI2_MISO of CSPI2 USBH2 OE USB Host2 Output Enable signal This signal is multiplexed with CSPI2_SCLK of CSPI2 USBH2 FS USB Host Full Speed output signal This signal is multiplexed with CSPI2_SS 0 of CSPI2 USBG SCL USB OTG l C Clock Output signal This signal is multiplexed with SLCDC1 DAT8 USBG SDA USB OTG l C Data Input Output signal This signal is multiplexed with SLCDC1 DAT7 USBG TXR INT USB OTG transceiver Interrupt input Multiplexed with USBG FS Secure Digital Interface SD1 CMD SD Command bidirectional signal lf the system designer does not want to make use of the internal pull up via the Pull up enable register a 4 7K 69K external pull up resistor must be added This signal is multiplexed with CSPI3_MOSI SD1 CLK SD Output Clock This signal is multiplexed with CSPI3 SCLK MC9328MX21 Product Preview Rev 1 1 12 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes SD1 D 3 0 SD Data bidirectional signals lf the system designer does not want to make use of the
75. ns the initialization sequence and it is initiated when the RPP control register bit is set When the presence pulse is detected this bit will be cleared The presence pulse is used by the bus master to determine if at least one DS2502 is connected Software will determine if more than one DS2502 exists The one wire will sample for the DS2502 presence pulse The presence pulse is latched in the one wire control register PST When the PST bit is set to a one it means that a DS2502 is present if the bit is set to a zero then no device was found 3 17 2 Write 0 The Write 0 function simply writes a zero bit to the DS2502 The sequence takes 117 us The one wire bus is held low for 100us Set WRO AutoClear WRO Write 0 Slot 128us 17us t 100us gt one wire BUS Figure 47 Write 0 Timing The Write 0 pulse sequence is initiated when the WRO control bit register is set When the write is complete the WRO register will be auto cleared 3 17 3 Write 1 Read Data The Write 1 and Read timing is identical The time slot is first driven low According to the DS2502 documentation the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus master one wire This delay circuit is triggered by the falling edge of the data line and is used to decide when the DS2502 should sample the line In the case of a write 1 or read 1 after a delay a 1 will be transmitted received When a read 0 slot is issued th
76. o ET conen Jer A enm one par aaa Valid Read Data Timing of stop command CMD12 data transfer mode Figure 28 Timing Diagrams at Data Read Figure 29 on page 41 shows the basic write operation timing As with the read operation after the card response the data transfer starts after Nwp cycles The data is suffixed with CRC check bits to allow the card to check for transmission errors The card sends back the CRC check result as a CC status token on the data line If there was a transmission error the card sends a negative CRC status 101 otherwise a positive CRC status 010 is returned The card expects a continuous flow of data blocks if it is configured to multiple block mode with the flow terminated by a stop transmission command MC9328MX 21 Product Preview Rev 1 1 40 Freescale Semiconductor Specifications PUBWWOD m 9ol q ejdninui eui jo Buru L sejo o YMN sejo o YMN lt lt snes 949 snieis QUO feng eed OM lt gt ered OM EERE PEPE ER PE PEPE PPP oo wowo seppe weweo ppp iva zp 1 BP sms pppp ouo weneo spbpp swes pzpp oso wewo ppp ivo a ono sejo o YMN gt l PUBLULWOD 91JM x9o q eui Jo Bui snes 2HO sng lt gt eped IUM MENN e A edi Ec Bees e meo O e dw EO ee eppo weeo LSE pppposo wewoo fjs ano esuodseg pueuJulo SOH s j o HON Figure 29 Timing Diagrams at Data Write The stop transmission command may occur when the card is in differ
77. of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners The ARM Powered logo and ARM926EJ S are trademarks of ARM Limited ARM is a registered trademark of ARM Ltd All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 All rights reserved freescale semiconductor WWW ALLDATASHEET COM Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
78. ogic to generate the read or write signals Data write cycles are continuously generated when TxFIFO is not emptied To issue a read cycle the user can write a value of 1 to the READ bit of control register This bit is cleared automatically when the read operation is completed A read cycle reads COUNT 1 data from the external bus slave The user can write a 1 to the READ bit while there is still data in the TxFIFO but the read cycle will not start until all data in the TxFIFO is emptied If the read cycle begins the write operation also cannot begin until this read cycle complete In this master mode operation Int Clk is derived from HCLK through an integer divider DIV of BMI control register and it is used to control the read write cycle timing by generate WRITE and CLK CS signals MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 27 Specifications 3 8 8 1 Memory Interface Master Mode Without WAIT Signal The WAIT control bit BMICTLR1 29 is used in this mode When this bit is cleared default the BMI WAIT signal is ignored and the CS cycle is terminated by Wait State WS control bits Figure 11 shows the BMI timing when the WAIT bit is cleared itws 1 l ws jaws 1 ws i a i 1 1 1 oa i Int CIk IN reference only i Int_write reference only
79. on n Nonseq n M Read Y vi A S mom Last Valid Adar Last Valid Data Write Data Last Valid Data n Read Data Address V1 Address V8 CS 2 R W m Read LBA Write eae OE EB EBC 0 EB EBC 1 DATA_IN D 31 0 Figure 67 WSC 2 WWS 1 WEA 1 WEN 2 EDC 1 A HALF E HALF DEN A a Read Data Last Valid Data Y Write Data MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 83 Specifications helk hselm weim cs 4 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK 24 0 CS 3 0 ie de gx i us Nee J y Nonseq Write y yi Last Valid Data Write Data Word Last Valid Data 5 Te Last Valid Addr Address V1 Address V1 2 R W LBA jM Write je xc Maca EB D 31 0 Last Valid Data Y Write Data 1 2 Half Word Write Data 2 2 Half Word Figure 68 WSC 2 CSA 1 WWS 1 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 84 Freescale Semiconductor helk hselm_weim_cs 4 htrans hwrite haddr hready hwd
80. r 71 Specifications hclk hselm weim cs 0 htrans hwrite haddr hready weim hrdata weim hready BCLK 24 0 PC ED XS B Crones Y M Reaal E E EE E Ae Last Valid Addr Address V1 y Address V1 2 CS 0 EB EBC 0 EB EBC 1 DATA IN Read 4 3 3 m 1 2 Half Word E 2 2 H alf Word Figure 56 WSC 1 OEA 1 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 72 Freescale Semiconductor Specifications me a ie Oe up Mu RM ae Os NE hselm_weim_cs 0 Gh o a htrans Y Noneq Y hwrite Write V haddr Y V1 meady CE KERN hwdata Last Valid Data Y Write Data V1 Word Y weim_hrdata Last Valid Data weim_hready E NE BCLK A 24 0 Last Valid Addr Y Address V1 Y Address V1 2 CSI0 RW Write o LBA ee OE z E ee D 31 0 1 2 Half Word Y 2 2 Half Word Figure 57 WSC 1 WEA 1 WEN 1 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 73 Specifications ek 7 le uon N IRSE hselm weim cs 3 S M htrans JNonseq Y hwrite V Read hadar Y vi Y hready d c weim hrdata Last Valid Data EE vo woe j bie
81. r and receiver each have their own clock and frame synchronization signals Continuous or gated clock mode can be selected In continuous mode the clock runs continuously In gated clock mode the clock functions only during transmission The internal and external clock timing diagrams are shown in Figure 42 through Figure 45 on page 54 Normal or network mode can also be selected In normal mode the SSI functions with one data word of I O per frame In network mode a frame can contain between 2 and 32 data words Network mode is typically used in star or ring time division multiplex networks with other processors or codecs allowing interface to time division multiplexed networks without additional logic Use of the gated clock is not allowed in network mode These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices The SSI can be connected to 4 set of ports SAP SSII SSI2 and SSI3 I 1 1 CK Output FS bl Output Os mi oi wl Outpu TA D STXD Output 61 SRXD Input Note SRXD input in synchronous mode only Figure 42 SSI Transmitter Internal Clock Timing Diagram CK Output RN gt 3 G gt lt FS bl Output N T gt FS wl Output p SRXD Input Figure 43 SSI Receiver Internal Clock Timing Diagram MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 53 Specifications CK Input
82. r circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture
83. r1 GPT1 This signal is multiplexed with SSI1_MCLK and SSI2 MCLK signal of SSI1 and SSI2 The pin name of this signal is simply TOUT TOUT2 Timer Output signal from General Purpose Timer1 GPT2 This signal is multiplexed with PWMO TOUT3 Timer Output signal from General Purpose Timer1 GPT3 This signal is multiplexed with PWMO USB On The Go USB_BYP USB Bypass input active low signal USB_PWR USB Power output signal USB_OC USB Over current input signal USBG_RXDP USB OTG Receive Data Plus input signal This signal is muxed with SLCDC1_DAT15 USBG_RXDM USB OTG Receive Data Minus input signal This signal is muxed with SLCDC1_DAT14 USBG_TXDP USB OTG Transmit Data Plus output signal This signal is muxed with SLCDC1_DAT13 USBG_TXDM USB OTG Transmit Data Minus output signal This signal is muxed with SLCDC1_DAT12 USBG_RXDAT USB OTG Transceiver differential data receive signal Multiplexed with CSPI1_SS2 USBG_OE USB OTG Output Enable signal This signal is muxed with SLCDC1_DAT11 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 11 Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes USBG_ON USB OTG Transceiver ON output signal This signal is muxed with SLCDC1_DAT9 USBG_FS USB OTG Full Speed output signal This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG This signal is
84. re 74 WSC 2 SYNC 1 DOL 1 0 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 90 Freescale Semiconductor hclk hselm weim cs 2 htrans hwrite haddr hready weim hrdata weim hready BCLK A 24 0 CS 2 Specifications Au Ur OP eT ERI P A Idle Last Valid Data Lo o V word MRNA V2 Word Ness riesgo NEUF es Ne TURN Last Valid Y Address V1 Addr Read ECB DATA_IN V1 1 2 Avi 2 2 d V2 1 2 Y V2 2 2 Figure 75 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 2 A WORD E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 91 Specifications eene Nor adr Re Al ENE aede Na eats Ng hselm_weim_cs 2 d htrans esp hwrite Read Read 5j haddr i V1 hready an weim_hrdata Last Valid Data g Word RR V2 Word weim_hready E N BCLK D NL ARD C E ME SU E en 3 A 24 0 ae ing Y Address V1 CS 2 TN QE R W Read or EB EBC 0 X EB EBC 1 DATA IN GE vio voy vwy vez j Figure 76 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 1 A WORD E HALF 3 20 DTACK Mode Memory Access Timing Di
85. relative precision 1 f 1 divider clock MHz 1 The Table 37 gathers relative time precision for different main clock frequencies MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Specifications Table 37 System Clock Requirements Main Clock Frequency MHz 13 16 8 19 44 Clock divide ratio 13 17 19 Generated frequency MHz 1 0 9882 1 023 Relative time imprecision 0 0 0117 0 023 This shows that the user should take care of the main clock frequency when using the one wire module If the main clock is an exact integer multiple of 1 MHz then the generated frequency will be exactly 1 MHz NOTE A main clock frequency below 10 MHz might cause a misbehavior of the module 3 18 USB On The Go Four types of data transfer modes exist for the USB module control transfers bulk transfers isochronous transfers and interrupt transfers From the perspective of the USB module the interrupt transfer type is identical to the bulk data transfer mode and no additional hardware is supplied to support it This section covers the transfer modes and how they work from the ground up Data moves across the USB in packets Groups of packets are combined to form data transfers The same packet transfer mechanism applies to bulk interrupt and control transfers Isochronous data is also moved in the form of packets but because isochronous pipes are given a fixed portion of the USB bandwidth at all times
86. rom RxFIFO much faster than the BMI interface Overflow interrupt is generated if RxFIFO overflow is detected Once this happens the new coming data is ignored 3 8 1 1 1 MMD Read BMI Timing Figure 6 shows the MMD read BMI timing when the MMD drives clock On each rising edge of BMI CLK CS BMI checks the BMI WRITE logic level to determine if the current cycle is a read cycle It puts data into the data bus and enables the data out on the rising edge of BMI CLK CS if BMI WRITE is logic high The BMI READ REQ is negated one hclk cycle after the BMI CLK CS rising edge of last data read The MMD cannot issues read command when BMI READ REQ is low no data in TxFIFO MC9328MX 21 Product Preview Rev 1 1 22 Freescale Semiconductor Specifications 1T gt BMI_CLK CS BMI READ REQ soe E d COT i BMI_D 15 0 net Anoe UNDE X X Z wo BMI_WRITE Figure 6 MMD ATI Drives Clock MMD Read BMI Timing MMD_MODE_SEL 1 MASTER_MODE_SEL 0 MMD_CLKOUT 0 Table 12 MMD Read BMI Timing Table when MMD Drives Clock Item Symbol Minimum Typical Maximum Unit Clock period 1T 33 3 ns write setup time Ts 11 ns read req hold time Trh 6 F 24 ns transfer data setup time Tds 6 14 ns transfer data hold time Tdh 6 14 ns Note All the timings assume that the hclk is running at 133 MHz Note The MIN period of the 1T is assumed that M
87. s design allows different peripheral supply voltage levels in a system Because AVDD pins are supply voltages to the analog pads it is recommended to isolate and noise filter the AVDD pins from other VDD pins For more information about I O pads grouping per VDD please refer to Table 4 on page 15 Table 4 Recommended Operating Range Rating Symbol Minimum Maximum Unit I O supply voltage NVDD 2 3 4 5 6 2 70 3 30 V I O supply voltage NVDD 1 1 70 3 30 V MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 15 Specifications Table 4 Recommended Operating Range Continued Rating Symbol Minimum Maximum Unit Internal supply voltage Core 266 MHz QVDD QVDDx 1 45 1 65 V Analog supply voltage AVDD 1 70 3 30 V 3 3 DC Electrical Characteristics Table 5 contains both maximum and minimum DC characteristics of the M X21 Table 5 Maximum and Minimum DC Characteristics Number rae Parameter Minimum Typical Maximum Unit or Symbol lop Full running operating current 120mA 5 mA QVDD amp QVDDx 1 65V NVDD1 1 8V NVDD2 QVDD QVDDx 6 amp AVDD 3 1V Full run Core 266MHz System 133MHz 8mA Doze Core 266MHz System 53MHz NVDD1 MPEG4 Playback QVGA from MMC SD card 30fps 44 1kHz audio 6 6mA NVDD2 6 AVDD Sidd Standby current QVDD QVDDx 1 55V 360 uA Vin Input high voltage 0 7NVDD NVD
88. s shut down XTAL26M Oscillator output to external crystal EXTAL32K 32 kHz crystal input XTAL32K Oscillator output to 32 kHz crystal CLKO Clock Out signal selected from internal clock signals Please refer to clock controller for internal clock selection EXT 48M This is a special factory test signal To ensure proper operation connect this signal to ground EXT 266M This is a special factory test signal To ensure proper operation connect this signal to ground RESET IN Master Reset External active low Schmitt trigger input signal When this signal goes active all modules except the reset module SDRAMC module and the clock control module are reset RESET OUT Reset Out Internal active low output signal from the Watchdog Timer module and is asserted from the following sources Power on reset External reset RESET IN and Watchdog time out POR Power On Reset Active low Schmitt trigger input signal The POR signal is normally generated by an external RC circuit designed to detect a power up event CLKMODE 1 0 These are special factory test signals To ensure proper operation leave these signals as no connects OSC26M_TEST This is a special factory test signal To ensure proper operation leave this signal as a no connect TEST WB 2 0 These are special factory test signals However these signals are also multiplexed with GPIO PORT E as well as alternate keypad signals If not utilizing these signals for GP
89. s valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 59 Specifications Table 35 SSI to SSI3 Ports Timing Parameter Table Ret 1 8V 0 10V 3 0V 0 30V l No Parameter o R E Unit Minimum Maximum Minimum Maximum Internal Clock Operation SSI3 Ports 1 Tx Rx CK clock period 90 91 90 91 ns 2 Tx CK high to FS bl high 2 09 0 66 2 09 0 66 ns 3 Rx CK high to FS bl high 2 74 0 84 2 74 0 84 ns 4 Tx CK high to FS bl low 2 09 0 66 2 09 0 66 ns 5 Rx CK high to FS bl low 2 74 0 84 2 74 0 84 ns 6 Tx CK high to FS wl high 2 09 0 66 2 09 0 66 ns 7 Rx CK high to FS wl high 2 74 0 84 2 74 0 84 ns 8 Tx CK high to FS wl low 2 09 0 66 2 09 0 66 ns 9 Rx CK high to FS wl low 2 74 0 84 2 74 0 84 ns 10 Tx CK high to STXD valid from high impedance 1 73 0 26 1 73 0 26 ns 11a Tx CK high to STXD high 2 87 0 80 2 87 0 80 ns 11b Tx CK high to STXD low 2 87 0 80 2 87 0 80 ns 12 Tx CK high to STXD high impedance 1 73 0 26 1 73 0 26 ns 13 SRXD setup time before Rx CK low 22 77 22 77 ns 14 SRXD hold time after Rx CK low 0 0 ns External Clock Operation SSI3 Ports 15 Tx Rx CK clock period 90 91 90 91
90. se width Tsclk WAIT 3 ns 6 SS input low to first SCLK edge T ns 7 SS input pulse width T ns 1 T CSPI system clock period PERCLK2 2 Tsclk Period of SCLK 3 WAIT Number of bit clocks SCLK or 32 768 KHz clocks per Sample Period Control Register 3 10 LCD Controller This section includes timing diagrams for the LCD controller For detailed timing diagrams of the LCD controller with various display configurations refer to the LCD controller chapter of the i MX21 Reference Specifications Manual T1 48 LSCLK LD 17 0 x x T2 13 M Figure 19 SCLK to LD Timing Diagram Table 18 LCDC SCLK Timing Parameter Table 3 0 0 3V Unit Symbol Parameter Minimum Maximum T1 SCLK period 23 2000 ns T2 Pixel data setup time 11 ns T3 Pixel data up time 11 ns The polarity of SCLK and L The pixel clock is equal to LCDC_CLK PCD 1 When it is in CSTN TFT or monochrome mode with bus width 1 SCLK is equal to the pixel clock When it is in monochrome with other bus width settings SCLK is equal to the pixel clock divided by bus width D can also be programmed Maximum frequency of SCLK is HCLK 3 for TFT and CSTN otherwise LD output will be incorrect MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 31 Specifications gt lt Non display region gt lt lt Display r
91. state e Logic level zero is a voltage that corresponds to Boolean false 0 state To seta bit or bits means to establish logic level one To clear a bit or bits means to establish logic level zero A signal is an electronic construct whose state conveys or changes in state convey information e A pin is an external physical connection The same pin can be used to connect a number of signals Asserted means that a discrete signal is in active logic state Active low signals change from logic level one to logic level zero Active high signals change from logic level zero to logic level one Negated means that an asserted discrete signal changes logic state Active low signals change from logic level zero to logic level one Active high signals change from logic level one to logic level zero e LSB means least significant bit or bits and MSB means most significant bit or bits References to low and high bytes or words are spelled out e Numbers preceded by a percent sign 96 are binary Numbers preceded by a dollar sign or Ox are hexadecimal 1 2 Target Applications The 1 MX21 is targeted for advanced information appliances smart phones Web browsers digital MP3 audio players handheld computers based on the popular Palm OS platform and messaging applications 1 3 Reference Documentation The following documents are required for a complete description of the i MX21 and are necessary to design properly with the
92. ta Transfer from USB Transceiver RX 3 0 0 3V Ref No Parameter Unit Minimum Maximum 1 trgopn Receiver SEO interval of EOP 82 ns The USBOTG C communication protocol consists of six components START Data Source Recipient Data Direction Slave Acknowledge Data Data Acknowledge and STOP USBG_SDA N Ji ECCO USBG SCL O Figure 52 USB Timing Diagram for Data Transfer from USB Transceiver IC MC9328MX21 Product Preview Rev 1 1 66 Freescale Semiconductor Specifications Table 40 USB Timing Parameter Table for Data Transfer from USB Transceiver I2C 1 8 0 10V Ref No Parameter Pp Unit Minimum Maximum 1 Hold time repeated START condition 188 ns 2 Data hold time 0 188 ns 3 Data setup time 88 ns 4 HIGH period of the SCL clock 500 ns 5 LOW period of the SCL clock 500 ns 6 Setup time for STOP condition 185 ns 3 19 External Interface Module EIM The External Interface Module EIM handles the interface to devices external to the i MX21 including generation of chip selects for external peripherals and memory The timing diagram for the EIM is shown in Figure 53 and Table 41 on page 68 defines the parameters of signals MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 67 Specifications Write Data negated falling HCLK Bus Clock Address Chip select R
93. ter Unit Minimum Maximum Minimum Maximum 9 Data hold time 2 45 2 x ns 1 Precharge cycle timing is included in the write timing diagram 2 tgp and tgcp SDRAM clock cycle time These settings can be found in the i MX21 reference manual DQM i i i i i i i Figure 40 SDRAM Refresh Timing Diagram Table 31 SDRAM Refresh Timing Parameter Table 1 8V 3 0V 10 Ref Ho Parameter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 3 00 4 ns 2 SDRAM clock low level width 3 00 4 ns 3 SDRAM clock cycle time 11 1 7 5 ns MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Specifications Table 31 SDRAM Refresh Timing Parameter Table Continued Bai 1 8V 3 0V 10 Ne Parameter Unit Minimum Maximum Minimum Maximum 4 Address setup time 3 67 3 ns 5 Address hold time 2 95 2 ns 6 Precharge cycle period tgp tgp ns 7 Auto precharge command period tac tac ns Figure 41 SDRAM Self Refresh Cycle Timing Diagram 3 16 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous In synchronous mode the transmitter and the receiver use a common clock and frame synchronization signal In asynchronous MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Specifications mode the transmitte
94. tes EB2 Byte Strobe Active low external enable byte signal that controls D 15 8 shared with SDRAM DQM2 and PCMCIA PC_REG EB3 LSB Byte Strobe Active low external enable byte signal that controls D 7 0 shared with SDRAM DQM3 and PCMCIA PC IORD OE Memory Output Enable Active low output enables external data bus shared with PCMCIA PC IOWR CS 5 0 Chip Select The chip select signals CS 3 2 are multiplexed with CSD 1 0 and are selected by the Function Multiplexing Control Register FMCR in the System Control chapter By default CSD 1 0 is selected DTACK is multiplexed with CS4 ECB Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on going burst sequence and initiate a new long first access burst sequence LBA Active low signal sent by flash device causing the external burst device to latch the starting burst address BCLK Clock signal sent to external synchronous memories such as burst flash during burst mode RW RW signal Indicates whether external access is a read high or write low cycle This signal is also shared with the PCMCIA PC WE DTACK DTACK signal External input data acknowledge signal multiplexed with CS4 Bootstrap BOOT 3 0 System Boot Mode Select The operational system boot mode of the i MX21 upon system reset is determined by the settings of these pins S
95. the data in the TXFIFO is larger or equal to the data transfer size of a single external BMI access This signal is muxed with LD 16 of LCDC BMI RXF FULL BMI Receive FIFO full active high output signal to reflect if the RxFIFO reaches water mark value This signal is muxed with VSYNC of the LCDC BMI WAIT BMI Wait Active low signal to wait for data ready read cycle or accepted write cycle Also multiplexed with VSYNC External DMA EXT DMAREQ External DMA Request input signal This signal is multiplexed with CSPI1_RDY EXT_DMAGRANT External DMA Grant output signal This signal is multiplexed with LD 16 NAND Flash Controller NF_CLE NAND Flash Command Latch Enable output signal This signal is multiplexed with PC_POE of PCMCIA NF_CE NAND Flash Chip Enable output signal This signal is multiplexed with PC_CE1 of PCMCIA NF_WP NAND Flash Write Protect output signal This signal is multiplexed with PC_CE2 of PCMCIA NF_ALE NAND Flash Address Latch Enable output signal This signal is multiplexed with PC_OE of PCMCIA NF_RE NAND Flash Read Enable output signal This signal is multiplexed with PC_RW of PCMCIA MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function Notes NF_W
96. to 1 or greater in the Chip Select 5 Control Register AGE bit set in the EIM Configuration Register Other bits such as DSZ OEA OEN and so on may be set according to system and timing requirements of the external device The requirement of setting CSA or CSN is required to allow the EIM to wait for the rising edge of DTACK during back to back external transfers such as during DMA transfers or an internal 32 bit access through an external 16 bit data port During level sensitive detection the EIM will first hold off sampling the DTACK signal for at least 2 HCLK cycles and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control Register After this insensitivity time the EIM will sample DTACK and if it detects that DTACK is logic high it will continue the data transfer at the programmed number of wait states However if the EIM detects that DTACK is logic low it will wait until DTACK goes to logic high to continue the access so long as this occurs within the 1024 HCLK cycle time If at anytime during an external data transfer DTACK goes to logic low the EIM will wait until DTACK returns to logic high to resume the data transfer Level detection is often used for asynchronous devices such graphic controller chips Level detection may be used with any chip select except CS 4 as it is multiplexed with the DTACK signal To configure a chip select for DTACK level sensitive detection the following bits must be programmed in the
97. w Rev 1 1 104 Freescale Semiconductor Document Revision History 5 Document Revision History This revision Rev 1 1 updates the functional block diagram Figure 1 on page 2 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 105 How to Reach Us USA Europe Locations Not Listed Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 Asia Pacific Freescale Semiconductor Hong Kong Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Home Page www freescale com MC9328MX21 D Rev 1 1 09 29 2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product o
98. weim hrdata weim hready BCLK A 24 0 CS 4 RW OE EB EBC 0 EB EBC 1 DATA_IN D 31 0 Specifications e ics eae cae PN y Nonseq E Read vt A j 0 Last Valid Data Write Data Last Valid Data n Read Data Last Valid Addr Address V1 y Address V8 CNC gt A Read V Write A P grec Data gi Last Valid Data X Write Data Figure 71 WSC 2 OEA 2 WEA 1 WEN 2 CNC 3 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 87 Specifications hclk hselm weim cs 2 htrans hwrite haddr hready weim hrdata weim hready BCLK A 24 0 CS 2 a ETE BE b us Y Nonseq JI Idle Read X vs A X X ai WR nm d oe i ae ee ee Last Valid Addr Address V1 Address V5 l R W LBA U OE EB EBC 0 EB EBC 1 ECB DATA_IN Read V1 Word JV2 Word V5 Word V6 Wo Figure 72 WSC 3 SYNC 1 A HALF E HALF MC9328MX21 Product Preview Rev 1 1 88 Freescale Semiconductor
99. wo Synchronous Serial Interfaces SSI with Inter IC Sound PS Digital Audio Mux One Wire Controller Keypad Interface e Memory Expansion and I O Card Support Two Multimedia Card and Secure Digital MMC SD Host Controller Modules Memory Interface External Interface Module EIM SDRAM Controller SDRAMC NAND Flash Controller NFC PCMCIA CF Interface e Standard System Resources Clock Generation Module CGM and Power Control Module Three General Purpose 32 Bit Counters Timers Watchdog Timer Real Time Clock Sampling Timer RTC Pulse Width Modulator PWM Module Direct Memory Access Controller DMAC General Purpose I O GPIO Ports Debug Capability 2 Signal Descriptions This section identifies and describes the 1 MX21 signals and their pin assignments The i MX21 signals are listed in Table 2 Table 2 i MX21 Signal Descriptions Signal Name Function Notes External Bus Chip Select EIM A 25 0 Address bus signals D 31 0 Data bus signals EBO MSB Byte Strobe Active low external enable byte signal that controls D 31 24 shared with SDRAM DQMO EB1 Byte Strobe Active low external enable byte signal that controls D 23 16 shared with SDRAM DQM1 MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor Signal Descriptions Table 2 i MX21 Signal Descriptions Continued Signal Name Function No
100. x write External device NOTE Assuming in worst case the data is read written from to External device as per the above waveform Figure 5 Safe Maximum Timings for External Request De Assertion MC9328MX21 Product Preview Rev 1 1 Freescale Semiconductor 21 Specifications Table 11 DMA External Request and Grant Timing Parameter Table 3 0V 1 8V Parameter Description Unit WCS BCS WCS BCS Minimum assertion time of 8helk 8 6 8hclk 2 74 8hclk 7 17 8 hclk 3 25 ns min assert External Grant signal Maximum External request 9 hclik 20 66 9hclk 6 7 9hclk 17 96 9 hclk 8 16 ns tmax_req_assert assertion time after assertion of Grant signal Maximum External request 8 hclk 6 21 8hclk 0 77 8hclk 5 84 8 hclk 0 66 ns lmax read assertion time after first read completion Maximum External request 3 hclk 15 87 S3hclk 8 83 3hclk 15 9 3hclk 9 12 ns tmax_write assertion time after completion of first write 3 8 BMI Interface Timing Diagram 3 8 1 Connecting BMI to ATI MMD Devices 3 8 1 1 ATI MMD Devices Drive the BMI CLK CS In this mode MMD MODE SEL bit is set and MMD CLKOUT bit is cleared BMI WRITE and BMI CLK CS are input signals to BMI driving by ATI MMD chip set Output signal BMI READ REQ can be used as interrupt signal to inform MMD that data is ready in BMI TxFIFO for read access MMD can write data to BMI RxFIFO anytime as CPU or DMA can move data out f

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