Home

freescale MC9328MX1 Manual

1. Ret 1 8V 0 10V 3 0V 0 30V f No Parameter Unit Minimum Maximum Minimum Maximum 6 STCK high to STFS wl high 1 71 4 79 1 5 4 2 ns 7 SRCK high to SRFS wl high 0 1 1 0 0 1 1 0 ns 8 STCK high to STFS wl low 3 08 5 24 2 7 4 6 ns 9 SRCK high to SRFS wl low 1 25 2 28 1 1 2 0 ns 10 STCK high to STXD valid from high 14 93 16 19 13 1 14 2 ns impedance 11a STCK high to STXD high 1 25 3 42 1 1 3 0 ns 11b STCK high to STXD low 2 51 3 99 2 2 3 5 ns 12 STCK high to STXD high impedance 12 43 14 59 10 9 12 8 ns 13 SRXD setup time before SRCK low 20 _ 17 5 _ ns 14 SRXD hold time after SRCK low 0 _ 0 _ ns External Clock Operation Port B Alternate Function 15 STCK SRCK clock period 92 8 81 4 i ns 16 STCK SRCK clock high period 27 1 _ 40 7 _ ns 17 STCK SRCK clock low period 61 1 40 7 ns 18 STCK high to STFS bl high _ 92 8 0 81 4 ns 19 SRCK high to SRFS bl high 92 8 0 81 4 ns 20 STCK high to STFS bl low 92 8 0 81 4 ns 21 SRCK high to SRFS bl low 92 8 0 81 4 ns 22 STCK high to STFS wl high _ 92 8 0 81 4 ns 23 SRCK high to SRFS wl high 92 8 0 81 4 ns 24 STCK high to STFS wl low i 92 8 0 81 4 ns 25 SRCK high to SRFS wl low 92 8 0 81 4 ns 26 STCK high to STXD valid from high 18 9 29 07 16 6 25 5 ns impedance 27a STCK high to STXD high 9 23 20 75 8 1 18 2 ns 27b
2. Figure 6 DTACK READ Cycle without DMA Table 14 Parameters for Read Cycle WSC 111111 DTACK_SEL 0 HKCL 96MHz 3 0 0 3 V Number Characteristic Unit Minimum Maximum 1 OE and EB assertion time See note 2 z ns 2 CS5 pulse width 3T _ ns 3 OE negated to address inactive 46 44 _ ns 4 DTACK asserted after CS5 asserted 1019T ns MC9328MX1 Advance Information Rev 4 24 Freescale Semiconductor Specifications Table 14 Parameters for Read Cycle WSC 111111 DTACK_SEL 0 HKCL 96MHz Continued 3 0 0 3 V Number Characteristic Unit Minimum Maximum 5 DTACK asserted to OE negated 3T 2 2 4T 6 86 ns 6 Data hold timing after OE negated 0 ns 7 Data ready after DTACK asserted 0 T ns 8 OE negated to CS negated 0 5T 0 24 0 5T 0 67 ns 9 OE negated after EB negated 0 5 1 5 ns 10 DTACK pulse width 1T 3T ns Note 0 DTACK assert means DTACK become low level 1 T is the system clock period For 96MHz system clock lt lt 2 OE and EB assertion time is programmable by OEA bit in CS5L register EB assertion in read cycle will occur only when EBC bit in CS5L register is clear 3 Address becomes valid and CS asserts at the start of read access cycle 4 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state 3 9 2 2 DTACK Read Cycle DMA Enabled Address CS5 programmab
3. Freescale Semiconductor 91 Specifications Table 43 Non Gated Clock Mode Parameters Continued Ref No Parameter Minimum Maximum Unit 5 csi pixclk low time 10 42 ns 6 csi pixclk frequency 0 48 MHz The limitation on pixel clock rise time fall time are not specified It should be calculated from the hold time and setup time according to max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time Ins setup time Ins positive duty cycle 10 2 5ns gt max rise time allowed 5 1 4ns negative duty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time max rise time allowed positive duty cycle setup time MC9328MX1 Advance Information Rev 4 92 Freescale Semiconductor Pin Out and Package Information xooJo 1sunq u SSA W9LrIVIX IN9FIVLX3 JLVISIYL LGGAV oyo FAMaS NDG LLYN oso SO 2S9 SSO 30 oV ISSA 1 ACE IV LX3 cadno OGL LOOd HOd O3ADOS ONDA od 1198 vg1 Sq 8a rS9 IV dd cdd Y ACE TV LX vas Odi 10S Oel ISHL 01009 LOOd LIMOAS ENOG
4. 312 5 usec Freq lock in time after FOL mode for non integer MF 250 280 300 Tref full reset does not include pre must lock in time 56 us Freq lock in time after FOL mode for non integer MF does not 220 250 270 Tref partial reset include pre multi lock in time 50 us Phase lock in time after FPL mode and integer MF does not include 300 350 400 Tref full reset pre multi lock in time 70 us Phase lock in time after FPL mode and integer MF does not include 270 320 370 Tref partial reset pre multi lock in time 64 us Freq jitter p p 0 005 0 01 2 T acr 0 0196 Phase jitter p p Integer MF FPL mode Vcc 1 8V _ 1 0 1 5 ns 10 Power supply voltage _ 1 7 _ 2 5 V Power dissipation FOL mode integer MF _ 4 mW fack 200 MHz Vcc 1 8V MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 19 Specifications 3 8 Reset Module The timing relationships of the Reset module with the POR and RESET IN are shown in Figure 3 and Figure 4 NOTE Be aware that NVDD must ramp up to at least 1 8V before QVDD is powered up to prevent forward biasing 90 AV 10 AVDD POR RESET POR Exact 300m7 lt gt 7 cycles CLK32 RESET_DRAM HRESET 14 cycles CLK32 RESET_OUT CLK32 HCLK G Figure 3 Timing Relationship with POR MC9328MX1 Advance Information Rev 4 20 Freescale
5. Freescale Semiconductor 81 Specifications 3 20 12C Module The C communication protocol consists of seven elements START Data Source Recipient Data Direction Slave Acknowledge Data Data Acknowledge and STOP SCL Figure 63 Definition of Bus Timing for PC Table 39 I C Bus Timing Parameter Table s 1 8V 0 10V 3 0V 0 30V f No Parameter Unit Minimum Maximum Minimum Maximum 1 Hold time repeated START condition 182 _ 160 _ ns 2 Data hold time 0 171 0 150 ns 3 Data setup time 11 4 10 ns 4 HIGH period of the SCL clock 80 _ 120 _ ns 5 LOW period of the SCL clock 480 320 _ ns 6 Setup time for STOP condition 182 4 _ 160 _ ns 3 21 Synchronous Serial Interface The MC9328MXI1 processor contains two identical SSI modules The transmit and receive sections of the SSI can be synchronous or asynchronous In synchronous mode the transmitter and the receiver use a common clock and frame synchronization signal In asynchronous mode the transmitter and receiver each have their own clock and frame synchronization signals Continuous or gated clock mode can be selected In continuous mode the clock runs continuously In gated clock mode the clock functions only during transmission The internal and external clock timing diagrams are shown in Figure 65 through Figure 67 on page 84 Normal or network mode can also be selected In normal mode the
6. dus IL Last Valid Data gt lt Write Data V1 Word Last Valid Data BCLK burst clock ADDR DATA LE Last Valid Addr Address V1 Y Address V1 2 Write Bx DN x 1 2 Half Word Y 2 2 Half Word Figure 13 WSC 1 WEA 1 WEN 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 33 Specifications dE WIPE E ae a cee hsel weim cs 3 Fan M htrans YNonseq X hwrite A Read haddr Y V1 ik hready A V weim_hready Ay BCLK burst clock Internal signals shown only for illustrative purposes ADDR Last Valid Addr Y Address V1 Y Address V1 2 ost F RAN Read A BR OE y l ON EBx EBC 0 EBx EBC 1 DATA ud 1 2 Half Word J MM 2 2 Half Word Note 1 x 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 14 WSC 3 OEA 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 34 Freescale Semiconductor Specifications hclk hsel weim cs 3 htrans hwrite haddr hready hwdata weim hrdata Internal signals shown only for illustrative purposes weim hready BCLK burst c
7. 0 10V 3 0V 0 30V N Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation Port C Primary Function 2 1 STCK SRCK clock period 95 _ 83 3 i ns 2 STCK high to STFS bl high 1 5 4 5 1 3 3 9 ns MC9328MX1 Advance Information Rev 4 84 Freescale Semiconductor Table 40 SSI 1 Timing Parameter Table Continued NOTES Ret 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 3 SRCK high to SRFS bl high 1 2 1 7 1 1 1 5 ns 4 STCK high to STFS bl low 2 5 4 3 2 2 3 8 ns 5 SRCK high to SRFS bl low 0 1 0 8 0 1 0 8 ns 6 STCK high to STFS wl high 1 48 4 45 1 3 3 9 ns 7 SRCK high to SRFS wl high3 1 1 1 5 1 1 1 5 ns 8 STCK high to STFS wl low 2 51 4 33 2 2 3 8 ns 9 SRCK high to SRFS wl low 0 1 0 8 0 1 0 8 ns 10 STCK high to STXD valid from high 14 25 15 73 12 5 13 8 ns impedance 11a STCK high to STXD high 0 91 3 08 0 8 2 7 ns 11b STCK high to STXD low 0 57 3 19 0 5 2 8 ns 12 STCK high to STXD high impedance 12 88 13 57 11 3 11 9 ns 13 SRXD setup time before SRCK low 21 1 _ 18 5 _ ns 14 SRXD hold time after SRCK low 0 _ 0 _ ns External Clock Operation Port C Primary Function 2 15 STCK SRCK clock period 92 8 _ 81 4 _ ns 16 STCK SRCK clock high period 27 1 _ 40 7 _ ns 17 STCK SRCK clock low period 61 1 40 7 _ ns
8. E CENE Z pi V1 X Fn Pope Lagt yal Y Write Data Word A Last Valid Data EE SN Last Valid Addr Address V1 Address V1 2 CS DATA RE Write e wf ERN 2 p Last Valid Data Y Write Data 1 2 Half Word A Write Data 2 2 Half Word Figure 24 WSC 2 CSA 1 WWS 1 A WORD E HALF MC9328MX1 Advance Information Rev 4 44 Freescale Semiconductor Internal signals shown only for illustrative purposes hclk hsel weim cs 4 htrans hwrite haddr hready hwdata weim hrdata Specifications E j js T Y Nonseq A Read INE JON fo Pu Last Valid Data Write Data A Last Valid Data gt lt Read Data weim_hready A f EE BCLK burst clock ADDR Last Valid Addr Address V1 Y Address V8 CS4 RW Read Write A LBA OE V EBx EBC 0 E EBx EBC 1 J DATA e Read Data DATA Last Valid Data hi Write Data Note 2 KEE Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 25 WSC 3 CSA 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor
9. EBx EBC 1 ITA PA PA PA 4 lan po JNonse ki Seq X Idle E Read Ta PS Read v y v4 Mr gt oO w o EHE e A A Le gt o w Ek uu KI ba oo X Last Valid Data Y V1 Word Y V2 Word Y V3 Word Y V4 Word i LO AL Va EF XJ A wa Bn A LR Last Valid Add Address V1 po Read Ault ag ECB DATA a Vi Word Y V2 Word X V3 Word X V4 Word n Note 1 x 20 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 29 WSC 2 SYNC 1 DOL 1 0 A WORD E WORD MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 49 Specifications Internal signals shown only for illustrative purposes hclk hsel weim cs 2 htrans hwrite haddr hready weim_hrdata weim_hready BCLK burst clock ADDR DES PA p Y Idle Last Valid Data ko V1 FERNI AV NE SAN AVAN Last Valid Y Address V1 M Address V2 EBx EBC2 0 EBx EBC2 1 ECB DATA a viva Y V1 2 2 END co Note 1 x
10. 45 P Specifications a A LA rooms hsel wem cs ans Ronseq Y ae Y sea Y mme N Read Read hadar Y V Y Y ve wes ON ETA ele weim hrdata Last Valid Data Y Read Data V1 Read Data V2 vein ready FN sct eusta LTA FEN ANAL ANAL ALAN ADDR Last Valid Y Address V1 Y Address V2 Internal signals shown only for illustrative purposes lt NO R W Read EBx EBC 0 EBx EBC 1 DATA e Read Data Y e Read Data Note 1 x 0 1 2or3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 26 WSC 2 OEA 2 CNC 3 BCM 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 46 Freescale Semiconductor hclk o o hsel weim cs 4 5 a o 2 htrans i D 3 5 hwrite gt o c haddr o E en o 2 hready o o hwdata 0 weim_hrdata weim_hready BCLK burst clock ADDR EBx EBC 0 Specifications WIRT AL Last Valid Data Write Data Y Last Valid Data M Read Data NL Last Valid Add Address V1 Y Address V8 lt CNC Write TC GIL CREE n EBx EBC 1 DATA
11. Transmit Ref No Parameter Minimum Typical Maximum Unit 1 FrameSync setup time relative to BT CLK rising edge _ 4 _ ns 2 FrameSync hold time relative to BT CLK rising edge 12 _ ns MC9328MX1 Advance Information Rev 4 58 Freescale Semiconductor Specifications Table 24 Motorola MC13180 Data Bus Timing Parameter Table Continued Ref No Parameter Minimum Typical Maximum Unit 3 Receive Data setup time relative to BT CLK rising edge _ 6 _ ns 4 Receive Data hold time relative to BT CLK rising edge 13 _ ns 5 Transmit Data setup time relative to RXTX_EN rising edge2 172 5 192 5 us 6 TX DATA period 1000 0 02 ns 7 BT CLK duty cycle 40 _ 60 96 8 Transmit Data hold time relative to RXTX EN falling edge 4 _ 10 us Please refer to Motorola 2 4 GHz RF Transceiver Module MC13180 Technical Data documentation 2 The setup and hold times of RX TX EN can be adjusted by programming Time A B register 0x00216050 and RF Status 0x0021605C registers SPI CLK BT13 SPI EN BT11 SPI DATA OUT BT12 WP SPI DATA IN BT4 Figure 39 SPI Interface Timing Diagram Using Motorola MC13180 Table 25 SPI Interface Timing Parameter Table Using Motorola MC13180 Ref No Parameter Minimum Maximum Unit 1 SPI EN setup time relative
12. on page 58 1 5 Product Documentation The following documents are required for a complete description of the MC9328MX1 and are necessary to design properly with the device Especially for those not familiar with the ARM920T processor or previous DragonBall products the following documents are helpful when used in conjunction with this manual ARM Architecture Reference Manual ARM Ltd order number ARM DDI 0100 ARM 9DTI Data Sheet Manual ARM Ltd order number ARM DDI 0029 ARM Technical Reference Manual ARM Ltd order number ARM DDI 0151C EMT Technical Reference Manual ARM Ltd order number DDI O157E MC9328MX1 Product Brief order number MC9328MX1P D MC9328MXIS Reference Manual order number MC9328MX1SRM D MC68VZ328 Product Brief order number MC68VZ328P D MC68VZ328 User s Manual order number MC68VZ328UM D MC68VZ328 User s Manual Addendum order number MC68VZ328UMAD D MC6858Z328 Product Brief order number MC68SZ328P D MC68SZ328 User 5 Manual order number MC68SZ328UM D The Motorola manuals are available on the Motorola Semiconductors Web site at http www motorola com semiconductors These documents may be downloaded directly from the Motorola Web site or printed versions may be ordered The ARM Ltd documentation is available from http www arm com MC9328MX1 Advance Information Rev 4 4 Freescale Semiconductor 1 6 Ordering Information Table 2 provides ordering information for the 256 lead mol
13. 1 2 or 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 22 WSC 2 WWS 2 WEA 1 WEN 2 A HALF E HALF MC9328MX1 Advance Information Rev 4 42 Freescale Semiconductor Specifications lt Read i lt sidiep gt Write j gt ra A RANA hsel weim cs 2 We ri M f M hians Nonseq Y Nonseq hwite Read J wid V pes EUM Cw we ON mon ATL Write Data Y Internal signals shown only for illustrative purposes hwdata Last Valid Data weim_hrdata Last Valid Data Y Read Data weim hready M f BCLK burst clock ADDR Last Valid AddrY Address V1 Y Address V8 cs2 i ANN RAW Read Write JE LBA A N a OE V EBx EBC 0 EBx EBC 1 DATA m Read Data DATA Last Valid Data Y Write Data Note 1 x 0 1 20r3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 23 WSC 2 WWS 1 WEA 1 WEN 2 EDC 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 43 Specifications Internal signals shown only for illustrative purposes hclk hsel weim cs 4 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK burst clock ADDR
14. 30 pF 3 18 SDRAM Memory Controller A write to an address within the memory region initiates the program sequence The first command issued to the SyncFlash is Load Command Register A 7 0 determine which operation the command performs For this write setup operation an address of 0x40 is hardware generated The bank and other address lines are driven with the address to be programmed The next command is Active which registers the row address and confirms the bank address The third command supplies the column address re confirms the bank address and supplies the data to be written SyncFlash does not support burst writes therefore a Burst Terminate command is not required A read to the memory region initiates the status read sequence The first command issued to the SyncFlash is the Load Command Register with A 7 0 set to 0x70 which corresponds to the Read Status Register operation The bank and other address lines are driven to the selected address The second command is Active which sets up the status register read The bank and row addresses are driven during this command The third command of the triplet is Read Bank and column addresses are driven on the address bus during this command Data is returned from memory on the low order 8 data bits following the CAS latency MC9328MX1 Advance Information Rev 4 74 Freescale Semiconductor Specifications Note CKE is high during the read write cycle Figure 57 SDRA
15. NSAC Data read access time 2 in CLK cycles NSAC 100 defined in CSD register bit 111 104 3 15 2 SDIO IRQ and ReadWait Service Handling In SDIO there is a 1 bit or 4 bit interrupt response from the SDIO peripheral card In 1 bit mode the interrupt response is simply that the SD DATII line is held low The SD DATT I1 line is not used as data in this mode The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed SD DATT 1 returns to its high level In 4 bit mode the interrupt is less simple The interrupt triggers at a particular period called the Interrupt Period during the data access and the controller must sample SD DATT 1 during this short period to determine the IRQ status of the attached card The interrupt period only happens at the boundary of each block 512 bytes JUUUU UU JOU t omo sii Content onokizzpis Response ley E DATI1 Interrupt Period Block Data IRQ Block Data IRQ For 4 bit a DATI1 Interrupt Period For 1 bit Figure 53 SDIO IRQ Timing Diagram ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer In this mode the block temporarily pauses the data transfer operation counter and related status yet keeps the clock running and allows the user to submit commands as normal After all commands are submitted the user can switch back to the data transfer operation and a
16. STCK high to STXD low 10 60 21 32 9 3 18 7 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 87 Specifications Table 41 SSI 2 Timing Parameter Table Continued Ret 1 8V 0 10V 3 0V 0 30V f No Parameter Unit Minimum Maximum Minimum Maximum 28 STCK high to STXD high impedance 17 90 29 75 15 7 26 1 ns 29 SRXD setup time before SRCK low 1 14 1 0 _ ns 30 SRXD hole time after SRCK low 0 i 0 ns Synchronous Internal Clock Operation Port B Alternate Function 31 SRXD setup before STCK falling 18 81 _ 16 5 _ ns 32 SRXD hold after STCK falling 0 _ 0 ns Synchronous External Clock Operation Port B Alternate Function 33 SRXD setup before STCK falling 1 14 1 0 ns 34 SRXD hold after STCK falling 0 2 0 _ ns 1 Allthe timings for both SSI modules are given for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures 2 There is one set of l O signals for the SSI2 module They are from Port C alternate function PC19 PC24 When SSI signals are configured as outputs they can be viewed at Port C alternate function a When SSI signals are configured as inputs
17. inner system and the application user programming Bus Clock CMD DAT Input CMD DAT Output Figure 47 Chip Select Read Cycle Timing Diagram Table 29 SDHC Bus Timing Parameter Table 1 8V 0 10V 3 0V 0 30V Ref N Parameter Unit Min Max Min Max 1 CLK frequency at Data transfer Mode PP 10 30 cards 0 25 5 0 25 5 MHz 2 CLK frequency at Identification Mode 0 400 0 400 KHz 3a Clock high time 10 30 cards 6 33 _ 10 50 ns 3b Clock low time 10 30 cards 15 75 10 50 ns 4a Clock fall time 10 30 cards 10 50 5 00 10 50 ns 4b Clock rise time 10 30 cards _ 14 67 6 67 10 50 ns 5a Input hold time2 10 30 cards 5 7 5 7 5 5 ns 5b Input setup time 10 30 cards 5 7 5 7 _ 5 5 ns 6a Output hold time 10 30 cards 5 7 5 7 5 5 ns 6b Output setup time 10 30 cards 5 7 5 7 _ 5 5 _ ns 7 Output delay time3 0 16 0 14 ns 1 C 100 pF 250 pF 10 30 cards 2 C 250 pF 21 cards 3 C lt 25 pF 1 card MC9328MX1 Advance Information Rev 4 64 Freescale Semiconductor Specifications 3 15 1 Command Response Timing on MMC SD Bus The card identification and card operation conditions timing are processed in open drain mode The card response to the host command starts after exactly Nip clock cycles For the card address assignment SET RCA is also processed in the open drain mode The minimum d
18. the SSI module selects the input based on FMCR register bits in the Clock controller module CRM By default the input is selected from Port C alternate function 3 bl bit length wl word length 3 22 CMOS Sensor Interface The CSI module consists of a control register to configure the interface timing a control register for statistic data generation a status register interface logic a 32 x 32 image data receive FIFO and a 16 x 32 statistic data FIFO 3 22 1 Gated Clock Mode Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 69 on page 89 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 42 on page 89 MC9328MX1 Advance Information Rev 4 88 Freescale Semiconductor 1 I VSYNC I I I I I I A 7 E I 4 1 I I I I l I N I I HSYNC I I 5 6 1 2 i I a i 1 gt I lt i i i PIXCLK 1 i I LI LI Li 1 Valid Data Valid Data Valid Data DATA 7 0 I 1 1 I 3 I 4 I I I I lt gt _ gt Figure 68 Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 1 1 7 1 I A 1 I I I I l L P I HSY
19. 18 STCK high to STFS bl high i 92 8 0 81 4 ns 19 SRCK high to SRFS bl high 92 8 0 81 4 ns 20 STCK high to STFS bl low 92 8 0 81 4 ns 21 SRCK high to SRFS bl low 92 8 0 81 4 ns 22 STCK high to STFS wl high 92 8 0 81 4 ns 23 SRCK high to SRFS wl high 92 8 0 81 4 ns 24 STCK high to STFS wl low 92 8 0 81 4 ns 25 SRCK high to SRFS wl low 92 8 0 81 4 ns 26 STCK high to STXD valid from high 18 01 28 16 15 8 24 7 ns impedance 27a STCK high to STXD high 8 98 18 13 7 0 15 9 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 85 Specifications Table 40 SSI 1 Timing Parameter Table Continued Ref 1 8V 0 10V 3 0V 0 30V NG Parameter Unit Minimum Maximum Minimum Maximum 27b STCK high to STXD low 9 12 18 24 8 0 16 0 ns 28 STCK high to STXD high impedance 18 47 28 5 16 2 25 0 ns 29 SRXD setup time before SRCK low 1 14 1 0 _ ns 30 SRXD hole time after SRCK low 0 0 ns Synchronous Internal Clock Operation Port C Primary Function 31 SRXD setup before STCK falling 15 4 _ 13 5 _ ns 32 SRXD hold after STCK falling 0 0 7 ns Synchronous External Clock Operation Port C Primary Function 33 SRXD setup before STCK falling 1 14 1 0 ns 34 SRXD hold after STCK falling 0 0 ns 1 All the timings for the SSI are given
20. SSI functions with one data word of T O per frame In network mode a frame can contain between 2 and 32 data words Network mode is typically used in star or ring time division multiplex networks with other processors or codecs allowing interface to time division multiplexed networks without additional logic Use of the gated clock is not allowed in network mode These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices MC9328MX1 Advance Information Rev 4 82 Freescale Semiconductor Specifications STCK Output STFS bl Output STFS wl Output STXD Output SRXD Input Note SRXD input in synchronous mode only Figure 64 SSI Transmitter Internal Clock Timing Diagram SRCK Output E TON gt m9 SRFS bl Output aa gt PORO SRFS wl Output 13 SRXD Input Figure 65 SSI Receiver Internal Clock Timing Diagram MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 83 Specifications STCK Input STFS bl Input STFS wl Input STXD Output SRXD Input Note SRXD Input in Synchronous mode only Figure 66 SSI Transmitter External Clock Timing Diagram SRCK Input SRFS bl Input NN l y SRFS wl Input SO SRXD Input Figure 67 SSI Receiver External Clock Timing Diagram Table 40 SSI 1 Timing Parameter Table Ref 1 8V
21. Signal Names and Descriptions Continued Signal Name Function Notes PS Control signal output for source driver Sharp panel dedicated signal CLS Start signal output for gate driver This signal is invert version of PS Sharp panel dedicated signal REV Signal for common electrode driving signal preparation Sharp panel dedicated signal SIM SIM CLK SIM Clock SIM RST SIM Reset SIM RX Receive Data SIM TX Transmit Data SIM PD Presence Detect Schmitt trigger input SIM SVEN SIM Vdd Enable SPI SPI1_MOSI Master Out Slave In SPI1_MISO Slave In Master Out SPI1_SS Slave Select Selectable polarity SPI1_SCLK Serial Clock SPI1_SPI_RDY Serial Data Ready SPI2_TXD SPI2 Master TxData Output This signal is multiplexed with a GPI O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table Refer to Chapter 16 Serial Peripheral Interface Modules SPI 1 and SPI 2 and Chapter 29 GPIO Module and I O Multiplexer IOMUX for information on how to bring this signal to the assigned pin SPI2 RXD SPI2 master RxData input This signal is multiplexed with a GPI O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table Refer to Chapter 16 Serial Peripheral Interface Modules SPI 1 and SPI 2 and Chapter 29 GPIO Module and I O Multiplexer IOMUX for information on how to
22. a ea goa 9a eso 093 6a ev d _ ANO aS IaL SNL ZA ISO W1OXId ISO cLOOH l13S3H 13838 NOA La ZIVd va ov Za old 493 vv N ps A _ a P NVIGN3 _ Sa Iso 9d ISO ONASA ISO ONASH ISO va ISO 919 NI 1L3S3H SVY OLVIN MH SSA 11908 9v Ha cta SV N A ISO za Iso La ISO 0d ISO MIOW ISO OWMd NIL MOL Svo SSA LAGAN vta Sia eld Zv 8V 1 SLAT LNOzUNL vial IGI ctal otal GAGAN GAGAN LAGAN SSA SSA LAGAN 210 6v 9Id OIV M SSA QadAo La sal al 9q1 SSA SSA LAGAN SSA LAGAN LAGAN 61d 841a LLY LV r ea sal sal val zal ay Sd LQGQAO SSA SSA LIGAN LIGAN oza viv ced CLV H LAT ONASA W1d ONASH d7 3O QOV LSVYLNOO S1O 618 ISOW LidS SL1O LLuvn X19 WIS Xd WIS Lea eza ved LIV SIV 9 tas dS 11981 LXd LAd AH cla olla OSIN tas S4AXL ISS GXL ZLEVN l1SH WIS 91v 6LV Sca ZeQ 8IV 3 Vou Xd GAd ON ON via ANE SS tldS LVGXL ISS S1H ZLEVN WA aasn elva as 9ca 82d Lev OZY 3 d _ _ 7 anasns u god vid ON ON ON 918 LIS AQUH las LdS LWaXY ISS OWA aasn odA aasn qasn N3AS WIS 63d oed cov a l _ E S816 ls _ alu SSA GaagAv ON GqQAdu18 818 QNOd3HIg axi tiuvn Sdxu ISS GOXu eiyvn ec1uvn AOU agsn dd NIS OLVA as red EzV 9 ON NIN WAY SSA LIG ZIg LLL MIOS Las WIOXL ISS W1IOXY ISS dA dasn 30 aasn XL WIS GNO GS LLVG as rev g ON din dAy vadAd ela Sia QdAN GXH LLEVAN SLY LLHYYN SSA vadAN 33v aasn SSA W1O as e1va GS SSA V 91 SL bi L eL LL OL 6 8 L 9 S r 4 L sjueuiufissy uld v58 LX
23. in Figure 2 TRACECLK Half Rate Clocking Mode Output Trace Port Valid Data E Valid Data OE X Man Figure 2 Trace Port Timing Diagram TRACECLK Table 10 Trace Port Timing Diagram Parameter Table 1 8V 0 10V 3 0V 0 30V Ref No Parameter I _ y uni Minimum Maximum Minimum Maximum 1 CLK frequency 0 85 0 100 MHz 2a Clock high time 1 3 2 xz ns 2b Clock low time 3 _ 2 ns 3a Clock rise time E 4 3 ns 3b Clock fall time 3 3 ns 4a Output hold time 2 28 _ 2 _ ns 4b Output setup time 3 42 3 _ ns MC9328MX1 Advance Information Rev 4 18 Freescale Semiconductor Specifications 3 7 DPLL Timing Specifications Parameters of the DPLL are given in Table 11 In this table T is a reference clock period after the pre divider and T is the output double clock period Table 11 DPLL Specifications Parameter Test Conditions Minimum Typical Maximum Unit Reference clock freq range Vcc 1 8V 5 _ 100 MHz Pre divider output clock Vcc 1 8V 5 _ 30 MHz freq range Double clock freq range Vcc 1 8V 80 _ 220 MHz Pre divider factor PD _ 1 _ 16 _ Total multiplication factor Includes both integer 5 _ 15 _ MF and fractional parts MF _ 5 _ 15 integer part MF Should be less than the 0 _ 1022 _ numerator denominator MF _ 1 _ 1023 _ denominator Pre multiplier lock in time
24. to rising edge of SPI CLK 15 _ ns 2 Transmit data delay time relative to rising edge of SPI_CLK 0 15 ns 3 Transmit data hold time relative to rising edge of SPI EN 0 15 ns 4 SPI CLK rise time 0 25 ns 5 SPI CLK fall time 0 25 ns 6 SPI EN hold time relative to falling edge of SPI CLK 15 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 59 Specifications Table 25 SPI Interface Timing Parameter Table Using Motorola MC13180 Continued Ref No Parameter Minimum Maximum Unit 7 Receive data setup time relative to falling edge of SPI CLK 15 _ ns 8 Receive data hold time relative to falling edge of SPI_CLK 15 _ ns 9 SPI CLK frequency 50 duty cycle required 20 MHz 1 The SPI CLK clock frequency and duty cycle setup and hold times of receive data can be set by programming SPI_Control 0x00216138 register together with system clock 3 13 SPI Timing Diagrams To use the internal transmit TX and receive RX data FIFOs when the SPI 1 module is configured as a master two control signals are used for data transfer rate control the SS signal output and the SPI_RDY signal input The SPI 1 Sample Period Control Register PERIODREG1 and the SPI 2 Sample Period Control Register PERIODREG2 can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2 When the SPI 1 module is configured as a slave the user can configure the SPI 1 Control Reg
25. which are multiplex with address signals A 10 1 MA 9 0 are selected on SDRAM SyncFlash cycles MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Signals and Connections Table 3 Signal Names and Descriptions Continued Signal Name Function Notes DQM 3 0 SDRAM data enable CSDO SDRAM SyncFlash Chip Select signal which is multiplexed with the CS2 signal These two signals are selectable by programming the system control register CSD1 SDRAM SyncFlash Chip Select signal which is multiplex with CS3 signal These two signals are selectable by programming the system control register By default CSD1 is selected so it can be used as SyncFlash boot chip select by properly configuring BOOT 3 0 input pins RAS SDRAM SyncFlash Row Address Select signal CAS SDRAM SyncFlash Column Address Select signal SDWE SDRAM SyncFlash Write Enable signal SDCKEO SDRAM SyncFlash Clock Enable O SDCKE1 SDRAM SyncFlash Clock Enable 1 SDCLK SDRAM SyncFlash Clock RESET SF SyncFlash Reset Clocks and Resets EXTAL16M Crystal input 4 MHz to 16 MHz or a 16 MHz oscillator input when internal oscillator circuit is shut down XTAL16M Crystal output EXTAL32K 32 kHz crystal input XTAL32K 32 kHz crystal output CLKO Clock Out signal selected from internal clock signals Please refer to clock controller for internal clock selection RESET_
26. 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register ea Y Figure 30 WSC 2 SYNC 1 DOL 1 0 A WORD E HALF MC9328MX1 Advance Information Rev 4 50 Freescale Semiconductor Specifications hclk s i m pos AAWON jep bia gt hsel weim cs 2 m htrans yNon XSeq Y Idle hwrite Rea Read haddr Yvi Y Y v2 hready a weim hrdata Last Valid Data ko word MN V2 Word weim hready I h A BOLK ra PPP mm ie ia B Internal signals shown only for illustrative purposes ADDR Last Y Address V1 CS2 AN ZEN RAN Read Ny EBx EBC 0 EBx EBC 1 DATA V1 1 2 vi 2 2 Y v21 2 V2 2 2 Note 1 x 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 31 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 51 Specifications Internal signals shown only for illustrative purposes AO AAA a hsel weim cs 2 p 1 N htrans on X Seq Y Idle hwrite VWea Re
27. 2 26668334 Home Page www freescale com MC9328MX1 D Rev 4 08 2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to sup
28. 22 Freescale Semiconductor Table 13 EIM Bus Timing Parameter Table Continued Specifications 1 8 0 10V 3 0 0 3V Ref No Parameter Unit Min Typical Max Min Typical Max 1b Clock fall to address invalid 1 55 2 48 5 69 1 5 2 4 5 5 ns 2a Clock fall to chip select valid 2 69 3 31 7 87 2 6 3 2 7 6 ns 2b Clock fall to chip select invalid 1 55 2 48 6 31 1 5 2 4 6 1 ns 3a Clock fall to Read Write Valid 1 35 2 79 6 52 1 3 2 7 6 3 ns 3b Clock fall to Read Write Invalid 1 86 2 59 6 11 1 8 2 5 5 9 ns 4a Clock rise to Output Enable Valid 2 32 2 62 6 85 233 2 6 6 8 ns 4b Clock rise to Output Enable Invalid 2 11 2 52 6 55 2 1 2 5 6 5 ns 4c Clock fall to Output Enable Valid 2 38 2 69 7 04 2 3 2 6 6 8 ns 4d Clock fall to Output Enable Invalid 2 17 2 59 6 73 2 1 2 5 6 5 ns ba Clock rise to Enable Bytes Valid 1 91 2 52 5 54 1 9 2 5 5 5 ns 5b Clock rise to Enable Bytes Invalid 1 81 2 42 5 24 1 8 2 4 5 2 ns 5c Clock fall to Enable Bytes Valid 1 97 2 59 5 69 1 9 2 5 5 5 ns 5d Clock fall to Enable Bytes Invalid 1 76 2 48 5 38 1 7 2 4 5 2 ns 6a Clock fall to Load Burst Address Valid 2 07 2 79 6 73 2 0 2 7 6 5 ns 6b Clock fall to Load Burst Address Invalid 1 97 2 79 6 83 1 9 2 7 6 6 ns 6c Clock rise to Load Burst Address Invalid 1 91 2 62 6 45 1 9 2 6 6 4 ns 7a Clock rise to Burst Clock rise 1 61 2 62 5 64 1 6 2 6
29. 5 6 ns 7b Clock rise to Burst Clock fall 1 61 2 62 5 84 1 6 2 6 5 8 ns 7C Clock fall to Burst Clock rise 1 55 2 48 5 59 1 5 2 4 5 4 ns 7d Clock fall to Burst Clock fall 1 55 2 59 5 80 1 5 2 5 5 6 ns 8a Read Data setup time 5 54 _ _ 5 5 _ _ ns 8b Read Data hold time 0 0 _ ns 9a Clock rise to Write Data Valid 1 81 2 72 6 85 1 8 2 7 6 8 ns 9b Clock fall to Write Data Invalid 1 45 2 48 5 69 1 4 2 4 5 5 ns 9c Clock rise to Write Data Invalid 1 63 1 62 _ ns 10a DTACK setup time 2 52 2 5 ns 1 Clock refers to the system clock signal HCLK generated from the System DPLL MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 23 Specifications 3 9 1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal When using the external DTACK signal as a data acknowledge signal the bus time out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement 3 9 2 DTACK Signal Timing Figure 6 through Figure 9 show the access cycle timing used by chip select 5 The signal values and units of measure for this figure are found in the associated tables 3 9 2 1 DTACK READ Cycle without DMA Address CS5 gt programmable EB min Ons DTACK Databus input to MX1
30. AX T5 T6 T7 T9 T10 Ts T3 VSYN pulse width T2 VWIDTH T2 Ts T4 End of VSYN to beginning of OE 2 VWAIT2 T2 Ts T5 HSYN pulse width 1 HWIDTH 1 Ts T6 End of HSYN to beginning to T9 1 HWAIT2 1 Ts T7 End of OE to beginning of HSYN 1 HWAIT1 1 Ts T8 SCLK to valid LD data 3 3 ns TO End of HSYN idle2 to VSYN edge 2 2 Ts for non display region TO End of HSYN idle2 to VSYN edge 1 1 Ts for Display region T10 VSYN to OE active Sharp 0 1 1 Ts when VWAIT2 0 T10 VSYN to OE active Sharp 1 2 2 Ts when VWAIT2 0 Note Ts is the SCLK period which equals LCDC CLK PCD 1 Normally LCDC CLK 15ns VSYN HSYN and OE can be programmed as active high or active low In Figure 46 all 3 signals are active low The polarity of SCLK and LD 15 0 can also be programmed SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period In Figure 46 SCLK is always active For T9 non display region VSYN is non active It is used as an reference XMAX is defined in pixels MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 63 Specifications 3 15 Multimedia Card Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus DMA access internal MMC SD module data bus and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content empty or full FIFO address and byte block counters for the MMC SD module
31. D VM Input Figure 61 USB Device Timing Diagram for Data Transfer to USB Transceiver TX Table 37 USB Device Timing Parameter Table for Data Transfer to USB Transceiver TX Ref No Parameter Minimum Maximum Unit 1 tRoE vpo USBD ROE active to USBD_VPO low 83 14 83 47 ns 2 troE vmo USBD_ROE active to USBD_VMO high 81 55 81 98 ns 3 typo Roe USBD_VPO high to USBD_ROE deactivated 83 54 83 80 ns 4 tvmo Rog USBD_VMO low to USBD ROE deactivated includes SEO 248 90 249 13 ns 5 tegopr SEO interval of EOP 160 00 175 00 ns MC9328MX1 Advance Information Rev 4 80 Freescale Semiconductor Specifications Table 37 USB Device Timing Parameter Table for Data Transfer to USB Transceiver TX Continued Ref No Parameter Minimum Maximum Unit 6 tpeRiop Data transfer rate 11 97 12 08 Mb s USBD AFE n x Output N USBD_ROE g Y Output USBD_VPO Output USBD_VMO Output USBD_SUSPND Output N USBD RCV Input rEoPR ji USBD VP N NUN PE Input USBD_VM Input Ks Figure 62 USB Device Timing Diagram for Data Transfer from USB Transceiver RX Table 38 USB Device Timing Parameter Table for Data Transfer from USB Transceiver RX No Parameter Minimum Maximum Unit 1 treoPr Receiver SEO interval of EOP 82 ns MC9328MX1 Advance Information Rev 4
32. DATA neo jy p Data Last Valid Data Y Write Data Note 1 x 0 1 20r3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 27 WSC 2 OEA 2 WEA 1 WEN 2 CNC 3 A HALF E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 47 Specifications Internal signals shown only for illustrative purposes hclk hsel weim cs 2 htrans hwrite haddr hready weim hrdata weim hready BCLK burst clock ADDR CS2 RW OE EBx EBC 0 EBx EBC 1 ECB DATA Note 1 x a eA VJ Idle En no ARR TUS FEE NUR X Last Valid Addy Address V1 Address V5 V Read 24 EE vi word Yo word IK vs word Ye won 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 28 WSC 3 SYNC 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 48 Freescale Semiconductor Specifications hclk a o 2 hsel weim cs 2 a eo 2 ki htrans I 3 S hwrite gt c E haddr foi a 2 S hready a T c A o weim hrdata weim hready BCLK burst clock ADDR EBx EBC 0
33. Figure 52 shows the different scenarios on the bus Buiuuuue165oid snq seuo2eq peg 4o0 q ejep 1se Jejje peAledEe UCISSIWSUBL dois HEREREREEREREERERRERRRH IHEEHHHEHHR ie Guluwel60 d Asnq seuio2eq peg 490Jd 81ep ISV 1 1Je pA UOISSIWSUBL dois p1e0 ay WOU JejsueJ SNIS Jyo Buunp uoissiusuen dois sOy ey WOUJ JejsueJ eyep Guunp uoissiuisueJ dois PPPEPPPPPPPPPEPPPPRPPPPPRPR ee PS Av zeep eo ISIS PEER va lt Buruwebod si peg sng eyed IMM PPPEPPPPPPPPPERPPPRPRPPPRPR o eo SPREE BEER wa oT e TE pueuJulo2 1S0H Pep ou wewoo rs ppplouo mewoo ifj ano esuodsay pre lt x puewwog ISOH sajo o HON Figure 52 Stop Transmission During Different Scenarios MC9328MX1 Advance Information Rev 4 69 Freescale Semiconductor Specifications Table 31 Timing Values for Figure 48 through Figure 52 Parameter Symbol Minimum Maximum Unit MMC SD bus clock CLK All values are referred to minimum VIH and maximum VIL Command response cycle NCR 2 64 Clock cycles Identification response cycle NID 5 5 Clock cycles Access time delay cycle NAC 2 TAAC NSAC Clock cycles Command read cycle NRC 8 Clock cycles Command command cycle NCC 8 Clock cycles Command write cycle NWR 2 Clock cycles Stop transmission cycle NST 2 2 Clock cycles TAAC Data read access time 1 defined in CSD register bit 119 112
34. Freescale Semiconductor Specifications hee A af ee pu ee ae z hsel weim cs 2 A htrans Nonseq X hwrite Write X Internal signals shown only for illustrative purposes haddr i Vi X hready Jo IN je 73 AM hwdata Lagt Valid Y Write Data V1 Word JUnknown weim hrdata Last Valid Data weim hready NI BCLK burst clock ADDR Last Valid Addr Address V1 X Address V1 2 x RAN Write poo LBA N OE DATA Last Valid Data X 1 2 Half Word X 2 2 Half Word Figure 21 WSC 1 WWS 2 WEA 1 WEN 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 41 Specifications a FN p ie ed s sel weim esf NE htrans YNonseq Y YNonseq Y hwrite Read J Write V wes DO Y C Y wey ON im pu Write Data hwdata Last Valid Data Internal signals shown only for illustrative purposes weim hrdata Last Valid Data X Read Data weim hready a M NN MEN BCLK burst clock ADDR Last Valid Addr Address V1 Y Address V8 os F RAN Read Write E EBx EBC 0 F EBx EBC 1 Y DATA e Read Data DATA Last Valid Data X Wirite Data Note 1 x 2 0
35. IN Master Reset External active low Schmitt trigger input signal When this signal goes active all modules except the reset module and the clock control module are reset RESET_OUT Reset Out Internal active low output signal from the Watchdog Timer module and is asserted from the following sources Power on reset External reset RESET_IN and Watchdog time out POR Power On Reset Internal active high Schmitt trigger input signal The POR signal is normally generated by an external RC circuit designed to detect a power up event JTAG TRST Test Reset Pin External active low signal used to asynchronously initialize the JTAG controller TDO Serial Output for test instructions and data Changes on the falling edge of TCK TDI Serial Input for test instructions and data Sampled on the rising edge of TCK MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Signals and Connections Table 3 Signal Names and Descriptions Continued Signal Name Function Notes TCK Test Clock to synchronize test logic and control register access through the JTAG port TMS Test Mode Select to sequence the JTAG test controller s state machine Sampled on the rising edge of TCK System BIG ENDIAN BIG_ENDIAN T his signal determines the memory endian configuration BIG ENDIAN is a static pin to inner module If the pin is driven logic high the memory system is configured into big endian If it i
36. IN N MAL MS_SCLKO lt EN a LG LE MS BS MS SDIO output x P4 MS SDIO input RED bit 0 GH m MS SDIO input X RED bit 1 Figure 55 MSHC Signal Timing Diagram Table 32 MSHC Signal Timing Parameter Table Ref No Parameter Minimum Maximum Unit 1 MS SCLKI frequency _ 25 MHz 2 MS_SCLKI high pulse width 20 _ ns 3 MS_SCLKI low pulse width 20 _ ns 4 MS SCLKI rise time 3 ns 5 MS SCLKI fall time 3 ns 6 MS SCLKO frequency 25 MHz 7 MS SCLKO high pulse width 20 ns 8 MS_SCLKO low pulse width 15 ns 9 MS_SCLKO rise time 5 ns 10 MS SCLKO fall time 5 ns MC9328MX1 Advance Information Rev 4 72 Freescale Semiconductor Table 32 MSHC Signal Timing Parameter Table Continued Specifications Ref No Parameter Minimum Maximum Unit 11 MS BS delay time 3 ns 12 MS SDIO output delay time 3 ns 13 MS SDIO input setup time for MS SCLKO rising edge RED bit 0 3 18 _ ns 14 MS SDIO input hold time for MS_SCLKO rising edge RED bit 0 0 ns 15 MS_SDIO input setup time for MS_SCLKO falling edge RED bit 1 23 ns 16 MS SDIO input hold time for MS_SCLKO falling edge RED bit 1 0 _ ns 1 Loading capacitor condition is less than or equal to 30pF 2 An external resistor 100 200 ohm should be inserted in seri
37. INSZEGOIN tr lqe L uoneunoju abeyoeg pue 1nQ uid MC9328MX1 Advance Information Rev 4 93 Freescale Semiconductor Pin Out and Package Information 4 4 MAPBGA Package Dimensions Figure 72 illustrates the MAPBGA 14 mm x 14 mm x 1 30 mm package which has 0 8 mm spacing between the pads The device designator for the MAPBGA package is VH B 0 1 4 Z 0 2 SEATING PLANE T R P N M L K J G F E D 6 Ak S 8 12345578910 12 14 16 I SH Al INDEX 256X DET A PRENDE SIDE VEN BOTTOM VIEW DEA NOTES 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A DATUM A THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS Figure 72 MC9328MX1 MAPBGA Mechanical Drawing MC9328MX1 Advance Information Rev 4 94 Freescale Semiconductor NOTES MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 95 How to Reach Us USA Europe Locations Not Listed Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 Asia Pacific Freescale Semiconductor Hong Kong Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 85
38. JAM CSS 328 ELIT Freescale Semiconductor MC9328MX1 D Advance Information Rev 4 08 2004 MC9328MX1 Package Information Plastic Package MC9328MX1 MAPBGA 256 Ordering Information See Table 2 on page 5 1 Introduction omens 1 Introduction 1 Motorola s 1 MX family of microprocessors has 2 Signals and Connections 6 demonstrated leadership in the portable handheld market 3 Specifications 14 Continuing this legacy the i MX series provides a leap in 4 Pin Out and Package Information 93 performance with an ARM9TM microprocessor core and Contact Information Last Page highly integrated system functions The 1 MX products specifically address the requirements of the personal portable product market by providing intelligent integrated peripherals an advanced processor core and power management capabilities The new MC9328MX1 features the advanced and power efficient ARM920T M core that operates at speeds up to 200 MHz Integrated modules which include an LCD controller static RAM USB support an A D converter with touch panel control and an MMC SD host controller support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience In addition the MC9328MX I is the first Bluetooth technology ready applications processor It is packaged in a 256 pin Mold Array Pro
39. M SyncFlash Read Cycle Timing Diagram Table 34 SDRAM Timing Parameter Table 1 8V 3 0V Ref NS Parameter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 2 67 4 ns 2 SDRAM clock low level width 6 _ 4 ns 3 SDRAM clock cycle time 10 4 10 _ ns 3S CS RAS CAS WE DQM setup time 3 42 _ 3 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Specifications Table 34 SDRAM Timing Parameter Table Continued Ret 1 8V 3 0V f No Parameter Unit Minimum Maximum Minimum Maximum 3H CS RAS CAS WE DQM hold time 2 28 2 _ ns 4S Address setup time 3 42 _ 3 _ ns 4H Address hold time 2 28 _ 2 ns 5 SDRAM access time CL 3 6 84 _ 6 ns 5 SDRAM access time CL 2 6 84 _ 6 ns 5 SDRAM access time CL 1 22 _ 22 ns 6 Data out hold time 2 85 _ 2 5 ns 7 Data out high impedance time CL 3 6 84 6 ns 7 Data out high impedance time CL 2 6 84 x 6 ns 7 Data out high impedance time CL 1 _ 22 22 ns 8 Active to read write command period RC 1 taco _ taco ns tacp SDRAM clock cycle time The tacp setting can be found in the MC9328MX1 reference manual MC9328MX1 Advance Information Rev 4 76 Freescale Semiconductor Specifications ADDR 7 E Figure 58 SDRAM SyncFlash Write Cycle Timing Diagram Tabl
40. NC l 5 6 I L o I i I I I PIXCLK I i I I i I 1 I DATA 7 0 1 I I I I 3 4 1 1 I I py Figure 69 Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 42 Gated Clock Mode Timing Parameters Ref No Parameter Minimum Maximum Unit 1 csi vsync to csi hsync 9 TucLk a ns 2 csi hsync to csi pixclk 3 Tp 2 3 ns 3 csi d setup time 1 _ ns MC9328MX1 Advance Information Rev 4 Specifications Freescale Semiconductor 89 Specifications Table 42 Gated Clock Mode Timing Parameters Continued Ref No Parameter Minimum Maximum Unit 4 csi d hold time 1 ns 5 csi pixclk high time 10 42 ns 6 csi_pixclk low time 10 42 _ ns 7 csi_pixclk frequency 0 48 MHz The limitation on pixel clock rise time fall time are not specified It should be calculated from the hold time and setup time according to Rising edge latch data max rise time allowed positive duty cycle hold time max fall time allowed negative duty cycle setup time In most of case duty cycle is 50 50 therefore max rise time period 2 hold time max fall time period 2 setup time For example Given pixel clock period 10ns duty cycle 50 50 hold time Ins setup time Ins positive duty cycle 10 2 5ns gt max rise time allowed 5 1 4ns negative d
41. Ring Indicator UART2 DCD Data Carrier Detect UART2 DTR Data Terminal Ready UART3 RXD Receive Data UART3 TXD Transmit Data UART3 RTS Request to Send UART3 CTS Clear to Send UART3 DSR Data Set Ready UART3 RI Ring Indicator UART3 DCD Data Carrier Detect UART3 DTR Data Terminal Ready Serial Audio Ports SSI configurable to I2S protocol SSH TXDAT TxD SSI1_RXDAT RxD SSI1_TXCLK Transmit Serial Clock SSI1_RXCLK Receive Serial Clock SSI1_TXFS Transmit Frame Sync SSI1_RXFS Receive Frame Sync SSI2_TXDAT TxD SSI2_RXDAT RxD MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 11 Signals and Connections Table 3 Signal Names and Descriptions Continued Signal Name Function Notes SSI2 TXCLK Transmit Serial Clock SSI2 RXCLK Receive Serial Clock SSI2 TXFS Transmit Frame Sync SSI2 RXFS Receive Frame Sync PC 12C_SCL 12C Clock I2C SDA 12C Data PWM PWMO PWM Output ASP UIN Positive U analog input for low voltage temperature measurement UIP Negative U analog input for low voltage temperature measurement PX1 Positive pen X analog input PY1 Positive pen Y analog input PX2 Negative pen X analog input PY2 Negative pen Y analog input R1A Positive resistance input a R1B Positive resistance input b R2A Negative resistance input a R2B Negative resistance input b RVP Positive reference for pen ADC RVM Ne
42. Semiconductor Specifications lt RESET_IN A 14 cycles CLK32 HRESET RESET OUT pup 4 CLK32 IIIIIAIIIII e IIGIIIIIIIIIIIIIIIIIIIIIWE scd Mmmm NE Figure 4 Timing Relationship with RESET_IN Table 12 Reset Module Timing Parameter Table Ref 1 8V 0 10V 3 0V 0 30V Parameter Unit Min Max Min Max 1 Width of input POWER_ON_RESET note note gt 2 Width of internal POWER_ON_RESET 300 300 300 300 ms 9600 CLK32 at 32 KHz 3 7K to 32K cycle stretcher for SDRAM reset 7 7 7 7 Cycles of CLK32 4 14K to 32K cycle stretcher for internal system reset 14 14 14 14 Cycles of HRESERT and output reset at pin RESET_OUT CLK32 5 Width of external hard reset RESET_IN 4 _ 4 Cycles of CLK32 6 4K to 32K cycle qualifier 4 4 4 4 Cycles of CLK32 POR width is dependent on the 32 or 32 768 kHz crystal oscillator start up time Design margin should allow for crystal tolerance i MX chip variations temperature impact and supply voltage influence Through the process of supplying crystals for use with CMOS oscillators crystal manufacturers have developed a working knowledge of start up time of their crystals Typically start up times range from 400 ms to 1 2 seconds for this type of crystal If an external stable clock source already running is used instead of a crystal the width of POR should be ignored in calculating timing for the start up proc
43. Specifications hclk hsel_weim_cs 2 htrans Nonseq TS Eu EU j gt lt hwrite A Read haddr X V1 hready weim hready A ue l Internal signals shown only for illustrative purposes BCLK burst clock ADDR Last Valid Addr Y Address V1 Y Address V1 2 CS2 RAN Read a y p EBx EBC 0 EBx EBC 1 DATA 2 Half Word P 2 Half Word LL Note 1 x 20 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 19 WSC 3 OEA 2 OEN 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 39 Specifications Internal signals shown only for illustrative purposes hclk hsel weim cs 2 htrans hwrite haddr hready hwdata weim hrdata weim hready BCLK burst clock ADDR CS2 DATA as ae Oe SERE a Baa Write Data V1 Word X Unknown Last Valid Data Last Valid Addr Y Address V1 X Address V1 2 Write 11 Last Valid Data Y 1 2 Half Word 2 2 Half Word Figure 20 WSC 2 WWS 1 WEA 1 WEN 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 40
44. a Last Valid Data Y Write Data V1 Y Unknown e Y weim_hrdata Last Valid Data 3 c weim_hready BCLK burst clock ADDR Last Valid Address V1 Write O a s T gt lt a DATA Last Valid Data Y Write Data V1 Figure 11 WSC 1 WEA 1 WEN 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 31 Specifications hclk j hsel weim cs 0 htrans Y Nonseq hwrite V Read haddr X vi wa Y o NL weim hrdata Last Valid Data AS V1 Word EE UN E S NOM ae Internal signals shown only for illustrative purposes weim hready BCLK burst clock ADDR Last Valid Addr Address V1 Y Address V1 2 em a RAN Read LBA D a F AES E 8 EBx EBC 0 EBx EBC 1 DATA 1 2 Half Word 2 2 Half Word Note 1 x 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 12 WSC 1 OEA 1 A WORD E HALF MC9328MX1 Advance Information Rev 4 32 Freescale Semiconductor Specifications hclk hsel weim cs 0 htrans hwrite haddr hready hwdata Internal signals shown only for illustrative purposes weim_hrdata weim_hready ES PA
45. ad hadar Y vi Y y v2 maa VON iT weim_hrdata Last Valid Data EE v wo v2 Word ae EN BOLK burst clock RA SE e ie eh ES ADDR Last Address V1 CS2 NN RW Read LBA 7 OE m EBx EBC 0 y pe EBx EBC 1 co y Wa m NEED v ee vx Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 32 WSC 7 OEA 8 SYNC 1 DOL 1 BCD 1 BCS 1 A WORD E HALF MC9328MX1 Advance Information Rev 4 52 Freescale Semiconductor Specifications LSCLK ZIEL WEM NEL NN LD 15 0 4 je Figure 33 SCLK to LD Timing Diagram Table 18 LCDC SCLK Timing 3 0 0 3V Num Characteristic n gt Unit Minimum Maximum 1 SCLK to LD valid 3 ns 3 9 4 Non TFT Panel Timing T1 VSYN TE T2 73 XMAX 74 T2 lt m a gt pa pap HSYN SCLK I x Ts LD 15 0 y A X Figure 34 Non TFT Panel Timing Table 19 Non TFT Panel Timing Diagram Symbol Parameter Allowed kn Minimum Actual Value Unit T1 HSYN to VSYN delay 0 HWAIT2 2 Tpix T2 HSYN pulse width 0 HWIDTH 1 Tpix T3 VSYN to SCLK _ 0 lt T3 lt Ts _ T4 SCLK to HSYN 0 HWAIT1 1 Tpix MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 53 p Specifications VSYN HSYN and SCLK can be programmed as active high or active low In the above timing diagram al
46. als Asserted means that a discrete signal is in active logic state Active low signals change from logic level one to logic level zero Active high signals change from logic level zero to logic level one Negated means that an asserted discrete signal changes logic state Active low signals change from logic level zero to logic level one Active high signals change from logic level one to logic level zero LSB means least significant bit or bits and MSB means most significant bit or bits References to low and high bytes or words are spelled out Numbers preceded by a percent sign are binary Numbers preceded by a dollar sign or Ox are hexadecimal MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Introduction 1 2 Features To support a wide variety of applications the MC9328MX1 provides a robust array of features including the following ARM920T Microprocessor Core AHB to IP Bus Interfaces AIPIs External Interface Module EIM SDRAM Controller SDRAMC e DPLL Clock and Power Control Module Three Universal Asynchronous Receiver Transmitters UART 1 UART 2 and UART 3 Two Serial Peripheral Interfaces SPI Two General Purpose 32 bit Counters Timers Watchdog Timer Real Time Clock Sampling Timer RTC LCD Controller LCDC Pulse Width Modulation PWM Module Universal Serial Bus USB Device Multimedia Card and Secure Digital MMC SD Host Controller Mod
47. bring this signal to the assigned pin SPI2 SS SPI2 Slave Select This signal is multiplexed with a GPI O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table Refer to Chapter 16 Serial Peripheral Interface Modules SPI 1 and SPI 2 and Chapter 29 GPIO Module and I O Multiplexer IOMUX for information on how to bring this signal to the assigned pin SPI2 SCLK SPI2 Serial Clock This signal is multiplexed with a GPI O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table Refer to Chapter 16 Serial Peripheral Interface Modules SPI 1 and SPI 2 and Chapter 29 GPIO Module and I O Multiplexer IOMUX for information on how to bring this signal to the assigned pin MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Signals and Connections Table 3 Signal Names and Descriptions Continued Signal Name Function Notes General Purpose Timers TIN Timer Input Capture or Timer Input Clock The signal on this input is applied to both timers simultaneously TMR2OUT Timer 2 Output USB Device USBD VMO USB Minus Output USBD VPO USB Plus Output USBD VM USB Minus Input USBD VP USB Plus Input USBD SUSPND USB Suspend Output USBD RCV USB RxD USBD OE USB OE USBD AFE USB Analog Front End Enable Secure Di
48. cess Ball Grid Array MAPBGA Figure 1 on page 2 shows the functional block diagram of the MC9328MX1 a L a Li E3 a ARM Freescale Semiconductor Inc 2004 All rights reserved m lt e This document contains information on a new product Specifications and information herein are H H Ti subject to change without notice z freescale semiconductor Introduction System Control Standard JTAG ICE Poner can System 1 0 Bootstrap Control DPLLx2 GPIO Connectivity MC9328MX1 PWM Memory Stick CPU Complex Host Controller ARM9TDMI sez menu Waichdog Accelerator 2 SSI I S 1 amp 2 AIPI1 VMMU ER kle 5 DMAC Bus USB Device AIPI 2 11 Chnl Human Interface SmartCard I F Analog Signal Processor Bluetooth EM eSRAM SDRAMC LCD Controller Figure 1 MC9328MX1 Functional Block Diagram 1 1 Conventions This document uses the following conventions OVERBAR is used to indicate a signal that is active when pulled low for example RESET Logic level one is a voltage that corresponds to Boolean true 1 state Logic level zero is a voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one To clear a bit or bits means to establish logic level zero A signal is an electronic construct whose state conveys or changes in state convey information A pin is an external physical connection The same pin can be used to connect a number of sign
49. cifications Freescale Semiconductor 55 Specifications Table 23 ASP Touch Panel Controller Electrical Spec Parameter Minimum Type Maximum Unit Offset 32768 Offset Error _ _ 8199 _ Gain _ 13 65 mv Gain Error 33 _ DNL 8 9 _ Bits INL _ 0 _ Bits Accuracy without missing code 8 9 Bits Operating Voltage Range Pen _ QVDD mV Operating Voltage Range U Negative QVDD _ QVDD mV On resistance of switches SW 8 1 10 Ohm Note that QVDD should be 1800mV 3 11 2 Gain Calculations The ideal mapping of input voltage to output digital sample is defined as follows 2400 1800 2400 Figure 35 Gain Calculations In general the mapping function is S G V C Where V is input S is output G is the slope and C is the y intercept Nominal Gain Gp 65535 4800 13 65m V Nominal Offset Cy 65535 2 32767 MC9328MX1 Advance Information Rev 4 Vi 56 Freescale Semiconductor Specifications 3 11 3 Offset Calculations The ideal mapping of input voltage to output digital sample is defined as Sample 65535 GO 2400 1800 2400 Figure 36 Offset Calculations In general the mapping function is S G V C Where V is input S is output G is the slope and C is the y intercept Nominal Gain Go 65535 4800 13 65mV Nominal Offset Co 65535 2 32767 3 11 4 Gain Error Calculations Gain error calculatio
50. d array process ball grid array MAPBGA package Introduction Table 2 MC9328MX1 Ordering Information Package Type Frequency Temperature Solderball Type Order Number 256 lead MAPBGA 200 MHz 0 C to 70 C Standard MC9328MX1VH20 R2 256 lead MAPBGA 200 MHz 0 C to 70 C Pb free MC9328MX1VM20 R2 256 lead MAPBGA 200MHz 30 C to 70 C Standard MC9328MX1DVH20 R2 256 lead MAPBGA 200MHz 30 C to 70 C Pb free MC9328MX1DVM20 R2 256 lead MAPBGA 150 MHz 40 C to 85 C Standard MC9328MX1CVH15 R2 256 lead MAPBGA 150MHz 40 C to 85 C Pb free MC9328MX1CVM15 R2 MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Signals and Connections 2 Signals and Connections Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins The signals are grouped by the internal module that they are connected to Table 3 Signal Names and Descriptions Signal Name Function Notes External Bus Chip Select EIM A 24 0 Address bus signals D 31 0 Data bus signals EBO MSB Byte Strobe Active low external enable byte signal that controls D 31 24 EB1 Byte Strobe Active low external enable byte signal that controls D 23 16 EB2 Byte Strobe Active low external enable byte signal that controls D 15 8 EB3 LSB Byte Strobe Active low external enable byte signal that con
51. data weim hrdata weim hready BCLK burst clock ADDR Specifications CANAL CESR i m Y Nonseq Y Write ER WO A a s Lag yan X Write Data V1 Word Y Last Valid Data Na Address V1 Address V1 2 Last Valid Addr Y CS2 ia R W Write ae LBA 73 EB DATA ip y Last Valid Data Y 1 2 Half Word 2 2 Half Word Figure 17 WSC 3 WEA 2 WEN 3 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 37 Specifications RR AA RER ERER j hsel weim cs 2 i A htrans ji Nonseq hwrite Read haddr y Vi Y wey SN NL weim hrdata Last Valid Data w en V1 Word weim_hready RA BCLK burst clock Internal signals shown only for illustrative purposes ADDR Last Valid Addr y Address V1 Y Address V1 2 CS2 V Li RAN Read oe EBx EBC 0 EBx EBC 1 DATA a 1 2 Half Word e 2 2 Half Word Note 1 x 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 18 WSC 3 OEN 2 A WORD E HALF MC9328MX1 Advance Information Rev 4 38 Freescale Semiconductor
52. e 35 SDRAM Write Timing Parameter Table Ref 1 8V 3 3V f No Parame ter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 2 67 4 2 SDRAM clock low level width 6 4 3 SDRAM clock cycle time 10 4 _ 10 4 Address setup time 3 42 3 5 Address hold time 2 28 2 6 Precharge cycle period tap the 7 Active to read write command delay taco taco MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 77 Specifications Table 35 SDRAM Write Timing Parameter Table Continued Ref 1 8V NC Parameter Unit d Minimum Maximum Minimum Maximum 8 Data setup time 4 0 2 _ ns 2 28 2 ns 9 Data hold time 1 Precharge cycle timing is included in the write timing diagram 2 tgp and tkcp SDRAM clock cycle time These settings can be found in the MC9328MX1 reference manual SDCLK Figure 59 SDRAM Refresh Timing Diagram Table 36 SDRAM Refresh Timing Parameter Table Ref 1 8V 3 3V No Parameter Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high level width 2 67 a 4 _ ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor Specifications Table 36 SDRAM Refresh Timing Parameter Table Continued Ret 1 8V 3 3V f No Parameter Unit Minimum Maximum Minimum Maximum 2 SDRAM clock low lev
53. ecifications 3 14 LCD Controller This section includes timing diagrams for the LCD controller For detailed timing diagrams of the LCD controller with various display configurations refer to the LCD controller chapter of the MC9328MX1 Reference Manual LSCLK XE NP NE MEN LD 15 0 X X gt 0 Figure 45 SCLK to LD Timing Diagram Table 27 LCDC SCLK Timing Parameter Table Ref No Parameter Minimum Maximum Unit 1 SCLK to LD valid _ 2 ns gt lt Non display region gt lt Display region sh i T1 T3 T4 a gt a VSYN T2 W po e mi mmm mm ws OE LD 15 0 m A f f f f Mona Y T5 T6 i XMAX T7 gt lt lt gt at p p uuu ae HSYN I l SCLK OE LD 15 0 VSYN Figure 46 4 8 16 Bit Pixel TFT Color Mode Panel Timing Diagram MC9328MX1 Advance Information Rev 4 62 Freescale Semiconductor Specifications Table 28 4 8 16 Bit Pixel TFT Color Mode Panel Timing Table Symbol Description Minimum Corresponding Register Value Unit T1 End of OE to beginning of VSYN T5 T6 VWAIT1 T2 T5 T6 T7 T9 Ts T7 T9 T2 HSYN period XMAX 5 XM
54. el width 6 _ 4 ns 3 SDRAM clock cycle time 10 4 _ 10 _ ns 4 Address setup time 3 42 3 ns 5 Address hold time 2 28 2 ns 6 Precharge cycle period tap _ tgp _ ns 7 Auto precharge command period trc _ tnc _ ns Figure 60 SDRAM Self Refresh Cycle Timing Diagram MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 79 Specifications 3 19 USB Device Port Four types of data transfer modes exist for the USB module control transfers bulk transfers isochronous transfers and interrupt transfers From the perspective of the USB module the interrupt transfer type 1s identical to the bulk data transfer mode and no additional hardware is supplied to support it This section covers the transfer modes and how they work from the ground up Data moves across the USB in packets Groups of packets are combined to form data transfers The same packet transfer mechanism applies to bulk interrupt and control transfers Isochronous data is also moved in the form of packets however because isochronous pipes are given a fixed portion of the USB bandwidth at all times there is no end of transfer USBD AFE N Output output t ROE_VPO t VMO_ROE gt lt gt USBD_ROE Output N mo gt m m7 USBD VPO Output USBD VMO Tun y zu onn E USBD_SUSPND ER o Output N USBD RCV Input USBD VP Input USB
55. elay between the host command and card response is NCR clock cycles as illustrated in Figure 48 The symbols for Figure 48 through Figure 52 are defined in Table 30 Table 30 State Signal Parameters for Figure 48 through Figure 52 Card Active Host Active Symbol Definition Symbol Definition Z High impedance state S Start bit 0 D Data bits T Transmitter bit Host 1 Card 0 Repetition P One cycle pull up 1 CRC Cyclic redundancy check bits 7 bits E End bit 1 Nip cycles Host Command lt CID OCR ovo BT Top EHI ene ERR Identification Timing Nor cycles Host Command lt CID OCR ovo BT Tcp EHI ene HR SET RCA Timing Figure 48 Timing Diagrams at Identification Mode After a card receives its RCA it switches to data transfer mode As shown on the first diagram in Figure 49 on page 66 SD CMD lines in this mode are driven with push pull drivers The command is followed by a period of two Z bits allowing time for direction switching on the bus and then by P bits pushed up by the responding card The other two diagrams show the separating periods Ngc and Nec MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 65 Specifications Nor cycles Host Command lt Response Ed zaMNN oewer eee Command response timing data transfer mode Nnc cycles Response lt Host Command ovo feji eee ene PEA OE T
56. em clock period For 96MHz system clock 2 CS5 assertion can be controlled by CSA bits EB assertion also can be programmed by WEA bits in the CS5L register 3 Address becomes valid and RW asserts at the start of write access cycle 4 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 29 Specifications 3 9 3 EIM External Bus Timing The following timing diagrams show the timing of accesses to memory or a peripheral hclk u EE hsel weim cs 0 htrans X Seq Nonseq Y hwrite Read haddr Y Vi A may EN po weim hrdata Last Valid Data EB vi weim_hready fee E BCLK burst clock Internal signals shown only for illustrative purposes ADDR Last Valid Address Y vi C82 RAN Read DATA vi Note 1 x 2 0 1 20r3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register L Figure 10 WSC 1 A HALF E HALF MC9328MX1 Advance Information Rev 4 30 Freescale Semiconductor Specifications helk mE NV hsel_weim_cs 0 2 o a htrans Nonse E de EN a o hwrite Write E E haddr Y V1 Y g hready 5 Gi hwdat
57. es to provide current control on the MS_SDIO pin because of a possibility of signal conflict between the MS SDIO pin and Memory Stick SDIO pin when the pin direction changes 3 If the MSC2 RED bit 0 MSHC samples MS SDIO input data at MS SCLKO rising edge 4 Ifthe MSC2 RED bit 1 MSHC samples MS SDIO input data at MS SCLKO falling edge 3 17 Pulse Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency The selected clock signal is passed through a divider and a prescaler before being input to the counter The output is available at the pulse width modulator output PWMO external pin System Clock PWM Output Figure 56 PWM Output Timing Diagram Table 33 PWM Output Timing Parameter Table Bof 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum 1 System CLK frequency 0 87 0 100 MHz 2a Clock high time 3 3 5 10 ns 2b Clock low time 7 5 5 10 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 73 Specifications Table 33 PWM Output Timing Parameter Table Continued 1 8V 0 10V 3 0V 0 30V Ref No Parameter Unit Minimum Maximum Minimum Maximum 3a Clock fall time i 5 5 10 ns 3b Clock rise time 6 67 5 10 ns 4a Output delay time 5 7 E 5 _ ns 4b Output setup time 5 7 _ 5 i ns 1 C of PWMO
58. ess MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 21 I 8 Specifications 3 9 External Interface Module The External Interface Module EIM handles the interface to devices external to the MC9328MX1 including generation of chip selects for external peripherals and memory The timing diagram for the EIM is shown in Figure 5 and Table 13 defines the parameters of signals E E Ja HCLK Bus Clock A A Y a lt lt Address Chip select nn ai Ga lt lt 3b Read Write OE rising edge eo l Sa l OE falling edge ls V E EB rising edge Oleg l B re EB falling edge laa V Kaipa LBA negated falling edge E s 100 LBA negated rising edge em je E la gt f gt Y fb BCLK burst clock rising edge c gt gt Gd BCLK burst clock falling edge E lt 8b fa lt gt m gt e fa lt ke Write Data negated rising WII UCTGCU CI I IIXIII DTACK_B ZI i oni Figure 5 EIM Bus Timing Diagram Table 13 EIM Bus Timing Parameter Table 1 8 0 10V 3 0 0 3V Ref No Parameter Unit Min Typical Max Min Typical Max 1a Clock fall to address valid 2 48 3 31 9 11 2 4 3 2 8 8 ns MC9328MX1 Advance Information Rev 4
59. f write access cycle 4 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state 3 9 2 4 DTACK Write Cycle DMA Enabled lt Address co E gt 10 programmable CS5 min Ons programmable min 0ns OE logic high DTACK Lye 12 lt Databus output from MX1 8 Figure 9 DTACK Write Cycle DMA Enabled Table 17 Parameters for Write Cycle WSC 111111 DTACK_SEL 0 HCLK 96MHz 3 0 0 3 V Number Characteristic Unit Minimum Maximum 1 CS5 assertion time See note 2 _ ns 2 EB assertion time See note 2 _ ns 3 CS5 pulse width 3T E ns 4 RW negated before CS5 is negated 1 5T 0 58 1 57 1 58 ns 5 Address inactive before CS negated _ 0 93 ns 6 DTACK asserted after CS5 asserted _ 1019T ns MC9328MX1 Advance Information Rev 4 28 Freescale Semiconductor Table 17 Parameters for Write Cycle WSC 111111 DTACK_SEL 0 HCLK 96MHz Continued Specifications 3 0 0 3 V Number Characteristic Unit Minimum Maximum 7 DTACK asserted to RW negated 2T 1 8 3T 5 26 ns 8 Data hold timing after RW negated 1 5T 0 59 ns 9 Data ready after CS5 is asserted _ T ns 10 CS deactive to next CS active T ns 11 EB negate to CS negate 0 5T 0 74 0 5T 2 17 ns 12 DTACK pulse width 1T 3T ns Note 0 DTACK assert mean DTACK become low 1 T is the syst
60. for a non inverted serial clock polarity TSCKP RSCKP 0 and a non inverted frame sync TFSI RFSI 0 If the polarity of the clock and or the frame sync have been inverted all the timing remains valid by inverting the clock signal STCK SRCK and or the frame sync STFS SRFS shown in the tables and in the figures 2 There are 2 sets of I O signals for the SSI module They are from Port C primary function PC3 PC8 and Port B alternate function PB14 PB19 When SSI signals are configured as outputs they can be viewed both at Port C primary function and Port B alternate function When SSI signals are configured as input the SSI module selects the input based on status of the FMCR register bits in the Clock controller module CRM By default the input are selected from Port C primary function 3 bi bit length wl word length Table 41 SSI 2 Timing Parameter Table Ref 1 8V 0 10V 3 0V 0 30V No Parameter Unit Minimum Maximum Minimum Maximum Internal Clock Operation Port B Alternate Function 2 1 STCK SRCK clock period 95 83 3 ns 2 STCK high to STFS bl high 1 7 4 8 1 5 4 2 ns 3 SRCK high to SRFS bl high 0 1 1 0 0 1 1 0 ns 4 STCK high to STFS bl low 3 08 5 24 2 7 4 6 ns 5 SRCK high to SRFS bl low 1 25 2 28 1 1 2 0 ns MC9328MX1 Advance Information Rev 4 86 Freescale Semiconductor Table 41 SSI 2 Timing Parameter Table Continued Specifications
61. g Diagrams at Data Read Figure 51 on page 68 shows the basic write operation timing As with the read operation after the card response the data transfer starts after Nyyp cycles The data is suffixed with CRC check bits to allow the card to check for transmission errors The card sends back the CRC check result as a CC status token on the data line If there was a transmission error the card sends a negative CRC status 101 otherwise a positive CRC status 010 is returned The card expects a continuous flow of data blocks if it is configured to multiple block mode with the flow terminated by a stop transmission command MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 67 Specifications puewwoo ejum 3oolq ajdiynu ayy JO Bulu l sejoAo YMN sejo o HMN lt gt j snes 949 snje1s OHO sng eed AMM a ered SIUM ZERPRRPR PRP E PEPE o wewo Hepere weweo ppl iva zp ap ees pppp ouo wew EkEkFEE mas pppp oso wewoo fep vo e am sejo o HMN gt lt puewwoo e1JM xoo q eui JO BUIWI snes Quo sng lt eje IUM AER m FRE RE l Hs HI A e HHHP C n j HH ee romo weweo fih meo ppp oso wenoo i ano esuodsey lt puewwo 1SOH s o o YON Timing Diagrams at Data Write Figure 51 MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 68 Specifications The stop transmission command may occur when the card is in different states
62. gative reference for pen ADC AVDD Analog power supply AGND Analog ground BlueTooth BT1 I O clock signal BT2 Output MC9328MX1 Advance Information Rev 4 12 Freescale Semiconductor Table 3 Signal Names and Descriptions Continued Signals and Connections Signal Name Function Notes BT3 Input BT4 Input BT5 Output BT6 Output BT7 Output BT8 Output BT9 Output BT10 Output BT11 Output BT12 Output BT13 Output TRISTATE Sets all I O pins to tristate Can be used for flash loading and is pulled low for normal operations BTRF VDD Power supply from external BT RFIC BTRF GND Ground from external BT RFIC Noisy Supply Pins NVDD Noisy Supply for the I O pins NVSS Noisy Ground for the I O pins Supply Pins Analog Modules AVDD Supply for analog blocks AVSS Quiet GND for analog blocks Internal Power Supply QVDD Power supply pins for silicon internal circuitry QVSS GND pins for silicon internal circuitry MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 13 Specifications 3 Specifications This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor 3 1 Maximum Ratings Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5
63. gital Interface SD CMD SD Command lf the system designer does not want to make use of the internal pull up via the Pull up enable register a 4 7K 69K external pull up resistor must be added SD CLK MMC Output Clock SD DAT 3 0 Data lf the system designer does not want to make use of the internal pull up via the Pull up enable register a 50 K 69K external pull up resistor must be added Memory Stick Interface MS BS Memory Stick Bus State Output Serial bus control signal MS SDIO Memory Stick Serial Data Input Output MS SCLKO Memory Stick Serial Clock Output Serial Protocol clock output MS SCLKI Memory Stick External Clock Input Test clock input pin for SCLK divider This pin is only for test purposes not for use in application mode MS PIO General purpose InputO Can be used for Memory Stick Insertion Extraction detect MS PI1 General purpose Inputi Can be used for Memory Stick Insertion Extraction detect UARTs IrDA Auto Bauding UART1 RXD Receive Data MC9328MX1 Advance Information Rev 4 10 Freescale Semiconductor Table 3 Signal Names and Descriptions Continued Signals and Connections Signal Name Function Notes UART1 TXD Transmit Data UART1 RTS Request to Send UART1 CTS Clear to Send UART2 RXD Receive Data UART2 TXD Transmit Data UART2 RTS Request to Send UART2 CTS Clear to Send UART2 DSR Data Set Ready UART2 RI
64. iming response end to next CMD start data transfer mode Ncc cycles Host Command lt Host Command ovo feji cewe js coren cnc d4da Timing of command sequences all modes Figure 49 Timing Diagrams at Data Transfer Mode Figure 50 on page 67 shows basic read operation timing In a read operation the sequence starts with a single block read command which specifies the start address in the argument field The response is sent on the SD CMD lines as usual Data transmission from the card starts after the access time delay Nac beginning from the last bit of the read command If the system is in multiple block read mode the card sends a continuous flow of data blocks with distance Nac until the card sees a stop transmission command The data stops two clock cycles after the end bit of the stop command MC9328MX1 Advance Information Rev 4 66 Freescale Semiconductor Specifications Ncn cycles Host Command lt Response ovo efi Kearen ene eer a E on ee J lt x Read Data Nac cycles Timing of single block read Ncn cycles Host Command lt Response cmo n fua 3 amz fpe sgg 2 7 Fb a ReadData lt gt Read Data Nac cycles Nac cycles Timing of multiple block read Nor cycles Host Command lt Response ovo ET TA AR eee oppo EC Timing of stop command Valid Read Data CMD12 data transfer mode Figure 50 Timin
65. ister CONTROLREGI to match the external SPI master s timing In this configuration SS becomes an input signal and is used to latch data into or load data out to the internal data shift registers as well as to increment the data FIFO 4 Figure 40 Master SPI Timing Diagram Using SPI_RDY Edge Trigger SPIRDY Figure 41 Master SPI Timing Diagram Using SPI RDY Level Trigger MC9328MX1 Advance Information Rev 4 60 Freescale Semiconductor Specifications SS output Figure 42 Master SPI Timing Diagram Ignore SPI RDY Level Trigger SS input I Figure 43 Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS input SCLK MOSI MISO Figure 44 Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 26 Timing Parameter Table for Figure 40 through Figure 44 in Parameter Minimum Maximum Unit 1 SPI RDY to SS output low oT ns 2 SS output low to first SCLK edge 3 Tsclk 2 ns 3 Last SCLK edge to SS output high 2 Tsclk ns 4 SS output high to SPI RDY low 0 ns 5 SS output pulse width Tsclk WAIT 3 ns 6 SS input low to first SCLK edge T _ ns 7 SS input pulse width T _ ns 1 T CSPI system clock period PERCLK2 2 Tsclk Period of SCLK 3 WAIT Number of bit clocks SCLK or 32 768 KHz clocks per Sample Period Control Register MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 61 Sp
66. l these 3 signals are active high Tsis the shift clock period Ts Tpix panel data bus width Tpix is the pixel clock period which equals LCDC CLK period PCD 1 Maximum frequency of LCDC CLK is 48 MHz which is controlled by Peripheral Clock Divider Register Maximum frequency of SCLK is HCLK 5 otherwise LD output will be wrong MC9328MX1 Advance Information Rev 4 54 Freescale Semiconductor 3 10 Pen ADC Specifications The specifications for the pen ADC are shown in Table 20 through Table 22 Table 20 Pen ADC System Performance Full Range Resolution 13 bits Non Linearity Error 4 bits Accuracy 9 bits 1 Tested under input 0 1 8V at 25 C Table 24 Pen ADC Test Conditions Vp max 1800 mV ip max 7 pA Vp min GND ip min 1 5 pA Vn GND in 1 5 LA Sample frequency 12 MHz Sample rate 1 2 KHz Input frequency 100 Hz Input range 0 1800 mV Note Rui Ru2 200K Table 22 Pen ADC Absolute Rating ip max 9 5 pA ip min 2 5 uA in max 9 5 pA in min 2 5 pA 3 11 ASP Touch Panel Controller The following sections contain the electrical specifications of the ASP touch panel controller The value of parameters and their corresponding measuring conditions are mentioned as well 3 11 1 Electrical Specifications Test conditions Temperature 25 C QVDD 1800mV MC9328MX1 Advance Information Rev 4 Spe
67. le min 0ns RW logic high 5 e DTACK Databus input to MX1 10 Figure 7 DTACK Read Cycle DMA Enabled MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 25 Specifications Table 15 Parameters for Read Cycle WSC 111111 DTACK SELz0 HCLK 96MHz 3 0 0 3 V Number Characteristic c i uni Minimum Maximum 1 OE and EB assertion time See note 2 E ns 2 CS pulse width 3T ns 3 OE negated before CS5 is negated 0 5T 0 24 0 5T 0 67 ns 4 Address inactive before CS negated 0 93 ns 5 DTACK asserted after CS5 asserted _ 1019T ns 6 DTACK asserted to OE negated 3T 2 2 4T 6 86 ns 7 Data hold timing after OE negated 0 ns 8 Data ready after DTACK is asserted _ T ns 9 CS deactive to next CS active T ns 10 OE negate after EB negate 0 5 1 5 ns 11 DTACK pulse width 1T 3T ns Note 0 DTACK assert mean DTACK become low 1 T is the system clock period For 96MHz system clock 2 OE and EB assertion time is programmable by OEA bit in CS5L register EB assertion in read cycle will occur only when EBC bit in CS5L register is clear 3 Address becomes valid and CS asserts at the start of read access cycle 4 The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state MC9328MX1 Advance Information Rev 4 26 Freescale Semiconductor Specifications 3 9 2 3 DTACK Wri
68. ll counter and status values are resumed as access continues MC9328MX1 Advance Information Rev 4 70 Freescale Semiconductor Specifications JUUUUUUUUUUUUUUUUUUN emo er As ovos DAT 1 S Block Data Data Elzizi 4 Block Data For 4 bit For 4 bit JUUU UU UU UU UU Figure 54 SDIO ReadWait Timing Diagram 3 16 Memory Stick Host Controller The Memory Stick protocol requires three interface signal line connections for data transfers MS BS MS SDIO and MS SCLKO Communication is always initiated by the MSHC and operates the bus in either four state or two state access mode The MS BS signal classifies data on the SDIO into one of four states BSO BS1 BS2 or BS3 according to its attribute and transfer direction BSO is the INT transfer state and during this state no packet transmissions occur During the BS1 BS2 and BS3 states packet communications are executed The BS1 BS2 and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length in four state access mode The Memory Stick usually operates in four state access mode and in BS1 BS2 and BS3 bus states When an error occurs during packet communication the mode is shifted to two state access mode and the BSO and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 71 Specifications monn
69. lock ADDR CS3 ie a ETE lt Xv X PON FEY Write Data V1 Word Last Va lid Data ED TR Last Valid AddrY Address V1 Address V1 2 R W Write LBA lb EB DATA je NY Last Valid Data Y 1 2 Half Word 2 2 Half Word Figure 15 WSC 3 WEA 1 WEN 3 A WORD E HALF MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 35 Specifications Ee oe a ae IE j hsel weim cs 2 l man A htrans Nonseq hwrite X Read hadar D vi Y hready NAO weim_hrdata Last Valid Data GENER V1 Word weim_hready p pes BCLK burst clock Internal signals shown only for illustrative purposes ADDR Last Valid Adar Address V1 X Address V1 2 CS2 E R W Read OE EBx EBC 0 EBx EBC2 1 weim_data_in AZ Half Word M2 Half Word Note 1 x 2 0 1 20r 3 Note 2 EBC Enable Byte Control bit bit 11 on the Chip Select Control Register Figure 16 WSC 3 OEA 4 A WORD E HALF MC9328MX1 Advance Information Rev 4 36 Freescale Semiconductor Internal signals shown only for illustrative purposes hclk hsel weim cs 2 htrans hwrite haddr hready hw
70. ltage Core 1 70 1 90 V 150 MHz QVDD Internal supply voltage Core 1 80 2 00 V 200 MHz AVDD Analog supply voltage 1 70 3 30 V BTRFVD Bluetooth l O voltage Bluetooth 1 70 3 10 V Di BTRFVD Bluetooth l O voltage Non Bluetooth 1 70 3 30 V D gt applications 1 Voltages referenced to Vss and BTRFGND which are both tied to the same potential 3 3 Power Sequence Requirements For required power up and power down sequencing please refer to the Power Up Sequence section of application note AN2537 on the i MX website page 3 4 DC Electrical Characteristics Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1 MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 15 Specifications Table 6 Maximum and Minimum DC Characteristics Number Parameter Minimum Typical Maximum Unit or Symbol lop Full running operating current at 1 8V for QVDD at 1 8v mA QVDD 3 3V for NVDD AVDD Core 96 MHz 120mA NVDD AVDD System 96 MHz MPEG4 decoding playback at 3 0v 30mA from external memory card to both external SSI audio decoder and TFT display panel and OS with MMU enabled memory system is running on external SDRAM Please refer to application note AN2537 Power Performance of MC9328MX1 Sidd Standby current QVDD 1 8V temp 25 C _ 25 _ uA Sidd Standby current QVDD 1 8V temp 55 C 45 LA Sidd S
71. ns are made using the information in this section Sample Gmax 65535 GO CO 2400 1800 2400 Figure 37 Gain Error Calculations Assuming the offset remains unchanged the mapping is rotated around y intercept to determine the maximum gain allowed This occurs when the sample at 1800mV has just reached the ceiling of the 16 bit range 65535 MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 57 Specifications Maximum Offset Gmax Gmax 65535 Co 1800 65535 32767 1800 18 20 Gain Error G G Gmax Go Go 100 18 20 13 65 13 65 100 3396 3 12 Bluetooth Accelerator IMPORTANT On chip accelerator hardware is not supported by software An external Bluetooth chip interfaced to a UART is recommended The Bluetooth Accelerator BTA radio interface supports the Motorola Radio MC13180 using an SPI interface This section provides the data bus timing diagrams and SPI interface timing diagrams shown in Figure 38 and Figure 39 on page 59 and the associated parameters shown in Table 24 and Table 25 on page 59 BT CLK BT1 FS BT5 _ PKT DATA BT3 RXTX EN BT9 PKT DATA BT2 iL et s LL L L L VU aki EX Ida Wn um ON 35 B KOK X2 Figure 38 Motorola MC13180 Data Bus Timing Diagram Table 24 Motorola MC13180 Data Bus Timing Parameter Table Receive
72. nt recorded in the factory environment max 5mA is consumed for OSC pads with each toggle GPIO consuming 4mA MC9328MX1 Advance Information Rev 4 14 Freescale Semiconductor Specifications 3 2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages The MC9328MX1 processor has multiple pairs of VDD and VSS power supply and return pins QVDD and QVSS pins are used for internal logic All other VDD and VSS pins are for the I O pads voltage supply and each pair of VDD and VSS provides power to the enclosed I O pads This design allows different peripheral supply voltage levels in a system Because AVDD pins are supply voltages to the analog pads it is recommended to isolate and noise filter the AVDD pins from other VDD pins BTRFVDD is the supply voltage for the Bluetooth interface signals It is quite sensitive to the data transmit receive accuracy Please refer to Bluetooth RF spec for special handling If Bluetooth is not used in the system these Bluetooth pins can be used as general purpose I O pins and BTRFVDD can be used as other NVDD pins For more information about I O pads grouping per VDD please refer to Table 3 on page 6 Table 5 Recommended Operating Range 1 Symbol Rating Minimum Maximum Unit NVDD I O supply voltage MSHC SPI BTA USBd LCD and 2 70 3 30 V CSI are only 3V interface NVDD I O supply voltage 1 70 3 30 V QVDD Internal supply vo
73. on page 15 or the DC Characteristics table Table 4 Maximum Ratings Symbol Rating Minimum Maximum Unit NVaq DC I O Supply Voltage _ V QVad DC Internal core Supply Voltage _ V AVad DC Analog Supply Voltage _ _ V BTRFVgg DC Bluetooth Supply Voltage _ _ V Vag Supply voltage 0 3 3 3 V TA Maximum operating temperature range 0 70 C MC9328MX1VH20 MC9328MX1VM20 TA Maximum operating temperature range 30 70 C MC9328MX1DVH20 MC9328MX1DVM20 TA Maximum operating temperature range 40 85 C MC9328MX1CVH15 MC9328MX1CVM15 VESD_HBM ESD at human body model HBM _ 2000 V VESD_MM ESD at machine model MM 100 V ILatchup Latch up current x 200 mA Test Storage temperature 55 150 C Pmax Power Consumption 8002 13003 mW 1 Voltages referenced to Vss and BTRFGND which are both tied to the same potential 2 Atypical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core that is 7x GPIO 15x Data bus and 8x Address bus 3 Aworst case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core that is 32x GPIO 30x Data bus 8x Address bus These calculations are based on the core running its heaviest OS application at 200MHz and where the whole image is running out of SDRAM QVDD at 2 0V NVDD and AVDD at 3 3V therefore 180mA is the worst measureme
74. port or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners The ARM POWERED logo is the registered trademark of ARM Limited ARM9 ARM920T and ARM9TDMI are the trademarks of ARM Limited Freescale Semiconductor Inc 2004 All rights reserved e freescale semiconductor
75. s Hi Z x 20 8 ns Table 8 32k 16M Oscillator Signal Timing Parameter Minimum RMS Maximum Unit EXTAL32k input jitter peak to peak for both System PLL and 5 20 ns MCUPLL EXTAL32k input jitter peak to peak for MCUPLL only 7 5 100 ns EXTAL32k startup time 800 _ ms EXTAL16M input jitter peak to peak TBD TBD _ EXTAL16M startup time TBD Table 9 CLKO Rise Fall Time at 30pF Loaded Best Worst Case Typical Case Units Rise Time 0 80 1 00 1 40 ns Fall Time 0 74 1 08 1 67 ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 17 Specifications 3 6 Embedded Trace Macrocell All registers in the ETM are programmed through a JTAG interface The interface is an extension of the ARM920T processor s TAP controller and is assigned scan chain 6 The scan chain consists of a 40 bit shift register comprised of the following e 32 bit data field e T bit address field e A read write bit The data to be written is scanned into the 32 bit data field the address of the register into the 7 bit address field and a 1 into the read write bit A register is read by scanning its address into the address field and a 0 into the read write bit The 32 bit data field is ignored A read or a write takes place when the TAP controller enters the UPDATE DR state The timing diagram for the ETM9 is shown in Figure 2 See Table 10 on page 18 for the ETM9 timing parameters used
76. s driven logic low the memory system is configured into little endian The pin is not supposed to be changed on the fly ETM ETMTRACESYNC ETM sync signal which is multiplexed with A24 ETMTRACESYNC is selected in ETM mode ETMTRACECLK ETM clock signal which is multiplexed with A23 ETMTRACECLK is selected in ETM mode ETMPIPESTAT 2 0 ETM status signals which are multiplex with A 22 20 ETMPIPESTAT 2 0 are selected in ETM mode ETMTRACEPKT 7 0 ETM packet signals which are multiplex with ECB LBA BCLK burst clock PA17 A 19 16 ETMTRACEPKT 7 0 are selected in ETM mode CMOS Sensor Interface CSI D 7 0 Sensor port data CSI MCLK Sensor port master clock CSI VSYNC Sensor port vertical sync CSI HSYNC Sensor port horizontal sync CSI PIXCLK Sensor port data latch clock LCD Controller LD 15 0 LCD Data Bus All LCD signals are driven low after reset and when LCD is off FLM VSYNC Frame Sync or Vsync This signal also serves as the clock signal output for gate driver dedicated signal SPS for Sharp panel HR TFT LP HSYNC Line Pulse or H Sync LSCLK Shift Clock ACD OE Alternate Crystal Direction Output Enable CONTRAST This signal is used to control the LCD bias voltage as contrast control SPL SPR Program horizontal scan direction Sharp panel dedicated signal MC9328MX1 Advance Information Rev 4 8 Freescale Semiconductor Signals and Connections Table 3
77. tandby current QVDD 2 0V temp 25 C _ 35 _ LA Sidd Standby current QVDD 2 0V temp 55 C 60 uA ViH Input high voltage 0 7Vpp Vdd 0 2 V VIL Input low voltage E 0 4 V VoH Output high voltage lop 2 0 mA 0 7Vpp EE Vdd V VoL Output low voltage Io 2 5 mA a 0 4 V liL Input low leakage current _ 1 uA Vin GND no pull up or pull down liy Input high leakage current 1 LA Vin Vpn no pull up or pull down lou Output high current m d 4 0 mA Voy 0 8Vpp Vpp 1 8V lou Output low current 4 0 mA VoL 0 4V Vpp 1 8V loz Output leakage current _ _ 5 uA Vout Vpp output is tri stated Ci Input capacitance _ _ 5 pF Co Output capacitance _ 5 pF MC9328MX1 Advance Information Rev 4 16 Freescale Semiconductor Specifications 3 5 AC Electrical Characteristics The AC characteristics consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of other signals All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz core operating frequency 150 MHz with an operating supply voltage from Voip min 9 Vpp max Under an operating temperature from Tr to Ty All timing is measured at 30 pF loading Table 7 Tri State Signal Timing Pin Parameter Minimum Maximum Unit TRISTATE Time from TRISTATE activate until O become
78. te Cycle without DMA Address 1 3 E programmable CS5 min Ons gt 10 a programmable min Ons OE logic high DTACK Databus output from MX1 8 Figure8 DTACK Write Cycle without DMA Table 16 Parameters for Write Cycle WSC 111111 DTACK_SEL 0 HKCL 96MHz 3 0 0 3 V Number Characteristic Unit Minimum Maximum 1 CS5 assertion time See note 2 _ ns 2 EB assertion time See note 2 _ ns 3 CS5 pulse width 3T i ns 4 RW negated before CS5 is negated 1 57 0 58 1 57 1 58 ns 5 RW negated to Address inactive 57 31 _ ns 6 DTACK asserted after CS5 asserted _ 1019T ns 7 DTACK asserted to RW negated 2T 1 8 3T 5 26 ns 8 Data hold timing after RW negated 1 5T 0 59 _ ns 9 Data ready after CS5 is asserted _ T ns 10 EB negated before CS5 is negated 0 5T 0 74 0 5T 2 17 ns 11 DTACK pulse width 1T 3T ns MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 27 Specifications Table 16 Parameters for Write Cycle WSC 111111 DTACK_SEL 0 HKCL 96MHz Continued 3 0 0 3 V Number Characteristic Unit Minimum Maximum Note 0 DTACK assert mean DTACK become low 1 T is the system clock period For 96MHz system clock 2 CS5 assertion can be controlled by CSA bits EB assertion can also be programmed by WEA bits in the CS5L register 3 Address becomes valid and RW asserts at the start o
79. trols D 7 0 OE Memory Output Enable Active low output enables external data bus CS 5 0 Chip Select The chip select signals CS 3 2 are multiplexed with CSD 1 0 and are selected by the Function Multiplexing Control Register FMCR By default CSD 1 0 is selected ECB Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on going burst sequence and initiate a new long first access burst sequence LBA Active low signal sent by flash device causing the external burst device to latch the starting burst address BCLK burst clock Clock signal sent to external synchronous memories such as burst flash during burst mode RW RW signal Indicates whether external access is a read high or write low cycle Used as a WE input signal by external DRAM Bootstrap BOOT 3 0 System Boot Mode Select The operational system boot mode of the MC9328MX1 upon system reset is determined by the settings of these pins SDRAM Controller SDBA 4 0 SDRAM SyncFlash non interleave mode bank address multiplexed with address signals A 15 11 These signals are logically equivalent to core address p addr 25 21 in SDRAM SyncFlash cycles SDIBA 3 0 SDRAM SyncFlash interleave addressing mode bank address multiplexed with address signals A 19 16 These signals are logically equivalent to core address p addr 12 9 in SDRAM SyncFlash cycles MA 11 10 SDRAM address signals MA 9 0 SDRAM address signals
80. ule Memory Stick amp Host Controller MSHC SmartCard Interface Module SIM Direct Memory Access Controller DMAC Two Synchronous Serial Interfaces and Inter IC Sound SSI 1 and SSI 2 8 Module nter IC C Bus Module Video Port General Purpose I O GPIO Ports Bootstrap Mode Analog Signal Processing ASP Module Bluetooth Accelerator BTA Multimedia Accelerator MMA 256 pin MAPBGA Package 1 3 Target Applications The MC9328MX I is targeted for advanced information appliances smart phones Web browsers digital MP3 audio players handheld computers based on the popular Palm OS platform and messaging applications such as Motorola s wireless cellular products including the Accompli 008 GSM GPRS interactive communicator MC9328MX1 Advance Information Rev 4 Freescale Semiconductor 3 Introduction 1 4 Document Revision History The following table provides revision history for this release This history includes technical content revisions only and not stylistic or grammatical changes Table 1 MC9328MX1 Data Sheet Revision History Revision Location Revision Throughout Clarified instances where BCLK signal is burst clock Table 4 on page 14 Maximum Ratings table replaced Section 3 3 Power Sequence Added reference to AN2537 Requirements on page 15 Section 3 12 Bluetooth Accelerator Added Important note regarding no software support for the BTA
81. uty cycle 10 2 5ns gt max fall time allowed 5 1 4ns Falling edge latch data max fall time allowed negative duty cycle hold time max rise time allowed positive duty cycle setup time 3 22 2 Non Gated Clock Mode Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge Figure 71 on page 91 shows the timing diagram when the CMOS sensor output data 1s configured for positive edge and the CSI is programmed to received data in negative edge The parameters for the timing diagrams are listed in Table 43 on page 91 MC9328MX1 Advance Information Rev 4 90 Freescale Semiconductor Specifications PIXCLK DATA 7 0 X Valid Data X Figure 70 Sensor Output Data on Pixel Clock Falling Edge 2 I 3 1 1 1 CSI Latches Data on Pixel Clock Rising Edge Valid Data Valid Data I I 1 I PIXCLK N N N 1 1 X valid Data x Valid Data Valid Data I 2 DATA 7 0 I I 3 I I I I I q p T 4 gt I Figure 71 Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 43 Non Gated Clock Mode Parameters Ref No Parameter Minimum Maximum Unit 1 csi vsync to csi pixclk 9 TucLk ns 2 csi_d setup time 1 ns 3 csi_d hold time 1 _ ns 4 csi_pixclk high time 10 42 ns MC9328MX1 Advance Information Rev 4

Download Pdf Manuals

Related Search

freescale MC9328MX1 Manual

freescale MC9328MX1 Manual

Contents

Download Pdf Manuals

Related Search

Related Contents