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freescale MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet

1. Effect 2 2 Operation Description onec 5 9 5 gt HINZ dz o PULA Pull A from Stack SP lt SP 1 Pull A 1 1 1 86 2 PULH Pull H from Stack SP lt SP 1 Pull 1 1 1 8 2 PULX Pull X from Stack SP lt SP 1 Pull X 1 1 1 INH 88 2 ROL opr DIR 39 dd 4 ROLA INH 49 1 ROLX INH 59 1 ROL Rotate Left through Carry 1 1111 69 f 4 ROL 57 bo IX 79 3 ROL opr SP SP1 9E69 ff 5 ROR opr DIR 36 4 4 RORA INH 46 1 ROB oprX Rotate Right through Carry gt 1 1111 Ee ff 1 ROR X 87 bO IX 76 3 ROR opr SP SP1 9E66 ff 5 RSP Reset Stack Pointer SP FF 1 1 1 INH 9C 1 SP lt SP 1 Pull CCR SP lt SP 1 Pull A RTI Return from Interrupt SP lt SP 1 Pull X 111111 INH 80 7 SP SP 1 Pull SP lt SP 1 Pull PCL SP lt SP 1 Pull PCH RTS Return from Subroutine SP amp SP 1 Pull PCL 1 1 1 INH 81 4 SBC opr IMM A2 ii 2 SBC opr DIR B2 dd 3 SBC opr EXT C2 hhll 4 B X IX2 D2 ff 4 Fa a Subtract with Carry lt A M t t ee SBC X IX F2 2 SBC opr SP SP1 9EE2 ff 4 SBC opr SP SP2 9ED2 ee ff 5 SEC Set Carry Bit Cei 1 1 1 INH 99 1 SEI Set Interrupt Mask 1 1 111 1 INH 9B 2 STA opr DI
2. 4 gt wn 5 VECTOR TO CPU FOR FETCH gt BILBIH DECODER INSTRUCTIONS a VDD lt lt ROPUD ivrERNAL PULLUP Y Q E DEVICE CUR i 7 SYNCHRO NER INTERRUPT REQUEST Vv RO LATCH IMASK pe MODE HIGH VOLTAGE DETECT LOGIC Figure 8 2 IRQ Module Block Diagram 8 3 1 MODE 1 If the MODE bit is set the IRQ pin is both falling edge sensitive and low level sensitive With MODE set both of the following actions must occur to clear the IRQ interrupt request e Return of the IRQ pin to high level As long as the IRQ pin is low the IRQ request remains active e RQ vector fetch or software clear An IRQ vector fetch generates an interrupt acknowledge signal to clear the IRQ latch Software generates the interrupt acknowledge signal by writing a 1 to ACK in INTSCR The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch Writing to ACK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACK does not affect subsequent transitions on the IRQ pin A falling edge that occurs after writing to ACK latches another interrupt request If the IRQ mask bit IMASK is clear the CPU loads t
3. MECHANICAI UTLINES DOCUMENT NO S8ASH70247A FREESCALE SEMICONDUCTOR semiconductor RESERVED a 5 ii 222 nii Uc RIMIS DO NUT SCALE THIS DRAWING NOTES 1 CONTROLLING DIMENSION MI 2 DIMENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 DIMENSION DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0 15 PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIO INT AD FLASH OR PROTRUSION SHALL NOT EXCEED 0 25 PER SIDE 5 DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 TOTAL IN EXCESS O HE DIMENSION AT MAXIMUM MATERIAL CONDITION 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ON A N DIMENSIONS ARE TO BE DETERMINED DATUM PLANE W TITLE CASE NUMBER 948 01 ic Lp TSSOP DIGSMM NEN PACKAGE CODE 611 SHEET 2 4 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456
4. Effect 2 2 o ue Operation Description 5 9 5 gt VH IIN ZIC BHS rel ae D C or Same lt PC 2 rel C 0 REL 24 13 rel Branch if IRQ Pin High PC lt 2 rel IRQ 1 REL 2F m 3 BIL rel Branch if IRQ Pin Low lt 2 rel IRQ 0 REL 2E 3 BIT IMM 5 2 DIR B5 dd 3 BIT opr EXT C5 hhil 4 EUM _ 2 05 jee ff 4 BIT opr X Bit Test A amp M 0 111 1X4 ES f 3 BIT X IX F5 2 BIT opr SP SP1 9EE5 ff 4 BIT opr SP SP2 9ED5 jee ff 5 B h if Less Than or Equal To BLE opr Signed Operands qu PC 2 rel Z NO V 1 REL 93 im 3 BLO rel Branch if Lower Same as BCS PC lt 2 rel 1 REL 25 3 BLS rel Branch if Lower or Same lt PC 2 rel 1 2 1 REL 23 3 BLT opr Branch if Less Than Signed Operands lt PC 2 rel V 1 REL 91 3 BMC rel Branch if Interrupt Mask Clear PC lt PC 2 rel I 0 REL 2C 3 BMI rel Branch if Minus PC lt 2 rel 1 REL 2B 3 BMS rel Branch if Interrupt Mask Set PC lt PC 2 rel I 1 REL 3 BNE Branch if Not Equal lt 2 rel 7 0 REL 26 3 BPL rel Branch if Plus PC lt 2 rel 20 REL 2A 3 BRA rel Branch Always PC lt 2
5. 41 i s p ee ee 41 o Ol eee A ee 41 ADU Pon EL PINS usus orae ends Po OC eee POR RC ed 41 volage CONOS qd P9244 ee ARCADE OH 44 p o en UD STETIT TOI T ULL I DIRMI 44 TERR hee SCE SERRE MARBRE EID 44 Laus 44 i or TTC oer 44 Low Power 44 Wat 22 21 33 1 45 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 9 Table of Contents 3 6 3 7 3 7 1 3 7 2 3 7 3 4 1 4 2 4 3 4 4 4 5 4 6 4 6 1 4 6 2 4 6 3 5 1 5 2 6 1 6 2 6 3 6 3 1 6 3 2 6 3 3 6 3 4 6 3 5 6 3 6 6 3 7 6 4 6 5 6 6 6 7 6 7 1 6 7 2 6 8 Se e P rrr 45 45 ADC Status and Control Register 45 ADC Data Register 47 ADC Input Clock Register occ au 47 Chapter 4 Auto Wakeup Module AWU ace Celis 49 bx Ehe Dri Loi do Deinde PO pb dou d 49 Funcional Lud ue Bre eR ORE RES t
6. 109 13 5 3 SIM Counter and Reset States 109 1 3 a aa 109 13 6 1 rem 109 13 6 1 1 Hardware MENUDES EM TE 111 13 6 1 2 OWI I T TET TRITT TT 112 13 6 2 Intemupt Status Registers add doa 112 13 6 2 1 Status Register T La soda 113 13 6 2 2 Interrupt Status Register 2 6s 113 13 6 2 3 Status Register ive iu ac cde oc ao ace lee ede DECR ROC CE OR e d ed 113 13 6 3 ee ee ee 114 13 6 4 Break SITs rU 114 13 6 5 Status Flag Protection in Break 114 117 114 13 7 1 ive eee eee E Wed red pe pee IMS P RS 114 13 72 2542 25 CU 115 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 13 Table of Contents Toe usse dud nA TT UNE buio aedi od iae 116 13 8 1 SIM Reset Status Register RP 117 13 8 2 Break Flag Control Pegi com 118 Chapter 14 Timer Interface Module TIM 141 uisa ci d pe HUGE 119 o EL 00 6 a
7. 162 1616 Memory Gharacteriellbs isa sacs oes add Ed CRI CRGA RO ER 163 Chapter 17 Ordering Information and Mechanical Specifications 12 41 ite qudd ENS 165 122 MG Order NUMDES e i44 ird od ead act ooo dO IEEE Reed CIRCE ROC CR RC 165 118 0 5 2 172 21077171275 270211200177 TT 165 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 15 Table of Contents MC68HC908QY QT Family Data Sheet Rev 5 16 Freescale Semiconductor Chapter 1 General Description 1 1 Introduction The MC68HC908QY4 is a member of the low cost high performance M68HC08 Family of 8 bit microcontroller units MCUs The M68HCO08 Family is a Complex Instruction Set Computer CISC with a Von Neumann architecture All MCUs in the family use the enhanced M68HC08 central processor unit 8 and are available with a variety of modules memory sizes and types and package types Table 1 1 Summary of Device Variations Device FLASH Analog to Digital Pin Memory Size Converter Count MC68HC908QT1 1536 bytes 8 pins MC68HC908QT2 1536 bytes 4 ch 8 bit 8 pins MC68HC908QT4 4096 bytes 4 ch 8 bit 8 pins MC68HC908QY 1 1536 bytes 16 pins MC68HC908QY2 1536 bytes 4 ch 8 bit 16 pins MC68HC908QY4 4096 bytes 4 ch 8 bit 16 pins 1 2 Features Features include e High performance M68HCO08 CPU core e Fully upward compatible
8. aav aav aav aav aav aav aav aav 195 HHSd 7 ZN8G 2 XZN8G VZN8G ZN8G s4109 Su 10HgH 2 v 6 6 2 2 2 v 9 6 6 5 v 6 XI 1495 245 1X3 HN L HN XI 1495 IXI z HN L HN L uia no xoaa voaa 91154 S1dSHH 4 v 6 v v E 2 2 4 5 S v L L v E v 6 XI 1495 245 t 2 1X3 HN L HN IXI z HN L HN oav oav oav oav oav 93S XHSd vH O8 6 2 v 9 v v E 2 L 2 9 v L v v 6 XI 1195 245 t 1X3 8 c L HN XI 195 IXI z HN L HN HH 019 x1Nd 151 151 151 x1 1 VIS 151 71359 vldSHud 8 v g 6 v v 5 v 1 1 v v 9 1495 6 LX 24858 6 c HNI HN XI 5 j IXI z HN L HN L Hia VIS VIS VIS VIS VIS VIS VIS SIV XYL VHSd usv usv usv XHSV 5 usv HIOHH 4 2 v v v 2 2 9 v 1 1 v v 9 145 LX 248 4 3 c HN 5 j IXI z HN L HN L uia
9. MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 95 Module OSC 11 8 1 Oscillator Status Register The oscillator status register OSCSTAT contains the bits for switching from internal to external clock sources Address 0036 Bit 7 6 5 4 3 2 1 Bit 0 Read ECGST ECGON Write Reset 0 0 0 0 0 0 0 0 R Reserved Unimplemented Figure 11 4 Oscillator Status Register OSCSTAT ECGON External Clock Generator On Bit This read write bit enables external clock generator so that the switching process can be initiated This bit is forced low during reset This bit is ignored in monitor mode with the internal oscillator bypassed PTM or CTM mode 1 External clock generator enabled 0 External clock generator disabled ECGST External Clock Status Bit This read only bit indicates whether or not an external clock source is engaged to drive the system clock 1 An external clock source engaged 0 An external clock source disengaged 11 8 2 Oscillator Trim Register OSCTRIM Address 0038 Bit 7 6 5 4 3 2 1 Bit 0 Read TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIMO rite Reset 1 0 0 0 0 0 0 0 Figure 11 5 Oscillator Trim Register OSCTRIM TRIM7 TRIMO Internal Oscillator Trim Factor Bits These read write bits change the size of the internal capacitor used by the internal
10. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 egister Low rite page 132 Reset Indeterminate after reset Read CHIF 0 2 au re ELS1B ELS1A TOVI CHIMAX See page 130 Reset 0 0 0 0 0 0 0 0 Read HH 8015 84 Bit 10 Bit 9 Bit 8 egister Hig rite See page 132 Reset Indeterminate after reset Read BU Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 egister Low rite page 132 Reset Indeterminate after reset Unimplemented Oscillator Status Register Read R R R R R R ECGON OSCSTAT Write See page 96 neget 0 0 0 0 0 0 0 0 Unimplemented Read Oscillator Trim Register Read 6 trims TRIMS OSCTRIM write See page 96 Reset 1 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 3 of 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 29 003C 003D 003E 003F FE00 FEO1 2 FE03 FE04 05 FE06 07 30 Register Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented Read COCO ADC Control ADCO CH CH3 CH2 CH1 CHO Register ADSCR Write R 45 Reset 0 0 0 1 1 1 1
11. RR POEs 100 12 3 1 o0 AMET mE 100 12 3 2 Data Direction Register BL enne 101 12 3 3 Port B Input Pullup Enable Register 22222 0 224 1 2 77 564 43 6 1 102 Chapter 13 System Integration Module SIM 123 PCIE mere 103 13 2 RST a d IRQ Pins 4 104 123 SIM Bus Clock Control and 104 13 3 1 ra EE 105 13 3 2 Clock StartUp fom POR 2224 105 13 435 Clocks in Stop Made and Wait Mode 105 13 4 Reset System Initialization PERPE 105 13 4 1 PEE 106 13 4 2 Active Resets from Internal Sources 106 13 4 2 1 OTT Terr 107 13 4 2 2 Computer Operating Properly COP 108 13 4 2 3 TUER 108 13 4 2 4 legal Address Mr 108 13 4 2 5 Low Voltage Inhibit LVI 108 Ioa 1 pe 7 METTI 108 13 5 1 SIM Counter During Power On 108 13 5 2 SIM Counter During Stop Mode
12. PTAO ADO TCHO KBIO gt CLOCK PTAT ADI TCHI KBIT 6 gt GENERATOR PTA2IRGIKBIZTCLK 3 _ lt OSCILLATOR lt 4 5 PTAA OSC2 AD2 KBM t SYSTEM INTEGRATION ODULE PTAS OSC1 AD3 KBIS a M6BHCO8 CPU SINGLE INTERRUPT ODULE 1 4 gt PTB2 3 m BREAK PTB a 5 9 ODULE 5 lt gt 2 POWER ON RESET lt gt ODULE MC68HC908QY4 AND MC68HC908QT4 KEYBOARD INTERRUPT 8 BIT ADC C 4096 BYTES MODULE MC68HC908QY2 MC68HC908QY1 MC68HC908QT2 AND MC68HC908QT1 1536 BYTES UE 128 BYTES RAM Co USER FLASH COP MODULE FE Vpp POWER SUPPLY L RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up 0 71 Not available on 8 pin devices MC68HC908QT1 MC68HC908QT2 and MC68HC908QT4 see note 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT 1 Figure 9 1 Block Diagram Highlighting Block and Pins MC68HC908QY QT Family Data Sheet Rev 5 80 Freescale Semiconductor Functional Description INTERNAL BUS lt n 2 VECTOR FETCH DECODER c ACKK KEYF Q 4 3 SYNCHR
13. 144 15 3 1 5 Beak 144 15 3 1 6 144 15 3 1 7 CODEN deb OS ee ee ER d 144 15 3 2 cQ SR M 148 Chapter 16 Electrical Specifications 149 152 Absoluie Maximum DSUBDE ccc cee eR re REPEPPL E ERI ERE ERE 149 163 Fauneuonal Operating Range ORE 6405560455004 00404 5000584585 150 2 0 150 16 5 5 V DG Electrical Characteristics ccccigceaigerncigeaeeeeesivksebigassanucees 151 16 6 Typical 5 V Output Drive Charactensiite 2 152 PI UR IR BER CR Re Cr doe d e pedes 153 16 8 5 7 OS aad o dar e d 154 16 9 3 V DC Electrical Ca acere eed 155 16 10 Typical 3 0 V Output Drive Characteristics 156 16 11 SV Comro TUG 32b db HOGS ROTSG RISES 157 16 12 Sf Oscilator os as kon ebd d Pap RR RR Eb Phan GER e 158 16 13 Supply Current Characteristics 159 16 14 Analog to Digital Converter 5 161 18 15 Timer Interface Module 5
14. the LVI will maintain a reset condition until Vpp rises above the rising trip point voltage This prevents a condition in which the MCU is continually entering and exiting reset if Vpp is approximately equal to is greater than by the hysteresis voltage 10 3 4 LVI Trip Selection The bit in the configuration register selects whether the LVI is configured for 5 V or 3 V protection NOTE The microcontroller is guaranteed to operate at a minimum supply voltage The trip point Vrgipe 5 V or V may be lower than this See 16 5 5 V DC Electrical Characteristics and 16 9 3 V DC Electrical Characteristics for the actual trip point voltages MC68HC908QY QT Family Data Sheet Rev 5 86 Freescale Semiconductor LVI Status Register 10 4 LVI Status Register The LVI status register LVISR indicates if the Vpp voltage was detected below the level while LVI resets have been disabled Address FEOC Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 R Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 10 2 LVI Status Register LVISR LVIOUT LVI Output Bit This read only flag becomes set when the Vpp voltage falls below the trip voltage and is cleared when Vpp voltage rises above The difference in these threshold levels results
15. bit ADSCR 003C is set after each conversion and will stay set until the next read of the ADC register When conversion is in process and the ADSCR is written the current conversion data should be discarded to prevent an incorrect reading 3 3 5 Accuracy and Precision The conversion process is monotonic and has no missing codes 3 4 Interrupts When the AIEN bit is set the ADC module is capable of generating a central processor unit CPU interrupt after each ADC conversion A CPU interrupt is generated if the COCO bit is at 0 The COCO bit is not used as a conversion complete flag when interrupts are enabled 3 5 Low Power Modes The following subsections describe the ADC in low power modes 3 5 1 Wait Mode The ADC continues normal operation during wait mode Any enabled CPU interrupt request from the ADC can bring the microcontroller unit MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting the CH 4 0 bits in ADSCR to 1s before executing the WAIT instruction MC68HC908QY QT Family Data Sheet Rev 5 44 Freescale Semiconductor Input Output Signals 3 5 2 Stop Mode The ADC module is inactive after the execution of a STOP instruction Any pending conversion is aborted ADC conversions resume when the MCU exits stop mode Allow one conversion cycle to stabilize the analog circuitry before using ADC data after exiting stop mode 3 6 Input Outpu
16. 1 3 V FLASH program bus clock frequency 1 MHz FLASH read bus clock frequency fread 0 8M Hz FLASH page erase time 1 k cycles tErase 0 9 1 1 1 ms gt 1 k cycles 3 6 4 5 5 FLASH mass erase time 4 E ms FLASH PGM ERASE to HVEN setup time tnvs 10 us FLASH high voltage hold time tNvH 5 us FLASH high voltage hold time mass erase tNVHL 100 us FLASH program hold time 5 us FLASH program time tPRoG 30 40 us FLASH return to read time 1 us FLASH cumulative program HV period 4 ms FLASH endurance 10k 100 k Cycles FLASH data retention time 9 15 100 Years 1 freag is defined as the frequency range for which the FLASH memory can be read 2 is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing HVEN to O 3 is defined as the cumulative high voltage programming time to the same row before next erase must satisfy this condition tyys tpRog X 32 tuy maximum 4 Typical endurance was evaluated for this product family For additional information on how Freescale defines Typical Endurance please refer to Engineering Bulletin EB619 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For addit
17. 273 C Pp x TA 273 C Constant K 5 Pp Oya Average junction temperature Ty Pp x 64 C Maximum junction temperature Tym 150 1 Power dissipation is a function of temperature 2 constant unique to the device can be determined for a known T4 and measured Pp With this value of Pp and Ty can be determined for any value of T4 MC68HC908QY QT Family Data Sheet Rev 5 150 Freescale Semiconductor 16 5 5 V DC Electrical Characteristics 5 V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Output high voltage li 2 0 mA all I O pins Vpp 0 4 10 0 mA all pins Vpp 1 5 715 0 mA PTAO 1 5 only Vpp 0 8 Maximum combined all pins lour 50 mA Output low voltage 1 6 mA all pins 0 4 VoL V 10 0 mA all I O pins m 1 5 15 0 mA PTAO PTA1 5 only 0 8 Maximum combined lo all I O pins lott 50 mA Input high voltage V 7xV 7 V 5 7 IH 0 7 x VDD DD M Input low voltage V V 2 V 5 7 P Input hysteresis Vuys 0 06 x Vpp V DC injection current all ports ling 2 2 mA Total dc current injection sum of all 1 0 liNJTOT 25 25 Ports Hi Z leakag
18. darc errem 76 cpi NT 76 Ia Module During Break IBITUBIS Eee ds 76 VO Signals 76 77 PeO O TIS T TET TII I T UTER 77 Chapter 9 Keyboard Interrupt Module IO UU eR 79 79 Funcional Deseripilli m nesses been Eq EE e e dd E Ed 79 Keyboard LOB Le RS RE ERE ENTE ERR 79 Keyb ard a iue drm ERR REX CERE RR Eu REER I EET CERE ERR RS 82 WAU MORE RES 82 Op MOJE LOTO 82 Keyboard Module During Break 82 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 11 Table of Contents 9 7 crue dud ij RePEc 83 9 7 1 Keyboard Status and Control 83 872 Keyboard Interrupt Enable 84 Chapter 10 Low Voltage Inhibit LVI 101 pue dae pd bea eda e Pd 85 IUE ee ORO dee iced 85 199 BUE 6 85 10 3 1 PPP 86 10 3 2 acc od o i4 r ool TT ren 86 10 3 3 Voltage Hysteresis Protection tatio 86 10 3 4 LYI T
19. ree 119 14 3 Pin Name ccs ch ceed HGS e bee sebeasecned dese RE HRS 119 oo hdd id ebd 121 14 4 1 122 14 4 2 in Ee 122 14 4 3 RR PCR aei RO Ade cre ddp qs 122 14 4 3 1 Unbuffered Output COmpafB RO REOR RR RUD ACA PKs ae RI KE RR RE 122 14 4 3 2 Cupit Gone Ea d RICE RORE RR HA ROLE EUER COR d OR 122 14 4 4 Pulse Width Modulation 123 14 4 4 1 Unbuffered PWM Signal Generation 124 14 4 4 2 Buttered PWM Signal Generation 124 14 4 4 3 xls 125 125 138 200 25 ee 126 TAS TIM Break 126 14 8 InputOutput Signals 126 14 8 1 WI lock 1 126 14 8 2 TIM Channel I O Pins PTAO TCHO and 1 126 149 126 14 9 1 TIM Status and Control Register 127 14 9 2 TM COUNT Registers 128 14 9 3 TIM Counter Modulo Registers 129 14 9 4 TIM Channel Status and Control 129 14 9 5 TIM Chamel R
20. 00 SP1 9E61 ff rr 6 CLC Clear Carry Bit 1 1 1 1 10 INH 98 1 CLI Clear Interrupt Mask 1 0 0 INH 9A 2 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 67 Central Processor Unit CPU Table 7 1 Instruction Set Summary Sheet 3 of 6 Effect 2 3 Operation Description onec 5 9 5 28 HIINZIC 45 6 6 6 lt 00 DIR dd 3 CLRA A 00 INH 4F 1 CLRX X 00 INH 5F 1 CLRH Clear lt 00 1 1011 INH 8C 1 CLR M 00 1 1 6F 3 CLR lt 00 IX 7F 2 CLR opr SP M lt 00 SP1 ff 4 CMP opr IMM A1 2 B1 dd 3 CMP opr EXT C1 hhll 4 1 2 01 4 Compare A with M A M 1 1111 Te E1 3 CMP X IX F1 2 opr SP SP1 9EE1 ff 4 CMP opr SP SP2 9ED1 eeff 5 COM opr M M FF M DIR 33 dd 4 COMA lt M INH 43 1 COMX X lt X FF KM INH 53 1 COM opr X Complement One s Complement M lt M SFF M 111 63 lt 4 COM lt FF IX 73 3 COM opr SP lt M FF SP1 9E63 ff 5 CPHX opr LY wi IMM 65 jiiii 1 3 CPHX opr Compare H X with M M M 1 1 1111 DIR 75 dd 4 CPX opr IMM iii 2 DIR dd 3 CPX opr EXT hhll
21. Section Register Name Bit 7 6 5 4 3 2 1 Bit 0 j Read 0 0 0 0 FLASH Control Register i HVEN MASS ERASE PGM FLCR Write 33 Reset 0 0 0 0 0 0 0 0 Read Break Address High gir4s Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Register BRKH Write page 136 Reset 0 0 0 0 0 0 0 0 Read Break Address low 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register BRKL Write See page 136 Reset 0 0 Read Break Status and Control i BRKE BRKA Register BRKSCR Write See page 136 Reset 0 0 LVI Status Register Read LVIOUT R LVISR Write 87 Reset 0 0 0 0 0 0 0 0 Reserved for FLASH Test R R R R R R R R FLASH Block Protect Read BPR7 BPR6 BPR5 4 BPR3 BPR2 BPR1 BPRO Register FLBPR Write Seepage38 Reset Unaffected by reset Reserved R R R R R R R R Read internal Oscillator Trim 22 7 TRIM6 TRIMS TRIM4 TRIM3 TRIM2 TRIM1 TRIMO Write Value Optional Reset Unaffected by reset Reserved R R R R R R R R COP Control Register Read LOW BYTE OF RESET VECTOR COPCTL Write WRITING CLEARS COP COUNTER ANY VALUE page 59 Reset Unaffected by reset Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 5 of 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semicondu
22. 13 3 2 Clock Start Up from POR When the power on reset module generates a reset the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKXA cycle POR time out has completed The IBUS clocks start upon completion of the time out 13 3 3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset the SIM allows BUSCLKXA to clock the SIM counter The CPU and peripheral clocks do not become active until after the stop delay time out This time out is selectable as 4096 or 32 BUSCLKXA cycles See 13 7 2 Stop Mode In wait mode the CPU clocks are inactive The SIM also produces two sets of clocks for other modules Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode 13 4 Reset and System Initialization The MCU has these reset sources e Power on reset module POR e External reset pin RST Computer operating properly module COP e Low voltage inhibit module LVI e Illegal opcode address All of these resets produce the vector FFFE FFFF FEFE FEFF in monitor mode and assert the internal reset signal IRST IRST causes all registers to be returned to their default values and all modules to be returned to their reset states An internal reset clears the SIM counter see 13 5 SIM Counter but an external reset does not Each of the rese
23. 6 v 5 2 v v 9 S v v 9 v S XI 1495 6 IX 24858 v c 3H 2 HNI XI 145 2 HN L HN L Hia ans ans ans ans ans ans ans ans 399g ILH SAN SAN SAN VOAN SAN VHH 01959 013SHH 0 4 14 6 S v 14 6 5 1 5 S 14 v 5 14 S 951 336 3 936 6 8 1 936 9 S v L 0 asn XI 145 LXI 5 1 3 uia WINI HNI HNI XI 145 HNI HNI 51 1043409 914M JIpo y peed dew epoodo MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 72 Chapter 8 External Interrupt IRQ 8 1 Introduction The IRQ pin external interrupt shared with general purpose input and keyboard interrupt KBI provides a maskable interrupt input 8 2 Features Features of the IRQ module include the following External interrupt pin IRQ interrupt control bits e Programmable edge only or edge and level interrupt sensitivity e Automatic interrupt acknowledge Selectable internal pullup resistor 8 3 Functional Description IRQ pin functionality is enabled by setting configuration register 2 CONFIG2 IRQEN bit accordingly A zero disables the IRQ function and PTA2 will assume the other shared functionalities A one enables the IRQ function A low level applied to the external interrupt request IRQ pin can latch a
24. AGE SH te DOCUMENT NO 98ASH70107A 2 MECHANICAL OUTLINES gt freescale DICTIONARY semiconductor PAGE 968 FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED VERSIONS GONT ROLLEN 5 GONTROLEES D 0 0 5 L E T H I S D R A W I N R E V A NOTES 1 DIMENSIONS AND TOLERANCES PER ASME Y14 5 1994 2 CONTROLLING DIMENSION MILLIMETER A DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE MOLD FLASH OR PROTRUSIONS SHALL EXCEDD 0 15mm PER SIDE 4 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY A THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION SHALL BE 0 08mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0 46mm CASE NUMBER 968 02 8 LEAD MFP STANDARD PACKAGE CODE 6003 SHEET 3 OF 4 f MECHANICAL OUTLINES DOCUMENT NO 98ARL10557D r eescale DICTIONARY PAGE 1452 Prou Tne Document conmo versions DO NOT SCALE THIS DRAWING PREV A PIN 1 INDEX AREA TERMINAL 0 8 PITCH 4 X 4 X 1 MECHANICAL OUTLINES DOCUMENT NO 98ARL10557D r eescale DICTIONARY PAGE 1452 Prou THe Docuwenr m
25. IRQ Interrupt Request Acknowledge Bit Writing a 1 to this write only bit clears the IRQ latch ACK always reads as O IMASK IRQ Interrupt Mask Bit Writing a 1 to this read write bit disables the IRQ interrupt request 1 IRQ interrupt request disabled 0 IRQ interrupt request enabled MODE IRQ Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ pin 1 IRQ interrupt request on falling edges and low levels 0 IRQ interrupt request on falling edges only MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 77 AB External Interrupt IRQ MC68HC908QY QT Family Data Sheet Rev 5 78 Freescale Semiconductor Chapter 9 Keyboard Interrupt Module 9 1 Introduction The keyboard interrupt module provides six independently maskable external interrupts which are accessible via the 5 pins 9 2 Features Features of the keyboard interrupt module include e Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask e Software configurable pullup device if input pin is configured as input port bit e Programmable edge only or edge and level interrupt sensitivity e Exit from low power modes 9 3 Functional Description The keyboard interrupt module controls the enabling disabling of interrupt functions on the six port A pins These six pins can be enabled disabled independently of each other
26. 12 MHz External clock reference frequency 4 foscxcLk de 32 MHz Crystal load capacitance C 20 pF Crystal fixed capacitance C4 2xC Crystal tuning capacitance 9 Feedback bias resistor 0 5 1 10 MQ RC oscillator external resistor Rgxr See Figure 16 4 Crystal series damping resistor f 1 2 foscxcik gt 8 MHz 0 1 Bus frequency fop is oscillator frequency divided by 4 2 Deviation values assumes trimming 25 C and midpoint of voltage range 3 Values are based on characterization results not tested in production 4 No more than 10 duty cycle deviation from 50 5 Consult crystal vendor data sheet 14 5 25 C RC FREQUENCY MHz 0 10 20 30 40 50 60 Reyr Figure 16 4 RC versus Frequency 5 Volts 25 MC68HC908QY QT Family Data Sheet Rev 5 154 Freescale Semiconductor 16 9 3 V DC Electrical Characteristics 3 V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Output high voltage 0 6 mA all I O pins Vpp 0 3 4 0 mA all I O pins Vpp 1 0 710 0 mA PTAO 1 5 only Vpp 0 8 Maximum combined all pins lour 50 mA Output low voltage 0 5 mA all pins zx
27. 4 CPX IX2 D3 4 GPX Compare X with M X M 1 1111 1X4 3 CPX IX F3 2 CPX opr SP SP1 ff 4 CPX opr SP SP2 9ED3 jee ff 5 DAA Decimal Adjust A AJo t t INH 72 2 lt A 1 orM lt M 1 lt X 1 5 DBNZ PC lt PC 3 rel result 0 DIR 3 DBNZA rel PC lt PC 2 rel result 0 INH 4B rr 3 DBNZX rel Decrement and Branch if Not Zero PC lt PC 2 rel result 0 INH 5B 5 DBNZ opr X rel PC lt PC 3 rel result 0 6B 4 DBNZ X rel PC lt PC 2 rel result 0 IX 7B i 6 DBNZ 5 PC lt PC 4 rel result 0 SP1 9E6B ff rr DEC opr M lt 1 DIR 3A dd 4 DECA A lt A 1 INH 4A 1 DECX lt 1 m INH 5A 1 DEC Decrement M e M 1 4 DEC M lt M 1 IX 7A 3 DEC opr SP M lt M 1 SP1 9E6A ff 5 lt H A X DIV Divide lt Remainder 1 INH 52 7 EOR opr IMM A8 ii 2 EOR opr DIR B8 dd 3 EOR opr EXT hhll 4 EOR 2 08 4 EOR Exclusive OR M with A lt A M 1 1111 3 EOR X IX F8 2 EOR opr SP SP1 9EE8 ff 4 EOR opr SP SP2 9ED8 ee ff 5 INC opr lt M 1 DIR 3C dd 4 INCA lt 1 INH 4C 1 INCX X lt X 1 INH 5C 1 INC Increment M e M 1 exe ph el 6C f 4 INC X M lt M 1 IX 7C 3 INC opr SP M lt
28. 84 2 TAX Transfer A to X X lt A 1 1 1 1 1 97 1 Transfer to lt 7 INH 85 1 TST opr DIR 3D dd 3 TSTA INH 4D 1 131X i INH 5D 1 TST oprX Test for Negative or Zero A 00 or X 00 00 0 11 1 60 3 TST IX 7D 2 TST 5 SP1 9E6D ff 4 TSX Transfer SP to H X lt SP 1 1 1 1 1 1 95 2 Transfer X to A A lt X 7 INH 9F 1 TXS Transfer H X to SP SP lt H X 1 1 1 1 1 1 94 2 bit lt 0 Inhibit CPU clocking WAIT Enable Interrupts Wait for Interrupt until interrupted 0 INH 8F 1 A Accumulator n Any bit C Carry borrow bit one or two bytes CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed 16 bit offset addressing SP1 Stack pointer 8 bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16 bit offset addressing mode ff Offset byte in indexed 8 bit offset addressing SP Stack pointer H Half carry bit U Undefined H Index register
29. 9 5 Stop Mode The keyboard module remains active in stop mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode 9 6 Keyboard Module During Break Interrupts The system integration module SIM controls whether the keyboard interrupt latch can be cleared during the break state The BCFE bit in the break flag control register BFCR enables software to clear status bits during the break state To allow software to clear the keyboard interrupt latch during a break interrupt write a 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state MC68HC908QY QT Family Data Sheet Rev 5 82 Freescale Semiconductor Input Output Registers To protect the latch during the break state write a O to the BCFE bit With BCFE at O its default state writing to the keyboard acknowledge bit ACKK in the keyboard status and control register during the break state has no effect 9 7 Input Output Registers The following 1 registers control and monitor operation of the keyboard interrupt module e Keyboard interrupt status and control register KBSCR e Keyboard interrupt enable register KBIER 9 7 1 Keyboard Status and Control Register The keyboard status and control register KBSCR e Flags keyboard interrupt requests e Acknowledges keyboard interrupt requests e Masks keyboard interrupt request
30. CLOCK BUS CLOCK GENERATOR ADIV 2 0 Figure 3 2 ADC Block Diagram MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 43 Analog to Digital Converter ADC 3 3 2 Voltage Conversion When the input voltage to the ADC equals Vpp the ADC converts the signal to FF full scale If the input voltage equals the ADC converts it to 00 Input voltages between Vpp and Vgg are a straight line linear conversion All other input voltages will result in FF if greater than Vpp and 00 if less than NOTE Input voltage should not exceed the analog supply voltages 3 3 3 Conversion Time Sixteen ADC internal clocks are required to perform one conversion The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR If the ADC internal clock is selected to run at 1 MHz then one conversion will take 16 us to complete With a 1 MHz ADC internal clock the maximum sample rate is 62 5 kHz 16 ADC Clock Cycles Conversion Time ADC Clock Frequency Number of Bus Cycles Conversion Time x Bus Frequency 3 3 4 Continuous Conversion In the continuous conversion mode ADCO 1 the continuously converts the selected channel filling the ADC data register ADR with new data after each conversion Data from the previous conversion will be overwritten whether that data has been read or not Conversions will continue until the ADCO bit is cleared The
31. rel REL 20 3 DIR 60 01 5 DIR 51 03 5 DIR 62 05 5 BRCLR n opr rel Branch if Bit n in M Clear PC c PC 3 rel Mn 0 LIDIR 05 ccu DIR 05 OB ddrr 5 DIR 06 OD 5 DIR b7 OF ddrr 5 BRN rel Branch Never lt 2 REL 21 jrr 3 DIR 60 00 ddrr 5 DIR b1 02 5 DIR 62 04 5 BRSET n opr rel Branch if Bit n in M Set lt 3 rel Mn 1 t DiR b4 08 e DIR 05 ddrr 5 DIR 66 OC ddrr 5 DIR 67 OE ddrr 5 DIR 60 10 dd 4 DIR b1 12 dd 4 DIR b2 14 dd 4 ma DIR b3 16 dd 4 BSET n opr Set Bit nin M Mn lt 1 DIR 18 Jad 4 DIR b5 1A 4 4 DIR b6 1C dd 4 DIR b7 dd 4 PC lt 2 push PCL BSR rel Branch to Subroutine 1 1 AD frr 4 PC rel PC PC 3 rel 00 DIR 31 ddrr 5 CBEQA stopr rel PC lt PC 3 rel A M 30 IMM 41 4 CBEQX stopr rel 3 12 500 51 4 and Branch if Equal lt PC 3 rel A M 00 1 1 61 5 CBEQ X rel lt PC 2 rel A 00 1 71 i 4 oprSP rel lt 4 rel A
32. 3 2 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 3 5 3 4 3 5 3 5 1 3 5 2 Chapter 1 General Description diss oro ek 17 Sc Lr sordes ed 17 MOU Bb DIA 19 CPRLN qni Dd 19 Lbirda i 22 Bae ee ION PNO 23 Chapter 2 Memory P T ETT 25 Unimplemented Memory LOCATIONS E PETERE ERR 25 Reserved Memory e uiu dedi EIER eric ebd PEOR Te CS E 25 DIT UE 27 Random Access Memory A d 22 FLASH Memory FLASH 225222222225 EO SEUSESe RU bed med d e dE 33 33 FLASH Page Erase CDI aou 34 FLASH Mass Erase Operation E SERRE 35 FLASH Program Operation 233424 4446s 35 FLASA PORON 36 FLASH Black Protect 80404 a 38 we a 39 re 39 Chapter 3 Analog to Digital Converter ADC digi Me T
33. E 0 3 n VoL V 6 0 mA all pins 1 0 10 0 mA PTAO PTA1 5 only 0 8 Maximum combined lo all pins lott 50 mA Input high voltage V 7xV V PTAO PTAS PTBO PTB7 n 0 7 x VoD DD y Input low voltage V V 2 03xV 5 PTBO PTB7 IL 55 Input hysteresis Vuys 0 06 x Vpp V DC injection current all ports ling 2 2 mA Total dc current injection sum of all 1 0 liNJTOT 25 25 mA Ports Hi Z leakage current liL 1 0 1 1 Capacitance Ports as input ram 12 Ports as input Cour 8 POR rearm voltage 0 100 mV POR rise time ramp rate 4 Rpon 0 035 V ms Monitor mode entry voltage Vpp 2 5 Vpp 4 0 V Pullup resistors 9 R 16 26 36 5 PTBO PTB7 PH Low voltage inhibit reset trip falling voltage VTRIPF 2 40 2 55 2 70 V Low voltage inhibit reset trip rising voltage VTRIPR 2 50 2 65 2 80 V Low voltage inhibit reset recover hysteresis Vuys 60 mV 1 2 7 to 3 3 Vdc Vss 0 Vdc T to Ty unless otherwise noted 2 Typical values reflect average measurements at midpoint of voltage range 25 C only 3 Maximum is highest voltage that POR is guaranteed 4 If minimum Vpp is not reached before the internal POR reset is released the LVI will hold the part in reset until minimum Vpp is reached 5 Rpy are measured at Vpp 3 0 V MC68HC90
34. INT2 FE06 Interrupt status register 3 FEO07 Reserved FE08 FLASH control register FLCR FEO09 Break address register high BRKH FEOA Break address register low BRKL FEOB Break status and control register BRKSCR FEOC LVI status register LVISR FEOD Reserved FFBE FLASH block protect register FLBPR FFCO Internal OSC trim value Optional FFFF COP control register COPCTL Register Name Bit 7 6 5 4 3 2 1 Bit 0 j Read AWUL PTA2 Port A Data Register 5 4 1 PTAO PTA Write Seepage98 Reset Unaffected by reset Read Port Data Register PTB7 5 PTB4 PTB3 PTB2 PTB1 PTBO PTB Write See page 100 Reset Unaffected by reset Unimplemented Unimplemented Read 0 Data Direction Register A R R DDRAS DDRA4 DDRA3 DDRA1 DDRAO DDRA Write Seepage98 Reset 0 0 0 0 0 0 0 acti Read Data Direction RegisterB DDRB7 DDRB6 ppRBs DDRB4 DDRB3 DDRB2 DDRB DDRBO DDRB Write 101 Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 1 of 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 27 0008 001 001B 001C 001D 001E 001F 0020 0021 28 Register Name Unimplemented
35. MC68HC908QY1 MC68HC908QT2 AND MC68HC908QT1 1536 BYTES USER FLASH RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up PTB 0 7 Not available 8 pin devices MC68HC908QT1 MC68HC908QT2 and MC68HC908QTA see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT1 CLOCK OSCILLATOR SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER ON RESET MODULE KEYBOARD INTERRUPT MODULE dub 16 BIT TIMER MODULE LI COP m MODULE MONITOR ROM Figure 14 1 Block Diagram Highlighting TIM Block and Pins MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 14 4 Functional Description Functional Description Figure 14 2 shows the structure of the TIM The central component of the TIM is the 16 bit TIM counter that can operate as a free running counter or a modulo up counter The TIM counter provides the timing reference for the input capture and output compare functions The TIM counter modulo registers TMODH TMODL control the modulo value of the TIM counter Software can read the TIM counter value at any time without affecting the counting sequence The two TIM channels are programmable independently
36. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD Y Y Y TCHx OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE Figure 14 8 CHxMAX Latency 14 9 5 TIM Channel Registers These read write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function The state of the TIM channel registers after reset is unknown In input capture mode MSxB MSxA 0 0 reading the high byte of the TIM channel x registers TCHxH inhibits input captures until the low byte TCHxL is read In output compare mode MSxB MSxA z 0 0 writing to the high byte of the TIM channel x registers inhibits output compares until the low byte TCHxL is written Address 0026 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Address 0027 TCHOL Bit 7 6 5 4 3 2 1 Bit 0 IN T Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Address 0029 TCH1H Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Address 02A TCH1L Bit
37. TEMPERATURE RANGE Figure 17 1 Device Numbering System 17 3 Package Dimensions Refer to the following pages for detailed package dimensions MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 165 DETAIL D 210 015 SEATING PLANE FREESCALE SEMICONDUCTOR INC MECHANICAL OUTLINE PRINT VERSION NOT TO SCALE DOCUMENT NO 98ASB42420B REV N 8 LD PDIP CASE NUMBER 626 06 19 MAY 2005 STANDARD NON JEDEC 10 DETAIL D FREESCALE SEMICONDUCTOR INC MECHANICAL OUTLINE PRINT VERSION NOT TO SCALE DOCUMENT NO 98ASB42420B REV N 8 LD PDIP CASE NUMBER 626 06 19 MAY 2005 STANDARD NON JEDEC 1 DIMENSIONING AND TOLERANCING ASME Y14 5M 1994 2 ALL DIMENSIONS ARE IN INCHES 3 626 03 TO 626 06 OBSOLETE NEW STANDARD 626 07 DIMENSION TO CENTER OF LEAD WHEN FORMED PARALLEL A PACKAGE CONTOUR OPTIONAL ROUND OR SQUARE CONERS STYLE 1 PIN 1 AC IN 5 GROUND 2 DC IN 6 OUTPUT 3 DC IN 7 AUXILIARY 4 AC IN 8 VCC FREESCALE SEMICONDUCTOR INC MECHANICAL OUTLINE PRINT VERSION NOT SCALE TITLE DOCUMENT NO 98ASB42420B REV N 8 LD PDIP CASE NUMBER 626 06 19 MAY 2005 STANDARD NON JEDEC MECHANICAL OUTLINES DOCUMENT ND 98 70107 freescale DICTIONARY ner Ere semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED
38. Typical 5 Volt Output Low Voltage versus Output Low Current 25 C MC68HC908QY QT Family Data Sheet Rev 5 152 Freescale Semiconductor 5 V Control Timing 16 7 5 V Control Timing Characteristic Symbol Min Max Unit Internal operating frequency 8 MHz Internal clock period 1 fop 125 ns RST input pulse width low 100 ns IRQ interrupt pulse width low edge triggered tii iH 100 ns IRQ interrupt pulse period Note 1 Vpp 4 5 to 5 5 Vss 0 T4 T to timing shown with respect to 20 Vpp and 70 unless otherwise noted 2 The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 toyc RST E ETE etH RaQ Figure 16 3 RST and IRQ Timing MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 153 Electrical Specifications 16 8 5 V Oscillator Characteristics Characteristic Symbol Min Typ Max Unit Internal oscillator frequency fiNTCLK 12 8 MHz Deviation from trimmed Internal oscillator 0909 12 8 MHZ fixed voltage fixed temp ACCNT 0 4 9 12 8 MHz 10 0 to 70 C 2 12 8 MHz Vpp 10 40 to 125 C 5 Crystal frequency XTALCLK foscxcLk 1 24 MHz External RC oscillator frequency 2
39. includes 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4 1536 bytes of user FLASH for MC68HC908QT2 MC68HC908QT 1 MC68HC908QY2 and MC68HC908QY 1 128 bytes of random access memory RAM 48 bytes of user defined vectors located in FLASH 416 bytes of monitor read only memory ROM 1536 bytes of FLASH program and erase routines located in ROM 2 2 Unimplemented Memory Locations Accessing an unimplemented location can have unpredictable effects on MCU operation In Figure 2 1 and in register figures in this document unimplemented locations are shaded 2 3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation In Figure 2 1 and in register figures in this document reserved locations are marked with the word Reserved or with the letter R MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 25 0000 I O REGISTERS mo 64 BYTES 0040 RESERVED 64 BYTES 0080 mm hie 128 BYTES 2 UNIMPLEMENTED 9984 BYTES 2800 AUXILIARY ROM ee 1536 BYTES endi UNIMPLEMENTED SEDES 49152 BYTES 00 FLASH MEMORY 68 9080 4 AND MC68HC908QY4 SFDEF 4096 BYTES FEOO BREAK STATUS REGISTER BSR FEO1 RESET STATUS REGISTER SRSR FE02 BREAK AUXILIARY REGISTER BRKAR BREAK FLAG CONTROL REGISTER BFCR 04 INTERRUPT STATUS REGISTER 1 1111 FE
40. val vaql vaq vai vai vaql Vind YOu YOU YOu XHOH VHOH HOH aNg 1354 9 4 14 6 6 14 v 6 5 S v L L 14 6 v S XI 1495 245 61 c HNI L HN c WAI 51 Lid lig lig Lid lig Lid Lid Lid XSL XHdO XHdO XHLS sog 5 2 v S v v 5 2 2 v v E v v 6 XI 1495 245 c HNI L HN XI bt bkdS IXI z HN L HN L Hia cl SXL asl 51 asl Xus1 vus1 asl 299 21368 c13SHH v 2 v 5 6 v v 5 2 2 2 5 6 v L v v 6 XI 1495 245 4 3 c HN XI 5 XI z HN L HN L Hia cl XdO XdO XdO XdO IMS WOO WOO WOO XINOO WOO 518 2 v 5 S v v 5 2 5 6 5 6 v L L v v 6 1495 24858 v c 3H c HNI HNI HN L HN HH 045 9845 ogs 9845 ogs 9845 9845 045 199 vya YSN NW 1959 119599 v 5 S v v 5 4 2 5 L S v S XI 5 6 IX 2485 v c IH 6145 6 51 0390 NHH L v
41. 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 13 11 Interrupt Status Register 1 INT1 IF1 and IF3 IF5 Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13 3 1 Interrupt request present 0 No interrupt request present 1 3 and 7 Always read 0 13 6 2 2 Interrupt Status Register 2 Address FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read IF14 0 0 0 0 0 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 13 12 Interrupt Status Register 2 INT2 IF14 Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 13 3 1 Interrupt request present 0 interrupt request present Bit 0 6 Always read 0 13 6 2 3 Interrupt Status Register 3 Address FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 0 IF15 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 13 13 Interrupt Status Register 3 INT3 IF15 Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13 3 1 Interrupt request present 0 interrupt request present Bit 1 7 Always read 0 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 113 System Integration Module SIM 13 6 3 Reset All reset sources always have equal
42. 1 1 2 ENI 8 NO0 15 5 5 10 4 90 21235725 1 20 EN 6740 10 ave aell SEATING 048 AN 0 15 0 05 ou BSC TITLE CASE NUMBER 948F 01 16 LD TSSOP PITCH 0 65MM STANDARD JEDEC PACKAGE 611 SHEET 4 MECHANICA UTLINES DOCUMENT 8 4 FREESCALE SEMICONDUCTOR RESERVED i i 2 4 8 tamm veu RENE DO NOT SCALE THIS DRAWING REV B IN RED 0 50 0 19 9 0 25 0 19 0 16 0 09 E SECTION N N 0 09 DETAIL d ER 948F 01 Bal lt ise T CAS TITL STANDARD JEDEC 1e LD TSSOP PITCH 0 65MM PACKAGE 611 SHEET c UF
43. 1 SP1 9E6C ff 5 MC68HC908QY QT Family Data Sheet Rev 5 68 Freescale Semiconductor Table 7 1 Instruction Set Summary Sheet 4 of 6 Instruction Set Summary Effect o o 2 5 ob Operation Description 5 9 33 81818 JMP opr DIR BC dd 2 JMP opr EXT hhll 3 JMP Jump PC lt Jump Address 1 1 1 1 11 2 DC 4 JMP EC ff 3 JMP IX FC 2 ISR opr Pe LPO alo Ext 11 5 us JSR opr X Jump to Subroutine Push PCH SP SP 1 pD e ff 2 JSR X PC Unconditional Address IX FD 4 LDA opr IMM iii 2 LDA DIR B6 dd 3 LDA opr EXT C6 4 LDA opr X 1 2 D6 4 Load lt 1 11111 E6 8 3 LDA X IX F6 2 LDA opr SP SP1 9EE6 ff 4 LDA opr SP SP2 9ED6 ee ff 5 LDHX EE _ JIMM 45 lij 3 LDHX opr Load H X from M H X lt 1 111 DIR 55 Idd 4 LDX opr IMM AE 2 LDX opr DIR dd 3 LDX opr EXT 4 LDX IX2 DE 4 LDX Load X from M X lt M 1 11111 1X4 EE 3 LDX X IX FE 2 LDX opr SP SP1 ff 4 LDX 5 SP2 9EDE ff 5 LSL opr DIR 38 4 LSLA INH 48 1 LSLX Logical Shift Left Cle PET 58 1 LSL Same as ASL b7
44. 7 6 5 4 3 2 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 14 9 TIM Channel Registers TCHOH L TCH1H L MC68HC908QY QT Family Data Sheet Rev 5 132 Freescale Semiconductor Chapter 15 Development Support 15 1 Introduction This section describes the break module the monitor read only memory MON and the monitor mode entry methods 15 2 Break Module BRK The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program Features include e Accessible input output I O registers during the break Interrupt e Central processor unit CPU generated break interrupts e Software generated break interrupts e Computer operating properly COP disabling during break interrupts 15 2 1 Functional Description When the internal address bus matches the value written in the break address registers the break module issues a breakpoint signal BKPT to the system integration module SIM The SIM then causes the CPU to load the instruction register with a software interrupt instruction SWI The program counter vectors to FFFC and FFFD FEFC and FEFD in monitor mode The following events can cause a break interrupt to occur e ACPU generated address the address in the program counter matches the contents of the break address registers Software writes 1 to the BRKA bit in the break status and control
45. CPU interrupt request Figure 8 2 shows the structure of the IRQ module Interrupt signals on the IRQ pin are latched into the IRQ latch The IRQ latch remains set until one of the following actions occurs e IRQ vector fetch An IRQ vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch Software clear Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt status and control register INTSCR e Reset A reset automatically clears the IRQ latch The external interrupt pin is falling edge triggered out of reset and is software configurable to be either falling edge or falling edge and low level triggered The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 73 External Interrupt IRQ PTAO ADO TCHO KBIO 1 1 1 2 1 gt lt 8 2 4 082 2 4 5 1 5 lt gt 68 08 CPU PTBO0 1 lt gt 2 gt PTB3 m e PTB4 2 9 5 gt PTB6 de PTB7 MC68HC908QY4 AND MC68HC908QT4 8 BIT ADC 4096 BYTES MC68HC908QY2 MC68HC908QY1 MC68HC908QT2 AND MC
46. CPUOSRM AD for a description of the instructions and addressing modes and more detail about the architecture of the CPU 7 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 7 5 1 Wait Mode The WAIT instruction e Clears the interrupt mask I bit in the condition code register enabling interrupts After exit from wait mode by interrupt the bit remains clear After exit by reset the bit is set e Disables the CPU clock 7 5 2 Stop Mode The STOP instruction e Clears the interrupt mask I bit in the condition code register enabling external interrupts After exit from stop mode by external interrupt the bit remains clear After exit by reset the I bit is set e Disables the CPU clock After exiting stop mode the CPU clock begins running after the oscillator stabilization delay 7 6 CPU During Break Interrupts If a break module is present on the MCU the CPU starts a break interrupt by e Loading the instruction register with the SWI instruction e Loading the program counter with FFFC FFFD with FEFC FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress If the break address register match occurs on the last cycle of a CPU instruction the break interrupt begins immediately A return from interrupt instruction RTI in the break routine ends the break interrupt and returns the MCU to normal operation if the break interru
47. DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY THIS DIMENSION DOES NOT INCLUDE INTER LEAD FLASH OR PROTRUSIONS INTER LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0 25 MM PER SIDE THIS DIMENSION 15 DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 62 mm 16LD 8016 M B 1 27 PITCH worm CASE OUTLINE PACKAGE CODE 2003 SHEET 2 OF 3 MECHANICAL OUTLINES DOCUMENT ND 98 70247 freescale DICTIONARY E semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED 18 m VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED DO SCALE THIS DRAWING REV B IN RED 45752207860 L 2 Eo s 250 6 40 BSC _ _ _ _
48. ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED D N S F H S D R W R i VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED IN RED E pe 0 94 Oro 1 2 05 MAX m C 20 D CO TITL CAS G LEAD MFP STANDARD EIAJ PACKAGE 6003 SHEET 1 OF 4 freescale semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED IN RED MECHANICA UTLINES DICTI DUCUM ENT N 98 5 010 268 SCALE THIS DRAWING RE 1 50 1 10 0 90 0 70 0 85 TAIL TITL LEAD M CAS STA PAC
49. English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support Q freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com 68 9080 4 Rev 5 06 2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and speci
50. FLASH Memory FLASH Y 10 CLEAR PGM BIT Y 11 WAIT FOR A TIME tyyp Y 12 CLEAR HVEN BIT Y 13 WAIT FOR A TIME Y d E END OF PROGRAMMING A Figure 2 4 FLASH Programming Flowchart MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 37 2 6 6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory and therefore can only be written during a programming sequence of the FLASH memory The value in this register determines the starting address of the protected range within the FLASH memory Address Bit 7 6 5 4 3 2 1 Bit 0 Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPRO Write Reset Unaffected by reset Initial value from factory is 1 Write to this register is by a programming sequence to the FLASH memory Figure 2 5 FLASH Block Protect Register FLBPR BPR 7 0 FLASH Protection Register Bits 7 0 These eight bits in FLBPR represent bits 13 6 of a 16 bit memory address Bits 15 14 are 1s and bits 5 0 are Os The resultant 16 bit address is used for specifying the start address of the FLASH memory for block protection The FLASH is protected from this start address to the end of FLASH memory at FFFF With this mechanism the protect start address can be 40 XX80 or XXCO within the FLASH memo
51. Interrupt Enable Register The port A keyboard interrupt enable register KBIER enables or disables each port A pin or auto wakeup to operate as a keyboard interrupt input Address 001B Bit 7 6 5 4 3 2 1 Bit 0 Read 0 AWUIE 5 KBIE4 KBIE3 KBIE2 KBIE1 KBIEO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 4 Keyboard Interrupt Enable Register KBIER KBIE5 KBIEO Port A Keyboard Interrupt Enable Bits Each of these read write bits enables the corresponding keyboard interrupt pin on port A to latch interrupt requests Reset clears the keyboard interrupt enable register 1 KBIx pin enabled as keyboard interrupt pin 0 KBIx pin not enabled as keyboard interrupt pin NOTE AWUIE bit is not used in conjunction with the keyboard interrupt feature To see a description of this bit see Chapter 4 Auto Wakeup Module AWU MC68HC908QY QT Family Data Sheet Rev 5 84 Freescale Semiconductor Chapter 10 Low Voltage Inhibit LVI 10 1 Introduction This section describes the low voltage inhibit LVI module which monitors the voltage on the Vpp pin and can force a reset when the Vpp voltage falls below the LVI trip falling voltage 10 2 Features Features of the LVI module include e Programmable LVI reset e Programmable power consumption Selectable LVI trip voltage e Programmable stop mode operation 10 3 Functional Description Figure 10 1 shows the st
52. Refer to Figure 9 2 9 3 1 Keyboard Operation Writing to the KBIEO KBIE5 bits in the keyboard interrupt enable register KBIER independently enables or disables each port A pin as a keyboard interrupt pin Enabling a keyboard interrupt pin in port A also enables its internal pullup device irrespective of PTAPUEx bits in the port A input pullup enable register see 12 2 3 Port A Input Pullup Enable Register A logic O applied to an enabled keyboard interrupt pin latches a keyboard interrupt request A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt e If the keyboard interrupt is edge sensitive only a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low To prevent losing an interrupt request on one input because another input is still low software can disable the latter input while itis low e f the keyboard interrupt is falling edge and low level sensitive an interrupt request is present as long as any keyboard interrupt input is low MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 79 _ _ _ _ _ _ _ Keyboard Interrupt Module KBI
53. as input capture or output compare channels INTERNAL BUS PTA2 IRQ KBIZ TCLK gt INTERNAL BUS CLOCK PRESCALER TSTOP TRST 16 BIT COUNTER 16 BIT COMPARATOR TMODH TMODL CHANNEL 0 16 BIT COMPARATOR TCHOH TCHOL 16 BIT LATCH CHANNEL 1 16 BIT COMPARATOR TCH1H TCHIL 16 BIT LATCH Freescale Semiconductor PRESCALER SELECT PS2 1 PSO ELSOB ELSOA TOVO CHOMAX CHOF MS0B CHOIE TOV1 CH1MAX CHIF Figure 14 2 TIM Block Diagram MC68HC908QY QT Family Data Sheet Rev 5 INTERRUPT LOGIC TCHO INTERRUPT LOGIC TCH1 INTERRUPT LOGIC 121 Timer Interface Module TIM 14 4 1 Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the TIM clock pin TCLK The prescaler generates seven clock rates from the internal bus clock The prescaler select bits PS 2 0 in the TIM status and control register TSC select the TIM clock source 14 4 2 Input Capture With the input capture function the TIM can capture the time at which an external event occurs When an active edge occurs on the pin of an input capture channel the TIM latches the contents of the TIM counter into the TIM channel registers TCHxH TCHXxL The polarity of the active ed
54. computer operating properly module COP is enabled and remains active in wait mode Figure 13 15 and Figure 13 16 show the timing for wait recovery ADDRESS BUS 6E0B 6E0C 00FF 00FE 00FD 00FC DATABUS 546 sae sas sor sop se EXITSTOPWAIT NOTE EXITSTOPWAIT RST pin OR CPU interrupt OR break interrupt Figure 13 15 Wait Recovery from Interrupt C EE ADDRESS BUS 86 1 E 000 RSTVCTH Y nsrvort DATABUS 548 sae Y E 1 1 1 RST BUSCLKX4 Figure 13 16 Wait Recovery from Internal Reset 13 7 2 Stop Mode In stop mode the SIM counter is reset and the system clocks are disabled An interrupt request from a module can cause an exit from stop mode Stacking for interrupts begins after the selected stop recovery time has elapsed Reset or break also causes an exit from stop mode The SIM disables the oscillator signals BUSCLKX2 and BUSCLKXA in stop mode stopping the CPU and peripherals Stop recovery time is selectable using the SSREC bit in the configuration register 1 CONFIG1 If SSREC is set stop recovery is reduced from the normal delay of 4096 BUSCLKXA cycles down to 32 This is ideal for the internal oscillator RC oscillator and external oscillator options which do not require long start up times from stop mode NOTE External crystal applications shoul
55. in a hysteresis that prevents oscillation into and out of reset see Table 10 1 Reset clears the LVIOUT bit Table 10 1 LVIOUT Bit Indication Vpp LVIOUT Vpp gt VTRIPR 0 lt VTRIPF 1 lt Vpp lt VrniPR Previous value 10 5 LVI Interrupts The LVI module does not generate interrupt requests 10 6 Low Power Modes The STOP and WAIT instructions put the MCU in low power consumption standby modes 10 6 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of wait mode 10 6 2 Stop Mode When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set the LVI module remains active in stop mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of stop mode MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 87 Azz eee Low Voltage Inhibit LVI MC68HC908QY QT Family Data Sheet Rev 5 88 Freescale Semiconductor Chapter 11 Oscillator Module OSC 11 1 Introduction The oscillator module is used to provide a stable clock source for the microcontroller system and bus The oscillator module generates two output clocks BUSCLKX2 and BUSCLKX4 The BUSCLKXA clock is used by the system integration module SIM and the computer operating properly module COP The BUSCLKXO clock
56. instruction is a non maskable instruction that causes an interrupt regardless of the state of the interrupt mask I bit in the condition code register NOTE A software interrupt pushes PC onto the stack A software interrupt does not push PC 1 as a hardware interrupt does 13 6 2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources Table 13 3 summarizes the interrupt sources and the interrupt status register flags that they set The interrupt status registers can be useful for debugging Table 13 3 Interrupt Sources INT Vector Priority Source Flag Mask Register Flag Highest Reset FFFE FFFF SWI instruction m FFFC FFFD IRQ pin IRQF IMASK IF1 Timer channel 0 interrupt CHOF CHOIE IF3 FFF6 FFF7 Timer channel 1 interrupt CH1F CHIIE 4 FFF4 FFF5 Timer overflow interrupt TOF TOIE IF5 FFF2 FFF3 Y Keyboard interrupt KEYF IMASKK IF14 FFEO FFE1 Lowest ADC conversion complete interrupt COCO AIEN IF15 FFDE FFDF 1 The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction MC68HC908QY QT Family Data Sheet Rev 5 112 Freescale Semiconductor Exception Control 13 6 2 1 Interrupt Status Register 1 Address FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 IF5 IF4 IF3 0 IF1 0
57. interrupts are not masked 1 bit clear in the condition code register and if the corresponding interrupt enable bit is set the SIM proceeds with interrupt processing otherwise the next instruction is fetched and executed If more than one interrupt is pending at the end of an instruction execution the highest priority interrupt is serviced first Figure 13 10 demonstrates what happens when two interrupts are pending If an interrupt is pending upon exit from the original interrupt service routine the pending interrupt is serviced before the LDA instruction is executed The LDA opcode is prefetched by both the INT1 and INT2 return from interrupt RTI instructions However in the case of the INT1 RTI prefetch this is a redundant operation NOTE To maintain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode software should save the H register and then restore it prior to exiting the routine MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 111 System Integration Module SIM CLI LDA FF BACKGROUND ROUTINE P INT1 PSHH 2 2 INT1 INTERRUPT SERVICE ROUTINE 2 PSHH EG I INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 13 10 Interrupt Recognition Example 13 6 1 2 SWI Instruction The SWI
58. is divided by two in the SIM to be used as the bus clock for the microcontroller Therefore the bus frequency will be one fourth of the BUSCLKXA frequency 11 2 Features The oscillator has these four clock source options available 1 2 3 4 Internal oscillator An internally generated fixed frequency clock trimmable to 5 This is the default option out of reset External oscillator An external clock that can be driven directly into OSC1 External RC A built in oscillator module RC oscillator that requires an external R connection only The capacitor is internal to the chip External crystal A built in oscillator module XTAL oscillator that requires an external crystal or ceramic resonator 11 3 Functional Description The oscillator contains these major subsystems Internal oscillator circuit Internal or external clock switch control External clock circuit External crystal circuit External RC clock circuit MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 89 Oscillator Module OSC PTAO ADO TCHO KBIO CLOCK 1 1 1 PTA2 IRQ KBI2 TCLK gt lt x OSCILLATOR PTAS RSTIKBI3 2 P
59. must be greater than the LVI s turn on time to avoid a period in startup where the LVI is not protecting the MCU STOP STOP Instruction Enable Bit STOP enables the STOP instruction 1 STOP instruction enabled 0 STOP instruction treated as illegal opcode COPD COP Disable Bit COPD disables the COP module 1 COP module disabled 0 2 COP module enabled MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 55 GEE Configuration Register CONFIG MC68HC908QY QT Family Data Sheet Rev 5 56 Freescale Semiconductor Chapter 6 Computer Operating Properly COP 6 1 Introduction The computer operating properly COP module contains a free running counter that generates a reset if allowed to overflow The COP module helps software recover from runaway code Prevent a COP reset by clearing the COP counter periodically The COP module can be disabled through the COPD bit in the configuration 1 CONFIG1 register 6 2 Functional Description BUSCLKX4 gt 12 BIT SIM COUNTER RESET CIRCUIT a RESET STATUS REGISTER Ce lt E n 2 z E lt 2 ui lt o STOP INSTRUCTION o a 2 INTERNAL RESET SOURCES 5 e COPCTL WRITE COP CLOCK COPEN FROM SIM 6 BIT COP COUNTER COP DISABLE COPD FROM CONFIG1 RESET CLEAR COPCTL WRITE COP COUNTER COP RATE SELECT 5 T COPRS FROM CONFIG1 Figure 6 1 COP Block Diagram MC68HC90
60. object code with M68HC05 Family e 5 V and 3 V operating voltages Vpp 8 MHz internal bus operation at 5 V 4 MHz at 3 V Trimmable internal oscillator 3 2 MHz internal bus operation 8 bit trim capability allows 0 4 accuracy 25 untrimmed e Auto wakeup from STOP capability e Configuration CONFIG register for MCU configuration options including Low voltage inhibit LVI trip point e In system FLASH programming FLASH security 1 The oscillator frequency is guaranteed to 5 over temperature and voltage range after trimming 2 No security feature is absolutely secure However Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 17 General Description On chip in application programmable FLASH memory with internal program erase voltage generation 68 9080 4 and 68 9080 4 4096 bytes MC68HC908QY2 MC68HC908QY 1 MC68HC908QT2 and MC68HC908QT1 1536 bytes 128 bytes of on chip random access memory RAM 2 channel 16 bit timer interface module TIM 4 channel 8 bit analog to digital converter ADC on MC68HC908QY2 MC68HC908QYA4 MC68HC908QT2 and MC68HC908QT4 5 or 13 bidirectional input output I O lines and one input only Six shared with keyboard interrupt function and ADC Two shared with timer channels One shared with external interrupt IRQ
61. of 3 Revision 252 Date Level Description Number s Reformatted to meet current documentation standards Throughout 6 3 1 BUSCLKX4 Clarified description of BUSCLKX4 58 Chapter 7 Central Processor Unit CPU In 7 7 Instruction Set Summary Reworked definitions for STOP instruction 70 Added WAIT instruction 71 4 0 13 8 1 SIM Reset Status Register Clarified SRSR flag setting 117 14 9 1 TIM Status and Control Register Added information to TSTOP note 127 16 8 5 V Oscillator Characteristics Added values for deviation from trimmed 155 inernal oscillator 16 12 3 V Oscillator Characteristics Added values for deviation from trimmed 158 inernal oscillator Figure 5 2 Configuration Register 1 CONFIG1 Clarified bit definitions for 54 COPRS July Chapter 8 External Interrupt IRQ Reworked for clarification 79 2005 50 11 3 4 RC Oscillator Improved RC oscillator wording 93 12 1 Introduction Added note pertaining to non bonded port pins 97 17 3 Package Dimensions Updated package information 165 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor List of Chapters Chapter 1 General Description 17 Ghapter 2 MEMO a ee ee eT 5 22 115 7717 71121215 1T 25 Chapter Analog to Digital Converter 41 Chapter 4 Auto Wakeup Module AW
62. operation See Table 14 3 1 Unbuffered output compare PWM operation 0 Input capture operation MC68HC908QY QT Family Data Sheet Rev 5 130 Freescale Semiconductor Input Output Registers When ELSxB A 00 this read write bit selects the initial output level of the TCHx pin see Table 14 3 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit set the TSTOP and TRST bits in the TIM status and control register TSC Table 14 3 Mode Edge and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration X 0 0 0 Pin under port control initial output level high Output preset 1 0 0 Pin under port control initial output level low 0 0 0 1 Capture on rising edge only 0 0 1 0 Input capture Capture on falling edge only 0 0 1 1 Capture on rising or falling edge 0 1 0 0 Software compare only 0 1 0 1 Output compare Toggle output on compare 0 1 1 0 or PWM Clear output on compare 0 1 1 1 Set output on compare 1 X 0 1 Buffered output Toggle output on compare 1 X 1 0 compare or Clear output on compare 1 X 1 1 buffered PWM Set output on compare ELSxB and ELSxA Edge Level Select Bits When channel x is an input capture channel these read write bits control the active edge sensing logic on channel x When channel x is an outpu
63. oscillator By measuring the period of the internal clock and adjusting this factor accordingly the frequency of the internal clock can be fine tuned Increasing decreasing this factor by one increases decreases the period by approximately 0 2 of the untrimmed period the period for TRIM 80 The trimmed frequency is guaranteed not to vary by more than 5 over the full specified range of temperature and voltage The reset value is 80 which sets the frequency to 12 8 MHz 3 2 MHz bus speed 25 MC68HC908QY QT Family Data Sheet Rev 5 96 Freescale Semiconductor Chapter 12 Input Output Ports PORTS 12 1 Introduction The MC68HC908QT1 MC68HC908QT2 and MC68HC908QTA have five bidirectional input output I O pins and one input only pin The MC68HC908QY 1 MC68HC908QY2 and MC68HC908QYA4 have thirteen bidirectional pins and one input only All pins are programmable as inputs or outputs NOTE Connect any unused pins to an appropriate logic level either or Vas Although the I O ports do not require termination for proper operation termination reduces excess current consumption and the possibility of electrostatic damage 8 pin devices have non bonded pins These pins should be configured either as outputs driving low or high or as inputs with internal pullups enabled Configuring these non bonded pins in this manner will prevent any excess current consumption caused by floating inputs 12 2 Port A P
64. peripherals and other chips within a system built around the MCU All internal reset sources actively pull the RST pin low for 32 BUSCLKXA cycles to allow resetting of external peripherals The internal reset signal IRST continues to be asserted for an additional 32 cycles see Figure 13 4 An internal reset can be caused by an illegal address illegal opcode COP time out LVI or POR see Figure 13 5 IRST RST RST PULLEDLOWBY MCU 32 CYCLES lt 5 4 32 CYCLES BUSCLKX4 m Figure 13 4 Internal Reset Timing MC68HC908QY QT Family Data Sheet Rev 5 106 Freescale Semiconductor Reset and System Initialization ILLEGAL ADDRESS RST 4 ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI 4 Figure 13 5 Sources of Internal Reset Table 13 2 Reset Recovery Timing Reset Recovery Type Actual Number of Cycles POR LVI 4163 4096 64 3 All others 67 64 3 13 4 2 1 Power On Reset When power is first applied to the MCU the power on reset module POR generates a pulse to indicate that power on has occurred The SIM counter counts out 4096 BUSCLKXA cycles Sixty four BUSCLKX4 cycles later the CPU and memories are released from reset to allow the reset vector sequence to occur At power on the following events occur A POR pulse is generated The internal reset signal is
65. read 0 The BIH and BIL instructions will behave as if the IRQ pin is enabled regardless of the settings in the configuration register See Chapter 5 Configuration Register CONFIG The COP module is disabled in forced monitor mode Any reset other than a power on reset POR will automatically force the MCU to come back to the forced monitor mode 15 3 1 3 Monitor Vectors In monitor mode the MCU uses different vectors for reset SWI software interrupt and break interrupt than those for user mode The alternate vectors are in the FE page instead of the FF page and allow code execution from the internal monitor firmware instead of user code NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power on reset POR Pulling RST when RST pin available low will not exit monitor mode in this situation Table 15 2 summarizes the differences between user mode and monitor mode regarding vectors MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 143 Development Support Table 15 2 Mode Difference Functions Modes Reset Reset Break Break SWI SWI Vector High Vector Low Vector High Vector Low Vector High Vector Low User FFFE FFFF FFFC FFFD FFFC FFFD Monitor FEFE FEFF FEFC FEFD FEFC FEFD 15 3 1 4 Data Format Communication with the monitor ROM is in standard non return to zero NRZ mark space data format Transmit an
66. register When a CPU generated address matches the contents of the break address registers the break interrupt is generated A return from interrupt instruction in the break routine ends the break interrupt and returns the microcontroller unit MCU to normal operation Figure 15 2 shows the structure of the break module MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 133 Development Support PTAO ADO TCHO KBIO CLOCK PTA1 AD1 TCH1 KBI gt BENER TOR PTAZ IRQKBIZ TCLK lt OSCILLATOR 5 gt 4 08 2 2 4 SYSTEM INTEGRATION MODULE 5 8 1 3 4 9 68 08 CPU SINGLE INTERRUPT 0 4 gt MODULE PTB1 2 lt gt 2 BREAK 4 _ gt MODULE PTB5 6 lt gt c POWER ON RESET PTB7 ODULE MC68HC908QY4 AND MC68HC908QT4 KEYBOARD INTERRUPT 8 BIT ADC 4096 BYTES ODULE MC68HC908QY2 MC68HC908QY1 MC68HC908QT2 AND MC68HC908QT1 1536 BYTES 16 BIT TIMER ODULE 128 BYTES RAM ODULE 4 Vpp POWER SUPPLY dub MONITOR ROM I Vss RST IR
67. requests are treated as regular keyboard interrupt requests with the difference that instead of a pin the interrupt signal is generated by an internal logic Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input see Figure 4 1 A logic 1 applied to the AWUIREQ input with auto wakeup interrupt request enabled latches an auto wakeup interrupt request Auto wakeup latch AWUL can be read directly from the bit 6 position of port A data register PTA This is a read only bit which is occupying an empty bit position on No associated registers such as data direction or pullup exist for this bit Entering stop mode will enable the auto wakeup generation logic An internal RC oscillator exclusive for the auto wakeup feature drives the wakeup request generator Once the overflow count is reached in the generator counter a wakeup request AWUIREQ is latched and sent to the KBI logic See Figure 4 1 Wakeup interrupt requests will only be serviced if the associated interrupt enable bit AWUIE in KBIER is set The AWU shares the keyboard interrupt vector The overflow count can be selected from two options defined by the COPRS bit in CONFIG1 This bit was borrowed from the computer operating properly COP using the fact that the COP feature is idle no MCU clock available in stop mode The typical values of the periodic wakeup request are at room temp
68. the stack by subtracting one from it 1 Wait mode was exited by break interrupt 0 Wait mode was not exited by break interrupt MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 137 Development Support 15 2 2 5 Break Flag Control Register The break control register BFCR contains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset 0 R Reserved Figure 15 8 Break Flag Control Register BFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break 15 2 3 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes If enabled the break module will remain enabled in wait and stop modes However since the internal address bus does not increment in these modes a break interrupt will never be triggered 15 3 Monitor Module MON This subsection describes the monitor module MON and the monitor mode entry methods The monitor allows debugging and programming of the microcontroller unit MCU through a single wire interface with a host computer Monitor mo
69. the reset vector is blank and monitor mode is entered the chip will see an additional reset cycle after the initial power on reset POR Once the reset vector has been programmed the traditional method of applying a voltage to IRQ must be used to enter monitor mode If monitor mode was entered as a result of the reset vector being blank the COP is always disabled regardless of the state of IRQ If the voltage applied to the IRQ is less than the MCU will come out of reset in user mode Internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased FF When the MCU comes out of reset it is forced into monitor mode without requiring high voltage on the IRQ pin Once out of reset the monitor code is initially executing with the internal clock at its default frequency If IRQ is held high all pins will default to regular input port functions except for PTAO and which will operate as a serial communication port and OSC1 input respectively refer to Figure 15 10 That will allow the clock to be driven from an external source through OSC1 pin If IRQ is held low all pins will default to regular input port function except for PTAO which will operate as serial communication port Refer to Figure 15 11 Regardless of the state of the IRQ pin it will not function as a port input pin in monitor mode Bit 2 of the Port A data register will always
70. to 0 by a power on reset POR only COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 09 0 0 0 1 One time writable register after each reset 2 LVI5OR3 reset to 0 by a power on reset POR only TOF 0 0 TOIE TSTOP 2 PS1 PSO 0 TRST 0 0 1 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 2 of 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Addr 0022 0023 0024 0025 0026 0027 0028 0029 0036 0037 0038 Input Output Section Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM Counter Register Low Read Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNTL Write See page 128 Reset 0 0 0 0 0 0 0 0 Read we 8115 884 Bit 10 Bit 9 Bit 8 egister Hig rite See page 129 1 1 1 1 1 1 Read Eee INDE s Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 egister Low rite See page 129 Reset 1 1 1 1 1 1 1 1 Read CHOF 5 a ee CHOIE MSOB MSOA ELSOB ELSOA TOVO CHOMAX See page 130 0 0 0 0 0 0 0 0 Read aaa Ca wite BU Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 egister Hig rite page 132 Reset Indeterminate after reset Read
71. 0 0 0 1 0 ADC2 4 0 0 0 1 1 5 0 0 1 0 0 1 1 Unused 1 1 0 1 0 1 1 0 1 1 Reserved 1 1 1 0 0 Unused 1 1 1 0 1 Vppa 1 1 1 1 0 1 1 1 1 1 m ADC power off If any unused channels are selected the resulting ADC conversion will be unknown The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in produc tion test and for user applications MC68HC908QY QT Family Data Sheet Rev 5 46 Freescale Semiconductor Input Output Registers 3 7 2 ADC Data Register One 8 bit result register is provided This register is updated each time an ADC conversion completes Address 003E Bit 7 6 5 4 3 2 1 Bit 0 Read AD7 AD6 AD5 AD4 AD2 AD1 ADO Write Reset Indeterminate after reset Unimplemented Figure 3 4 ADC Data Register ADR 3 7 3 ADC Input Clock Register This register selects the clock frequency for the ADC Address 003F Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 ADIV2 ADIV1 ADIVO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 3 5 ADC Input Clock Register ADICLK ADIV2 ADIVO ADC Clock Prescaler Bits ADIV2 ADIV1 and ADIVO form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC cl
72. 1 Unimplemented j Read ADC Data Register 7 Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR Write See page 47 Reset Indeterminate after reset i Read 0 0 0 0 0 ADC Input Clock Register i ADIV2 ADIV1 ADIVO ADICLK Write 47 Reset 0 0 0 0 0 0 0 0 Read SBSW Break Status Register BSR Write See note 1 See page 137 Reset 0 1 Writing a 0 clears SBSW SIM Reset Status Register Read PIN COP ILOP MODRST LVI 0 SRSR Write 117 pop 1 0 Tm Read 0 Break Auxiliary i Register BRKAR Write See page 137 Reset 0 0 0 0 0 0 0 0 Read Break Flag Control Register Write See page 138 Reset 0 Interrupt Status Register 1 Read 0 IFS 4 0 0 0 INT1 Write R R R R R R R R See 77 Reset 0 0 0 0 0 0 0 0 Interrupt Status Register Read IF14 0 0 0 0 0 0 0 INT2 Write R R R R R R R R 77 Reset 0 0 0 0 0 0 0 0 Interrupt Status Register 3 Read 0 0 0 0 0 0 0 15 INT3 Write R R R R R R R R 77 Reset 0 0 0 0 0 0 0 0 Reserved R R R R R R R R Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 4 of 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Addr FE08 FE09 FEOA FFBE FFBF FFCO FFC1 FFFF Input Output
73. 1 Bit 0 Read Write Reset Unaffected by reset Figure 7 2 Accumulator A 7 3 2 Index Register The 16 bit index register allows indexed addressing of a 64 Kbyte memory space H is the upper byte of the index register and X is the lower byte H X is the concatenated 16 bit index register In the indexed addressing modes the CPU uses the contents of the index register to determine the conditional address of the operand The index register can serve also as a temporary data storage location Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write Ree 0 0 0 0 0 0 0 0 X X X X X X X X X Indeterminate Figure 7 3 Index Register H X MC68HC908QY QT Family Data Sheet Rev 5 62 Freescale Semiconductor CPU Registers 7 3 3 Stack Pointer The stack pointer is a 16 bit register that contains the address of the next location on the stack During a reset the stack pointer is preset to 00FF The reset stack pointer RSP instruction sets the least significant byte to FF and does not affect the most significant byte The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack In the stack pointer 8 bit offset and 16 bit offset addressing modes the stack pointer can function as an index register to access data on the stack The CPU uses the contents of the stack pointer to determine the conditional address of the ope
74. 13 8 1 SIM Reset Status Register The SRSR register contains flags that show the source of the last reset The status register will automatically clear after reading SRSR A power on reset sets the POR bit and clears all other bits in the register All other reset sources set the individual flag bits but do not clear the register More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset For example the POR and LVI bit can both be set if the power supply has a slow rise time Address FEO1 Bit 7 6 5 4 3 2 1 Bit 0 Read PIN COP ILOP ILAD MODRST LVI 0 Write POR 1 0 0 0 0 0 0 0 Unimplemented Figure 13 19 SIM Reset Status Register SRSR POR Power On Reset Bit 1 Last reset caused by POR circuit 0 Read of SRSR PIN External Reset Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode Reset Bit 1 Last reset caused an illegal opcode 0 POR or read of SRSR ILAD Illegal Address Reset Bit illegal attempt to fetch an opcode from an unimplemented address 1 Last reset caused by an opcode fetch from an illegal address 0 POR or read of SRSR MODRST Monitor Mode Entry Module Reset Bit 1 Last reset caused by monitor mode entry when v
75. 38 dd 4 ASLA 4 INH 48 1 ASLX Arithmetic Shift Left INH 58 1 ASL Same as LSL Che iia al 68 ff 4 ASL X b7 bO IX 78 3 ASL opr SP SP1 9E68 ff 5 ASR opr DIR 37 dd 4 ASRA gt INH 47 1 ASRX ES INH 57 1 ASR opr X Arithmetic Shift Right gt C 1 1111 X1 67 4 ASR b7 50 77 3 ASR opr SP SP1 9E67 5 BCC rel Branch if Carry Bit Clear PC lt 2 rel 20 REL 24 jrr 3 DIR 60 11 dd 4 DIR 61 13 dd 4 DIR b2 15 dd 4 i DIR b3 17 dd 4 BCLR n opr Clear Bit n in M Mn 0 1 1 1 DIR 4 19 dd 4 DIR b5 1B dd 4 DIR b6 1D dd 4 DIR b7 dd 4 BCS rel Branch if Carry Bit Set Same as BLO PC lt 2 rel 1 REL 25 3 BEQ rel Branch if Equal PC lt PC 2 rel 2 1 REL 27 3 Branch if Greater Than or Equal To BGE opr Signed Operands lt PC 2 rel NO V 20 REL 90 rr 3 Branch if Greater Than Signed BGT opr Operands Sig PC lt 2 rel Z NO V 0 REL 92 ir 3 BHCC rel Branch if Half Carry Bit Clear lt PC 2 rel 0 REL 28 3 BHCS rel Branch if Half Carry Bit Set PC lt PC 2 rel 1 REL 29 jrr 3 BHI Branch if Higher lt 2 rel 1 2 0 REL 22 3 66 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Instruction Set Summary Table 7 1 Instruction Set Summary Sheet 2 of 6
76. 5 to the TIM counter modulo registers produces PWM period of 256 times the internal bus clock period if the prescaler select value is 000 See 14 9 1 TIM Status and Control Register The value in the TIM channel registers determines the pulse width of the PWM output The pulse width of an 8 bit PWM signal is variable in 256 increments Writing 0080 128 to the TIM channel registers produces a duty cycle of 128 256 or 5096 OVERFLOW OVERFLOW OVERFLOW 4 PERIOD gt gt a POLARITY 1 ELSxA 0 PULSE 46 POLARITY 0 y NEM ELSxA 1 1 OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 14 3 PWM Period and Pulse Width MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 123 Timer Interface Module TIM 14 4 4 1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 14 4 4 Pulse Width Modulation PWM The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period Also using a
77. 68HC908QT1 1536 BYTES 128 BYTES RAM USER FLASH POWER SUPPLY Vpop gt Vss RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up PTB 0 7 Not available 8 pin devices MC68HC908QT1 MC68HC908QT2 MC68HC908QTA see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT1 CLOCK GENERATOR OSCILLATOR SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER ON RESET MODULE KEYBOARD INTERRUPT MODULE 16 BIT TIMER MODULE COP MODULE MONITOR ROM Figure 8 1 Block Diagram Highlighting IRQ Block and Pins When set the IMASK bit in INTSCR masks the IRQ interrupt request A latched interrupt request is not presented to the interrupt priority logic unless IMASK is clear NOTE The interrupt mask 1 in the condition code register CCR masks all interrupt requests including the IRQ interrupt request A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch An IRQ vector fetch software clear or reset clears the IRQ latch 74 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Functional Description
78. 68HC908QT4 KEYBOARD INTERRUPT 8 BIT ADC C3 4096 BYTES MODULE MC68HC908QY2 MC68HC908QY1 MC68HC908QT2 AND MC68HC908QT1 1536 BYTES 16 BIT TIMER MODULE 128 BYTES RAM Co USER FLASH LI COP Aet i MODULE 4 Vpp POWER SUPPLY MONITOR ROM L Vss RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up 0 7 Not available on 8 pin devices MC68HC908QT1 MC68HC908QT2 MC68HC908QT4 see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT 1 Figure 1 1 Block Diagram MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Vop 1 d Vss 5 0801 2 7 PTAO TCHO KBIO PTA4 OSC2 KBI4 3 6 PTA1 TCH1 KBI1 PTAS RST KBI3 4 5 PTAZ IRQ KBIZ TCLK 8 PIN ASSIGNMENT MC68HC908QT1 PDIP SOIC Pin Assignments Voo 1 8 Vss 5 08 1 2 7 1 PTAO ADO TCHO KBIO PTA4 OSC2 AD2 KBM 6 PTA1 AD1 TCH1 KBI1 PTAS RST KBIS 4 5 PTA2 RO KBI2 TCLK 8 PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 PDIP SOIC 2 Vpp 1 16 __ Vss PTB7 2 15 PTBO PTB6 3 14 PTB1
79. 80 19 55 740 0 770 B 6 35 6 85 250 0 270 C 3 69 4 44 145 0 175 D 0 39 0 53 0 015 0 021 F 1 02 i 0 040 0 070 B 2 54 BSC 0 100 BSC H 1 22 RG 0 050 BSC j 0 21 0 38 008 0 015 2 80 5 50 0 110 0 130 L 7 50 135 295 0 305 0 10 0 107 5 0 51 1 01 0 020 0 040 TITLE CASE NUMBER 648 08 To LE FBIP STANDARD NON JEDEC PACKAGE CODE 0006 SHEET 2 OF 4 MECHANICAL OUTLINES freescale DICTIONARY semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY IN RED 8x 10 55 10 05 0 25 0 10 16 0 49 0 35 0 25 E 14X LN SECTION 16 0 5016 W amp 10 87 senec wsom CASE OUTLINE PACKAGE CODE 2003 SHEET 1 OF 3 MECHANICAL OUTLINES DOCUMENT NO 98ASB42567B freescale DICTIONARY AGE E EESCALE SEMICONDUCTOR ind ALL RIGHTS RESERVED imr menm m Do NOT SCALE THIS DRAWING REV NOTES 1 DIMENSIONS ARE IN MILLIMETERS DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY THIS DIMENSION DOES NOT INCLUDE MOLD FLASH PROTRUSION OR GATE BURRS MOLD FLASH PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0 15 MM PER SIDE THIS
80. 8HC908QY4 TSSOP PTAO ADO TCHO KBIO PTA1 AD1 TCH1 KBI1 Vss PTA2 IRO KBI2 TCLK 5 PTAB OSC1 AD3 KB15 PTA4 OSC2 AD2 KBI4 8 PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 DFN Figure 1 2 MCU Pin Assignments MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 21 General Description 1 5 Pin Functions Table 1 2 provides a description of the pin functions Table 1 2 Pin Functions Description Input Output Power supply Power Vss Power supply ground Power PTAO General purpose port Input Output ADO A D channel 0 input Input PTAO TCHO Timer Channel 0 I O Input Output KBIO Keyboard interrupt input O Input PTA1 General purpose port Input Output AD1 A D channel 1 input Input PTA1 TCH1 Timer Channel 1 Input Output Keyboard interrupt input 1 Input PTA2 General purpose input only port Input IRQ External interrupt with programmable pullup and Schmitt trigger input Input KBI2 Keyboard interrupt input 2 Input TCLK Timer clock input Input General purpose I O port Input Output RST Reset input active low with internal pullup and Schmitt trigger Input KBI3 Keyboard interrupt input 3 Input PTA4 General purpose port Input Output OSC2 XTAL oscillator output XTAL option only Output PTA4 RC
81. 8QY QT Family Data Sheet Rev 5 Freescale Semiconductor 155 Electrical Specifications 16 10 Typical 3 0 V Output Drive Characteristics 1 5 e 3V 3V PTB ea S 05 0 0 0 5 10 15 20 IOH mA Figure 16 5 Typical 3 Volt Output High Voltage versus Output High Current 25 C 1 5 1 0 e 3V o E 3V gt 0 5 0 0 10 IOL mA 156 Figure 16 6 Typical 3 Volt Output Low Voltage versus Output Low Current 25 C MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 16 11 3 V Control Timing 3 V Control Timing Characteristic Symbol Min Max Unit Internal operating frequency 4 MHz Internal clock period 1 fop 250 ns RST input pulse width low tn 200 ns IRQ interrupt pulse width low edge triggered 200 ns IRQ interrupt pulse period tru Note 1 Vpp 2 7 to 3 3 Vss 0 TA T to Ty timing shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 lt LH Figure 16 7 RST and IRQ Timing MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 157 Electrical Specifications 16 12 3 V Oscillator Character
82. 8QY QT Family Data Sheet Rev 5 Freescale Semiconductor 57 Computer Operating Properly COP The COP counter is a free running 6 bit counter preceded by the 12 bit system integration module SIM counter If not cleared by software the COP counter overflows and generates an asynchronous reset after 262 128 or 8176 BUSCLKXA cycles depending on the state of the COP rate select bit COPRS in configuration register 1 With a 262 128 BUSCLKXA cycle overflow option the internal 12 8 MHz oscillator gives a COP timeout period of 20 48 ms Writing any value to location FFFF before an overflow occurs prevents COP reset by clearing the COP counter and stages 12 5 of the SIM counter NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow A COP reset pulls the RST pin low if the RSTEN bit is set in the CONFIG1 register for 32 BUSCLKX4 cycles and sets the COP bit in the reset status register See 13 8 1 SIM Reset Status Register NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly 6 3 Signals The following paragraphs describe the signals shown in Figure 6 1 6 3 1 BUSCLKX4 BUSCLKXA is the oscillator output signal BUSCLKXA frequency is equal to the intern
83. AEODERD ness 49 WA aod e aee cO Ope 50 LO T p 50 Ee IE EE Id 51 PORAT PETO E renerne a eaa a te 51 Keyboard Status and Control 5 51 Keyboard 52 5 Configuration Register CONFIG Iri ci dee ROC EE ERU CR UR OR de dodo arc acd b ded oC ded ode 53 vesens olas dedo 53 Chapter 6 Computer Operating Properly COP a bcr o e ek do i o C eR dO e AER Ee o od oo a e e 57 57 58 aceon dt 58 STOP We Ol 58 58 25d d abs on dc E odi ii pad Bees d 58 nad eae CORR 58 COPD COP Disable perti o eia dct dtp dri dra 58 CP ris Rate Selon i idus rro ted AO CR Rd o d ORC KR ae d 59 59 dE od 59 UP 59 Los Power MOQES
84. ANI paq 8 ueuJeJ9u 1504 1950 19 91 pepueix4 1 3 951 UUM ON pexepu SHO 19 8 LXI ula epoodo eig 0 1950 18 91 2816 246 ON pexepu WNI asi 1950 8 2715 LdS HNI XI 1145 IX 245 v 1X3 c XI 1145 IXI HN L HNI HH XLS XLS XLS XLS XLS XLS XLS XIV VXL LIVM 419 419 x410 419 29199 Zu 10H8 2 v 6 6 v v 5 2 v g 1 5 v 6 XI 45 1 24858 t 1X3 6 c HNI 2 aw 6 xdi 4015 AOW AOW AOW AOW 2119589 Z13SHH 3 v S v v 5 v v v S v S Xl z HN XI 145 j IXI z HN L HN L uia usr ysr ysr ysr ysr ysg dON 181 151 161 XLSL 181 941028 99410849 v S 9 S v v 4 v 5 5 6 v S XI 1X3 c HN L HN XI 1495 IXI z HN L HN L wld VONI ong 91454 91 5 5 14 6 5 S v L 14 6 v S XI 19 245 1X3 HN L HN XI 21145 IXI
85. Be careful when using nested subroutines The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation MC68HC908QY QT Family Data Sheet Rev 5 32 Freescale Semiconductor FLASH Memory FLASH 2 6 FLASH Memory FLASH This subsection describes the operation of the embedded FLASH memory The FLASH memory can be read programmed and erased from a single external supply The program and erase operations are enabled through the use of an internal charge pump The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors The minimum size of FLASH memory that can be erased is 64 bytes and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes a row Program and erase operations are facilitated through control bits in the FLASH control register FLCR Details for these operations appear later in this section The address ranges for the user memory and vectors are e FDFF user memory 4096 bytes 68 9080 4 and MC68HC908QT4 e F800 FDFF user memory 1536 bytes MC68HC908QY2 MC68HC908QT2 MC68HC908QY 1 and MC68HC908QT 1 e FFDO FFFF user interrupt vectors 48 bytes NOTE An erased bit reads as 1 and a programmed bit reads as 0 A security feature prevents viewing of the FLASH contents 2 6 1 FLASH Control Register The FLASH control register FLCR controls FLASH program and erase operatio
86. CEN TO OSCILLATOR SIM COUNTER COP CLOCK BUSCLKX4 FROM OSCILLATOR BUSCLKX2 FROM OSCILLATOR 2 Vpp T Y Y CLOCK GENERATORS L gt INTERNAL CLOCKS INTERNAL PULL UP BERET ILLEGAL OPCODE FROM CPU POR CONTROL ILLEGAL ADDRESS FROM ADDRESS PIN LOGIC MASTER DECODERS RESET PIN CONTROL 21 I COP TIMEOUT FROM COP MODULE SIM RESET STATUS REGISTER I LVI RESET FROM LVI MODULE 4 FORCED MON MODE ENTRY FROM MENRST MODULE RESET NTERRUPTCONTROL INTERRUPT SOURGES AND PRIORITY DECODE lt CPU INTERFACE Figure 13 1 SIM Block Diagram 13 2 RST and Pins Initialization RST and IRQ pins come out of reset as PTA3 and respectively RST and IRQ functions can be activated by programing CONFIG2 accordingly Refer to Chapter 5 Configuration Register CONFIG 13 3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU The system clocks are generated from an incoming clock BUSCLKX2 as shown in Figure 13 2 MC68HC908QY QT Family Data Sheet Rev 5 104 Freescale Semiconductor Reset and System Initialization FROM BUSCLKX4 OSCILLATOR SIM COUNTER FROM BUSCLKX2 2 BUS CLOCK OSCILLATOR GENERATORS SIM Figure 13 2 SIM Clock Signals 13 3 1 Bus Timing In user mode the internal bus frequency is the oscillator frequency BUSCLKXA divided by four
87. CPU SINGLE INTERRUPT PTBO a MODULE 1 4 gt PTB2 2 BREAK 8 MODULE 5 lt gt 2 POWER ON 7 MODULE MC68HC908QY4 MC68HC908QT4 KEYBOARD INTERRUPT KOX 4096 5 MODULE MC68HC908QY2 68 908 1 MC68HC908QT2 AND MC68HC908QT1 1536 BYTES ES 128 BYTES RAM Co USER FLASH COP 7 MODULE Vpp POWER SUPPLY eae H Vas RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up PTB 0 7 Not available on 8 pin devices MC68HC908QT1 MC68HC908QT2 and MC68HC908QTA see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT1 Figure 3 1 Block Diagram Highlighting ADC Block and Pins MC68HC908QY QT Family Data Sheet Rev 5 42 Freescale Semiconductor Functional Description INTERNAL DATA BUS WY READ DDRA WRITE DDRA DISABLE DDRAx e WRITE PTA PTAx ADCx READ PTA 9 DISABLE ADC CHANNEL x ADC DATA REGISTER Y ADC VOLTAGE IN ADCVIN CHANNEL SELECT CH 4 0 1 OF 4 CHANNELS CONVERSION INTERRUPT COMPLETE LOGIC ADC CLOCK AIEN COCO
88. Ci 13 14 NC Vpp 15 16 NC The rising edge of the internal RST signal latches the monitor mode Once monitor mode is latched the values on PTA1 and 4 pins can be changed Once out of reset the MCU waits for the host to send eight security bytes see 15 3 2 Security After the security bytes the MCU sends a break signal 10 consecutive logic Os to the host indicating that it is ready to receive a command 15 3 1 1 Normal Monitor Mode RST and 5 1 functions will be active on the PTA3 and PTAS pins respectively as long is applied to the IRQ pin If the IRQ pin is lowered no longer then the chip will still be operating in monitor mode but the pin functions will be determined by the settings in the configuration registers see Chapter 5 Configuration Register CONFIG when was lowered With lowered the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register MC68HC908QY QT Family Data Sheet Rev 5 142 Freescale Semiconductor Monitor Module MON If monitor mode was entered with then the COP is disabled as long as is applied to IRQ 15 3 1 2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ then startup port pin requirements and conditions PTA1 PTAA are not in effect This is to reduce circuit requirements when performing in circuit programming NOTE If
89. EG dE 59 Wal MOdS 25098444 59 SLE MOE obo VS Rd ED 59 Module During Break Mode 59 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 7 1 T2 7 3 7 3 1 7 3 2 7 3 3 7 3 4 7 3 5 7 4 7 5 7 5 1 7 5 2 7 6 7 8 8 1 8 2 8 3 8 3 1 8 3 2 8 4 8 5 8 5 1 8 5 2 8 6 8 7 8 7 1 8 8 9 1 9 2 9 3 9 3 1 9 3 2 9 4 9 5 8 8 Chapter 7 Central Processor Unit CPU We adds da wd 61 i s tor E TE 61 OPRU 61 li pP 62 EET 62 63 63 Condition Code 64 65 Low Power 65 65 65 D ring Break I prr 65 Ser SUMMAN eo Ro SERO X REC e o AA 66 Lo 71 Chapter 8 External Interrupt IRQ ci nio rm 73 iz p rrr 73 guise 73 MODE Ad 75 MODE Fed ep Pi edF Fo dod Eel eed e Ree i 75 NEM M 76 E ad fH EMEN rm 76
90. Eight extra I O lines 16 pin package only High current sink source capability on all port pins Selectable pullups on all ports selectable on an individual bit basis Three state ability on all port pins 6 bit keyboard interrupt with wakeup feature KBI Low voltage inhibit LVI module features Software selectable trip point in CONFIG register System protection features Computer operating properly COP watchdog Low voltage detection with reset Illegal opcode detection with reset Illegal address detection with reset External asynchronous interrupt pin with internal pullup IRQ shared with general purpose input pin Master asynchronous reset pin RST shared with general purpose input output I O pin Power on reset Internal pullups on IRQ and RST to reduce external components Memory mapped registers Power saving stop and wait modes MC68HC908QY4 MC68HC908QY2 and MC68HC908QY1 are available in these packages 16 pin plastic dual in line package PDIP 16 pin small outline integrated circuit SOIC package 16 pin thin shrink small outline package TSSOP MC68HC908QT4 MC68HC908QT2 68 9080 1 are available in these packages 8 pin PDIP 8 pin SOIC 8 dual flat no lead DFN package MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Block Diagram Features of the CPUOS include the following e Enhanced 5 programming mod
91. Enabled Vpp 5 Typical 0 65 mA Enabled 1 Source impedances greater than 10 kQ adversely affect internal RC charging time during input sampling 2 Zero input full scale reading requires sufficient decoupling measures for accurate conversions 3 The external system error caused by input leakage current is approximately equal to the product of R source and input current Freescale Semiconductor MC68HC908QY QT Family Data Sheet Rev 5 161 Electrical Specifications 16 15 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit Timer input capture pulse width trn trL 2 Timer input capture period tru Note Timer input clock pulse width ttc 5 ns 1 The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 toyc lt tnm tty gt lt INPUT CAPTURE RISING EDGE m INPUT CAPTURE FALLING EDGE lt tr tty r tn _ INPUT CAPTURE BOTH EDGES trc 39 Figure 16 11 Timer Input Timing MC68HC908QY QT Family Data Sheet Rev 5 162 Freescale Semiconductor 16 16 Memory Characteristics Memory Characteristics Characteristic Symbol Min Typ Max Unit RAM data retention voltage
92. Features Features of the CPU include e Object code fully upward compatible with M68HCO5 Family e 16 bit stack pointer with stack manipulation instructions 16 bit index register with x register manipulation instructions e 8 MHz CPU internal bus frequency e 64 Kbyte program data memory space e 16 addressing modes e Memory to memory data moves without using accumulator e Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions e Enhanced binary coded decimal BCD data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes e Low power stop and wait modes 7 3 CPU Registers Figure 7 1 shows the five CPU registers CPU registers are not part of the memory map MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 61 Central Processor Unit CPU 7 0 ACCUMULATOR 15 0 X INDEX REGISTER H X STACK POINTER SP PROGRAM COUNTER PC lt z N e CONDITION CODE REGISTER CCR CARRY BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG Figure 7 1 CPU Registers 7 3 1 Accumulator The accumulator is a general purpose 8 bit register The CPU uses the accumulator to hold operands and the results of arithmetic logic operations Bit 7 6 5 4 3 2
93. HC908QY2 68 9080 4 12 3 1 Port B Data Register The port B data register PTB contains a data latch for each of the eight port B pins Address 0001 Bit 7 6 5 4 3 2 1 Bit 0 Read PTB7 PTB6 5 4 2 PTB1 PTBO Write Reset Unaffected by reset Figure 12 5 Port B Data Register PTB PTB 7 0 Port B Data Bits These read write bits are software programmable Data direction of each port B pin is under the control of the corresponding bit in data direction register B Reset has no effect on port B data MC68HC908QY QT Family Data Sheet Rev 5 100 Freescale Semiconductor Port B 12 3 2 Data Direction Register B Data direction register B DDRB determines whether each port B pin is an input or an output Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin a O disables the output buffer Address 0005 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO rite Reset 0 0 0 0 0 0 0 0 Figure 12 6 Data Direction Register B DDRB DDRB 7 0 Data Direction Register B Bits These read write bits control port B data direction Reset clears DDRB 7 0 configuring all port B pins as inputs 1 Corresponding port B pin configured as output 0 Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing d
94. IRQ interrupt requests to bring the MCU out of wait mode 8 5 2 Stop Mode The IRQ module remains active in stop mode Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode 8 6 IRQ Module During Break Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the break flag control register BFCR enables software to clear status bits during the break state See Chapter 13 System Integration Module SIM To allow software to clear status bits during a break interrupt write a 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a 0 to BCFE With BCFE cleared its default state software can read and write registers during the break state without affecting status bits Some status bits have a two step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is cleared After the break doing the second step clears the status bit 8 7 I O Signals The IRQ module shares its pin with the keyboard interrupt input output ports and timer interface modules NOTE When the IRQ function is enabled in the CONFIG2 register the BIH and BIL instructions can be used to read the logic level on the IRQ pin I
95. IX1 68 4 LSL X IX 78 3 LSL opr SP SP1 9 68 ff 5 LSR opr DIR 34 dd 4 LSRA gt INH 44 1 LSH Logical Shift Right 0 1 1914 EHE 3 LSR X b7 bo IX 74 3 LSR oprSP SP1 9 64 5 MON iKa M pestination lt M source Bet ad dd 1 MOV opr opr ove 7 IMD 6E lidd 4 MOV X opr lt H X 1 IX D DIX 04 4 MUL Unsigned multiply lt X x 01 1 1 101 6 42 5 NEGA M 00 M 1 NEGX A INH 50 1 NEG opr X Negate Two s Complement X lt X 00 X 1 111111 1 1 60 f 4 NEG X M M 00 M IX 70 3 NEG opr SP M lt 00 SP1 9E60 ff 5 NOP No Operation None INH 9D 1 NSA Nibble Swap A 3 0 7 4 iNH 62 3 ORA opr IMM AA 2 ORA opr DIR BA dd 3 ORA opr EXT CA 4 ORA IX2 DA 4 ORA opr X Inclusive OR A and M lt A M 1 11111 EA 3 ORA IX FA 2 ORA 5 SP1 9EEA ff 4 ORA opr SP SP2 9EDA ee ff 5 PSHA Push A onto Stack Push A SP lt SP 1 iNH 87 2 PSHH Push H onto Stack Push H SP SP 1 1 1 1 1 1 8B 2 PSHX Push X onto Stack Push X SP SP 1 INH 89 2 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 69 Central Processor Unit CPU Table 7 1 Instruction Set Summary Sheet 5 of 6
96. K PTA2 TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock Select the PTA2 TCLK input by writing 1s to the three prescaler select bits PS 2 0 See 14 9 1 Status and Control Register When the PTA2 TCLK pin is the TIM clock input itis an input regardless of port pin initialization 14 8 2 TIM Channel I O Pins PTAO TCHO and PTA1 TCH1 Each channel I O pin is programmable independently as an input capture pin or an output compare PTAO TCHO can be configured as a buffered output compare or buffered PWM pin 14 9 Input Output Registers The following registers control and monitor operation of the TIM e status and control register TSC counter registers TCNTH TCNTL counter modulo registers TMODH TMODL channel status and control registers TSCO and TSC1 e channel registers TCHOH TCHOL and TCH1H TCH1L MC68HC908QY QT Family Data Sheet Rev 5 126 Freescale Semiconductor Input Output Registers 14 9 1 TIM Status and Control Register The TIM status and control register TSC does the following e Enables TIM overflow interrupts Flags TIM overflows e Stops the TIM counter Resets the TIM counter e Prescales the TIM counter clock Address 0020 Bit 7 6 5 4 3 2 1 Bit 0 Read TOF 0 0 TOIE TSTOP PS2 PS1 50 Write 0 TRST Reset 0 0 1 0 0 0 0 0 Unimplemen
97. M channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 TCH1 is available as a general purpose pin NOTE In buffered output compare operation do not write new output compare values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered output compares 14 4 4 Pulse Width Modulation PWM By using the toggle on overflow feature with an output compare channel the TIM can generate a PWM signal The value in the TIM counter modulo registers determines the period of the PWM signal The channel pin toggles when the counter reaches the value in the TIM counter modulo registers The time between overflows is the period of the PWM signal As Figure 14 3 shows the output compare value in the TIM channel registers determines the pulse width of the PWM signal The time between overflow and output compare is the pulse width Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1 ELSxA 0 Program the to set the pin if the state of the PWM pulse is logic 0 ELSxA 1 The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8 bit PWM signal is variable in 256 increments Writing 25
98. M signal from the linked channels MSOB takes priority over MSOA Clearing the toggle on overflow bit TOVx inhibits output toggles on TIM overflows Subsequent output compares try to force the output to a state it is already in and have no effect The result is 0 duty cycle output Setting the channel x maximum duty cycle bit CHxMAX and setting the TOVx bit generates a 100 duty cycle output See 14 9 4 TIM Channel Status and Control Registers 14 5 Interrupts The following TIM sources can generate interrupt requests TIM overflow flag TOF The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers The TIM overflow interrupt enable bit TOIE enables TIM overflow CPU interrupt requests TOF and TOIE are in the TIM status and control register TIM channel flags CH1F CHOF The bit is set when an input capture or output compare occurs on channel x Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit CHxIE Channel x TIM CPU interrupt requests are enabled when 1 CHxF and CHXxIE are in the TIM channel x status and control register MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 125 Timer Interface Module TIM 14 6 Wait Mode The WAIT instruction puts the MCU in low power consumption standby mode The TIM remains active after the execution of a WAIT instruction In wait mode the TIM registers a
99. MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet 68 08 Microcontrollers MC68HC908QY4 D ev 07 2005 freescale com freescale 68 9080 4 68 9080 4 68 9080 2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy may be an earlier revision To verify you have the latest information available refer to http freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Revision History The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Revision History Sheet 1 of 3 Revision Page Date Level Description Number s September T 2002 N A Initial release N A 1 2 Features Added 8 pin dual flat no lead DFN packages to features list 19 Figure 1 2 MCU Pin Assignments Figure updated to include DFN packages 21 Figure 2 1 Memory Map Clarified illegal add
100. Maximum current for pins PTAO PTA5 25 Storage temperature 55 to 150 Maximum current out of Vss IMvss 100 mA Maximum current into Vpp IMVDD 100 mA 1 Voltages references to Vas NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that Vj and be constrained to the range Vss lt Vout lt Vpp Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either Vss or Vpp MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 149 Electrical Specifications 16 3 Functional Operating Range Characteristic Symbol Value Unit Temp Code 40 to 125 M Operating temperature range TA 40 to 105 C V 40 to 85 C Operating voltage range Vpp 2 7 to 5 5 V 16 4 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 8 pin PDIP 105 8 pin SOIC 142 8 pin DEN 173 C W 16 pin PDIP 76 16 pin SOIC 90 16 pin TSSOP 133 pin power dissipation User determined Pp Ipp X Vpp issipation P Power dissipation D Pyo
101. NTL value until TCNTL is read Reset clears the TIM counter registers Setting the TIM reset bit TRST also clears the TIM counter registers NOTE If you read TCNTH during a break interrupt be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt Otherwise TCNTL retains the value latched during the break Address 0021 TCNTH Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Address 0022 TCNTL Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 5 TIM Counter Registers TCNTH TCNTL MC68HC908QY QT Family Data Sheet Rev 5 128 Freescale Semiconductor Input Output Registers 14 9 3 TIM Counter Modulo Registers The read write TIM modulo registers contain the modulo value for the TIM counter When the TIM counter reaches the modulo value the overflow flag TOF becomes set and the TIM counter resumes counting from 0000 at the next timer clock Writing to the high byte TMODH inhibits the TOF bit and overflow interrupts until the low byte TMODL is written Reset sets the TIM counter modulo registers Address 0023 TMODH Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset 1 1 1 1 1 1 1 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addre
102. O is used in a wired OR configuration and requires a pullup resistor The monitor code has been updated from previous versions of the monitor code to allow enabling the internal oscillator to generate the internal clock This addition which is enabled when IRQ is held low out of reset is intended to support serial communication programming at 9600 baud in monitor mode by using the internal oscillator and the internal oscillator user trim value OSCTRIM FLASH location FFCO if programmed to generate the desired internal frequency 3 2 MHz Since this feature is enabled only when IRQ is held low out of reset it cannot be used when the reset vector is programmed i e the value is not FFFF because entry into monitor mode in this case requires on IRQ The IRQ pin must remain low during this monitor session in order to maintain communication Table 15 1 shows the pin conditions for entering monitor mode As specified in the table monitor mode may be entered after a power on reset POR and will allow communication at 9600 baud provided one of the following sets of conditions is met e f FFFE and do not contain FF programmed state external clock is 9 8304 MHz IRQ e f FFFE and FFFF contain FF erased state external clock is 9 8304 MHz IRQ Vpp this can be implemented through the internal IRQ pullup f FFFE and FFFF contain FF erased state internal oscillat
103. O5 INTERRUPT STATUS REGISTER 2 INT2 FEO6 INTERRUPT STATUS REGISTER 3 1113 07 RESERVED FOR FLASH TEST CONTROL REGISTER FLASH CONTROL REGISTER FLCR 5 09 BREAK ADDRESS HIGH REGISTER BRKH FEOA BREAK ADDRESS LOW REGISTER BRKL FEOB BREAK STATUS AND CONTROL REGISTER BRKSCR LVISR RESERVED FOR FLASH TEST nos 3 BYTES 10 MONITOR ROM 416 BYTES SFFAF nl FLASH run 14 BYTES FLASH BLOCK PROTECT REGISTER FLBPR RESERVED FLASH FFCO INTERNAL OSCILLATOR TRIM VALUE 1 RESERVED FLASH ia FLASH Ta 14 BYTES SHE USER VECTORS FFFF 48 BYTES 26 Note 1 Attempts to execute code from addresses in this range will generate an illegal address reset UNIMPLEMENTED 51712 BYTES FLASH MEMORY 1536 BYTES MC68HC908QT1 MC68HC908QT2 MC68HC908QY1 and MC68HC908QY2 Memory Map Figure 2 1 Memory Map MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Input Output Section 2 4 Input Output 10 Section Addresses 0000 003F shown in Figure 2 2 contain most of the control status and data registers Additional I O registers have these addresses 0004 0005 Break status register BSR FEO01 Reset status register SRSR FE02 Break auxiliary register BRKAR FE03 Break flag control register BFCR FE04 Interrupt status register 1 INT1 FE05 Interrupt status register 2
104. OCO bit position MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 45 Analog to Digital Converter ADC AIEN ADC Interrupt Enable Bit When this bit is set an interrupt is generated at the end of an ADC conversion The interrupt signal is cleared when ADR is read or ADSCR is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disabled ADCO ADC Continuous Conversion Bit When set the ADC will convert samples continuously and update ADR at the end of each conversion Only one conversion is allowed when this bit is cleared Reset clears the ADCO bit 1 Continuous conversion 0 One ADC conversion CH 4 0 ADC Channel Select Bits CH4 CH3 CH2 CH1 and CHO form a 5 bit field which is used to select one of the four ADC channels The five select bits are detailed in Table 3 1 Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal The ADC subsystem is turned off when the channel select bits are all set to 1 This feature allows for reduced power consumption for the MCU when the ADC is not used Reset sets all of these bits to 1 NOTE Recovery from the disabled state requires one conversion cycle to stabilize Table 3 1 MUX Channel Select AOC Input Select 0 0 0 0 0 ADCO PTAO 0 0 0 0 1 ADC1 PTA1
105. ONIZER CK TO PULLUP ENABLE INTERRUPT FF KEYBOARD EAE p IMASKK REQUEST MODEK 5 TO PULLUP ENABLE AWUIREQ 1 For AWUGEN logic refer to Figure 4 1 Auto Wakeup Interrupt Request Generation Logic Figure 9 2 Keyboard Interrupt Block Diagram If the MODEK bit is set the keyboard interrupt inputs are both falling edge and low level sensitive and both of the following actions must occur to clear a keyboard interrupt request e Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the interrupt request Software may generate the interrupt acknowledge signal by writing a 1 to the ACKK bit in the keyboard status and control register KBSCR The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the keyboard interrupt request Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACKK does not affect subsequent transitions on the keyboard interrupt inputs A falling edge that occurs after writing to the ACKK bit latches another interrupt request If the keyboard interrupt mask bit IMASKK is clear the centr
106. OSC2 M 7 Xk di Note 1 Rg can be zero shorted when used with higher frequency crystals Refer to manufacturer s data See Chapter 16 Electrical Specifications for component value recommendations Figure 11 2 XTAL Oscillator External Connections MC68HC908QY QT Family Data Sheet Rev 5 92 Freescale Semiconductor Oscillator Module Signals 11 3 4 RC Oscillator The RC oscillator circuit is designed for use with an external resistor to provide a clock source with a tolerance within 25 of the expected frequency See Figure 11 3 The capacitor C for the RC oscillator is internal to the MCU The value must have a tolerance of 196 or less to minimize its effect on the frequency In this configuration the OSC2 pin can be left in the reset state as PTA4 Or the OSC2EN bit in the port A pullup enable register can be set to enable the OSC2 output function on the pin Enabling the OSC2 output slightly increases the external RC oscillator frequency D OSCRCOPT FROM SIM TO SIM TO SIM INTCLK 0 BUSCLKX4 BUSCLKX2 SIMOSCEN EXTERNAL RC OSCILLATOR EN 4 10 4 MCU OSC2EN 0 1 PTA4 BUSCLKX4 OSC2 T Rext AW See Chapter 16 Electrical Specifications for component value requirements Figure 11 3 RC Oscillator External Connections 11 4
107. OW RETURN Table 15 8 RUN Run User Program Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode 28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode The RUN command tells the MCU to execute the PULH and RTI instructions Before sending the RUN command the host can modify the stacked CPU registers to prepare to run the host program The READSP command returns the incremented stack pointer value SP 1 The high and low bytes of the program counter are at addresses SP 5 and SP 6 SP HIGH BYTE OF INDEX REGISTER SP 1 CONDITION CODE REGISTER SP 2 ACCUMULATOR SP 3 LOW BYTE OF INDEX REGISTER SP 4 HIGH BYTE OF PROGRAM COUNTER SP 5 LOW BYTE OF PROGRAM COUNTER SP 6 SP 7 Figure 15 17 Stack Pointer at Monitor Mode Entry MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 147 Development Support 15 3 2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations FFF6 FFFD Locations FFF6 FFFD contain user defined data NOTE Do not leave locations FFF6 FFFD blank For security reasons program locations FFF6 FFFD even if they are not used for vectors During m
108. Oscillator Module Signals The following paragraphs describe the signals that are inputs to and outputs from the oscillator module 11 4 1 Crystal Amplifier Input Pin OSC1 The OSCt1 pin is either an input to the crystal oscillator amplifier an input to the RC oscillator circuit or an external clock source For the internal oscillator configuration the OSC1 pin can assume other functions according to Table 1 3 Function Priority in Shared Pins MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 93 Oscillator Module OSC 11 4 2 Crystal Amplifier Output Pin OSC2 PTA4 BUSCLKX4 For the XTAL oscillator device the OSC2 pin is the crystal oscillator inverting amplifier output For the external clock option the OSC2 pin is dedicated to the PTA4 I O function The OSC2EN bit has no effect For the internal oscillator or RC oscillator options the OSC2 pin can assume other functions according to Table 1 3 Function Priority in Shared Pins or the output of the oscillator clock BUSCLKX4 Table 11 1 OSC2 Pin Function Option OSC2 Pin Function XTAL oscillator Inverting OSC1 External clock 4 Internal oscillator Controlled by OSC2EN bit in PTAPUE register OSC2EN 0 PTA4 I O RC oscillator 2 1 BUSCLKXA output 11 4 3 Oscillator Enable Signal SIMOSCEN The SIMOSCEN signal comes from the system integration module SIM and enables disables either the XTAL oscillator c
109. PTAS OSC1 KBI5 4 13 PTAO TCHO KBIO 4 05 2 4 5 12 PTAT TCH1 KBI PTB5 6 11 PTB2 4 7 10 PTA3 RST KBI3 8 9 PTA2 IRQ KBI2 TCLK 16 PIN ASSIGNMENT MC68HC908QY1 PDIP SOIC Iw 1 16 Vss 2 15 PTBO 3 14 1 PTAS OSC1 AD3 KBI5 4 13 1 PTAO ADO TCHO KBIO PTA4 OSC2 AD2 KBI4 5 12 PTA1 AD1 TCH1 KBI1 PTBS 6 11 PTB2 4 7 10 PTAS RST KBI3 8 9 PTA2 RO KBI2 TCLK 16 PIN ASSIGNMENT MC68HC908QY2 AND MC68HC908QY4 PDIP SOIC PTAO TCHO KBIO 1 16 PTA1 TCH1 KBI1 PTB1 C 2 15 2 PTBO 3 14 __ C 4 13 PTA2 IRQ KBIZ TCLK 5 12 PTB7 6 11 4 PTB6 7 10 5 5 0801 8 9 1 PTA4 OSC2 KBI4 16 PIN ASSIGNMENT MC68HC908QY1 TSSOP PTA1 TCH1 KBI1 PTA2 IRQ KBI2 TCLK PTA3 RST KBI3 PTA4 OSC2 KBI4 8 PIN ASSIGNMENT MC68HC908QT1 DFN PTAO ADO TCHO KBIO 1 16 PTA1 AD1 TCH1 KBI1 PTB1 2 15 1 PTB2 PTBO 3 14 PTB3 Vss C 4 13 PTA2 IRQ KBIZ TCLK Vpp 5 12 PTAS RST KBI3 PTB7 6 11 PTB4 PTB6 7 10 5 PTAS OSC1 AD3 KBIb 8 9 1 PTA4 OSC2 AD2 KBI4 16 PIN ASSIGNMENT MC68HC908QY2 AND MC6
110. Q Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up PTB 0 7 Not available on 8 pin devices MC68HC908QT1 MC68HC908QT2 and MC68HC908QTA see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT 1 Figure 15 1 Block Diagram Highlighting BRK and MON Blocks ADDRESS BUS 15 8 BREAK ADDRESS REGISTER HIGH 8 BIT COMPARATOR ADDRESS BUS 15 0 pee CONTROL BKPT TO SIM 8 BIT COMPARATOR BREAK ADDRESS REGISTER LOW 5 ADDRESS BUS 7 0 Figure 15 2 Break Module Block Diagram MC68HC908QY QT Family Data Sheet Rev 5 134 Freescale Semiconductor Break Module When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register the CPU starts a break interrupt by e Loading the instruction register with the SWI instruction e Loading the program counter with FFFC and FFFD FEFC and FEFD in monitor mode The break interrupt timing is e When a break address is placed at the address of the instruction opcode the instruction is not executed until after completion of the break interrupt routine When a break address is placed at an address of an instruction operand the instruction is executed before the break interrupt
111. R Reset Unaffected by reset Figure 6 2 COP Control Register COPCTL 6 5 Interrupts The COP does not generate CPU interrupt requests 6 6 Monitor Mode COP is disabled in monitor mode when is present on the IRQ pin 6 7 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 6 7 1 Wait Mode The COP continues to operate during wait mode To prevent a COP reset during wait mode periodically clear the COP counter 6 7 2 Stop Mode Stop mode turns off the BUSCLKXA input to the COP and clears the SIM counter Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode 6 8 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register BRKAR MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 59 pa Computer Operating Properly MC68HC908QY QT Family Data Sheet Rev 5 60 Freescale Semiconductor Chapter 7 Central Processor Unit CPU 7 1 Introduction The M68HCO08 CPU central processor unit is an enhanced and fully object code compatible version of the M68HCO05 CPU CPU08 Reference Manual document order number CPUOBRM AD contains a description of the CPU instruction set addressing modes and architecture 7 2
112. R B7 3 STA opr EXT C7 hhll 4 STA opr X 2 D7 4 STA Store A in M lt 1 1111 1 1 E7 3 STA X IX F7 2 STA opr SP SP1 9EE7 ff 4 STA opr SP SP2 9 07 ee ff 5 STHX opr Store H X in M 1 lt H X 1 1111 DIR 35 dd 4 Enable Interrupts Stop Processing 3 412 5 Refer to MCU Documentation lt 0 Stop Processing 0 INH 8 1 5 DIR BF dd 3 STX opr EXT CF 4 STX 1 2 DF 4 STX opr X Store X in M lt X 1 1111 1 1 EF ff 3 STX X IX FF 2 STX oprSP SP1 9EEF ff 4 STX oprSP SP2 9EDF ff 5 SUB opr IMM AO iii 2 SUB opr DIR BO dd 3 SUB opr EXT CO hhll 4 SUB IX2 DO 4 SUB opr X Subtract A lt A M 1 1111 EO f 3 SUB X IX FO 2 SUB opr SP SP1 9EEO ff 4 SUB opr SP SP2 9EDO ee ff 5 MC68HC908QY QT Family Data Sheet Rev 5 70 Freescale Semiconductor Table 7 1 Instruction Set Summary Sheet 6 of 6 Opcode Map Effect 2 o ul Operation Description 5 g 9 S 28 VIHILINIZ PC lt 1 Push PCL SP lt SP 1 Push SP lt SP 1 Push X SWI Software Interrupt gee ise 1 111 1 1 83 9 SP lt SP 1 1 lt 1 lt Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAP Transfer A to CCR lt sf
113. TA4 OSC2 AD2 KBIA at SYSTEM INTEGRATION ODULE PTAS OSC1 AD3 KBI5 68 08 CPU SINGLE INTERRUPT 0 5 gt ODULE PTB1 PTB2 mo 2 BREAK PTB4 5 5 ODULE PTB5 POWER ON RESET 7 4 ODULE MC68HC908QY4 AND MC68HC908QT4 KEYBOARD INTERRUPT 8 ADC 4096 BYTES ODULE MC68HC908QY2 MC68HC908QY1 MC68HC908QT2 AND 68 908011 1536 BYTES 16 BIT TIMER ODULE 128 BYTES RAM USER FLASH COP ODULE Vpp POWER SUPPLY MONITOR ROM gt Vss RST IRQ Pins have internal about 30K Ohms pull up PTA 0 5 High current sink and source capability PTA 0 5 Pins have programmable keyboard interrupt and pull up PTB 0 7 Not available on 8 pin devices MC68HC908QT1 MC68HC908QT2 and 68 908 4 see note in 12 1 Introduction ADC Not available on the MC68HC908QY1 and MC68HC908QT1 Figure 11 1 Block Diagram Highlighting OSC Block and Pins 11 3 1 Internal Oscillator The internal oscillator circuit is designed for use with no external components to provide a clock source with tolerance less than 25 untrimmed An 8 bit trimming register allows adjustment to a tolerance of less than 5 The internal oscillator will generate a clock of 12 8 MHz typical INTCLK resulting in a bus speed internal clock 4 of 3 2 MHz 3 2 MHz came from the maximum bus speed guaranteed at 3 V which is 4 MHz Since the internal oscillato
114. TIM overflow interrupt routine to write a new smaller pulse width value may cause the compare to be missed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x When changing to a shorter pulse width enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current pulse The interrupt routine has until the end of the PWM period to write the new value e When changing to a longer pulse width enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current PWM period Writing a larger value in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same PWM period NOTE In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 0 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value 14 4 4 2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCHO pin The TIM
115. The ADC resolution is eight bits When the conversion is completed ADC puts the result in the ADC data register and sets a flag or generates an interrupt Figure 3 2 shows a block diagram of the ADC 3 3 1 ADC Port I O Pins PTAO PTA1 PTA4 and PTAS are general purpose I O pins that are shared with the ADC channels The channel select bits ADC status and control register ADSCR 003C define which ADC channel port pin will be used as the input signal The ADC overrides the port I O logic by forcing that pin as input to the ADC The remaining ADC channels port pins are controlled by the port I O logic and can be used as general purpose Writes to the port register or data direction register DDR will not have any affect on the port pin that is selected by the ADC Read of a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is at 0 If the DDR bit is at 1 the value in the port data latch is read MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 41 _ 3 _ __ _ _ _ _ Analog to Digital Converter ADC PTAO ADO TCHO KBIO ap CLOCK 1 1 1 1 a3 GENERATOR PTAZ ROKBIITOLK gt lt OSCILLATOR E PTAIRST KBIS 6 PTAA OSC2 AD2 KBH a SYSTEM INTEGRATION MODULE 5 5 lt M6BHCO8
116. U 49 Chapter 5 Configuration Register CONFIG 53 Chapter 6 Computer Operating Properly 57 Chapter 7 Central Processor Unit 61 Chapter 8 External Interrupt 73 Chapter 9 Keyboard Interrupt Module 79 Chapter 10 Low Voltage Inhibit 1 1 85 Chapter 11 Oscillator Module 5 89 Chapter 12 Input Output Ports 97 Chapter 13 System Integration Module SIM 103 Chapter 14 Timer Interface Module 119 Chapter 15 Development 133 Chapter 16 Electrical 5 149 Chapter 17 Ordering Information and Mechanical Specifications 165 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 7 pa List of Chapters MC68HC908QY QT Family Data Sheet Rev 5 8 Freescale Semiconductor Table of Contents 1 1 1 2 1 3 1 4 1 5 1 6 2 1 2 2 3 2 4 2 5 2 6 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 6 6 2 6 7 2 6 8 3 1
117. USCLKX2 will be divided MC68HC908QY QT Family Data Sheet Rev 5 94 Freescale Semiconductor Low Power Modes again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK RCCLK or INTCLK frequency 11 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 11 5 1 Wait Mode The WAIT instruction has no effect on the oscillator logic BUSCLKX2 and BUSCLKXA continue to drive to the SIM module 11 5 2 Stop Mode The STOP instruction disables either the XTALCLK the RCCLK or INTCLK output hence BUSCLKX2 and BUSCLKX4 11 6 Oscillator During Break Mode The oscillator continues to drive BUSCLKX2 and BUSCLKXA when the device enters the break state 11 7 CONFIG2 Options Two CONFIG2 register options affect the operation of the oscillator module OSCOPT1 and OSCOPTO All CONFIG2 register bits will have a default configuration Refer to Chapter 5 Configuration Register CONFIG for more information on how the CONFIG2 register is used Table 11 2 shows how the OSCOPT bits are used to select the oscillator clock source Table 11 2 Oscillator Modes OSCOPT1 OSCOPTO Oscillator Modes 0 0 Internal oscillator 0 1 External oscillator 1 0 External RC 1 1 External crystal 11 8 Input Output I O Registers The oscillator module contains these two registers 1 Oscillator status register OSCSTAT 2 Oscillator trim register
118. Unimplemented Port A Input Pullup Enable Read Register PTAPUE Write page 99 Reset Port Input Pullup Enable Read Register PTBPUE Write See page 102 Reset Unimplemented Keyboard Status and Read Control Register KBSCR Write page 83 Reset Keyboard Interrupt Read Enable Register KBIER Write 84 Reset Unimplemented IRQ Status and Control Read Register INTSCR Write See page 77 Reset Configuration Register 2 Read coNFIG2 Write 53 Reset Configuration Register 1 Read CONFIG1 Write See page 54 eget TIM Status and Control Read Register TSC Write See page 127 Reset TIM Counter Register High Read TCNTH Write See page 128 Reset Bit 7 6 5 4 3 2 1 Bit 0 0 OSC2EN 5 PTAPUE4 PTAPUE2 PTAPUE1 PTAPUEO 0 0 0 0 0 0 0 0 PTBPUE7 PTBPUE6 5 PTBPUE4 PTBPUE2 PTBPUE1 0 0 0 0 0 0 0 0 0 0 0 0 KEYF 0 IMASKK MODEK ACKK 0 0 0 0 0 0 0 AWUIE KBIE5 KBIE4 KBIE2 KBIE1 KBIEO 0 0 0 0 0 0 0 0 0 0 0 0 IRQF 0 IMASK MODE ACK 0 0 0 0 0 0 0 0 IRQPUD IRQEN R OSCOPT1 OSCOPTO R R RSTEN 0 0 0 0 0 0 0 02 1 writable register after each reset 2 RSTEN reset
119. Vpp aD 1 16 9 8304 MHz CLOCK 11 0 1 zd ae 31 1 B e 7 10 PTA1 C2 V 2 7 IRQ PTA2 16 PTA4 N C 5 c2 tur SE Wr 10 74 125 2 7 107 6 ge 74HC125 3 8 gt 3 2 3 4 H1 5 Value not critical Figure 15 11 Monitor Mode Circuit External Clock No High Voltage MC68HC908QY QT Family Data Sheet Rev 5 140 Freescale Semiconductor Monitor Module MON Vpp o N C RST 4 0 1 uF MAX232 Voo 0801 PTAS L C1 8 1 uF je ue PTA1 NC 20122 10 199 vel PTA4 L NC 1 uF 2 w uF N 6 9 5 c2 10 Kos T EM 74HC125 2 7 4 gt lt 74 125 ds Vss 3 8 gt B E _ Value not critical Figure 15 12 Monitor Mode Circuit Internal Clock No High Voltage Simple monitor commands can access any memory address In monitor mode the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions All communication between the host computer and the MCU is through the PTAO pin A level shifting and multiplexing interface is required between PTAO and the host computer PTA
120. When software writes a 1 to the bit the break interrupt occurs just before the next instruction is executed By updating a break address and clearing the BRKA bit in a break interrupt routine a break interrupt can be generated continuously CAUTION A break address should be placed at the adaress of the instruction opcode When software does not change the break address and clears the BRKA bit in the first break interrupt routine the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers 15 2 1 1 Flag Protection During Break Interrupts The system integration module SIM controls whether or not module status bits can be cleared during the break state The BCFE bit in the break flag control register BFCR enables software to clear status bits during the break state See 13 8 2 Break Flag Control Register and the Break Interrupts subsection for each module 15 2 1 2 TIM During Break Interrupts A break interrupt stops the timer counter 15 2 1 3 COP During Break Interrupts The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register BRKAR 15 2 2 Break Module Registers These registers control and monitor operation of the break module e Break status and control register BRKSCR e Break address register high BRKH e Break address register low BRKL e Break
121. a valid FLASH address unpredictable behavior may occur if this location is written while HVEN is set This program sequence is repeated throughout the memory until all data is programmed NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order shown other unrelated operations may occur between the steps Do not exceed maximum see 16 16 Memory Characteristics 2 6 5 FLASH Protection Due to the ability of the on board charge pump to erase and program the FLASH memory in the target application provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction This protection is done by use of a FLASH block protect register FLBPR The FLBPR determines the range of the FLASH memory which is to be protected The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory SFFFF When the memory is protected the HVEN bit cannot be set in either ERASE or PROGRAM operations NOTE In performing a program or erase operation the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is programmed with all 0 s the entire memory is protected from being programmed and erased When all the bits are erased all 1 s the entire memory is accessible for pr
122. a msec NUT SCALE THIS DRAWING REV 4 T SAN UM a 16 9 i D BAN T 8 hd ld hd 153 EM m SEATING A FW PLANE Gl DbD 16 PL 0 25 0 010 T A TITLE CASE NUMBER 648 08 16 LD PDIP STANDARD JEDEC PACKAGE CODE 0006 SHEET fae Ss DOCUMENT 98ASB42431B 2 freescale DICTIONARY 1 FREESCALE SEMICONDUCTOR semicondueior RESERVED G 4 o MN e GONT BORED CE E 3 D 5 L E T H I S D R W I R E T NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 CONTROLLING DIMENSION INCH ZA DIMENSION TO CENTER OF LEADS WHEN FORMED PARALLEL DIMENSIONS DOES NOT INCLUDE MOLD FLASH 5 ROUNDED CORNERS OPTIONAL 6 648 01 THRU 08 OBSOLETE NEW STANDARD 648 09 MILLIMETERS INCHES MILLIMETERS INCHES DIM MIN MAX MIN MAX DIM MIN MAX MIN MAX 18
123. al processor unit CPU loads the program counter with the vector address at locations FFEO and FFE1 e Return of all enabled keyboard interrupt inputs to logic 1 As long as any enabled keyboard interrupt pin is at logic O the keyboard interrupt remains set The auto wakeup interrupt input AWUIREQ will be cleared only by writing to ACKK bit in KBSCR or reset The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order If the MODEK bit is clear the keyboard interrupt pin is falling edge sensitive only With MODEK clear a vector fetch or software clear immediately clears the keyboard interrupt request Reset clears the keyboard interrupt request and the MODEK bit clearing the interrupt request even if a keyboard interrupt input stays at logic O The keyboard flag bit KEYF in the keyboard status and control register can be used to see if a pending interrupt exists The KEYF bit is not affected by the keyboard interrupt mask bit IMASKK which makes it useful in applications where polling is preferred MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 81 Keyboard Interrupt Module KBI To determine the logic level on a keyboard interrupt pin use the data direction register to configure the pin as an input and then read the data register NOTE Setting a keyboard interrupt enable bit KBIEx forces the corresponding keyboard interrupt pin to be an i
124. al oscillator frequency the crystal frequency or the RC oscillator frequency 6 3 2 STOP Instruction The STOP instruction clears the SIM counter 6 3 3 COPCTL Write Writing any value to the COP control register COPCTL see 6 4 COP Control Register clears the COP counter and clears stages 12 5 of the SIM counter Reading the COP control register returns the low byte of the reset vector 6 3 4 Power On Reset The power on reset POR circuit in the SIM clears the SIM counter 4096 x BUSCLKXA cycles after power up 6 3 5 Internal Reset An internal reset clears the SIM counter and the COP counter 6 3 6 COPD COP Disable The COPD signal reflects the state of the COP disable bit COPD in the configuration register 1 CONFIG1 See Chapter 5 Configuration Register CONFIG MC68HC908QY QT Family Data Sheet Rev 5 58 Freescale Semiconductor COP Control Register 6 3 7 COPRS COP Rate Select The COPRS signal reflects the state of the COP rate select bit COPRS in the configuration register 1 CONFIG1 See Chapter 5 Configuration Register CONFIG 6 4 COP Control Register The COP control register COPCTL is located at address FFFF and overlaps the reset vector Writing any value to FFFF clears the COP counter and starts a new timeout period Reading location FFFF returns the low byte of the reset vector Address FFFF Bit 7 6 5 4 3 2 1 Bit 0 Read LOW BYTE OF RESET VECTOR Write CLEAR COP COUNTE
125. ale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 All rights reserved 2 freescale semiconductor
126. and highest priority and cannot be arbitrated 13 6 4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output See Chapter 15 Development Support The SIM puts the CPU into the break state by forcing it to the SWI vector location Refer to the break interrupt subsection of each module to see how each module is affected by the break state 13 6 5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit BCFE in the break flag control register BFCR Protecting flags in break mode ensures that set flags will not be cleared while in break mode This protection allows registers to be freely read and written during break mode without losing status flag information Setting the BCFE bit enables the clearing mechanisms Once cleared in break mode a flag remains cleared even when break mode is exited Status flags with a two step clearing mechanism for example a read of one register followed by the read or write of another are protected even when the first step is accomplished prior to entering break mode Upon leaving break mode execution of the second step will clear the flag as normal 13 7 Low Power Modes Executing the WAIT or STOP instruction pu
127. antee the maximum amount of time before the first time out The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register BRKAR 13 4 2 3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions An illegal instruction sets the ILOP bit in the SIM reset status register SRSR and causes a reset If the stop enable bit STOP in the mask option register is O the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset The SIM actively pulls down the RST pin for all internal reset sources 13 4 2 4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR and resetting the MCU A data fetch from an unmapped address does not generate a reset The SIM actively pulls down the RST pin for all internal reset sources See Figure 2 1 Memory Map for memory ranges 13 4 2 5 Low Voltage Inhibit LVI Reset The LVI asserts its output to the SIM when the Vpp voltage falls to the LVI trip voltage The LVI bit in the SIM reset status register SRSR is set and the external reset pin RST is held low while the SIM counter counts out 4096 BUSCLKXA cycles after Vpp rises above Sixty four BUSCLKX4 cycles later the CPU and memories are released fr
128. apter 16 Electrical Specifications Extensive changes made to electrical 169 specifications 17 5 8 Pin Dual Flat No Lead DFN Package Case 1452 Added case 177 outline drawing for DFN package Chapter 17 Ordering Information and Mechanical Specifications Added jen 185 ordering information for DFN package y e 0 2 4 2 Features Corrected third bulleted item 49 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Revision History Sheet 2 of 3 Revision x Page Date Level Description Number s Reformatted to meet latest M68HC08 documentation standards N A Figure 1 1 Block Diagram Diagram redrawn to include keyboard interrupt 20 module and TCLK pin designator Figure 1 2 MCU Pin Assignments Added TCLK pin designator 21 Table 1 2 Pin Functions Added TCLK pin description 22 Table 1 3 Function Priority in Shared Pins Revised table for clarity and to 23 add TCLK Figure 2 1 Memory Map Corrected names for the IRQ status and control 26 August register INTSCR bits 3 0 2003 WB 3 7 3 ADC Input Clock Register Clarified bit description for the ADC clock 47 prescaler bits 4 3 Functional Description Updated periodic wakeup request values 51 Figure 6 1 COP Block Diagram Reworked for clarity 59 Chapter 8 External Interrupt IRQ Corrected bit names for MODE IRQF 77 79 ACK and IMASK Chapte
129. asserted The SIM enables the oscillator to drive BUSCLKX4 Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKXA cycles to allow stabilization of the oscillator The POR bit of the SIM reset status register SRSR is set See Figure 13 6 osi 211117 PORRST T T T 4096 32 32 CYCLES CYCLES CYCLES ra q 4 gt 5 5 b D BUSCLKX4 BUSCLKX2 55 2 5 5 RST 5 5 5 5 5 5 ADDRESS BUS T T T FFFE y FFFF Figure 13 6 POR Recovery MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 107 System Integration Module SIM 13 4 2 2 Computer Operating Properly COP Reset An input to the SIM is reserved for the COP reset signal The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register SRSR The SIM actively pulls down the RST pin for all internal reset sources To prevent COP module time out write any value to location FFFF Writing to location FFFF clears the COP counter and stages 12 5 of the SIM counter The SIM counter output which occurs at least every 4080 BUSCLKXA cycles drives the COP counter The COP should be serviced as soon as possible out of reset to guar
130. ata direction register B bits from 0 to 1 Figure 12 7 shows the port B I O logic DDRB 50005 1 WRITE DDRB 0005 DDRBx 2 30k 5 WRITE 0001 PTBx oc Lu z READ 0001 Figure 12 7 Port B I O Circuit When DDRBx is a 1 reading address 0001 reads the PTBx data latch When DDRBx is a 0 reading address 0001 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 12 2 summarizes the operation of the port B pins Table 12 2 Port B Pin Functions DDRB PTB Pin Accesses to DDRB Accesses to PTB Bit Bit Mode Read Write Read Write 0 X Input Hi Z DDRB7 DDRBO Pin 7 1 Output DDRB7 DDRBO Pin PTB7 PTBO 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect the input MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 101 Input Output Ports PORTS 12 3 3 Port B Input Pullup Enable Register The port B input pullup enable register PTBPUE contains a software configurable pullup device for each of the eight port B pins Each bit is individually configurable and requires the corresponding data direction register DDRBx be configured as input Each pullup device is automatically and dynamically di
131. ay at the end of each command allows the host to send a break character to cancel the command A delay of two bit times occurs before each echo and before READ IREAD or READSP data is returned The data returned by a read command appears after the echo of the last byte of the command NOTE Wait one bit time after each echo before sending the next byte FROM rd Y Y Ces Ya gt 4 1 4 1 4 1 4 RETURN Notes 1 Echo delay 2 bit times 3 Cancel command delay 11 bit times 2 Data return delay 2 bit times 4 Wait 1 bit time before sending next byte Figure 15 15 Read Transaction ADDRESS ADDRESS ADDRESS VADDRESS fere Quee eme Cio 288 3 1 3 1 3 1 3 1 2 3 Notes 1 Echo delay 2 bit times 2 Cancel command delay 11 bit times 3 Wait 1 bit time before sending next byte Figure 15 16 Write Transaction A brief description of each monitor mode command is given in Table 15 3 through Table 15 8 Table 15 3 READ Read Memory Command Description Read byte from memory Operand 2 byte address in high byte low byte order Data Returned Returns contents of specified address Opcode 4A Command Sequence SENT TO MONITOR ECHO RETURN MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 145 Development Support Table 15 4 WRITE Write Memory Command Description Wri
132. by step procedure to program a row of FLASH memory Figure 2 4 shows a flowchart of the programming algorithm 5 2298 22 28 Only bytes which are currently FF may be programmed Set the PGM bit This configures the memory for program operation and enables the latching of address and data for programming Read the FLASH block protect register Write any data to any FLASH location within the address range desired Wait for a time tuys minimum 10 us Set the HVEN bit Wait for a time teas minimum 5 us Write data to the FLASH address being programmed 1 When in monitor mode with security sequence failed see 15 3 2 Security write to the FLASH block protect register instead of any FLASH address 2 The time between each FLASH address change or the time between the last FLASH address programmed to clearing bit must not exceed the maximum programming time 1 maximum MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 35 8 Wait for time minimum 30 us 9 Repeat step 7 and 8 until all desired bytes within the row are programmed 10 Clear the 11 Wait for time tyyp minimum 5 us 12 Clear the HVEN bit 13 After time typical 1 us the memory can be accessed in read mode again NOTE The COP register at location FFFF should not be written between steps 5 12 when the HVEN bit is set Since this register is located at
133. channel registers of the linked pair alternately control the pulse width of the output Setting the MSOB bit TIM channel 0 status and control register TSCO links channel 0 and channel 1 The TIM channel 0 registers initially control the pulse width on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period At each subsequent overflow the TIM channel registers 0 or 1 that control the pulse width are the ones written to last controls and monitors the buffered PWM function and TIM channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 pin 1 is available as a general purpose pin NOTE In buffered PWM signal generation do not write new pulse width values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered PWM signals MC68HC908QY QT Family Data Sheet Rev 5 124 Freescale Semiconductor Interrupts 14 4 4 3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals use the following initialization procedure 1 5 In the TIM status and control register TSC a Stop the TIM counter by setting the TIM stop bit TSTOP b Reset the TIM cou
134. ctor 31 Table 2 1 Vector Addresses Vector Priority Vector Address Vector Lowest IF15 FFDE ADC conversion complete vector high A FFDF ADC conversion complete vector low Keyboard vector high FFE1 Keyboard vector low IF13 4 Not used IF6 2 TIM overflow vector high FFF3 TIM overflow vector low E FFF4 TIM Channel 1 vector high FFF5 TIM Channel 1 vector low FFF6 TIM Channel 0 vector high FFF7 TIM Channel 0 vector low IF2 Not used FFFA IRQ vector high FFFB IRQ vector low FFFC SWI vector high FFFD SWI vector low Y FFFE Reset vector high Highest FFFF Reset vector low 2 5 Random Access Memory RAM Addresses 0080 00FF are RAM locations The location of the stack RAM is programmable The 16 bit stack pointer allows the stack to be anywhere in the 64 Kbyte memory space NOTE For correct operation the stack pointer must point only to RAM locations Before processing an interrupt the central processor unit CPU uses five bytes of the stack to save the contents of the CPU registers NOTE For M6805 M146805 and M68HCO05 compatibility the H register is not stacked During a subroutine call the CPU uses two bytes of the stack to store the return address The stack pointer decrements during pushes and increments during pulls NOTE
135. d receive baud rates must be identical NEXT 2 4 STOP VAM Figure 15 13 Monitor Data Format 15 3 1 5 Break Signal A start bit logic 0 followed by nine logic 0 bits is a break signal When the monitor receives a break signal it drives the PTAO pin high for the duration of two bits and then echoes back the break signal MISSING STOP BIT 2 STOP BIT DELAY BEFORE ZERO ECHO 6 Teme Figure 15 14 Break Transaction 15 3 1 6 Baud Rate The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in Table 15 1 Table 15 1 also lists the bus frequencies to achieve standard baud rates The effective baud rate is the bus frequency divided by 256 when using an external oscillator When using the internal oscillator in forced monitor mode the effective baud rate is the bus frequency divided by 335 15 3 1 7 Commands The monitor ROM firmware uses these commands e READ read memory WRITE write memory e IREAD indexed read e indexed write e READSP read stack pointer RUN run user program MC68HC908QY QT Family Data Sheet Rev 5 144 Freescale Semiconductor Monitor Module MON The monitor ROM firmware echoes each received byte back to the PTAO pin for error checking An 11 bit del
136. d use the full stop recovery time by clearing the SSREC bit MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 115 System Integration Module SIM The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery It is then used to time the recovery period Figure 13 17 shows stop mode entry timing and Figure 13 18 shows the stop mode recovery time from interrupt or break NOTE To minimize stop current all pins configured as inputs should be driven to a logic 1 or logic O CPUSTOP ADDRESS BUS STOP ADDR STOP ADDR 1 SAME SAME DATA BUS PREVIOUS DATA NEXT OPCODE SAME SAME Jj NOTE Previous data can be operand data or the STOP opcode depending on the last instruction Figure 13 17 Stop Mode Entry Timing gt M STOP RECOVERY PERIOD BUSCLKX4 l INTERRUPT ADDRESS BUS 1 STOP 1 Goze stop 2 sp sp 1 sp 2 8 3 Figure 13 18 Stop Mode Recovery from Interrupt 13 8 SIM Registers The SIM has three memory mapped registers Table 13 4 shows the mapping of these registers Table 13 4 SIM Registers Address Register Access Mode BSR User FEO1 SRSR User FE03 BFCR User MC68HC908QY QT Family Data Sheet Rev 5 116 Freescale Semiconductor SIM Registers
137. de entry be achieved without use of the higher test voltage as long as vector addresses FFFE and FFFF are blank thus reducing the hardware requirements for in circuit programming Features include Normal user mode pin functionality on most pins One pin dedicated to serial communication between MCU and host computer e Standard non return to zero NRZ communication with host computer e Execution of code in random access memory RAM or FLASH FLASH memory security feature e FLASH memory programming interface e Use of external 9 8304 MHz oscillator to generate internal frequency of 2 4576 MHz e Simple internal oscillator mode of operation no external clock or high voltage e Monitor mode entry without high voltage if reset vector is blank SFFFE and FFFF contain FF Standard monitor mode entry if high voltage is applied to IRQ 1 No security feature is absolutely secure However Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users MC68HC908QY QT Family Data Sheet Rev 5 138 Freescale Semiconductor 15 3 1 Functional Description Monitor Module MON Figure 15 9 shows a simplified diagram of monitor mode entry The monitor module receives and executes commands from a host computer Figure 15 10 Figure 15 11 and Figure 15 12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS 232 interfac
138. dress Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Figure 15 5 Break Address Register Low BRKL MC68HC908QY QT Family Data Sheet Rev 5 136 Freescale Semiconductor Break Module 15 2 2 3 Break Auxiliary Register The break auxiliary register BRKAR contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode Address FE02 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 15 6 Break Auxiliary Register BRKAR BDCOP Break Disable COP Bit This read write bit disables the COP during a break interrupt Reset clears the BDCOP bit 1 COP disabled during break interrupt 0 COP enabled during break interrupt 15 2 2 4 Break Status Register The break status register BSR contains a flag to indicate that a break caused an exit from wait mode This register is only used in emulation mode Address FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW R R R R R R 1 R Write Note Reset 0 R Reserved 1 Writing a 0 clears SBSW Figure 15 7 Break Status Register BSR SBSW SIM Break Stop Wait SBSW can be read within the break state SWI routine The user can modify the return address on
139. e POR RESET CONDITIONS 1 PTAO 1 FROM Table 15 1 RESET VECTOR 0 PTA1 1 AND BLANK 4 0 YES FORCED NORMAL NORMAL INVALID MONITOR MODE USER MODE MONITOR MODE USER MODE HOST SENDS 8 SECURITY BYTES IS RESET YES POR NO ARE ALL Mes SECURITY BYTES CORRECT Y Y ENABLE FLASH DISABLE FLASH y MONITOR MODE ENTRY Y y DEBUGGING AND FLASH EXECUTE PROGRAMMING MONITORCODE T IF FLASH IS ENABLED _ YES DOES RESET OCCUR Figure 15 9 Simplified Monitor Mode Entry Flowchart MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 139 Development Support 10ko Voo 4 RST PTA3 04 uF 9 8304 MHz CLOCK L MAASSE Vpp e OSC1 PTA5 o 1 16 18 lt c1 g 2 1kQ 5 10 4 S V 4 Vo _ FO uF 6 5 C2 Tyr 10 DB9 74 125 PTA4 PTAO Vss Value not critical Figure 15 10 Monitor Mode Circuit External Clock with High Voltage o N C RST PTA3 Voo 0 1 uF MAX232
140. e bit is set when an active edge occurs on the channel x pin When channel x is an output compare channel CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing 0 to CHxF If another interrupt request occurs before the clearing sequence is complete then writing a 0 to CHxF has no effect Therefore an interrupt request cannot be lost due to inadvertent clearing of CHxF Reset clears the CHxF bit Writing a 1 to CHxF has no effect 1 Input capture or output compare on channel 0 No input capture or output compare on channel x Channel x Interrupt Enable Bit This read write bit enables TIM CPU interrupt service requests on channel x Reset clears the CHxIE bit 1 Channel x CPU interrupt requests enabled 0 Channel x CPU interrupt requests disabled MSxB Mode Select Bit B This read write bit selects buffered output compare PWM operation MSxB exists only in the TIM channel 0 status and control register Setting MSOB disables the channel 1 status and control register and reverts TCH1 to general purpose Reset clears the 5 bit 1 Buffered output compare PWM operation enabled 0 Buffered output compare PWM operation disabled MSxA Mode Select Bit A When ELSxB A z 00 this read write bit selects either input capture operation or unbuffered output compare PWM
141. e current liL 1 0 1 1 Capacitance Ports as input CiN 12 Ports as input Cour 8 POR rearm voltage 0 100 mV POR rise time ramp rate Rpon 0 035 V ms Monitor mode entry voltage Vist Vpp 2 5 9 1 V Pullup resistors R 16 26 36 5 7 Low voltage inhibit reset trip falling voltage VTRIPF 3 90 4 20 4 50 V Low voltage inhibit reset trip rising voltage VrTRIPR 4 00 4 30 4 60 V Low voltage inhibit reset recover hysteresis Vuys 100 mV 1 4 5 to 5 5 Vdc Vss 0 Vdc T to Ty unless otherwise noted 2 Typical values reflect average measurements at midpoint of voltage range 25 C only 3 Maximum is highest voltage that POR is guaranteed 4 If minimum Vpp is not reached before the internal POR reset is released the LVI will hold the part in reset until minimum Vpp is reached 5 Rpy is measured at Vpp 5 0 V MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 151 Electrical Specifications 16 6 Typical 5 V Output Drive Characteristics 2 0 1 5 5 e 5V PTA O 10 a W 5V PTB a gt 0 5 0 0 0 5 10 15 0 25 30 35 mA Figure 16 1 Typical 5 Volt Output High Voltage versus Output High Current 25 C 2 0 1 5 e 5V PTA a 10 5 0 5 0 0 0 5 10 15 20 25 30 35 IOL mA Figure 16 2
142. e long start up times from stop mode External crystal applications should use the full stop recovery time that is with SSREC cleared in the configuration register 1 CONFIG1 13 5 3 SIM Counter and Reset States External reset has no effect on the SIM counter see 13 7 2 Stop Mode for details The SIM counter is free running after all reset states See 13 4 2 Active Resets from Internal Sources for counter control and internal reset recovery sequences 13 6 Exception Control Normal sequential program execution can be changed in three different ways 1 Interrupts a Maskable hardware CPU interrupts b Non maskable software interrupt instruction SWI 2 Reset 3 Breakinterrupts 13 6 1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event Figure 13 7 flow charts the handling of system interrupts Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing The arbitration result is a constant that the CPU uses to determine which vector to fetch Once an interrupt is latched by the SIM no other interrupt can take precedence regardless of priority until the latched interrupt is serviced or the I bit is cleared At the beginning of an interrupt the CPU saves the CPU register contents on the stack and sets the interrupt mask 1 bit to prevent additional interrupts At the end of an interrupt the RTI instruction recovers the CPU r
143. e the trip point to 5 V operation If the user requires 5 V mode and sets the LVIBORG bit after power on reset while the Vpp supply is not above the for 5 V mode the microcontroller unit MCU will immediately go into reset The next time the LVI releases the reset the supply will be above the for 5 V mode Once an LVI reset occurs the MCU remains in reset until Vpp rises above a voltage which causes the to exit reset See Chapter 13 System Integration Module SIM for the reset recovery sequence The output of the comparator controls the state of the LVIOUT flag in the LVI status register LVISR and can be used for polling LVI operation when the LVI reset is disabled 10 3 1 Polled LVI Operation In applications that can operate at Vpp levels below the level software can monitor Vpp by polling the LVIOUT bit In the configuration register the LVIPWRD bit must be cleared to enable the LVI module and the LVIRSTD bit must be at set to disable LVI resets 10 3 2 Forced Reset Operation In applications that require Vpp to remain above the level enabling LVI resets allows the LVI module to reset the MCU when Vpp falls below the level In the configuration register the LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets 10 3 3 Voltage Hysteresis Protection Once the LVI has triggered by having Vpp fall below
144. ect on port A data AWUL Auto Wakeup Latch Data Bit This is a read only bit which has the value of the auto wakeup interrupt request latch The wakeup request signal is generated internally see Chapter 4 Auto Wakeup Module AWU There is no port nor any of the associated bits such as PTA6 data register pullup enable or direction KBI 5 0 Port A Keyboard Interrupts The keyboard interrupt enable bits 5 in the keyboard interrupt control enable register KBIER enable the port A pins as external interrupt pins see Chapter 9 Keyboard Interrupt Module KBI 12 2 2 Data Direction Register A Data direction register DDRA determines whether each port A pin is an input or an output Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin a O disables the output buffer Address 0004 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 R R DDRA5 DDRA4 DDRA3 DDRA1 DDRAO Write Reset 0 0 0 0 0 0 0 0 R Reserved Unimplemented Figure 12 2 Data Direction Register A DDRA DDRA 5 0 Data Direction Register A Bits These read write bits control port A data direction Reset clears DDRA 5 0 configuring all port A pins as inputs 1 Corresponding port A pin configured as output 0 Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction regist
145. ector locations FFFE and FFFF are FF after POR while IRQ z Vist 0 POR or read of SRSR LVI Low Voltage Inhibit Reset Bit 1 Last reset caused by LVI circuit 0 POR or read of SRSR MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 117 System Integration Module SIM 13 8 2 Break Flag Control Register The break control register BFCR contains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 13 20 Break Flag Control Register BFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break MC68HC908QY QT Family Data Sheet Rev 5 118 Freescale Semiconductor Chapter 14 Timer Interface Module TIM 14 1 Introduction This section describes the timer interface module TIM The TIM is a two channel timer that provides a timing reference with input capture output compare and pulse width modulation functions Figure 14 2 is a block diagram of the TIM 14 2 Features Features of the TIM include the following Two input capture output compare channels Rising edge falling edge or an
146. egister contents from the stack so that normal processing can resume Figure 13 8 shows interrupt entry timing Figure 13 9 shows interrupt recovery timing MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 109 System Integration Module SIM FROM RESET ru YES BREAK INTERRUPT iRQ YES INTERRUPT gt TIMER INTERRUPT 8 2 11 STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP INSTRUCTION UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Figure 13 7 Interrupt Processing MC68HC908QY QT Family Data Sheet Rev 5 110 Freescale Semiconductor Exception Control MODULE INTERRUPT BIT ADDRESS BUS Dummy 3 sp 1 sp 2 sp 3 SP 4 STARTADDAL 1 DATABUS pummy 17 01 1158 X a VDATAL OPCODE RAV J Figure 13 8 Interrupt Entry MODULE INTERRUPT ADDRESS BUS Y X x eco od RW Figure 13 9 Interrupt Recovery 13 6 1 1 Hardware Interrupts A hardware interrupt does not stop the current instruction Processing of a hardware interrupt begins after completion of the current instruction When the current instruction is complete the SIM checks all pending hardware interrupts If
147. egisters 132 Chapter 15 Development Support 123 rcrum 133 152 Beak Module BRK 5 133 15 2 1 d do en c d 133 15 2 1 1 Flag Protection During Break 1 135 15 2 1 2 D ring Break 135 15 2 1 3 Burng Break ede DORR REA 135 15 2 2 Break Registe ueri 135 15221 Break Status and Control 5 136 15 2 2 2 Break Address Registers 136 15 2 23 Break Auxiliary neneman 137 15 2 2 4 Break Status Regisier co rcr ETT ETT QT sues CT to ot IT 137 15 2 2 5 Break Flag Control 138 15 2 3 138 MC68HC908QY QT Family Data Sheet Rev 5 14 Freescale Semiconductor 199 Botner Mod le MON 138 15 3 1 Funcional 139 15 3 1 1 Normal Monitor Mode siiis mk Rem dee cee ke dem 142 15 3 1 2 Forced Monitor Mode se wine eR eS ERR Red rep RE KR 143 15 3 1 3 MONG VECOS 143 15 3 1 4
148. el e Extensive loop control functions e 16 addressing modes eight more than the 5 e 16 bit index register and stack pointer Memory to memory data transfers e Fast8x8 multiply instruction e Fast 16 8 divide instruction e Binary coded decimal BCD instructions e Optimization for controller applications e Efficient C language support 1 3 MCU Block Diagram Figure 1 1 shows the structure of the MC68HC908QY4 1 4 Pin Assignments The MC68HC908QT4 MC68HC908QT2 and MC68HC908QT 1 are available in 8 pin packages and the 68 9080 4 MC68HC908QY2 and MC68HC908QY 16 pin packages Figure 1 2 shows the pin assignment for these packages MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 19 General Description 20 10 CLOCK PTAZ IRQKBIZ TOLK gt lt OSCILLATOR c PTAS RST KBIS 4 08 2 2 4 SYSTEM INTEGRATION MODULE 5 08 1 68 08 CPU SINGLE INTERRUPT MODULE PTB1 PTB2 mo 2 BREAK PTBA MODULE PTB5 6 lt gt POWER ON 7 lt gt MODULE MC68HC908QY4 AND MC
149. er A bits from O to 1 MC68HC908QY QT Family Data Sheet Rev 5 98 Freescale Semiconductor Port A Figure 12 3 shows the port A I O logic 0004 1 WRITE DDRA 0004 d DDRAx a RESET 30k 5 WRITE 0000 lt 9 4 Lu E READ PTA 0000 i Y TO KEYBOARD INTERRUPT CIRCUIT Figure 12 3 Port A I O Circuit NOTE Figure 12 3 does not apply to PTA2 When DDRAx is a 1 reading address 0000 reads the PTAx data latch When DDRAx is 0 reading address 0000 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit 12 2 3 Port A Input Pullup Enable Register The port A input pullup enable register PTAPUE contains a software configurable pullup device for each if the six port A pins Each bit is individually configurable and requires the corresponding data direction register DDRAx to be configured as input Each pullup device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output Address 000B Bit 7 6 5 4 9 2 1 Bit 0 Read m OSC2EN 5 4 PTAPUES PTAPUE2 PTAPUE1 PTAPUEO rite Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 4 Port A Input Pullup Enable Register PTAPUE OSC2EN Enable PTA4 on OSC2 Pin T
150. erature e COPRS 0 650 ms 5 V 875 ms 3 V e COPRS 1 16ms 5V 22ms 3V MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 49 Auto Wakeup Module AWU COPRS FROM CONFIG1 AUTOWUGEN TO PTA READ BIT 6 9 SHORT 1 DIV2 D 0 AWUL 0 DIV 214 INT RC OSC OVERFLOW AWUIREQ R EN 32 kHz CLK BST TO KBI INTERRUPT LOGIC SEE Figure 9 2 Keyboard Interrupt Block Diagram CLRLOGIC in RESET ACKK CGMXCLK aie BUSCLKX4 RST ISTOP AWUIE Figure 4 1 Auto Wakeup Interrupt Request Generation Logic The auto wakeup RC oscillator is highly dependent on operating voltage and temperature This feature is not recommended for use as a time keeping function The wakeup request is latched to allow the interrupt source identification The latched value AWUL can be read directly from the bit 6 position of PTA data register This is a read only bit which is occupying an empty bit position on No associated registers such as PTA6 data direction and pullup exist for this bit The latch can be cleared by writing to the ACKK bit in the KBSCR register Reset also clears the latch AWUIE bit in KBI interrupt enable register see Figure 4 1 has no effect on AWUL reading The AWU oscillator and counters are inactive in normal operating mode and become acti
151. ero versions DO NOT SCALE THIS DRAWING REV A DETAIL M EXPOSED DIE PIN INDEX ATTACH PAD 5 05 2 95 2 55 2 45 DETAIL FLAT NO LEAD PACKAGE DFN STANDARD 8 TERMINAL 0 8 PITCH 4 X 4 X 1 ECT 212 freescale semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY IN RED MECHANICAL OUTLINES DICTIONARY DETAIL M BACKSIDE PIN 1 INDEX DETAIL N MECHANICAL OUTLINES DOCUMENT NO 98ARL10557D freescale DICTIONARY ae EESCALE SEMICONDUCTOR ae ALL RIGHTS RESERVED V ON CONT ROGEN pu ii STAMPED onTROLEE D D 0 0 5 L E ii H I S D R A R E V NOTES 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 3 THE COMPLETE DESIGNATOR FOR THIS PACKAGE IS HP VFDFP N COPLANARITY APPLIES TO LEADS AND DIE ATTACH PAD FLAT NO LEAD PACKAGE DFN STANDARD NON JEDEC S TERMINAL 0 8 BETCHUS X 4 X cone ser ors MECHANICAI UTLINES DOCUMENT 98 5 42431 FREESCALE SEMICONDUCTOR RESERVED E 5 1 5 i 1
152. ers CONFIG1 and CONFIG2 The configuration registers enable or disable the following options e Stop mode recovery time 32 x BUSCLKXA cycles or 4096 x BUSCLKXA cycles STOP instruction e Computer operating properly module COP e COP reset period COPRS 8176 x BUSCLKXA or 262 128 x BUSCLKX4 e Low voltage inhibit LVI enable and trip voltage selection e OSC option selection e IRQ pin e RST pin e Auto wakeup timeout period 5 2 Functional Description The configuration registers are used in the initialization of various options The configuration registers can be written once after each reset Most of the configuration register bits are cleared during reset Since the various options affect the operation of the microcontroller unit MCU it is recommended that this register be written immediately after reset The configuration registers are located at 001E and 001F and may be read at anytime NOTE The CONFIG registers are one time writable by the user after each reset Upon a reset the CONFIG registers default to predetermined settings as shown in Figure 5 1 and Figure 5 2 Address 001E Bit 7 6 5 4 3 2 1 Bit 0 Read IRQPUD IRQEN R OSCOPT1 OSCOPTO R R RSTEN Reset 0 0 0 0 0 0 0 U POR 0 0 0 0 0 0 0 0 R Reserved U Unaffected Figure 5 1 Configuration Register 2 CONFIG2 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 53 Configuration Re
153. f the IRQ function is disabled these instructions will behave as if the IRQ pin is a logic 1 regardless of the actual level on the pin Conversely when the IRQ function is enabled bit 2 of the port A data register will always read 0 When using the level sensitive interrupt trigger avoid false interrupts by masking interrupt requests in the interrupt routine An internal pullup resistor to Vpp is connected to the IRQ pin this can be disabled by setting the IRQPUD bit in the CONFIG2 register 001E MC68HC908QY QT Family Data Sheet Rev 5 76 Freescale Semiconductor Registers 8 7 1 IRQ Input Pins IRQ The IRQ pin provides a maskable external interrupt source The IRQ pin contains an internal pullup device 8 8 Registers The IRQ status and control register INTSCR controls and monitors operation of the IRQ module See Chapter 5 Configuration Register CONFIG The INTSCR has the following functions e Shows the state of the IRQ flag e Clears the IRQ latch e Masks the IRQ interrupt request Controls triggering sensitivity of the IRQ interrupt pin Address 001D Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 IRQF 0 IMASK MODE Write ACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 8 3 IRQ Status and Control Register INTSCR IRQF IRQ Flag This read only status bit is set when the IRQ interrupt is pending 1 IRQ interrupt pending 0 IRQ interrupt not pending ACK
154. fically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freesc
155. ge is programmable Input captures can generate TIM central processor unit CPU interrupt requests 14 4 3 Output Compare With the output compare function the TIM can generate a periodic pulse with a programmable polarity duration and frequency When the counter reaches the value in the registers of an output compare channel the TIM can set clear or toggle the channel pin Output compares can generate TIM CPU interrupt requests 14 4 3 1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 14 4 3 Output Compare The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period Also using a TIM overflow interrupt routine to write a new smaller output compare value may cause the compare to be missed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the output compare value on channel x e When changing to a smaller value enable channel x output compare interrupts and write the new value in t
156. gister CONFIG IRQPUD IRQ Pin Pullup Control Bit 1 Internal pullup is disconnected m 0 Internal pullup is connected between IRQ pin and Vpp IRQEN IRQ Pin Function Selection Bit 1 Interrupt request function active in pin 0 Interrupt request function inactive in pin 1 and OSCOPTO Selection Bits for Oscillator Option 0 0 Internal oscillator 0 1 External oscillator 1 0 External RC oscillator 1 1 External XTAL oscillator RSTEN RST Pin Function Selection 1 Reset function active in pin 0 Reset function inactive in pin NOTE The RSTEN bit is cleared by a power on reset POR only Other resets will leave this bit unaffected Address 001F Bit 7 6 5 4 3 2 1 Bit 0 Read Write COPRS LVISTOP LVIRSTD LVIPWRD LVIBOR3 SSREC STOP COPD Reset 0 0 0 0 U 5 NM 0 0 0 0 0 0 0 U Unaffected Figure 5 2 Configuration Register 1 CONFIG1 COPRS Out of STOP Mode COP Reset Period Selection Bit 1 COP reset short cycle 8176 x BUSCLKX4 0 COP reset long cycle 262 128 x BUSCLKX4 COPRS In STOP Mode Auto Wakeup Period Selection Bit 1 Auto wakeup short cycle 512 x INTRCOSC 0 Auto wakeup long cycle 16 384 x INTRCOSC LVISTOP LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear setting the LVISTOP bit enables the LVI to operate during stop mode Reset clears LVISTOP 1 LVI enabled during stop mode 0 LVI disabled duri
157. he output compare interrupt routine The output compare interrupt occurs at the end of the current output compare pulse The interrupt routine has until the end of the counter overflow period to write the new value When changing to a larger output compare value enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current counter overflow period Writing a larger value in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same counter overflow period 14 4 3 2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCHO pin The TIM channel registers of the linked pair alternately control the output Setting the MSOB bit TIM channel 0 status and control register TSCO links channel 0 and channel 1 The output compare value in the TIM channel 0 registers initially controls the output on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows At each subsequent overflow the TIM channel registers 0 or 1 that MC68HC908QY QT Family Data Sheet Rev 5 122 Freescale Semiconductor Functional Description control the output are the ones written to last TSCO controls and monitors the buffered output compare function and TI
158. he program counter with the IRQ vector address The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order The interrupt request remains pending as long as the IRQ pin is low A reset will clear the IRQ latch and the MODE control bit thereby clearing the interrupt even if the pin stays low Use the BIH or BIL instruction to read the logic level on the IRQ pin 8 3 2 MODE 0 If the MODE bit is clear the IRQ pin is falling edge sensitive only With MODE clear an IRQ vector fetch or software clear immediately clears the IRQ latch The IRQF bit in INTSCR can be read to check for pending interrupts The IRQF bit is not affected by IMASK which makes it useful in applications where polling is preferred NOTE When using the level sensitive interrupt trigger avoid false IRQ interrupts by masking interrupt requests in the interrupt routine MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 75 External Interrupt IRQ 8 4 Interrupts The following IRQ source can generate interrupt requests e Interrupt flag IRQF The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode The IRQ interrupt mask bit IMASK is used to enable or disable IRQ interrupt requests 8 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 8 5 1 Wait Mode The IRQ module remains active in wait mode Clearing IMASK in INTSCR enables
159. high byte V Overflow bit hh Il High and low bytes of operand address in extended addressing X Index register low byte Interrupt mask 2 Zero bit ii Immediate operand byte amp Logical AND IMD Immediate source to direct destination addressing mode Logical OR IMM Immediate addressing mode Logical EXCLUSIVE OR INH Inherent addressing mode Contents of IX Indexed no offset addressing mode Negation two s complement 1 Indexed no offset post increment addressing mode Immediate value 1 0 Indexed with post increment to direct addressing mode Sign extend Indexed 8 bit offset addressing mode lt Loaded with IX1 Indexed 8 bit offset post increment addressing mode If IX2 Indexed 16 bit offset addressing mode Concatenated with M Memory location 1 Set or cleared N Negative bit affected 7 8 Opcode Map See Table 7 2 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 71 Central Processor Unit CPU pexepul jejuiod 10 apo seg jo jequnN 1604 epoodo 0145 8 0 epoodo 1950 eiAg L pexepu LXI oeurq ejeipeuuul
160. his read write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected This bit has no effect for the XTAL or external oscillator options 1 OSC2 pin outputs the internal or RC oscillator clock BUSCLKX4 0 5 2 pin configured for PTA4 I O having all the interrupt and pullup functions MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 99 Input Output Ports PORTS PTAPUE 5 0 Port A Input Pullup Enable Bits These read write bits are software programmable to enable pullup devices on port A pins 1 Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0 0 Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Table 12 1 summarizes the operation of the port A pins Table 12 1 Port A Pin Functions PTAPUE DDRA PTA Pin Accesses to DDRA Accesses to PTA Bit Bit Bit Mode Read Write Read Write 1 0 Input DDRA5 DDRAO Pin PTA5 PTAO 0 0 X Input Hi Z DDRAS5 DDRAO Pin PTA5 PTAO X 1 X Output 5 5 PTA5 PTAO 1 X 2 don t care 2 pin pulled to Vpp by internal pullup 3 Writing affects data register but does not affect input 4 Hi Z high impedance 5 Output does not apply to PTA2 12 3 Port B Port B is an 8 bit general purpose port Port B is only available the MC68HC908QY 1 MC68
161. ional information on how Freescale defines Typical Data Retention please refer to Engineering Bulletin EB618 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 163 Electrical Specifications MC68HC908QY QT Family Data Sheet Rev 5 164 Freescale Semiconductor Chapter 17 Ordering Information and Mechanical Specifications 17 1 Introduction This section contains order numbers for the MC68HC908QY 1 MC68HC908QY2 MC68HC908QYA MC68HC908QT1 MC68HC908QT2 and MC69HC908QT4 Dimensions are given for e 8 plastic dual in line package PDIP 8 small outline integrated circuit SOIC package e 8 dual flat no lead DFN package 16 PDIP e 16 pin SOIC e 16 pin thin shrink small outline package TSSOP 17 2 MC Order Numbers Table 17 1 MC Order Numbers MC Order Number ADC FLASH Memory Package MC908QY 1 1536 bytes 16 pins MC908QY2 Yes 1536 bytes PDIP SOIC MC908QY4 Yes 4096 bytes and TSSOP MC908QT1 1536 bytes MC908QT2 Yes 1536 bytes PDIP SOIC MC908QT4 Yes 4096 bytes and DFN Temperature and package designators C 40 C to 85 C V 40 to 105 M 40 to 125 P Plastic dual in line package PDIP DW Small outline integrated circuit package SOIC DT Thin shrink small outline package TSSOP FQ Dual flat no lead DFN MC908QY1XXXE Pb FREE FAMILY gt PACKAGE DESIGNATOR
162. ip Selection 86 10 4 LYI Stains Ease xad E d CR ERE Od 87 55 NEm bp 12 9 0 997 dodi pO de DEG Fer 87 VR PRIM S DRESS 87 10 6 1 ir emp TU 87 10 6 2 cara D LAE M LLL 87 Chapter 11 Oscillator Module OSC TES 89 89 The Funcional De 89 11 3 1 Menna OSMA o eee eee eee ee ee ee ee 90 11 3 1 1 intemal Oscilator 91 11 4 1 2 Internal to External Clock Switching 91 11 3 2 Exiemal iiia ka 91 11 3 3 4p me r 92 11 3 4 RC MUT 93 Oscilator Module 93 11 4 1 Crystal Amplifier Input Pin OSC1 93 11 4 2 Crystal Amplifier Output Pin OSC2 PTA4 BUSCLKX4 94 11 4 3 Oscillator Enable Signal SIMOSCEN anae 94 11 4 4 FOAL Cec 94 11 4 5 RC Oscillator Clock RCGLK ehe vb roba qe AME dM 94 11 4 6 deq
163. ircuit the RC oscillator or the internal oscillator 11 4 4 XTAL Oscillator Clock XTALCLK XTALCLK is the XTAL oscillator output signal It runs at the full speed of the crystal fc and comes directly from the crystal oscillator circuit Figure 11 2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors Also the frequency and amplitude of XTALCLK can be unstable at start up 11 4 5 RC Oscillator Clock RCCLK RCCLK is the RC oscillator output signal Its frequency is directly proportional to the time constant of external R and internal C Figure 11 3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry 11 4 6 Internal Oscillator Clock INTCLK INTCLK is the internal oscillator output signal Its nominal frequency is fixed to 12 8 MHz but it can be also trimmed using the oscillator trimming feature of the OSCTRIM register see 11 3 1 1 Internal Oscillator Trimming 11 4 7 Oscillator Out 2 BUSCLKX4 BUSCLKXA is the same as the input clock XTALCLK RCCLK or INTCLK This signal is driven to the SIM module and is used to determine the COP cycles 11 4 8 Oscillator Out BUSCLKX2 The frequency of this signal is equal to half of the BUSCLKXA this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU B
164. istics Characteristic Symbol Min Typ Max Unit Internal oscillator frequency fINTCLK 12 8 MHz Deviation from trimmed Internal oscillator 2 9 12 8 MHZ fixed voltage fixed temp ACCNT 0 4 9 12 8 MHz Vpp 10 0 70 2 12 8 MHz Vpp 10 40 to 125 C 5 Crystal frequency XTALCLK foscxcLk 1 16 MHz External RC oscillator frequency RCCLK 0 2 10 MHz External clock reference frequency 0 foscxcLk dc 16 MHz Crystal load capacitance C 20 pF Crystal fixed capacitance Cy Crystal tuning capacitance Feedback bias resistor Rp 0 5 1 10 MQ RC oscillator external resistor Rgxr See Figure 16 8 Crystal series damping resistor f 1 2 foscxcuc 4 Rs E 5 foscxcLk gt 8 MHz 0 1 Bus frequency is oscillator frequency divided by 4 2 Deviation values assumes trimming 25 C and midpoint of voltage range 3 Values are based on characterization results not tested in production 4 No more than 10 duty cycle deviation from 50 5 Consult crystal vendor data sheet 3 25 C 10 8 5 6 e 4 2 0 0 10 20 30 40 50 60 Reyr Figure 16 8 RC versus Frequency 3 Volts 25 MC68HC908QY QT Family Data Sheet Rev 5 158 Freescale Semic
165. ng a 1 to this read write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup Reset clears the IMASKK bit 1 Keyboard auto wakeup interrupt requests masked 0 Keyboard auto wakeup interrupt requests not masked NOTE is not used in conjuction with the auto wakeup feature To see description of this bit see 9 7 1 Keyboard Status and Control Register 4 6 3 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables the auto wakeup to operate as a keyboard auto wakeup interrupt input Address 001B Bit 7 6 5 4 3 2 1 Bit 0 Read 0 AWUIE KBIE5 KBIE4 KBIE1 KBIEO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 4 4 Keyboard Interrupt Enable Register KBIER AWUIE Auto Wakeup Interrupt Enable Bit This read write bit enables the auto wakeup interrupt input to latch interrupt requests Reset clears AWUIE 1 Auto wakeup enabled as interrupt input 0 Auto wakeup not enabled as interrupt input NOTE 5 bits are not used in conjuction with the auto wakeup feature To see a description of these bits see 9 7 2 Keyboard Interrupt Enable Register MC68HC908QY QT Family Data Sheet Rev 5 52 Freescale Semiconductor Chapter 5 Configuration Register CONFIG 5 1 Introduction This section describes the configuration regist
166. ng stop mode LVIRSTD LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module 1 LVI module resets disabled 0 LVI module resets enabled MC68HC908QY QT Family Data Sheet Rev 5 54 Freescale Semiconductor Functional Description LVIPWRD LVI Power Disable Bit LVIPWRD disables the LVI module 1 LVI module power disabled 0 LVI module power enabled LVI5OR3 LVI 5 V or 3 V Operating Mode Bit LVIBORG selects the voltage operating mode of the LVI module The voltage mode selected for the LVI should match the operating Vpp for the LVI s voltage trip points for each of the modes 1 LVI operates in 5 V mode 0 LVI operates in 3 V mode NOTE The LVI5OR3 bit is cleared by a power on reset POR only Other resets will leave this bit unaffected SSREC Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKXA cycles instead of a 4096 BUSCLKXA cycle delay 1 Stop mode recovery after 32 BUSCLKXA cycles 0 Stop mode recovery after 4096 BUSCLKXA cycles NOTE Exiting stop mode by an LVI reset will result in the long stop recovery The system stabilization time for power on reset and long stop recovery both 4096 BUSCLKX4 cycles gives a delay longer than the LVI enable time for these startup scenarios There is no period where the MCU is not protected from a low power condition However when using the short stop recovery configuration option the 32 BUSCLKXA delay
167. nloaded into internal RAM The mass erase operation clears the security code locations so that all eight security bytes become FF blank Vpp 4096 32 CGMXCLK CYCLES RST a gt gt gt e a FROM HOST um Tea 256 BUS CYCLES MINIMUM SN 1 to x I lt a as o g Notes m 2 1 Echo delay 2 bit times E c lt 2 Data return delay 2 bit times 4 Wait 1 bit time before sending next byte 9 Figure 15 18 Monitor Mode Entry Timing MC68HC908QY QT Family Data Sheet Rev 5 148 Freescale Semiconductor Chapter 16 Electrical Specifications 16 1 Introduction This section contains electrical and timing specifications 16 2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit MCU can be exposed without permanently damaging it NOTE This device is not guaranteed to operate properly at the maximum ratings Refer to 16 5 5 V DC Electrical Characteristics and 16 9 3 V DC Electrical Characteristics for guaranteed operating conditions Characteristic Symbol Value Unit Supply voltage Vpp 0 3 to 6 0 V Input voltage Vss 0 3 to Vpp 0 3 V Mode entry voltage IRQ pin Vist Vss 0 3 to 9 1 V Maximum current per pin excluding PTAO PTAS Vpp and Vas 15 mA
168. nput overriding the data direction register However the data direction register bit must be a 0 for software to read the pin 9 3 2 Keyboard Initialization When a keyboard interrupt pin is enabled it takes time for the internal pullup to reach a logic 1 Therefore a false interrupt can occur as soon as the pin is enabled To prevent a false interrupt on keyboard initialization 1 Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register 2 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3 Write to the ACKK bit in the keyboard status and control register to clear any false interrupts 4 Clear the IMASKK bit An interrupt signal on an edge triggered pin can be acknowledged immediately after enabling the pin An interrupt signal on an edge and level triggered interrupt pin must be acknowledged after a delay that depends on the external load Another way to avoid a false interrupt 1 Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A 2 Write 1s to the appropriate port A data register bits 3 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 9 4 Wait Mode The keyboard module remains active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode
169. ns Address 9 08 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 HVEN MASS ERASE PGM Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 2 3 FLASH Control Register FLCR HVEN High Voltage Enable Bit This read write bit enables high voltage from the charge pump to the memory for either program or erase operation It can only be set if either 1 or ERASE 1 and the proper sequence for program or erase is followed 1 High voltage enabled to array and charge pump 0 High voltage disabled to array and charge pump off MASS Mass Erase Control Bit This read write bit configures the memory for mass erase operation 1 Mass erase operation selected 0 Mass erase operation unselected 1 No security feature is absolutely secure However Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 33 ERASE Erase Control Bit This read write bit configures the memory for erase operation ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Erase operation selected 0 Erase operation unselected PGM Program Control Bit This read write bit configures the memory for program operation PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Program
170. nter and prescaler by setting the TIM reset bit TRST In the TIM counter modulo registers TMODH TMODL write the value for the required PWM period In the TIM channel x registers TCHxH TCHXxL write the value for the required pulse width In TIM channel x status and control register TSCx a Write 0 1 for unbuffered output compare or PWM signals or 1 0 for buffered output compare or PWM signals to the mode select bits MSxB MSxA See Table 14 3 b Write 1 to the toggle on overflow bit TOVx Write 1 0 polarity 1 to clear output on compare or 1 1 polarity 0 to set output on compare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 14 3 NOTE In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 0 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value In the TIM status control register TSC clear the TIM stop bit TSTOP Setting MSOB links channels 0 and 1 and configures them for buffered PWM operation The TIM channel 0 registers TCHOH TCHOL initially control the buffered PWM output TIM status control register 0 TSCRO controls and monitors the PW
171. ock Table 3 2 shows the available clock configurations The ADC clock frequency should be set between fapicqminy and fapic max The analog input level should remain stable for the entire conversion time maximum 17 ADC clock cycles Table 3 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADIVO ADC Clock Rate 0 0 0 Bus clock 1 0 0 1 Bus clock 2 0 1 0 Bus clock 4 0 1 1 Bus clock 8 1 X X Bus clock 16 X 2 don t care MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 47 AE eee Analog to Digital Converter ADC MC68HC908QY QT Family Data Sheet Rev 5 48 Freescale Semiconductor Chapter 4 Auto Wakeup Module AWU 4 1 Introduction This section describes the auto wakeup module AWU The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal Figure 4 1 is a block diagram of the AWU 4 2 Features Features of the auto wakeup module include e One internal interrupt with separate interrupt enable bit sharing the same keyboard interrupt vector and keyboard interrupt mask bit e Exit from low power stop mode without external signals Selectable timeout periods e Dedicated low power internal oscillator separate from the main system clock sources 4 3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit MCU out of stop mode The wakeup
172. of the instruction just executed Bits 6 and 5 are set permanently to 1 The following paragraphs describe the functions of the condition code register Bit 7 6 5 4 3 2 1 Bit 0 Read V 1 1 H 2 C Write Reset X 1 1 X 1 X X X X Indeterminate Figure 7 6 Condition Code Register CCR V Overflow Flag The CPU sets the overflow flag when a two s complement overflow occurs The signed branch instructions BGT BGE BLE and BLT use the overflow flag 1 Overflow 0 No overflow H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor 1 Carry between bits 3 and 4 0 No carry between bits 3 and 4 Interrupt Mask When the interrupt mask is set all maskable CPU interrupts are disabled CPU interrupts are enabled when the interrupt mask is cleared When a CPU interrupt occurs the interrupt mask is set automatically after the CPU registers are saved on the stack but before the interrupt vector is fetched 1 Interrupts disabled 0 Interrupts enabled NOTE To maintain M6805 Family compatibility the upper byte of the index register H is not stacked automatically If the interrupt ser
173. ogram and erase When bits within the FLBPR are programmed they lock a block of memory The address ranges are shown in 2 6 6 FLASH Block Protect Register Once the FLBPR is programmed with a value other than FF any erase or program of the FLBPR or the protected block of FLASH memory is prohibited Mass erase is disabled whenever any block is protected FLBPR does not equal FF The FLBPR itself can be erased or programmed only with an external voltage present on the IRQ pin This voltage also allows entry from reset into the monitor mode MC68HC908QY QT Family Data Sheet Rev 5 36 Freescale Semiconductor Algorithm for Programming a Row 32 Bytes of FLASH Memory SET READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED Y WAIT FOR A TIME tyyg Y SET HVEN BIT Y WAIT FOR A TIME NOTES The time between each FLASH address change step 7 to step 7 or the time between the last FLASH address programmed to clearing PGM bit step 7 to step 10 must not exceed the maximum programming time 1 max This row program algorithm assumes the row s to be programmed are initially erased WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME Y COMPLETED PROGRAMMING THIS ROW
174. om reset to allow the reset vector sequence to occur The SIM actively pulls down the RST pin for all internal reset sources 13 5 SIM Counter The SIM counter is used by the power on reset module POR and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus IBUS clocks The SIM counter also serves as a prescaler for the computer operating properly module COP The SIM counter uses 12 stages for counting followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module The SIM counter is clocked by the falling edge of BUSCLKXA 13 5 1 SIM Counter During Power On Reset The power on reset module POR detects power applied to the MCU At power on the POR circuit asserts the signal PORRST Once the SIM is initialized it enables the oscillator to drive the bus clock state machine MC68HC908QY QT Family Data Sheet Rev 5 108 Freescale Semiconductor Exception Control 13 5 2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery The STOP instruction clears the SIM counter After an interrupt break or reset the SIM senses the state of the short stop recovery bit SSREC in the configuration register 1 CONFIG1 If SSREC bit is a 1 then the stop recovery is reduced from the normal delay of 4096 BUSCLKXA cycles down to 32 BUSCLKXA cycles This is ideal for applications using canned oscillators that do not requir
175. onductor Supply Current Characteristics 16 13 Supply Current Characteristics Bus Characteristic Voltage Frequency Symbol Typ Max Unit MHz 5 0 3 2 Bi 6 0 7 0 Mode Vpp supply current 3 0 32 DD 25 32 5 0 3 2 1 0 1 5 i 4 Wait Mode Vpp supply current 3 0 32 Wlpp 0 67 1 0 mA Stop Mode Vpp supply current 40 to 85 C 0 04 1 0 40 to 105 C 2 0 5 0 SI A 40 to 125 DD 5 0 25 with auto wakeup enabled 7 Incremental current with LVI enabled at 25 125 Stop Mode Vpp supply current 40 to 85 C 0 02 0 5 40 to 105 C 1 0 3 0 SI A 40 to 125 DD 4 0 25 with auto wakeup enabled 5 Incremental current with LVI enabled at 25 100 Vss 0 Vdc Ta T to Ty unless otherwise noted 2 Typical values reflect average measurements at 25 C only 3 Run operating measured using trimmed internal oscillator off all other modules enabled All pins configured as inputs and tied to 0 2 V from 4 Wait Ipp measured using trimmed internal oscillator ADC off all other modules enabled All pins configured as inputs and tied to 0 2 V from rail 5 Stop Ipp measured with all pins tied to 0 2 V or less from rail No dc loads On the 8 pin versions port B is configured as inputs with pullups enabled MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 159 Electrical Specifica
176. onitor mode entry the MCU waits after the power on reset for the host to send the eight security bytes on pin If the received bytes match those at locations F FF6 FFFD the host bypasses the security feature and can read all FLASH locations and execute code from FLASH Security remains bypassed until a power on reset occurs If the reset was not a power on reset security remains bypassed and security code entry is not required See Figure 15 18 Upon power on reset if the received bytes of the security code do not match the data at locations FFF6 FFFD the host fails to bypass the security feature The MCU remains in monitor mode but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset After receiving the eight security bytes from the host the MCU transmits a break character signifying that it is ready to receive a command NOTE The MCU does not transmit a break character until after the host sends the eight security bytes To determine whether the security code entered is correct check to see if bit 6 of RAM address 80 is set If it is then the correct security code has been entered and FLASH can be accessed If the security sequence fails the device should be reset by a power on reset and brought up in monitor mode to attempt another entry After failing the security sequence the FLASH module can also be mass erased by executing an erase routine that was dow
177. operation selected 0 Program operation unselected 2 6 2 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory A page consists of 64 consecutive bytes starting from addresses XX40 XX80 or XXCO The 48 byte user interrupt vectors area also forms a page Any FLASH memory page can be erased alone 1 Setthe ERASE bit and clear the MASS bit in the FLASH control register Read the FLASH block protect register Write any data to any FLASH location within the address range of the block to be erased Wait for a time tuys minimum 10 us Set the HVEN bit Wait for a time tErase minimum 1 ms 4 ms Clear the ERASE bit Wait for a time tyyp minimum 5 us Clear the HVEN bit After time tracy typical 1 us the memory can be accessed in read mode again NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order as shown but other unrelated operations may occur between the steps en oZ ee I9 CAUTION A page erase of the vector page will erase the internal oscillator trim value at FFCO In applications that require more than 1000 program erase cycles use the 4 ms page erase specification to get improved long term reliability Any application can use this 4 ms page erase specification However in applications where a FLASH location will be erased and
178. or internal oscillator output OSC2EN 1 in PTAPUE register Output AD2 A D channel 2 input Input KBl4 Keyboard interrupt input 4 Input 5 General purpose port Input Output OSC1 XTAL RC or external oscillator input Input AD3 A D channel input Input KBI5 Keyboard interrupt input 5 Input PTB 0 7 8 general purpose ports Input Output 1 The PTB pins are not available on the 8 pin packages see note in 12 1 Introduction 22 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Pin Function Priority 1 6 Pin Function Priority Table 1 3 is meant to resolve the priority if multiple functions are enabled on a single pin NOTE Upon reset all pins come up as input ports regaraless of the priority table Table 1 3 Function Priority in Shared Pins Pin Name Highest to Lowest Priority Sequence PTAO ADO PTA1 AD1 TCH1 KBl1 PTA1 PTA2 IRQ 5 KBI2 TCLK RST gt gt PTA4 OSC2 AD2 5 KBI4 gt 4 5 OSC1 gt AD3 5 KBI5 gt 5 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 23 General Description MC68HC908QY QT Family Data Sheet Rev 5 24 Freescale Semiconductor Chapter 2 Memory 2 1 Introduction The central processor unit CPU08 can address 64 Kbytes of memory space The memory map shown in Figure 2 1
179. or is selected no external clock required MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 141 Development Support Table 15 1 Monitor Mode Signal Requirements and Options Communication RQ RST Reset Communk Selection Speed cation Mode PTA2 PTA3 Vector COP 5 Comments xterna us au PEAU Clock Frequency Rate Normal 9 8304 2 4576 Provide external V Monitor Tel VoD 5 Disabled MHz MHz 3900 clock at OSC1 FFFF 9 8304 2 4576 Provide external V Forced PP X ban 1 X X Disabled MHz MHz 9600 OSCI Monitor FFFF 3 2 MHz Internal clock Vss x blank x Trimmed 9600 is active Not User X X FFFF X X X Enabled X X X MONOS Vist RST _ COM MoDo MOD _ osci 7 Pinno M 112 10 13 1 PTAO must have a pullup resistor to Vpp in monitor mode 2 Communication speed in the table is an example to obtain a baud rate of 9600 Baud rate using external oscillator is bus frequency 256 and baud rate using internal oscillator is bus frequency 335 3 External clock is a 9 8304 MHz oscillator on OSC1 4 X don t care 5 MONOS pin refers to P amp E Microcomputer Systems MONO8 Cyclone 2 by 8 pin connector NC 1 2 GND 3 4 RST 5 6 IRQ 7 8 NC 9 10 NC 11 12 PTA1 OS
180. ort A is a 6 bit special function port that shares all six of its pins with the keyboard interrupt module see Chapter 9 Keyboard Interrupt Module KBI Each port A pin also has a software configurable pullup device if the corresponding port pin is configured as an input port NOTE is input only When the IRQ function is enabled in the configuration register 2 CONFIG2 bit 2 of the port A data register PTA will always read 0 In this case the BIH and BIL instructions can be used to read the logic level on the pin When the IRQ function is disabled these instructions will behave as if the PTA2 pin is a logic 1 However reading bit 2 of PTA will read the actual logic level on the pin MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 97 Input Output Ports PORTS 12 2 1 Port A Data Register The port A data register PTA contains a data latch for each of the six port A pins Address 0000 Bit 7 6 5 4 3 2 1 Bit 0 Read AWUL PTA2 R 5 4 PTA1 PTAO Write Reset Unaffected by reset Additional Functions KBI5 KBI4 KBI3 2 KBH KBIO R Reserved Unimplemented Figure 12 1 Port A Data Register PTA PTA 5 0 Port A Data Bits These read write bits are software programmable Data direction of each port A pin is under the control of the corresponding bit in data direction register A Reset has no eff
181. pt has been deasserted MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 65 Central Processor Unit CPU 7 7 Instruction Set Summary Table 7 1 provides a summary of the M68HC08 instruction set Table 7 1 Instruction Set Summary Sheet 1 of 6 Effect 2 o g 4 Operation Description CCR 5 g 9 S 28 H IINZIC 23 6 6 6 IMM A9 Jii 2 ADC opr DIR B9 4 3 ADC opr EXT C9 hhll 4 AD X IX2 D ff 4 ADC pa Add with Carry A lt A C ES 89 3 ADC X IX F9 2 ADC opr SP SP1 9EE9 ff 4 ADC opr SP SP2 9ED9 5 ADD opr IMM AB 2 ADD opr DIR BB dd 3 ADD opr EXT hhll 4 ADD 1 2 DB 4 ADD Add without Carry A lt M 11 1111 1X4 EB f 3 ADD IX FB 2 ADD 5 SP1 9EEB ff 4 ADD opr SP SP2 9EDB 5 AIS opr Add Immediate Value Signed to SP SP lt SP 16 M IMM A7 2 AIX opr Add Immediate Value Signed to H X lt 16 M epe IMM AF ii 2 AND opr IMM A4 iii 2 AND opr DIR 4 3 AND opr EXT C4 hhil 4 AND _ _ IX2 D4 4 AND opr X Logical AND A lt A amp M 111 1X4 ff 3 AND IX 2 AND opr SP SP1 9EEA ff 4 AND opr SP SP2 9ED4 ff 5 ASL opr DIR
182. r 14 Timer Interface Module TIM Added TCLK function 131 139 15 3 Monitor Module MON Updated with additional data 147 Chapter 16 Electrical Specifications Updated with additional data 169 173 Figure 2 2 Control Status and Data Registers Deleted unimplemented areas FFBO FFBD and FFC2 FFCF as they are actually available 27 Also corrected FFBF designation from unimplemented to reserved Figure 6 1 COP Block Diagram Reworked for clarity 59 6 3 2 STOP Instruction Added subsection 60 13 4 2 Active Resets from Internal Sources Reworked notes for clarity 111 October Table 13 2 Reset Recovery Timing Replaced previous table with new 2 0 4 112 2003 information Chapter 14 Timer Interface Module TIM Updated with additional data 131 Figure 15 3 Break I O Register Summary Corrected bit designators for the 143 BRKAR register 15 3 Monitor Module MON Clarified seventh bullet 147 Table 17 1 MC Order Numbers Corrected temperature and package 175 designators Figure 2 2 Control Status and Data Registers Corrected reset state for the FLASH Block Protect Register at address location FFBE and the Internal 32 3 0 Oscillator Trim Value at FFCO Figure 2 5 FLASH Block Protect Register FLBPR Restated reset state for 38 clarity Freescale Semiconductor MC68HC908QY QT Family Data Sheet Rev 5 Revision History Revision History Sheet 3
183. r will have a 25 tolerance pre trim then the 25 case should not allow a frequency higher than 4 MHz 3 2 MHz 25 4 MHz Figure 11 3 shows how BUSCLKXA is derived from INTCLK and like the RC oscillator OSC2 can output BUSCLKXA by setting OSC2EN in PTAPUE register See Chapter 12 Input Output Ports PORTS MC68HC908QY QT Family Data Sheet Rev 5 90 Freescale Semiconductor Functional Description 11 3 1 1 Internal Oscillator Trimming The 8 bit trimming register OSCTRIM allows a clock period adjust of 127 and 128 steps Increasing OSCTRIM value increases the clock period Trimming allows the internal clock frequency to be set to 12 8 MHz x 5 All devices are programmed with a trim value in a reserved FLASH location FFCO This value can be copied from the FLASH to the OSCTRIM register 0038 during reset initialization Reset loads OSCTRIM with a default value of 80 WARNING Bulk FLASH erasure will set location FFCO to FF and the factory programmed value will be lost 11 3 1 2 Internal to External Clock Switching When external clock source external OSC RC or XTAL is desired the user must perform the following steps 1 For external crystal circuits only OSCOPT 1 0 1 1 To help precharge an external crystal oscillator set PTA4 OSC2 as an output and drive high for several cycles This may help the crystal circuit start more robustly 2 Set CONFIG2 bits OSCOPT 1 0 according to The oscillator mod
184. rand Bit Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Figure 7 4 Stack Pointer SP NOTE The location of the stack is arbitrary and may be relocated anywhere in random access memory RAM Moving the SP out of page 0 0000 to 00FF frees direct address page 0 space For correct operation the stack pointer must point only to RAM locations 7 3 4 Program Counter The program counter is a 16 bit register that contains the address of the next instruction or operand to be fetched Normally the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched Jump branch and interrupt operations load the program counter with an address other than that of the next sequential location During reset the program counter is loaded with the reset vector address located at FFFE and FFFF The vector address is the address of the first instruction to be executed after exiting the reset state Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write Reset Loaded with vector from FFFE and FFFF Figure 7 5 Program Counter PC MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 63 Central Processor Unit CPU 7 3 5 Condition Code Register The 8 bit condition code register contains the interrupt mask and five flags that indicate the results
185. re not accessible by the CPU Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode If TIM functions are not required during wait mode reduce power consumption by stopping the TIM before executing the WAIT instruction 14 7 TIM During Break Interrupts A break interrupt stops the TIM counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the break flag control register BFCR enables software to clear status bits during the break state See 13 8 2 Break Flag Control Register To allow software to clear status bits during a break interrupt write a 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a O to the BCFE bit With BCFE at 0 its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a two step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at O After the break doing the second step clears the status bit 14 8 Input Output Signals Port A shares three of its pins with the TIM Two TIM channel I O pins are PTAO TCHO and PTA1 TCH1 and an alternate clock source is PTA2 TCLK 14 8 1 TIM Clock Pin PTA2 TCL
186. reprogrammed less than 1000 times and speed is important use the 1 ms page erase specification to get a shorter cycle time MC68HC908QY QT Family Data Sheet Rev 5 34 Freescale Semiconductor FLASH Memory FLASH 2 6 3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1 1 JT eI Set both the ERASE bit and the MASS bit in the FLASH control register Read the FLASH block protect register Write any data to any FLASH address within the FLASH memory address range Wait for a time tyys minimum 10 us Set the HVEN bit Wait for a time tMErase minimum 4 ms Clear the ERASE and MASS bits NOTE Mass erase is disabled whenever any block is protected FLBPR does not equal FF Wait for a time tyyp minimum 100 us Clear the HVEN bit After time tracy typical 1 us the memory be accessed in read mode again NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order as shown but other unrelated operations may occur between the steps CAUTION A mass erase will erase the internal oscillator trim value at FFCO 2 6 4 FLASH Program Operation Programming of the FLASH memory is done on a row basis A row consists of 32 consecutive bytes starting from addresses 5 XX20 XX40 XX60 XX80 XXAO XXCO or XXEO Use the following step
187. ress and unimplemented 27 memory Figure 2 2 Control Status and Data Registers Corrected bit definitions for 27 Port A Data Register PTA and Data Direction Register A DDRA Table 13 3 Interrupt Sources Corrected vector addresses for keyboard 118 interrupt and ADC conversion complete interrupt Chapter 13 System Integration Module SIM Removed reference to break 274 113 status register as it is duplicated in break module 11 3 1 Internal Oscillator and 11 3 1 1 Internal Oscillator Trimming Clarified oscillator trim option ordering information and what to expect with untrimmed 92 device Figure 11 5 Oscillator Trim Register OSCTRIM Bit 1 designation corrected 98 Figure 15 13 Monitor Mode Circuit Internal Clock No High Voltage 150 December a Diagram updated for clarity 2002 Figure 12 1 1 Port Register Summary Corrected bit definitions for 7 99 DDRAT and DDRA6 Figure 12 2 Port A Data Register PTA Corrected bit definition for PTA7 100 Figure 12 3 Data Direction Register A DDRA Corrected bit definitions for 101 DDRA7 and DDRA6 Figure 12 6 Port B Data Register PTB Corrected bit definition for PTB1 103 Chapter 9 Keyboard Interrupt Module KBI Section reworked after deletion 83 of auto wakeup for clarity Chapter 4 Auto Wakeup Module AWU New section added for clarity 49 Figure 10 1 LVI Module Block Diagram Corrected LVI stop representation 87 Ch
188. rnally There is no port or any of the associated bits such as PTA6 data direction or pullup bits 1 Auto wakeup interrupt request is pending 0 Auto wakeup interrupt request is not pending NOTE 5 bits are not used in conjuction with the auto wakeup feature To see a description of these bits see 12 2 1 Port A Data Register 4 6 2 Keyboard Status and Control Register The keyboard status and control register KBSCR e Flags keyboard auto wakeup interrupt requests e Acknowledges keyboard auto wakeup interrupt requests e Masks keyboard auto wakeup interrupt requests Address 001A Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 4 3 Keyboard Status and Control Register KBSCR MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 51 Auto Wakeup Module AWU Bits 7 4 Not used These read only bits always read as Os KEYF Keyboard Flag Bit This read only bit is set when a keyboard interrupt is pending on port A or auto wakeup Reset clears the KEYF bit 1 Keyboard auto wakeup interrupt pending 0 No keyboard auto wakeup interrupt pending ACKK Keyboard Acknowledge Bit Writing a 1 to this write only bit clears the keyboard auto wakeup interrupt request on port A and auto wakeup logic ACKK always reads as 0 Reset clears ACKK IMASKK Keyboard Interrupt Mask Bit Writi
189. ructure of the LVI module LVISTOP LVIPWRD and LVIRSTD user selectable options found in the configuration register CONFIG1 See Chapter 5 Configuration Register CONFIG STOP INSTRUCTION FROM CONFIG FROM CONFIG LVIRSTD FROM CONFIG LOW Vpp Vpp LVITRIP 0 LVI RESET DETECTOR v LVITRIP 1 LVIOUT LVIBOR3 FROM CONFIG Figure 10 1 LVI Module Block Diagram The LVI is enabled out of reset The LVI module contains a bandgap reference circuit and comparator Clearing the LVI power disable bit LVIPWRD enables the LVI to monitor Vpp voltage Clearing the LVI reset disable bit LVIRSTD enables the LVI module to generate a reset when Vpp falls below a voltage MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 85 Low Voltage Inhibit LVI Setting the LVI enable in stop mode bit LVISTOP enables the LVI to operate in stop mode Setting the LVI 5 V or 3 V trip point bit LVIBORS enables the trip point voltage Vtpipr to be configured for 5 V operation Clearing the LVIBORG bit enables the trip point voltage to be configured for 3 V operation The actual trip thresholds are specified in 16 5 5 V DC Electrical Characteristics and 16 9 3 V DC Electrical Characteristics NOTE After a power on reset the LVI s default mode of operation is 3 volts If a 5 V system is used the user must set the 5 bit to rais
190. ry See Figure 2 6 and Table 2 2 START ADDRESS OF FLASH BLOCK PROTECT 16 BIT MEMORY ADDRESS Figure 2 6 FLASH Block Protect Start Address BPR 7 0 Table 2 2 Examples of Protect Start Address Start of Address of Protect Range 00 B8 The entire FLASH memory is protected B9 1011 1001 EE40 1110 1110 0100 0000 BA 1011 1010 EE80 1110 1110 1000 0000 EECO 1110 1110 1100 0000 BB 1011 1011 BC 1011 1100 EFOO 1110 1111 0000 0000 and so on DE 1101 1110 F780 1111 0111 1000 0000 DF 1101 1111 F7CO 1111 0111 1100 0000 FE 1111 1110 FF80 1111 1111 1000 0000 FLBPR OSCTRIM and vectors are protected FF The entire FLASH memory is not protected 38 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor FLASH Memory FLASH 2 6 7 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly but there will not be any memory activity since the CPU is inactive The WAIT instruction should not be executed while performing a program or erase operation on the FLASH or the operation will discontinue and the FLASH will be on standby mode 2 6 8 Stop Mode Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly but there will not be any memory activi
191. s e Controls keyboard interrupt triggering sensitivity Address 001A Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 3 Keyboard Status and Control Register KBSCR Bits 7 4 Not used These read only bits always read as Os KEYF Keyboard Flag Bit This read only bit is set when a keyboard interrupt is pending on port A or auto wakeup Reset clears the KEYF bit 1 2 Keyboard interrupt pending 0 No keyboard interrupt pending ACKK Keyboard Acknowledge Bit Writing a 1 to this write only bit clears the keyboard interrupt request on port A and auto wakeup logic ACKK always reads as 0 Reset clears ACKK IMASKK Keyboard Interrupt Mask Bit Writing a 1 to this read write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup Reset clears the IMASKK bit 1 2 Keyboard interrupt requests masked 0 Keyboard interrupt requests not masked MODEK Keyboard Triggering Sensitivity Bit This read write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wakeup Reset clears MODEK 1 Keyboard interrupt requests on falling edges and low levels 0 Keyboard interrupt requests on falling edges only MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 83 Keyboard Interrupt Module KBI 9 7 2 Keyboard
192. sabled when its corresponding DDRBx bit is configured as output Address 000C Bit 7 6 5 4 3 2 1 Bit 0 Read PTBPUE7 PTBPUE6 5 PTBPUE4 PTBPUE2 PTBPUE2 PTBPUEO rite Reset 0 0 0 0 0 0 0 0 Figure 12 8 Port B Input Pullup Enable Register PTBPUE PTBPUE 7 0 Port B Input Pullup Enable Bits These read write bits are software programmable to enable pullup devices on port B pins 1 Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0 0 Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit Table 12 3 summarizes the operation of the port B pins Table 12 3 Port B Pin Functions PTBPUE DDRB PTB 1 0 Pin Accesses to DDRB Accesses to PTB Bit Bit Bit Mode Read Write Read Write 1 0 Input Vpp 2 DDRB7 DDRBO Pin 7 0 0 X Input Hi Z DDRB7 DDRBO Pin 7 X 1 X Output DDRB7 DDRBO PTB7 PTBO PTB7 PTBO 1 X 2 don t care 2 pin pulled to Vpp by internal pullup 3 Writing affects data register but does not affect input 4 Hi Z high impedance MC68HC908QY QT Family Data Sheet Rev 5 102 Freescale Semiconductor Chapter 13 System Integration Module SIM 13 1 Introduction This section describes the system integration module SIM which supports up to 24 external and or internal interr
193. set it must be cleared by clearing TSTOP then clearing the flag then setting TSTOP again MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 127 Timer Interface Module TIM TRST TIM Reset Bit Setting this write only bit resets the TIM counter and the TIM prescaler Setting TRST has no effect on any other registers Counting resumes from 0000 TRST is cleared automatically after the TIM counter is reset and always reads as a 0 Reset clears the TRST bit 1 Prescaler and TIM counter cleared 0 No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of 0000 PS 2 0 Prescaler Select Bits These read write bits select either the PTA2 TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 14 2 shows Reset clears the PS 2 0 bits Table 14 2 Prescaler Selection PS2 PS1 PSO TIM Clock Source 0 0 0 Internal bus clock 1 0 0 1 Internal bus clock 2 0 1 0 Internal bus clock 4 0 1 1 Internal bus clock 8 1 0 0 Internal bus clock 16 1 0 1 Internal bus clock 32 1 1 0 Internal bus clock 64 1 1 1 2 14 9 2 TIM Counter Registers The two read only TIM counter registers contain the high and low bytes of the value in the TIM counter Reading the high byte TCNTH latches the contents of the low byte TCNTL into a buffer Subsequent reads of TCNTH do not affect the latched TC
194. so divided by two to create BUSCLKX2 In this configuration the OSC2 pin cannot output BUSCLKX4 So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I O functions on the pin MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 91 Oscillator Module OSC 11 3 3 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source In this configuration the OSC2 pin is dedicated to the external crystal circuit The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected In its typical configuration the XTAL oscillator is connected in a Pierce oscillator configuration as shown in Figure 11 2 This figure shows only the logical representation of the internal components and may not represent actual circuitry The oscillator configuration uses five components e Crystal X e Fixed capacitor e Tuning capacitor can also be a fixed capacitor e Feedback resistor Rg e Series resistor optional NOTE The series resistor Rg is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation especially with high frequency crystals Refer to the crystal manufacturer s data for more information FROM SIM TO SIM TO SIM BUSCLKX4 BUSCLKX2 XTALCLK 5154 SIMOSCEN MCU OSC1
195. ss 0024 TMODL Read Write Reset 1 1 1 1 1 1 1 1 Figure 14 6 TIM Counter Modulo Registers TMODH TMODL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NOTE Reset the TIM counter before writing to the TIM counter modulo registers 14 9 4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following Flags input captures and output compares Enables input capture and output compare interrupts e Selects input capture output compare PWM operation e Selects high low or toggling output on output compare e Selects rising edge falling edge or any edge as the active input capture trigger e Selects output toggling on TIM overflow e Selects 0 and 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 129 Timer Interface Module TIM Address 0025 TSCO Bit 7 6 5 4 3 2 1 Bit 0 Read CHOF CHOIE 50 50 ELSOB ELSOA TOVO CHOMAX Write 0 Reset 0 0 0 0 0 0 0 0 Address 0028 TSC1 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write 0 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 7 TIM Channel Status and Control Registers TSCO TSC1 CHxF Channel x Flag Bit When channel x is an input capture channel this read writ
196. status register BSR e Break flag control register BFCR MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 135 Development Support 15 2 2 1 Break Status and Control Register The break status and control register BRKSCR contains break module enable and status bits Address FEOB Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 BRKE BRKA Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 15 3 Break Status and Control Register BRKSCR BRKE Break Enable Bit This read write bit enables breaks on break address register matches Clear BRKE by writing a O to bit 7 Reset clears the BRKE bit 1 Breaks enabled on 16 bit address match 0 Breaks disabled BRKA Break Active Bit This read write status and control bit is set when a break address match occurs Writing a 1 to BRKA generates a break interrupt Clear BRKA by writing a 0 to it before exiting the break routine Reset clears the BRKA bit 1 Break address match 0 No break address match 15 2 2 2 Break Address Registers The break address registers BRKH and BRKL contain the high and low bytes of the desired breakpoint address Reset clears the break address registers Address 5 09 Bit 7 6 5 4 3 2 1 Bit 0 Read 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Figure 15 4 Break Address Register High BRKH Ad
197. t Signals The ADC module has four channels that are shared with I O port A ADC voltage in ADCVIN is the input voltage signal from one of the four ADC channels to the ADC module 3 7 Input Output Registers These registers control and monitor ADC operation ADC status and control register ADSCR ADC data register ADR e ADC clock register ADICLK 3 7 1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register ADSCR When a conversion is in process and the ADSCR is written the current conversion data should be discarded to prevent an incorrect reading Address 003C Bit 7 6 5 4 3 2 1 Bit 0 ADCO CH4 CH3 CH2 CH1 CHO Write R Reset 0 0 0 1 1 1 1 1 R Reserved Figure 3 3 ADC Status and Control Register ADSCR COCO Conversions Complete Bit In non interrupt mode AIEN 0 is a read only bit that is set at the end of each conversion COCO will stay set until cleared by a read of the ADC data register Reset clears this bit In interrupt mode AIEN 1 COCO is a read only bit that is not set at the end of a conversion It always reads as a O 1 Conversion completed AIEN 0 0 Conversion not completed AIEN 0 or CPU interrupt enabled AIEN 1 NOTE The write function of the COCO bit is reserved When writing to the ADSCR register always have a 0 in the C
198. t compare channel ELSxB and ELSxA control the channel x output behavior when an output compare occurs When ELSxB and ELSxA are both clear channel x is not connected to an port and pin TCHx is available as a general purpose pin Table 14 3 shows how ELSxB and ELSxA work Reset clears the ELSxB and ELSxA bits NOTE After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity clear CHxF to ignore any erroneous edge detection flags TOVx Toggle On Overflow Bit When channel x is an output compare channel this read write bit controls the behavior of the channel x output when the TIM counter overflows When channel x is an input capture channel TOVx has no effect Reset clears the bit 1 Channel x pin toggles on TIM counter overflow 0 Channel x pin does not toggle on counter overflow NOTE When TOVXx is set TIM counter overflow takes precedence over channel x output compare if both occur at the same time MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 131 Timer Interface Module TIM CHxMAX Channel x Maximum Duty Cycle Bit When the TOVXx bit is at a 1 setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As Figure 14 8 shows the CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after is cleared
199. te byte to memory Operand 2 byte address in high byte low byte order low byte followed by data byte Data Returned None Opcode 49 Command Sequence FROM HOST 5 VABDRES8 ADDRESS ADDRES ware Y HIGH HIGH LOW 4 LOW 1 DATA A Table 15 5 IREAD Indexed Read Command Description Read next 2 bytes in memory from last address accessed Operand None Data Returned Returns contents of next two addresses Opcode 1A Command Sequence FROM HOST IREAD IREAD ECHO DATA DATA RETURN Table 15 6 IWRITE Indexed Write Command Description Write to last address accessed 1 Operand Single data byte Data Returned None Opcode 19 Command Sequence FROM HOST A sequence of IREAD or IWRITE commands can access block of memory sequentially over the full 64 Kbyte memory map 146 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor Monitor Module MON Table 15 7 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Returns incremented stack pointer value SP 1 in high byte low byte order Opcode 0C Data Returned Command Sequence FROM HOST SP SP READSP READSP HIGH L
200. ted Figure 14 4 TIM Status and Control Register TSC TOF TIM Overflow Flag Bit This read write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers Clear TOF by reading the TIM status and control register when TOF is set and then writing a O to TOF If another TIM overflow occurs before the clearing sequence is complete then writing O to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a 1 to TOF has no effect 1 TIM counter has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIM overflow interrupts enabled 0 TIM overflow interrupts disabled TSTOP TIM Stop Bit This read write bit stops the TIM counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIM counter until software clears the TSTOP bit 1 TIM counter stopped 0 TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode When the TSTOP bit is set and the timer is configured for input capture operation input captures are inhibited until the TSTOP bit is cleared When using TSTOP to stop the timer counter see if any timer flags are set If a timer flag is
201. tions e 10 Crystal w o ADC 8 a Er Crystal w ADC 6 Internal Osc w o 4 ADC Internal Osc w 2 0 0 1 2 3 4 5 6 7 Bus Frequency MHz Figure 16 9 Typical 5 Volt Run Current versus Bus Frequency 25 C 4 8 ux o Crystal w o ADC E a Crystal w ADC Internal Osc w o ADC 1 Internal Osc w ADC 0 1 2 3 4 5 Bus Frequency MHz Figure 16 10 Typical 3 Volt Run Current versus Bus Frequency 25 MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 16 14 Analog to Digital Converter Characteristics Analog to Digital Converter Characteristics Characteristic Symbol Min Max Unit Comments Supply voltage Vppap V Input voltages VADIN Vas Vpp V m jg RES 10 5 21 5 mV Absolute ETUE 1 5 LSB Includes quantization Total unadjusted error ADC internal clock 0 5 1 048 MHz Noon ele Conversion range VAIN Vss Vpp V Power up time tappu 16 tapic cycles tapic 1 fapic Conversion time tADC 16 17 tapic cycles tanic l fApic Sample time taps 5 tapic cycles tapic 1 fapic Zero input reading ZADI 00 01 Hex Vin Vss Full scale reading FADI FE FF Hex Vin Input capacitance Capi 8 pF Not tested Input leakage lu x 1 ADC supply current Vpp23V lADAD Typical 2 0 45 mA
202. ts sets a corresponding bit in the SIM reset status register SRSR See 13 8 SIM Registers MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 105 System Integration Module SIM 13 4 1 External Pin Reset The RST pin circuits include an internal pullup device Pulling the asynchronous RST pin low halts all processing The PIN bit of the SIM reset status register SRSR is set as long as RST is held low for at least the minimum tg time Figure 13 3 shows the relative timing The RST pin function is only available if the RSTEN bit is set in the CONFIG2 register BUSCLKX2 RST anaes aus J ec E Figure 13 3 External Reset Timing 13 4 2 Active Resets from Internal Sources The RST pin is initially setup as a general purpose input after a POR Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function This section assumes the RSTEN bit is set when describing activity on the RST pin NOTE For POR and LVI resets the SIM cycles through 4096 BUSCLKX4 cycles during which the SIM forces the RST pin low The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 13 4 The COP reset is asynchronous to the bus clock The active reset feature allows the part to issue a reset to
203. ts the MCU in a low power consumption mode for standby situations The SIM holds the CPU in a non clocked state The operation of each of these modes is described below Both STOP and WAIT clear the interrupt mask 1 in the condition code register allowing interrupts to occur 13 7 1 Wait Mode In wait mode the CPU clocks are inactive while the peripheral clocks continue to run Figure 13 14 shows the timing for wait mode entry ADDRESSBUS WAIT ADDR WAITADDR 1 SAME SAME DATA BUS PREVIOUSDATA NEXTOPCODE SAME RW J NOTE Previous data can be operand data or the WAIT opcode depending on the last instruction Figure 13 14 Wait Mode Entry Timing MC68HC908QY QT Family Data Sheet Rev 5 114 Freescale Semiconductor Low Power Modes A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred In wait mode the CPU clocks are inactive Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode Wait mode can also be exited by a reset or break in emulation mode A break interrupt during wait mode sets the SIM break stop wait bit SBSW in the break status register BSR If the COP disable bit COPD in the configuration register 1 0 then the
204. ty since the CPU is inactive The STOP instruction should not be executed while performing a program or erase operation on the FLASH or the operation will discontinue and the FLASH will be on standby mode NOTE Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 39 MC68HC908QY QT Family Data Sheet Rev 5 40 Freescale Semiconductor Chapter 3 Analog to Digital Converter ADC 3 1 Introduction This section describes the analog to digital converter ADC The ADC is an 8 bit 4 channel analog to digital converter The ADC module is only available on the MC68HC908QY2 MC68HC908QT2 MC68HC908QY4 and MC68HC908QTA 3 2 Features Features of the ADC module include e 4channels with multiplexed input e Linear successive approximation with monotonicity e 8 bit resolution Single or continuous conversion e Conversion complete flag or conversion complete interrupt e Selectable ADC clock frequency 3 3 Functional Description Four ADC channels are available for sampling external sources at pins PTAO PTA1 4 and 5 An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC voltage input ADCVIN ADCVIN is converted by the successive approximation register based counters
205. ule control logic will then set OSC as an external clock input and if the external crystal option is selected OSC2 will also be set as the clock output 3 Create a software delay to wait the stabilization time needed for the selected clock source crystal resonator RC as recommended by the component manufacturer A good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency i e for a 4 MHz crystal wait approximately 1 msec 4 After the manufacturer s recommended delay has elapsed the ECGON bit in the OSC status register OSCSTAT needs to be set by the user software 5 After ECGON set is detected the OSC module checks for oscillator activity by waiting two external clock rising edges 6 The OSC module then switches to the external clock Logic provides a glitch free transition 7 The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal oscillator NOTE Once transition to the external clock is done the internal oscillator will only be reactivated with reset No post switch clock monitor feature is implemented clock does not switch back to internal if external clock dies 11 3 2 External Oscillator The external clock option is designed for use when a clock signal is available in the application to provide a clock source to the microcontroller The OSC1 pin is enabled as an input by the oscillator module The clock signal is used directly to create BUSCLKXA and al
206. uo HESS da P REREEXEEEE ERE DES CES 94 11 4 7 Oscillator Out 2 BUSCLKXA dpi rb Y EROR Kian ER CE A 94 11 4 8 Oscillator Qut BUSCLKXZ2 ririri reris tisano OREERT CR 94 1322 OURS 5 de 95 Wat MOOR 6 a5 5856446 95 11 5 2 or Feu TF 95 11 6 Oscillator During 22 222 222 25 5 2 5245 26 55 95 CONFIG OPOS fica dew OR RE Ra E AG Pda NERA repudio 95 112 95 11 8 1 Oscillator Statue Register 2d aco 104504605644 EC 96 11 8 2 Oscillator Trim Register OSGTRIM oeXw kk t RC ROR o 96 MC68HC908QY QT Family Data Sheet Rev 5 12 Freescale Semiconductor Chapter 12 Input Output Ports PORTS IDHOGUDUOSE Lauda cama Ed heen eee ckedaresd wed dau waddqda ded ida qam 97 IDEE e per PECIA arde Paar OE PEE a bb fed 97 12 2 1 Pon A Data 65469500984 do OR MORE Ro ES 98 18 2 2 Data Direction Register Yd d db o PEEL de OR Cbr be dowd de dr 98 12 2 3 Port A Input Pullup Enable CACHE ORA OR ACE
207. upts Together with the central processor unit CPU the SIM controls all microcontroller unit activities A block diagram of the SIM is shown in Figure 13 1 The SIM is a system state controller that coordinates CPU and exception timing The SIM is responsible for Bus clock generation and control for CPU and peripherals Stop wait reset break entry and recovery Internal clock control Master reset control including power on reset POR and computer operating properly COP timeout Interrupt control Acknowledge timing Arbitration control timing Vector address generation CPU enable disable timing Table 13 1 Signal Name Conventions Signal Name Description BUSCLKX4 Buffered clock from the internal RC or XTAL oscillator circuit BUSCLKX2 The BUSCLKX4 frequency divided by two This signal is again divided by two in the SIM to generate the internal bus clocks bus clock BUSCLKXA 4 Address bus Internal address bus Data bus Internal data bus PORRST Signal from the power on reset module to the SIM IRST Internal reset signal RAV Read write signal MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 103 System Integration Module SIM MODULE STOP MODULE WAIT CPU STOP FROM CPU CPU WAIT FROM CPU STOP WAIT CONTROL SIMOS
208. ve only upon entering stop mode 4 4 Wait Mode The AWU module remains inactive in wait mode 4 5 Stop Mode When the AWU module is enabled AWUIE 1 in the keyboard interrupt enable register it is activated automatically upon entering stop mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode The AWU counters start from 0 each time stop mode is entered MC68HC908QY QT Family Data Sheet Rev 5 50 Freescale Semiconductor Input Output Registers 4 6 Input Output Registers The AWU shares registers with the keyboard interrupt module and the port A module The following 1 registers control and monitor operation of the AWU e Port A data register e Keyboard interrupt status and control register KBSCR e Keyboard interrupt enable register 4 6 1 Port A I O Register The port A data register PTA contains a data latch for the state of the AWU interrupt request in addition to the data latches for port A Address 0000 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 AWUL PTA2 5 4 1 PTAO Write Reset 0 0 Unaffected by reset Unimplemented Figure 4 2 Port A Data Register PTA AWUL Auto Wakeup Latch This is a read only bit which has the value of the auto wakeup interrupt request latch The wakeup request signal is generated inte
209. vice routine modifies H then the user must stack and unstack H using the PSHH and PULH instructions After the bit is cleared the highest priority interrupt request is serviced first A return from interrupt RTI instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack After any reset the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction CLI N Negative Flag The CPU sets the negative flag when an arithmetic operation logic operation or data manipulation produces a negative result setting bit 7 of the result 1 Negative result 0 Non negative result MC68HC908QY QT Family Data Sheet Rev 5 64 Freescale Semiconductor Arithmetic Logic Unit ALU Z Zero Flag The CPU sets the zero flag when an arithmetic operation logic operation or data manipulation produces a result of 00 1 Zero result 0 Non zero result C Carry Borrow Flag The CPU sets the carry borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow Some instructions such as bit test and branch shift and rotate also clear or set the carry borrow flag 1 Carry out of bit 7 0 No carry out of bit 7 7 4 Arithmetic Logic Unit ALU The ALU performs the arithmetic and logic operations defined by the instruction set Refer to the CPU08 Reference Manual document order number
210. y edge input capture trigger Set clear or toggle output compare action Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIM clock input T frequency internal bus clock prescaler selection External TIM clock input Free running or modulo up count operation Toggle any channel pin on overflow TIM counter stop and reset bits 14 3 Pin Name Conventions The TIM shares two input output I O pins with two port A I O pins The full names of the TIM I O pins are listed in Table 14 1 The generic pin name appear in the text that follows Table 14 1 Pin Name Conventions TIM Generic Pin Names TCHO TCH1 TCLK Full TIM Pin Names PTA1 TCH1 PTA2 TCLK MC68HC908QY QT Family Data Sheet Rev 5 Freescale Semiconductor 119 Timer Interface Module TIM 120 PTAO ADO TCHO KBIO PTA1 AD1 TCH1 KBI1 PTAZ IRQ KBIZ TCLK 9 lt lt PTAS RSTIKBI3 9 2 8 PTA4 OSC2 AD2 KBI4 5 5 1 5 gt PTB0 PTB1 PTB2 PTB3 5 me PTBA 5 gt PTB6 PTB7 8 BIT ADC 128 BYTES RAM POWER SUPPLY lt Vpp gt Vss 68 08 CPU MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2

freescale MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet

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