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freescale MOTOROLA MC68HC908GR8 MC68HC908GR4 handbook

1. Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 boa i PTA3 PTA2 PTA1 PTAO Port A Data Register 0000 PTA Write Reset Unaffected by reset mo PTB5 PTB4 PTB3 PTB2 PTB1 PTBO 0001 Port B Data Register Write PTB Reset Unaffected by reset Read 0 0 0 0 0 0 PTCH PTCO Port C Data Register a 0002 PTC Write Reset Unaffected by reset bu PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTDO 0003 Port D Data Register Write PTD Reset Unaffected by reset ju DDRA3 DDRA2 DDRA1 DDRAO Data Direction Register A 0004 DDRA Write Reset 0 0 0 0 0 0 0 0 iiis DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO 0005 Data Direction Register B Write DDRB Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 pact ERES Data Direction Register C 0006 DDRO Write Reset 0 0 0 0 0 0 0 0 Read 0 Data Direction Register D DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO 0007 Write DDRD Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 paa E Port E Data Register 0008 PTE Write Reset Unaffected by reset Read 0009 Unimplemented Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 1 of 8 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 39 For More Information On This Product Go to www freescale com Freescale Semic
2. hk p V DETAIL Y NOTES 1 DIMENSIONS AND TOLERANCING AS PER ANSI Y Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS CONSISTENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT U20 0 009 lac EM z THE BOTTOM OF THE PARTING LINE ATUMS T U AND Z TO BE DETERMINED AT ATUM PLANE AB MENSIONS S AND V TO BE DETERMINED AT EATING PLANE AC MENSIONS A AND B DO NOT INCLUDE MOLD ROTRUSION ALLOWABLE PROTRUSION IS DETAIL AD 0 250 0 010 PER SIDE DIMENSIONS A AND B DO HK NCLUDE MOLD MISMATCH AND ARE gs G 4 DETERMINED AT DATUM PLANE AB 7 DIMENSION D DOES NOT INCLUDE DAMBAR AB PROTRUSION DAMBAR PROTRUSION SHALL AA NOT CAUSE THE D DIMENSION TO EXCEED A f 0 520 0 020 Seating are MINIMUM SOLDER PLATE THICKNESS SHALL BE 0 0076 0 0003 plane CI 0 10 0 004 lac EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION DN 9r 1 UOOUOOCUO oo o MILLIMETERS INCHES MIN MAX MIN MAX A 7 000 BSC 0 276 BSC At 3 500 BSC 0 138 BSC B 7 000 BSC 0 276 BSC 3 500 BSC 0 138 BSC 1 400 1 600 0 055 0 063 0 300 0 450 0 012 0 018 1 350 1 450 0 053
3. 14 12 Ej 10 rt a 1 40 Xx X H 0 CN Ea k 25 3 6 85 4 2 0 02 04 06 08 10 12 14 16 VoL lt 0 3 V Q Io 0 5 mA VoL lt 1 0 V lo 6 0 mA Figure 23 8 Typical Low Side Driver Characteristics Port PTA3 PTAO Vpp 2 7 Vdc MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 373 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 60 4 50 cr qe 40 artes 4 40 E ng mig x m 0 5 AT bh 25 20 X 85 10 0 04 06 08 10 12 14 16 VoL lt 1 0 V Q lo 15 mA Figure 23 9 Typical Low Side Driver Characteristics Port PTC1 PTCO Vpp 4 5 Vdc 25 I 9 e 12 1 lo mA X 85 VoL lt 0 8 V Io 10 mA Figure 23 10 Typical Low Side Driver Characteristics Port PTC1 PTCO Vpp 2 7 Vdc Technical Data MC68HC908GR8 Rev 4 0 374 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Output Low Voltage Characteristics 25 v 1 40 N 0 j a k 25 X 85 lo mA
4. Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 22 15 TIM Channel 0 Register Low TCHOL Address T1CH1H 0029 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 22 16 TIM Channel 1 Register High TCH1H Address T1CH1L 002A Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 22 17 TIM Channel 1 Register Low TCH1L Technical Data MC68HC908GR8 Rev 4 0 360 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 23 1 Contents 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23 9 23 10 23 11 23 12 23 13 23 14 23 15 23 16 23 17 MC68HC908GR8 Rev 4 0 Section 23 Electrical Specifications Absolute Maximum Ratings reece 362 Functional Operating Range a 363 Thermal Characteristics a ee arn KA KAKA Rr RR 363 5 0 V DC Electrical Characteristics 364 3 0 V DC Electrical Characteristics 366 5 0 V Control PNDILIB LL a2 eid de pe REDI ee Ke CO I RR Ra 368 BO V Control TRU Ls d debeo d ap tS CHIC Ro i dp todos 369 Output High Voltage Characteristics 370 Output Low
5. Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 BRKE BRKA Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 6 3 Break Status and Control Register BRKSCR BRKE Break Enable Bit This read write bit enables breaks on break address register matches Clear BRKE by writing a logic O to bit 7 Reset clears the BRKE bit 1 Breaks enabled on 16 bit address match 0 Breaks disabled on 16 bit address match BRKA Break Active Bit This read write status and control bit is set when a break address match occurs Writing a logic 1 to BRKA generates a break interrupt Clear BRKA by writing a logic O to it before exiting the break routine Reset clears the BRKA bit 1 When read Break address match 0 When read No break address match MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Break Module BRK 95 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK 6 6 2 Break Address Registers The break address registers BRKH and BRKL contain the high and low bytes of the desired breakpoint address Reset clears the break address registers Address SFE09 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Figure 6 4 Break Address Register High BRKH Address SFEOA Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0
6. SPE SPMSTR MODFEN SPI Configuration State of SS Logic General purpose O 1 ie X Neb enabled SS ignored by SPI 1 0 X Slave Input only to SPI General purpose O 1 1 0 Master without MODF SS ignored by SPI 1 1 1 Master with MODF Input only to SPI Note 1 X Don t care 20 13 5 CGND Clock Ground CGND is the ground return for the serial clock pin SPSCK and the ground for the port output buffers It is internally connected to Vgs as shown in Table 20 1 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI For More Information On This Product Go to www freescale com 321 Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 14 I O Registers Three registers control and monitor SPI operation e SPI control register SPCR e SPI status and control register SPSCR e SPI data register SPDR 20 14 1 SPI Control Register The SPI control register e Enables SPI module interrupt requests e Configures the SPI module as master or slave Selects serial clock polarity and phase e Configures the SPSCK MOSI and MISO pins as open drain outputs e Enables the SPI module Address 0010 Bit 7 6 5 4 3 2 1 Bit 0 Read DMAS SPRIE SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Reset 0 0 1 0 1 0 0 0 Unimplemented Figure 20 13 SPI Control Register SPCR Technical Data MC68HC908GR8
7. T1SCO Reset 0 0 0 0 0 0 0 0 Read Timer 1 ChannelO Bit15 14 13 12 11 10 9 Bit 8 0026 Write Register High T1CHOH Reset Indeterminate after reset i Read f Timer 1 ChannelO Bit7 6 5 4 3 2 1 Bit 0 0027 Write Register Low T1CHOL Reset Indeterminate after reset Timer 1 Channel 1 Status Read CHIF 0 0028 and Control Register Write 0 CHIIE MS1A ELS1B ELS1A TOV1 CHIMAX T1SC1 Reset O 0 0 0 0 0 0 0 5 Read Timer 1 Channel 1 Bit15 14 13 12 11 10 9 Bit 8 0029 Register High TICH1H te 9 9 Reset Indeterminate after reset Read Timer 1 Channel 1 ul Bit7 6 5 4 3 2 1 Bit 0 002A Write Register Low T1CH1L Reset Indeterminate after reset Timer SulusandConag PET TOP loe Depp PS PS1 PSO 002B Register T2SC Write 0 TRST g Reset 0 0 1 0 0 0 0 0 Read Bit 1 14 1 12 11 1 Bit 002C Timer 2 Counter Register theta 2 is High T2CNTH Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 2 TIM I O Register Summary Sheet 1 of 2 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 339 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Counter Register seat Biy i 3 Pibo S002D Write Low T2CNTL Reset 0 0 0 0 0 0 0
8. 111 Not available MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM For More Information On This Product Go to www freescale com 351 Freescale Semiconductor Inc Timer Interface Module TIM 22 10 2 TIM Counter Registers NOTE Technical Data The two read only TIM counter registers contain the high and low bytes of the value in the TIM counter Reading the high byte TCNTH latches the contents of the low byte TCNTL into a buffer Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read Reset clears the TIM counter registers Setting the TIM reset bit TRST also clears the TIM counter registers If you read TCNTH during a break interrupt be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt Otherwise TCNTL retains the value latched during the break Address T1CNTH 0021 and T2CNTH 002C Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 5 TIM Counter Registers High TCNTH Address T1CNTL 0022 and T2CNTL 002D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 6 TIM Counter Registers Low TCNTL MC68HC908GR8 Rev 4 0 352 Timer Interface Module TIM MOTOROLA For More
9. MOTOROLA Electrical Specifications 381 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications ss INPUT SPSCK INPUT CPOL 0 SPSCK INPUT CPOL 1 Note Not defined but normally MSB of character just received a SPI Slave Timing CPHA 0 SS N y INPUT a 1 SPSCK INPUT lt q 5 pp CPOL 0 i 4 gt 2 3 SPSCK INPUT kag 5 Jp CPOL 1 4 3 Note Not defined but normally LSB of character previously transmitted b SPI Slave Timing CPHA 1 Figure 23 17 SPI Slave Timing Technical Data MC68HC908GR8 Rev 4 0 382 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Timer Interface Module Characteristics 23 15 Timer Interface Module Characteristics Table 23 8 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit Input capture pulse width 11H TIL 1 toyo 23 16 Clock Generation Module Characteristics 23 16 1 CGM Component Specifications Table 23 9 CGM Component Specifications Characteristic Symbol Min Typ Max Unit Crystal reference frequency XCLK 30 32 768 100 kHz Crystal load capacitance CL E pF Crystal fixed capacitance C 6 2xC 40 pF Cryst
10. 7 0 ACCUMULATOR A 15 0 H X INDEX REGISTER H X 15 0 STACK POINTER SP 15 0 PROGRAM COUNTER PC 7 0 VI111 H 1 N Z C CONDITION CODE REGISTER CCR CARRY BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG Figure 10 1 CPU registers Technical Data MC68HC908GR8 Rev 4 0 140 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU CPU registers 10 4 1 Accumulator A The accumulator is a general purpose 8 bit register The CPU uses the accumulator to hold operands and the results of arithmetic logic operations Bit 7 6 5 4 3 2 1 Bit 0 Read A Write Reset Unaffected by reset Figure 10 2 Accumulator A 10 4 2 Index register H X The 16 bit index register allows indexed addressing of a 64K byte memory space H is the upper byte of the index register and X is the lower byte H X is the concatenated 16 bit index register In the indexed addressing modes the CPU uses the contents of the index register to determine the conditional address of the operand Reset 0 0 0 0 0 0 0 0 X X X X X X X X X Indeterminate Figure 10 3 Index register H X The index register can also be used as a temporary data stora
11. A CPU interrupt request from the TIM2 loads the program counter with the contents of Technical Data MOTOROLA Low Power Modes 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes FFEC and FFED TIM2 overflow FFFO and SFFF1 TIM2 channel 0 Serial peripheral interface module SPI interrupt A CPU interrupt request from the SPI loads the program counter with the contents of SFFE8 and SFFES SPI transmitter FFEA and FFEB SPI receiver Serial communications interface module SCI interrupt A CPU interrupt request from the SCI loads the program counter with the contents of FFE2 and SFFE3 SCI transmitter SFFE4 and SFFE5 SCI receiver FFE6 and FFE7 SCI receiver error e Analog to digital converter module ADC interrupt A CPU interrupt request from the ADC loads the program counter with the contents of FFDE and FFDF ADC conversion complete e Timebase module TBM interrupt A CPU interrupt request from the TBM loads the program counter with the contents of FFDC and FFDD TBM interrupt 3 16 Exiting Stop Mode Technical Data These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector e External reset A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations SFFFE and FFFF Ex
12. CGMRDV REFERENCE CGMRCLK DIVIDER CLOCK CGMOUT BCS SELECT gt CIRCUIT TO SIM RDS3 RDS0 VPR1 VPRO VRS7 VRSO VOLTAGE PHASE d LOOP i t CONTROLLED p e CGMVCLK DETECTOR FILTER OSCILLATOR PLL ANALOG IPLLIREQ AUTOMATIC LOCK INTERRUPT MODE gt DETECTOR CONTROL CONTROL To SIM LOCK AUTO ACQ PLLIE PLLF MUL11 MULO PRE1 PREO CGMVDV FREQUENCY FREQUENCY DIVIDER DIVIDER Figure 7 1 CGMC Block Diagram MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 4 1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal The OSC1 pin is the input to the amplifier and the OSC2 pin is the output The SIMOSCEN signal from the system integration module SIM or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency CGMXCLK is then buffered to produce CGMRCLK the PLL reference clock CGMXCLK can be used by other modules which require precise timing for operation The duty cycle o
13. An LVI reset also drives the RST pin low to provide low voltage protection to external peripheral devices STOP INSTRUCTION FROM CONFIG FROM CONFIG LVIRSTD FROM CONFIG Y LOW Vpp Voo gt LVIrrip 0 EN LVI RESET DETECTOR y p lt LVimp 1 LVIOUT LVI5OR3 FROM CONFIG Figure 14 1 LVI Module Block Diagram MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Voltage Inhibit LVI 185 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI Addr FEOC Register Name LVI Status Register LVISR Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 2 LVI I O Register Summary 14 4 1 Polled LVI Operation In applications that can operate at Vpp levels below the Vrpipr level software can monitor Vpp by polling the LVIOUT bit In the configuration register the L VIPWRD bit must be at logic 0 to enable the LVI module and the LVIRSTD bit must be at logic 1 to disable LVI resets 14 4 2 Forced Reset Operation In applications that require Vpp to remain above the V ppr level enabling LVI resets allows the LVI module to reset the MCU when Vpp falls below the Vrgipr level In the configuration register the LVIPWRD and LVIRSTD bits must be at logic O to enable the L VI module and to enable LVI resets 14 4
14. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports I O Port E 16 7 Port E Port E is a 2 bit special function port that shares two of its pins with the serial communications interface SCI module 16 7 1 Port E Data Register The port E data register contains a data latch for each of the two port E pins Address 0008 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 PTE1 PTEO Write Reset Unaffected by reset Alternate RxD TxD Function Unimplemented Figure 16 17 Port E Data Register PTE PTE1 and PTEO Port E Data Bits PTE1 and PTEO are read write software programmable bits Data direction of each port E pin is under the control of the corresponding bit in data direction register E NOTE Data direction register E DDRE does not affect the data direction of port E pins that are being used by the SCI module However the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins See Table 16 6 RxD SCI Receive Data Input The PTE1 RxD pin is the receive data input for the SCI module When the enable SCI bit ENSCI is clear the SCI module is disabled and the PTE1 RxD pin is available for general purpose I O See Serial Communications Interface SCI MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 225 For Mor
15. Incoming data Address 0017 Bit 7 6 5 4 3 2 1 Bit 0 Read BKF RPF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 18 14 SCI Status Register 2 SCS2 BKF Break Flag Bit This clearable read only bit is set when the SCI detects a break character on the PE1 RxD pin In SCS1 the FE and SCRF bits are also set In 9 bit character transmissions the R8 bit in SCC3 is cleared BKF does not generate a CPU interrupt request Clear BKF by reading SCS2 with BKF set and then reading the SCDR Once cleared BKF can become set again only after logic 1s again appear on the PE1 RxD pin followed by another break character Reset clears the BKF bit 1 Break character detected 0 No break character detected RPF Reception in Progress Flag Bit This read only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search RPF does not generate an interrupt request RPF is reset after the receiver detects false start bits usually from noise or a baud rate mismatch or when the receiver detects an idle character Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress 1 Reception in progress 0 No reception in progress Technical Data MC68HC908GR8 Rev 4 0 264 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semic
16. Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 4 8 Base Clock Selector Circuit This circuit is used to select either the crystal clock CGMXCLK or the VCO clock CGMVCLK as the source of the base clock CGMOUT The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other During this time CGMOUT is held in stasis The output of the transition control circuit is then divided by two to correct the duty cycle Therefore the bus clock frequency which is one half of the base clock frequency is one fourth the frequency of the selected clock CGMXCLK or CGMVCLK The BCS bit in the PLL control register PCTL selects which clock drives CGMOUT The VCO clock cannot be selected as the base clock source if the PLL is not turned on The PLL cannot be turned off if the VCO clock is selected The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0 This value would set up a condition inconsistent with the operation of the PLL so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock 7 4 9 CGMC Exte
17. Technical Data The COP remains active in wait mode To prevent a COP reset during wait mode periodically clear the COP counter in a CPU interrupt routine or a DMA service routine MC68HC908GR8 Rev 4 0 52 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com 3 7 2 Stop Mode Freescale Semiconductor Inc Low Power Modes External Interrupt Module IRQ Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode The STOP bit in the configuration register CONFIG enables the STOP instruction To prevent inadvertently turning off the COP with a STOP instruction disable the STOP instruction by clearing the STOP bit 3 8 External Interrupt Module IRQ 3 8 1 Wait Mode 3 8 2 Stop Mode The IRQ module remains active in wait mode Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode The IRQ module remains active in stop mode Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode 3 9 Keyboard Interrupt Module KBI 3 9 1 Wait Mode The keyboard module remains active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keybo
18. gt cs cs TE cs Ces EEO SHIFT REGISTER Gug Zug oug gug SHIFT REGISTER FETA zo zo czo zo fe TXINV SCTIE R8 TCIE T8 SCRIE HE DMARE TE SCTE Le DMATE RE TC RWU SCRF OR ORIE SBK IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS ENSCI gt WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL SCIBDSRC FROM aa BKF M CONFIG RPF WAKE ILTY CGMKOLK fA ba PRE BA PEN IT12 B i SCALER DIVI Pry SL 0 gt X A SL 1 gt X B d DATA SELECTION CONTROL Figure 18 1 SCI Module Block Diagram Technical Data MC68HC908GR8 Rev 4 0 234 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read iis SCI Control Register 1 Wie LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCC1 f Reset 0 0 0 0 0 0 0 0 Read SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0014 SCI Control Register 2 Write SCC2 Reset 0 0 0 0 0 0 0 0 Read R8 SCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE 0015 SCC3 Write Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 0016 SCS1 Write Reset 1 1 0 0 0 0 0 0 Read BKF RPF
19. mi il COP TIMEOUT COP CLOCK COP MODULE 6 BIT COP COUNTER eR COP COUNTER Figure 9 1 COP Block Diagram The COP counter is a free running 6 bit counter preceded by a 12 bit prescaler counter If not cleared by software the COP counter overflows and generates an asynchronous reset after 219 2 or 213 24 CGMXCLK cycles depending on the state of the COP rate select bit COPRS in the configuration register With a 213 2 CGMXCLK cycle overflow option a 32 768 kHz crystal gives a COP timeout period of 250 ms Writing any value to location F FFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow A COP reset pulls the RST pin low for 33 CGMXCLK cycles and sets the COP bit in the reset status register RSR MC68HC908GR8 Rev 4 0 134 Computer Operating Properly COP MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly COP O Signals In monitor mode the COP is disabled if the RST pin or the IRQ1 is held at Vrg7 During the break state Vrsy on the RST pin disables the COP NOTE Place COP clearing instructions in the main program and not in an interrup
20. w Constant S j i i ib Average junction temperature Tj Ta Pp x Oja Ke Maximum junction temperature TJM 140 C Notes 1 Power dissipation is a function of temperature 2 K is a constant unique to the device K can be determined for a known T4 and measured Pp With this value of K Pp and Ty can be determined for any value of TA MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 363 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 5 5 0 V DC Electrical Characteristics Table 23 4 5 0V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Output high voltage ILoad 72 0 mA all 1 0 pine Vou Vpp 0 8 u u 7 ILoad 710 0 mA all I O pins Vou Vpop 1 5 _ V ILoad 710 0 mA pins PTCO PTC1 only Vou Vas s 0 8 E V Maximum combined lo for port C port E loH1 50 mA port PTD0 PTD3 Maximum combined loj for port PTD4 PTD6 lou 50 mA port A port B Maximum total loj for all port pins lour sawa a 100 mA Output low voltage ILoad 1 6 MA all I O pine VoL u E T V ILoad 10 MA all I O pins VoL a 15 V ILoad 15 MA pins PTCO PTC1 only VoL 1 0 V Maximum combined lo for port C port E lout xm 5 mA port PTDO PTD3 Maximum combined lo for port PTD4 PTD6 loro EC CE 50 mA port A port B Maximum total lo for all port
21. 0 02 04 06 08 10 12 14 1 6 VoL lt 0 4 V Q Io 1 6 mA VoL lt 1 5 V Io 10 0 mA Figure 23 11 Typical Low Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 5 5 Vdc 14 12 PE gt m ET 1 40 S N27 arap 2 pan E hk 25 p 8 X 85 4 2 0 0 02 04 06 08 10 12 14 16 Vol V VoL lt 0 3 V lo 0 5 mA VoL lt 1 0 V Io 6 0 mA Figure 23 12 Typical Low Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 2 7 Vdc MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 375 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 11 Typical Supply Currents Ipp mA co 2 bcm 5 5 V 0 1 2 3 4 5 6 7 8 9 fbus MHz Figure 23 13 Typical Operating Ipp with All Modules Turned On 40 C to 125 C Ipp mA wo eo 4 fpus MHz Figure 23 14 Typical Wait Mode Ipp with all Modules Disabled 7 40 C to 125 C Technical Data MC68HC908GR8 Rev 4 0 376 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Spe
22. PULLUP DEVICE kang Figure 16 4 Port A I O Circuit When bit DDRAx is a logic 1 reading address 0000 reads the PTAx data latch When bit DDRAx is a logic O reading address 0000 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 16 2 summarizes the operation of the port A pins Table 16 2 Port A Pin Functions Accesses to DDRA Accesses to PTA PTAPUE Bit DDRA Bit PTA Bit I O Pin Mode Read Write Read Write 3 1 0 xt Input Vpp DDRA3 DDRAO Pin EIAS Bro 3 0 0 X Input Hi Z DDRA3 DDRAO Pin a Tao X 1 X Output DDRA3 DDRAO PTAS PTAO PTAS PTAO NOTES 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect input 4 I O pin pulled up to Vpp by internal pullup device MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O For More Information On This Product Go to www freescale com 211 Freescale Semiconductor Inc Input Output Ports 1 0 16 3 3 Port A Input Pullup Enable Register The port A input pullup enable register PTAPUE contains a software configurable pullup device for each of the four port A pins Each bit is individually configurable and requires that the data direction register DDRA bit be configured as an input Each pullup is automatically and dynamically disabled when a port bits
23. Rev 4 0 322 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI O Registers SPRIE SPI Receiver Interrupt Enable Bit This read write bit enables CPU interrupt requests generated by the SPRF bit The SPRF bit is set when a byte transfers from the shift register to the receive data register Reset clears the SPRIE bit 1 SPRF CPU interrupt requests enabled 0 SPRF CPU interrupt requests disabled DMAS DMA Select Bit This read only bit has no effect on this version of the SPI This bit always reads as a 0 0 SPRF DMA and SPTE DMA service requests disabled SPRF CPU and SPTE CPU interrupt requests enabled SPMSTR SPI Master Bit This read write bit selects master mode operation or slave mode operation Reset sets the SPMSTR bit 1 Master mode 0 Slave mode CPOL Clock Polarity Bit This read write bit determines the logic state of the SPSCK pin between transmissions See Figure 20 4 and Figure 20 6 To transmit data between SPI modules the SPI modules must have identical CPOL values Reset clears the CPOL bit CPHA Clock Phase Bit This read write bit controls the timing relationship between the serial clock and SPI data See Figure 20 4 and Figure 20 6 To transmit data between SPI modules the SPI modules must have identical CPHA values When CPHA 0 the SS pin of
24. Rev 4 0 34 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 2 1 Contents 2 2 2 3 2 4 2 5 2 2 Introduction Section 2 Memory Map ji pus ir KE Ke TT 35 Unimplemented Memory Locations 20 35 Reserved Memory Locations n n naana 36 Input Output 1 0 Section os sua REOR RC A 4C e e RR 36 The CPU08 can address 64K bytes of memory space The memory map shown in Figure 2 1 includes 8K bytes of FLASH memory 7680 bytes of user space on the MC68HC908GR8 or 4K bytes of FLASH memory 4096 bytes of user space on the MC68HC908GR4 384 bytes of random access memory RAM 36 bytes of user defined vectors 310 bytes of monitor routines in read only memory ROM 544 bytes of integrated FLASH burn in routines in ROM 2 3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled In the memory map Figure 2 1 andin register figures in this document unimplemented locations are shaded MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map 2 4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation In the Figure 2 1 and
25. Rev 4 0 Technical Data MOTOROLA Analog to Digital Converter ADC 83 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC 5 7 1 ADC Analog Power Pin Vppap ADC Voltage Reference High Pin Vperp The ADC analog portion uses Vppap as its power pin Connect the Vppap pin to the same voltage potential as Vpp External filtering may be necessary to ensure clean Vpppp for good results NOTE For maximum noise immunity route Vppap carefully and place bypass capacitors as close as possible to the package 5 7 2 ADC Analog Ground Pin VssAp ADC Voltage Reference Low Pin VperL The ADC analog portion uses Vssap as its ground pin Connect the Vssap pin to the same voltage potential as Vas NOTE Route VssAp cleanly to avoid any offset errors 5 7 3 ADC Voltage In Vapin VapiN is the input voltage signal from one of the six ADC channels to the ADC module Technical Data MC68HC908GR8 Rev 4 0 84 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC O Registers 5 8 I O Registers These I O registers control and monitor ADC operation e ADC status and control register ADSCR e ADC data register ADR e ADC clock register ADCLK 5 8 1 ADC Status and Control Register Function of the ADC status and control register ADS
26. 182 LVI Module Block Diagram aannaaien 185 LVI KO Register Summary ccs kaaa wa eR raza Ran 186 LVI Status Register LVISR an KAKA RARE RR n OR KANG 187 Monitor Mode Circuit AA 191 Low Voltage Monitor Mode Entry Flowchart 195 Monitor Data PENE 64 6546 KALA KAKA COA TR deca 196 Break RG is li AA AAP 196 bp AA APA 198 Wie TTANSACHON PAA AA 198 Stack Pointer at Monitor Mode Entry 202 MC68HC908GR8 Rev 4 0 20 List of Figures MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 15 8 Monitor Mode Entry Timing 16 1 O Port Register Summary 16 2 Port A Data Register PTA 16 3 Data Direction Register A DDRA 16 4 Port A PO Circuit sao aca Wk KAKA KA KA E dea 16 5 Port A Input Pullup Enable Register PTAPUE 16 6 Port B Data Register PTB 16 7 Data Direction Register B DDRB 16 8 Port B I O Circuit cede a ech Ra RR ACE RR dnd 16 9 Port C Data Register PTC 16 10 Data Direction Register C DDRC 1547 POE VO GE wa 04K eR x RRERERURCH WK WG a 16 12 Port C Input Pullup Enable Register PTCPUE 16 13 Port D Data Register PTD 16 14 Data Direction Register D DDRD 16 15 Por D PO S DUI iu nddkci x dob ord bae a OR KA 16 16 Port D Input Pullup Enable Register PTD
27. 33 NU a GA KARO AA OI DOO t T LET TT 332 Low Power Modes a a ka a ABAKA KAKA AGA KAKA 333 Section 22 Timer Interface Module TIM LOG a Km Bh ce at kaka ONUS dh a pa 335 MC68HC908GR8 Rev 4 0 14 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pa 22 3 22 4 Hp ila 22 5 22d 22 8 22 9 22 10 23 1 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23 9 23 10 23 11 23 12 23 13 23 14 23 15 MC68HC908GR8 Rev 4 0 Table of Contents K OduUCIO e aa KA AA ee ae EEE 335 PERDERE La d doe PANAPAAN ded e d OC OEC Re E Ree de d din 336 Fin Name ConvenlloliB isa nd EG GG RR REOR COLOR de OR ee 336 Functional DeSEIIO pa uox x ded did e ER RACE RO UHR 337 i a EG KARA AA KK t TIL 346 Low Power Modes uae ob do cR RIA ERROR COGO Red 347 TIM During Break Inlerpls iiia Ka KG REOR RECO CR 348 E SM As dee ep TE i i E ER EP ES Ed EP NAKS 348 ned o o n ihe bd a he hd ide ee m 349 Section 23 Electrical Specifications GIS PPP 361 Absolute Maximum Ratings 2 0055 362 Functional Operating Range 222005 363 Thermal Characteristics Luisa eoe hom BAWA KAKA eR 363 5 0 V DC Electrical Characteristics 364 3 0 V DC Electrical Characteristics 366 5 0 V Control TIMING xad eae e ate ee ke Coe CR CA 368 BO V Control TIMING s GA ode e eode qe dpi edo 369 Output High Voltage Characteris
28. BYTE 4 SETS SPRF BIT 8 BYTE 2 SETS SPRF BIT 12 CPU READS SPSCR CPU READS SPSCR WITH SPRF BIT SET AND OVFF BIT CLEAR AA BANGGI T BYTE 3 SETS OVRF BIT BYTE 3 IS LOST CPU HEADS SPRCRAGAIN TO CHECK OVRF BIT Figure 20 10 Clearing SPRF When OVRF Interrupt Is Not Enabled 20 8 2 Mode Fault Error Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output The mode fault bit MODF becomes set any time the state of the slave select pin SS is inconsistent with the mode selected by SPMSTR To prevent SPI pin contention and damage to the MCU a mode fault error occurs if TheSS pin of a slave SPI goes high during a transmission The SS pin of a master SPI goes low at any time For the MODF flag to be set the mode fault error enable bit MODFEN must be set Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared Technical Data MC68HC908GR8 Rev 4 0 312 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com NOTE NOTE Freescale Semiconductor Inc Serial Peripheral Interface SPI Error Conditions MODF generates a receiver error CPU interrupt request if the error interrupt enable bit ERRIE is also set The SPRF
29. MODF and OVRF interrupts share the same CPU interrupt vector See Figure 20 11 It is not possible to enable MODF or OVRF individually to generate a receiver error CPU interrupt request However leaving MODFEN low prevents MODF from being set In a master SPI with the mode fault enable bit MODFEN set the mode fault flag MODF is set if SS goes to logic 0 A mode fault in a master SPI causes the following events to occur If ERRIE 1 the SPI generates an SPI receiver error CPU interrupt request e The SPE bit is cleared e The SPTE bit is set e The SPI state counter is cleared The data direction register of the shared I O port regains control of port drivers To prevent bus contention with another master SPI after a mode fault error clear all SPI bits of the data direction register of the shared I O port before enabling the SPI When configured as a slave SPMSTR 0 the MODF flag is set if SS goes high during a transmission When CPHA 0 a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit When CPHA 1 the transmission begins when the SPSCK leaves its idle level and SS is already low The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit See Transmission Formats Setting the MODF flag does not clear the SPMSTR bit The SPMSTR bit has no function when SPE 0 Heading
30. PLLON 1 NOTE The default divide value of 1 is recommended for all applications PMDS7 PMDS4 Unimplemented Bits These bits have no function and always read as logic Os Technical Data MC68HC908GR8 Rev 4 0 122 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Interrupts 7 7 Interrupts When the AUTO bit is set in the PLL bandwidth control register PBWC the PLL can generate a CPU interrupt request every time the LOCK bit changes state The PLLIE bit in the PLL control register PCTL enables CPU interrupts from the PLL PLLF the interrupt flag in the PCTL becomes set whether interrupts are enabled or not When the AUTO bit is clear CPU interrupts from the PLL are disabled and PLLF reads as logic O Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock When the PLL enters lock the VCO clock CGMVCLK divided by two can be selected as the CGMOUT source by setting BCS in the PCTL When the PLL exits lock the VCO clock frequency is corrupt and appropriate precautions should be taken If the application is not frequency sensitive interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations NOTE Software can select the CGMVCLK divided b
31. Refer to the wait mode subsection of each module to see if the module is active or inactive in MC68HC908GR8 Rev 4 0 290 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Low Power Modes wait mode Some modules can be programmed to be active in wait mode Wait mode also can be exited by a reset or break A break interrupt during wait mode sets the SIM break stop wait bit SBSW in the SIM break status register SBSR If the COP disable bit COPD in the mask option register is logic O then the computer operating properly module COP is enabled and remains active in wait mode IAB WAITADDR WAITADDR 1 J SAME SAME y IDB PREVIOUS DATA NEXT OPCODE SAME SAME RAW y Note Previous data can be operand data or the WAIT opcode depending on the last instruction Figure 19 15 Wait Mode Entry Timing Figure 19 16 and Figure 19 17 show the timing for WAIT recovery IAB 6E0B seEoc 00FF 00FE ooFD soorc IDB SAGY SA6 j s Ae so Y sob sek Y Y y EXITSTOPWAIT Note EXITSTOPWAIT RST pin CPU interrupt or break interrupt Figure 19 16 Wait Recovery from Interrupt or Break MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 291 For More information On This Product Go to www freescale com Free
32. SPI The SCI module is inactive in stop mode The STOP instruction does not affect SCI register states SCI module operation resumes after the MCU exits stop mode Because the internal clock is inactive during stop mode entering stop mode during an SCI transmission or reception results in invalid data 3 12 Serial Peripheral Interface Module SPI 3 12 1 Wait Mode 3 12 2 Stop Mode The SPI module remains active in wait mode Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode If SPI module functions are not required during wait mode reduce power consumption by disabling the SPI module before executing the WAIT instruction The SPI module is inactive in stop mode The STOP instruction does not affect SPI register states SPI operation resumes after an external interrupt If stop mode is exited by reset any transfer in progress is aborted and the SPI is reset 3 13 Timer Interface Module TIM1 and TIM2 3 13 1 Wait Mode The TIM remains active in wait mode Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode If TIM functions are not required during wait mode reduce power consumption by stopping the TIM before executing the WAIT instruction MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Power Modes 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes 3 13 2 Stop Mode
33. This read write bit reverses the polarity of transmitted data Reset clears the TXINV bit 1 Transmitter output inverted 0 Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values including idle break start and stop bits M Mode Character Length Bit This read write bit determines whether SCI characters are eight or nine bits long See Table 18 5 The ninth bit can serve as an extra stop bit as a receiver wakeup signal or as a parity bit Reset clears the M bit MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 253 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 1 9 bit SCI characters 0 8 bit SCI characters WAKE Wakeup Condition Bit This read write bit determines which condition wakes up the SCI a logic 1 address mark in the most significant bit position of a received character or an idle condition on the PE1 RxD pin Reset clears the WAKE bit 1 Address mark wakeup 0 Idle line wakeup ILTY Idle Line Type Bit This read write bit determines when the SCI starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the stop bit may cause false recognition of an idle character Beginning the count a
34. Write ACK1 Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 3 of 8 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Configuration Register 2 eat o S 9 i OSC SCIBD 001E CONFIG2 t Write STOPENB SRC Reset 0 0 0 0 0 0 0 0 Read Configuration Register 1 COPRS LVISTOP LVIRSTD LVIPWRD LVIBOR3 SSREC STOP COPD 001F CONFIG1 Write Reset 0 0 0 0 0 0 0 0 TOR IOS TOIE TSTOP PS2 PS1 PSO Timer 1 Status and Control 0020 Register T1SC Write 0 TRST Reset 0 0 1 0 0 0 0 0 Read Bit15 14 13 12 11 10 9 Bit 8 Timer 1 Counter Register 0021 High T CNTH Write Reset 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 Timer 1 Counter Register 0022 Low TACNTL Write Reset 0 0 0 0 0 0 0 0 kaa Bit 15 14 13 12 11 10 9 Bit 8 i j 0023 Timer 1 Counter Modulo Write Register High T1MODH Reset 1 1 1 1 1 1 1 1 idt Bit 7 6 5 4 3 2 1 Bit 0 Timer 1 Counter Modulo l l 0024 Register Low TIMODL Me Reset 1 1 1 1 1 1 1 1 Read CHOF Timer 1 Channel 0 Status f CHOIE MS0B MS0A ELSOB ELSOA TOVO CHOM
35. X A CCR VDATAH VDATAL OPCODE No A oum j Pomo romsa A X A A A CCR jVDWAH vata J orcooe RAW N Figure 19 8 Interrupt Entry Timing MODULE INTERRUPT BIT IAB y sp 4 sp 3 sP 2 sp 1 Y sp pc Post IDB y jJ cR J a x po 1rof r58 f oPCoDE J OPERAND y RW J Figure 19 9 Interrupt Recovery Timing MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 283 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM FROM RESET BREAK YES INTERRUPT YES IRQO YES INTERRUPT a IRQ YES INTERRUPT ma NO STACK CPU REGISTERS AS MANY INTERRUPTS i GADPOWIRHINTERB ETVEGTOR AS EXIST ON CHIP mla UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 19 10 Interrupt Processing 19 6 1 1 Hardware Interrupts A hardware interrupt does not stop the current instruction Processing of a hardware interrupt begins after completion of the current instruction When the current instruction is complete the SIM checks all pending hardware interrupts If interrupts are not masked bit clear in the Technical Data MC68HC908GR8 Rev 4 0 284 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integr
36. and more code efficient than CPU interrupts DMA See direct memory access module DMA DMA service request A signal from a peripheral to the DMA module that enables the DMA module to transfer data duty cycle A ratio of the amount of time the signal is on versus the time it is off Duty cycle is usually represented by a percentage EEPROM Electrically erasable programmable read only memory A nonvolatile type of memory that can be electrically reprogrammed EPROM Erasable programmable read only memory A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed exception An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program external interrupt module IRQ A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins fetch To copy data from a memory location into the accumulator firmware Instructions and data programmed into nonvolatile memory free running counter A device that counts from zero to a predetermined number then rolls over to zero and begins counting again full duplex transmission Communication on a channel in which data can be sent and received simultaneously H The upper byte of the 16 bit index register H X in the CPU08 H The half carry bit in the condition code registe
37. comparator A device that compares the magnitude of two inputs A digital comparator defines the equality or relative differences between two binary numbers computer operating properly module COP A counter module in the M68HC08 Family that resets the MCU if allowed to overflow Technical Data MC68HC908GR8 Rev 4 0 396 Glossary MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Glossary condition code register CCR An 8 bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed control bit One bit of a register manipulated by software to control the operation of the module control unit One of two major units of the CPU The control unit contains logic functions that synchronize the machine and direct various operations The control unit decodes instructions and generates the internal control signals that perform the requested operations The outputs of the control unit drive the execution unit which contains the arithmetic logic unit ALU CPU registers and bus interface COP See computer operating properly module COP counter clock The input clock to the TIM counter This clock is the output of the TIM prescaler CPU See central processor unit CPU CPUO8 The central processor unit of the M68HC08 Family CPU clock The CPU clock is derived
38. data Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register OVRF generates a receiver error CPU interrupt request if the error interrupt enable bit ERRIE is also set The SPRF MODF and OVRF MC68HC908GR8 Rev 4 0 310 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Error Conditions interrupts share the same CPU interrupt vector See Figure 20 11 It is not possible to enable MODF or OVRF individually to generate a receiver error CPU interrupt request However leaving MODFEN low prevents MODF from being set If the CPU SPRF interrupt is enabled and the OVRF interrupt is not watch for an overflow condition Figure 20 9 shows how it is possible to miss an overflow The first part of Figure 20 9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems However as illustrated by the second transmission example the OVRF bit can be set in between the time that SPSCR and SPDR are read BYTE 1 BYTE2 BYTE 3 BYTE 4 sPRF J OVRF l READ SPSCR No IN O READ SPDR NO NO 1 BYTE SETS SPRF BIT 5 CPU READS SPSCR WITH SPRF BIT SET 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BINGUEAR AND OVRF BIT CLEAR 6 BYTE 3 SETS OVRF BIT BYTE 3 IS LOST CPU READS BYTE 1 IN SPDR CLEARING SPRF BIT D G
39. 0 057 0 300 0 400 0 012 0 016 0 800 BSC 0 031 BSC 0 050 0 150 0 002 0 006 0 090 0 200 0 004 0 008 0 500 0 700 0 020 0 028 12 REF 12 REF 0 090 0 160 0 004 0 006 0 400 BSC 0 016 BSC r 5 1 5 0 150 0 250 0 006 0 010 9 000 BSC 0 354 BSC 4 500 BSC 0 177 BSC V 9 000 BSC 0 354 BSC vi 4 500 BSC 0 177 BSC W 0 200 REF 0 008 REF DETAIL AD X 1 000 REF 0 039 REF Base Metal DIM lo 0 20 0 008 M AC T U Z Gs Section AE AE A o D O d z Z Ac T 9 n m 9 O z JL Gauge Plane 0 25 0 010 Technical Data MC68HC908GR8 Rev 4 0 388 Mechanical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 28 Pin PDIP Case 710 24 4 28 Pin PDIP Case 710 F J D a a k Seating Plane Dim Min Max Notes Dim Min Max A 36 45 37 21 H 1 65 2 16 1 All dimensions in mm B 13 72 14 28 2 Positional tolerance of leads D shall be within 0 25 mm at J 0 20 T C 3 94 5 08 maximum material condition in relation to seating plane and to K 2 92 343 D 0 36 0 56 each other l L 15 24 BSC F 1 02 1 52 3 Dimension tis to c
40. 0 1 0 0 0 Read SPRF OVRF MODF SPTE R ERRIE MODFEN PR1 PRO 0011 SPI Status and Control Write Register SPSCR Reset 0 0 0 0 1 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SPI Data Register 0012 SPDR Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Unimplemented Figure 20 1 SPI I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 299 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI INTERNAL BUS CGMOUT 2 FROM SIM CLOCK DIVIDER TRANSMIT DATA REGISTER SHIFT REGISTER 5 4 3 2 MISO MOSI SPSCK RESERVED ua TRANSMITTER CPU INTERRUPT REQUEST SPI P RESERVED CONTROL m RECEIVER ERROR CPU INTERRUPT REQUEST Technical Data Figure 20 2 SPI Module Block Diagram The SPI module allows full duplex synchronous serial communication between the MCU and peripheral devices including other MCUs Software can poll the SPI status flags or SPI operation can be interrupt driven If a port bit is configured for input then an internal pullup device may be enabled for that port bit See Port D Input Pullup Enable Register MC68HC908GR8 Rev 4 0 300 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freesc
41. 328 Serial Peripheral Interface SPI For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Technical Data MC68HC908GR8 21 1 Contents 21 2 21 9 21 4 Elo 21 6 ZI 21 2 Introduction Section 21 Timebase Module TBM BUSH e gore robo APR OR be Kd AA 329 PROP o aca dede rd UH ede nA ara ded Ree d 004 04 UE EUR ERE 329 Functional Description 24a dd dee SERE d RO e ERR De Rn 330 Timebase Register Description 331 NG TE NAA Fae KA ds de TOT O Kh T 332 Low Power Modes nA kan Rech ROC dra ke 333 This section describes the timebase module TBM The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external crystal clock This TBM version uses 15 divider stages eight of which are user selectable For further information regarding timers on M68HC08 family devices please consult the HC08 Timer Reference Manual TIMOBRM AD 21 3 Features Features of the TBM module include MC68HC908GR8 Rev 4 0 Software programmable 1 Hz 4 Hz 16 Hz 256 Hz 512 Hz 1024 Hz 2048 Hz and 4096 Hz periodic interrupt using external 32 768 kHz crystal User selectable oscillator clock source enable during stop mode to allow periodic wakeup from stop Technical Data MOTOROLA Timebase Module TBM 329 For More Information On This Product Go to www freescale com Freescale Semiconducto
42. 40 to 125 MC908GR8MDWR2 40 to 125 Tape and Reel MC908GR4CFAR2 40 to 85 MC908GR4CDWR2 40 to 85 MC908GR4VFAR2 40 to 105 MC908GR4VDWR2 40 to 105 MC908GR4MFAR2 40 to 125 MC908GR4MDWR2 40 to 125 T FA quad flat pack P plastic dual in line package DW Small outline integrated circuit SOIC package Technical Data MC68HC908GR8 Rev 4 0 392 Ordering Information MOTOROLA For More information On This Product Go to www freescale com Freescale Semiconductor Inc Ordering Information Development Tools 25 4 Development Tools Table 25 2 Development Tool Kits Ordering Part Number Description HC908GR8 ICS KIT includes M68ICSO8GR programmer board Windows M681CS08GR based IDE 68HC908GR8 sample ICS Board amp IDE documentation Universal Power Supply Serial cable HC908GR8 EVS KIT includes M68MMPFB0508 M68EML08GP32 KITMMEVS08GR M68CBLO5C M68TCO8GR8P28 M68TCO8GR8FA32 M68TQS032SAG1 M68TQP032SA1 M68ICS08GR Kit HC908GR8 MMDS KIT includes M68MMDS0508 M68EML08GP32 KITMMDS08GR M68CBLO5C M68TCO8GR8P28 M68TCO8GR8FA32 M68TQS032SAG1 M68TQP032SA1 M68ICS08GR Kit Table 25 3 Development Tool Components Ordering Part Number Description Comments M68MMDS0508 High performance emulator M68MMPFB0508 MMEVS Platform Board M68EMLO8GP32 HC908GP32 Emulator Board Used for HC908GR8 GR4 emulation M68CBL05C Low noise flex cable M68TC08GR8P28 2
43. 4096 CGMXCLK cycles COP timeout period 218 24 or 213 24 CGMXCLK cycles STOP instruction Computer operating properly module COP Low voltage inhibit LVI module control and voltage trip point selection Enable disable the oscillator OSC during stop mode 8 3 Functional Description The configuration registers are used in the initialization of various options The configuration registers can be written once after each reset All of the configuration register bits are cleared during reset Since the various options affect the operation of the MCU it is recommended that these registers be written immediately after reset The configuration registers are located at 001E and 001F The configuration register may be read at anytime MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Configuration Register CONFIG 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration Register CONFIG NOTE To ensure correct operation of the MCU under all operating conditions the user must write data 1C to address 0033 immediately after reset This is to ensure proper termination of an unused module within the MCU NOTE On a FLASH device the options except LVISOR3 are one time writeable by the user after each reset The LVI5OR3 bit is one time writeable by the user only after each POR power on reset The CONFIG registers are not in the FLASH memory but are
44. 5 5 PLL Analog Ground Pin VssA Technical Data NOTE Vssa is a ground pin used by the analog portions of the PLL Connect the Vssa pin to the same voltage potential as the Vas pin Route Vss carefully for maximum noise immunity and place bypass capacitors as close as possible to the package MC68HC908GR8 Rev 4 0 112 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC O Signals 7 5 6 Oscillator Enable Signal SIMOSCEN The SIMOSCEN signal comes from the system integration module SIM and enables the oscillator and PLL 7 5 7 Oscillator Stop Mode Enable Bit OSCSTOPENB OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during stop mode If this bit is set the Oscillator continues running during stop mode If this bit is not set default the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode 7 5 8 Crystal Output Frequency Signal CGMXCLK CGMXCLK is the crystal oscillator output signal It runs at the full speed of the crystal fc x and comes directly from the crystal oscillator circuit Figure 7 2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors Also th
45. 53 170 18 5 3 8 Receiver Wakeup Technical Data So that the MCU can ignore transmissions intended only for other receivers in multiple receiver systems the receiver can be put into a standby state Setting the receiver wakeup bit RWU in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled Depending on the state of the WAKE bit in SCC1 either of two conditions on the PE1 RxD pin can bring the receiver out of the standby state Address mark An address mark is a logic 1 in the most significant bit position of a received character When the WAKE bit is set an address mark wakes the receiver from the standby state by clearing the RWU bit The address mark also sets the SCI receiver full bit SCRF Software can then compare the character containing the address mark to the user defined address of the receiver If they are the same the receiver remains awake and processes the characters that follow If they are not the same software can set the RWU bit and put the receiver back into the standby state e ldle input line condition When the WAKE bit is clear an idle character on the PE1 RxD pin wakes the receiver from the standby state by clearing the RWU bit The idle character that wakes the receiver does not set the receiver idle bit IDLE or the MC68HC908GR8 Rev 4 0 248 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www fr
46. Break Module BRK To allow software to clear the IRQ latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect CPU interrupt flags during the break state write a logic O to the BCFE bit With BCFE at logic O its default state writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA External Interrupt IRQ 171 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 12 7 IRQ Status and Control Register The IRQ status and control register INTSCR controls and monitors operation of the IRQ module The INTSCR Shows the state of the IRQ flag e Clears the IRQ latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ1 interrupt pin Address 001D Bit 7 6 5 4 3 2 1 Bit 0 Read IRQF 0 IMASK MODE Write ACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 3 IRQ Status and Control Register INTSCR IRQF IRQ Flag Bit This read only status bit is high when the IRQ interrupt is pending 1 IRQ interrupt pending 0 IRQ interrupt not pending ACK IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write only bit clears the
47. CCR SP lt SP 1 Pull A RTI Return from Interrupt SP lt SP 1 Pull X tititi INH 80 7 SP lt SP 1 Pull PCH SP lt SP 1 Pull PCL n SP lt SP 1 Pull PCH RTS Return from Subroutine SP amp SP 1 Pull PCL INH 81 4 Technical Data MC68HC908GR8 Rev 4 0 152 Central Processing Unit CPU For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Central Processing Unit CPU Table 10 1 Instruction Set Summary Continued Instruction Set Summary Effect on o o Source CCR 0 Ela Operation Description Col lo Sl o Form So o gt H IINZC 5161616 SBC opr IMM A2 iii 2 SBC opr DIR B2 dd 3 SBC opr EXT C2 hhil 4 B X IX2 D2 ff 4 Sap dX Subtract with Carry A A M C s HEIDE De Belt Nd SBC X IX F2 2 SBC opr SP SP1 9EE2 ff 4 SBC opr SP SP2 9ED2 eeff 5 SEC Set Carry Bit C 1 i 7 1 INH 99 1 SEI Set Interrupt Mask 1 1 INH 9B 2 STA opr DIR B7 dd 3 STA opr EXT C7 hhil 4 STA opr X IX2 D7 jeeff 4 STA opr X Store A in M M c A iitf Ixt E7 ff 3 STA X IX F7 2 STA opr SP SP1 9EE7 ff 4 STA opr SP SP2 9ED7 eeff 5 STHX opr Store H X in M M M 1 H X t DIR 35 dd 4 STOP Enable IRQ Pin Stop Oscillator 0 Stop Oscillator 0 INH 8E 1 STX opr DIR BF dd 3 STX opr EXT CF hhil 4 STX op
48. COUME nakaka KAANAK dd ud eal Rcx La Kb coe S KAKA 281 19 6 Exception COW uu da caca a duda RAUS RR RO WA par raa 282 19 7 Low Power Modes iila as suen mue RE idee an AR mdr dn 290 15 8 BI MODI couscesadaidena bids dd Rd i maxi 293 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Table of Contents 13 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Table of Contents 20 1 20 2 20 3 20 4 20 5 20 6 20 7 20 8 20 9 20 10 20 11 20 12 20 13 20 14 21 1 1 2 21 9 21 4 21 5 21 6 21 7 22 1 Section 20 Serial Peripheral Interface SPI LAGA ohne 444k a ad A EE 297 PICMG AA AAP 297 PANGS aiiiar a a PEPING 298 Pin Name Conventions and I O Register Addresses 298 PUNCIONS Dese BIO 24 164 ceeded oo iR CR cla a 299 Transmission Formats auis dod ed PERI EX ERR E Edo 303 Queuing Transmission Dala aa et sh kh mee 309 Emo GO DE 4 ke aca CX xaO d d d eRe kkr 310 ENG kaaa KA KEAN PBA al APA NAA kap ER 314 Resetting NE SP aas ed vdd AKALA KR EXEC GRABA 316 Low Power Modes sid PG KAKA dh E Edo rarae dea 317 SPI During Break Interrupts a 9er ROO Re 318 PUN MET ee ee ee rere eer E 318 PO ROGE a vada wA 4 DOR ob NAKAKA RG KPA DEL EA RO ede d 322 Section 21 Timebase Module TBM HG NA E IEEE EEE A E E E E E 329 Lili APA AA AA 329 AA APA od dete e Hin 329 F nctional Descr 6a eed ac e KKK EOD ORA ckek 330 Timebase Register Description
49. Coni Register IPETLE us uoa KA dca DOC OR e 115 PLL Bandwidth Control Register PBWC 118 PLL Multiplier Select Register High PMSH 119 PLL Multiplier Select Register Low PMSL 120 PLL VCO Range Select Register PMRS 121 PLL Reference Divider Select Register PMDS 122 9 ACT 127 Configuration Register 2 CONFIG2 130 Configuration Register 1 CONFIG1 130 COF BIDOR DUBII BU sasa ke ch doccia 4 doceo CO d p FA 134 COP Control Register COPCTL amahan 136 tg o t 140 UU ERO acia PAA eke dd one oed odo doi bae 141 index register ERI is id a ke ka REA ER Re RERO 141 iral CT cosa ua 3 RE HII bra ee CORRER RR 142 Program counter PEDI Coca acd oe eee ee hones 143 Condition code register CCR 143 FLASH Control Register FLOR 2 esses 159 FLASH Programming Flowchart 2 4 sede deed een 164 FLASH Block Protect Register FLBPR 165 FLASH Block Protect Start Address 165 IRQ Module Block Diagram a a nG pA En Rh RC doc Ren 169 IRQ I O Register Summary ici paawa m rR RES 169 IRQ Status and Control Register INTSCR 172 Keyboard Module Block Diagram issus 177 KO Register Summary oot ct ce cede ce Re Re ROsAR de 177 Keyboard Status and Control Register INTKBSCR 181 Keyboard Interrupt Enable Register INTKBIER
50. Control Registers The following TIM sources can generate interrupt requests MC68HC908GR8 Rev 4 0 346 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Low Power Modes e TIM overflow flag TOF The TOF bit is set when the TIM counter value reaches the modulo value programmed in the TIM counter modulo registers The TIM overflow interrupt enable bit TOIE enables TIM overflow CPU interrupt requests TOF and TOIE are in the TIM status and control register e TIM channel flags CH1F CHOF The CHXF bit is set when an input capture or output compare occurs on channel x Channel x TIM CPU interrupt requests and TIM DMA service requests are controlled by the channel x interrupt enable bit CHxIE Channel x TIM CPU interrupt requests are enabled when CHxIE 1 CHxF and CHXxIE are in the TIM channel x status and control register DMAXS is in the TIM DMA select register 22 7 Low Power Modes 22 7 1 Wait Mode 22 7 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The TIM remains active after the execution of a WAIT instruction In wait mode the TIM registers are not accessible by the CPU Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode If TIM functions are not required during wait mode reduce power consumption by stop
51. D Data Bits These read write bits are software programmable Data direction of each port D pin is under the control of the corresponding bit in data direction register D Reset has no effect on port D data T2CHO Timer 2 Channel I O Bits The PTD6 T2CHO pin is the TIM2 input capture output compare pin The edge level select bits ELSxB ELSxA determine whether the PTD6 T2CHO pin is a timer channel I O pin or a general purpose I O pin See Timer Interface Module TIM Technical Data MC68HC908GR8 Rev 4 0 220 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports I O Port D T1CH1 and T1CHO Timer 1 Channel I O Bits The PTD5 T1CH1 PTD4 T1CHO pins are the TIM1 input capture output compare pins The edge level select bits ELSxB and ELSxA determine whether the PTD5 T1CH1 PTD4 T1CHO pins are timer channel I O pins or general purpose l O pins See Timer Interface Module TIM SPSCK SPI Serial Clock The PTDS SPSCK pin is the serial clock input of the SPI module When the SPE bit is clear the PTDS SPSCK pin is available for general purpose O MOSI Master Out Slave In The PTD2 MOSI pin is the master out slave in terminal of the SPI module When the SPE bit is clear the PTD2 MOSI pin is available for general purpose I O MISO Master In Slave Out The PTD1 MISO pin is the master in slave out terminal of the
52. DDRA is configured for output mode Address S000D Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUEO Write Reset 0 0 0 0 0 0 0 0 Figure 16 5 Port A Input Pullup Enable Register PTAPUE PTAPUE3 PTAPUEO Port A Input Pullup Enable Bits These writeable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port A pin configured to have internal pullup 0 Corresponding port A pin has internal pullup disconnected Technical Data MC68HC908GR8 Rev 4 0 212 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports I O Port B 16 4 Port B Port B is an 6 bit special function port that shares all six of its pins with the analog to digital converter ADC module 16 4 1 Port B Data Register The port B data register PTB contains a data latch for each of the six port pins Address 0001 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 PTB5 PTB4 PTB3 PTB2 PTB1 PTBO Write Reset Unaffected by reset Atema aps Apa aps AD2 ADi abo Function Figure 16 6 Port B Data Register PTB PTB5 PTBO Port B Data Bits These read write bits are software programmable Data direction of each port B pin is under the control of the corresponding bit in data direction register B Reset has no
53. Data MOTOROLA Electrical Specifications 371 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Electrical Specifications lou mA 20 E 0 s SA a 50 PG st ad e x 85 haee Vou gt Vpp 0 8 V lou 2 0 mA Vou gt Vpp 1 5V lou 10 0 mA Figure 23 5 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 5 5 Vdc 0 5 ten 40 ee A 25 15 X 85 L 9 20 1 9 25 1 3 1 5 1 7 1 9 2 1 2 3 2 5 Vou V Vou gt Vpp 0 3 V loH 0 6 mA VoH gt Vpp 1 0V loy 4 0 mA Figure 23 6 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 2 7 Vdc MC68HC908GR8 Rev 4 0 372 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Output Low Voltage Characteristics 23 10 Output Low Voltage Characteristics CHE mo 20 Exc k 25 15 RT x 85 lo mA VoL lt 0 4 V Q Io 1 6 mA VoL lt 1 5 V Q Io 10 0 mA Figure 23 7 Typical Low Side Driver Characteristics Port PTA3 PTAO Vpp 5 5 Vdc
54. Data Direction Register C Data direction register C DDRC determines whether each port C pin is an input or an output Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin a logic 0 disables the output buffer Address 0006 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 DDRC1 DDRCO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 10 Data Direction Register C DDRC DDRC1 DDRCO Data Direction Register C Bits These read write bits control port C data direction Reset clears DDRC1 DDROO configuring all port C pins as inputs 1 Corresponding port C pin configured as output 0 Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from O to 1 Figure 16 11 shows the port C I O logic NOTE Forthose devices packaged in a 28 pin DIP and SOIC package PTC1 0 are not connected Set DDRC1 0 to a 1 to configure PTC1 0 as outputs MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 217 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 Z w READ DDRC 0006 WRITE DDRC 0006 DDRCx RESET WRITE PTC 50002 INTERNAL DATA BUS PTCPUEx Sod READ PTC 0002 Vpp o PULLUP DEVICE IN
55. Enable 000F Register PTDPUE Reset Input Output Ports I O Write Write Write Write Write Figure 16 1 I O Port Register Summary Continued MC68HC908GR8 Rev 4 0 Introduction Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 PTE1 PTEO Unaffected by reset 0 0 0 0 0 DDRE1 DDREO 0 0 0 0 0 0 0 0 0 0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUEO 0 0 0 0 0 0 0 0 0 0 0 0 PTCPUE1 PTCPUEO 0 0 0 0 0 0 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUES PTDPUE2 PTDPUE1 PTDPUEO 0 0 0 0 0 0 0 Unimplemented Technical Data MOTOROLA Input Output Ports I O For More Information On This Product Go to www freescale com 207 Technical Data Freescale Semiconductor Inc Input Output Ports 1 0 Table 16 1 Port Control Register Bits Summary Port Bit DDR Module Control Pin 0 DDRAO KBIEO PTAO KBDO 1 DDRA1 KBIE1 PTA1 KBD1 2 DDRA2 KBIE2 PTA2 KBD2 3 DDRAS3 KBD KBIES PTA3 KBD3 0 DDRBO CHO PTBO ATDO 1 DDRB1 CH1 PTB1 ATD1 2 DDRB2 CH2 PTB2 ATD2 B 3 DDRB3 ADC CH3 PTB3 ATD3 4 DDRB4 CH4 PTB4 ATD4 5 DDRB5 CH5 PTB5 ATD5 0 DDRCO PTCO 1 DDRC1 PTC1 C 3 m 3 0 DDRDO PTDO SS 1 DDRD1 PTD1 MISO 2 DDRD2 ux P
56. FFFC SWI Vector High FFFD SWI Vector Low FFFE Reset Vector High Highest E FFFF Reset Vector Low MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 47 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Technical Data MC68HC908GR8 Rev 4 0 48 Memory Map MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 3 1 Contents 3 2 Introduction 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 Section 3 Low Power Modes il ana cbe de in Vedi deni a o eir oho qeu d ep ee 49 Analog to Digital Converter ADC aa 50 Break Module BRK aa acier PAA 51 Central Processor Unit GPU cs sesso erra n 51 Clock Generator Module CGM 00 0a 52 Computer Operating Properly Module COP 52 External Interrupt Module IRQ 5 53 Keyboard Interrupt Module KBI 53 Low Voltage Inhibit Module LVI 54 Serial Communications Interface Module SCI 54 Serial Peripheral Interface Module SPI 55 Timer Interface Module TIM1 and TIM2 55 Timebase Module TBM sulllesslllessnne 56 Exiting Want EIOS aao plenresenzPPeqerGasd AA 57 Exiting Stop Mode 2000 eee 58 The
57. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output 1 0 Section Table 2 1 Vector Addresses Vector Priority Vector Address Vector Lowest IF16 SFFDC Timebase Vector High SFFDD Timebase Vector Low IF15 SFFDE ADC Conversion Complete Vector High SFFDF ADC Conversion Complete Vector Low IF14 SFFEO Keyboard Vector High SFFE1 Keyboard Vector Low IF13 FFE2 SCI Transmit Vector High SFFE3 SCI Transmit Vector Low E12 SFFE4 SCI Receive Vector High SFFE5 SCI Receive Vector Low F1 FFE6 SCI Error Vector High FFE7 SCI Error Vector Low IF10 SFFE8 SPI Transmit Vector High SFFE9 SPI Transmit Vector Low IF9 FFEA SPI Receive Vector High FFEB SPI Receive Vector Low IF8 FFEC TIM2 Overflow Vector High FFED TIM2 Overflow Vector Low IF7 FFEE Reserved FFEF Reserved IFG FFFO TIM2 Channel 0 Vector High SFFF1 TIM2 Channel 0 Vector Low IF5 FFF2 TIM1 Overflow Vector High FFF3 TIM1 Overflow Vector Low IF4 SFFF4 TIM1 Channel 1 Vector High SFFF5 TIM1 Channel 1 Vector Low IF3 FFF6 TIM1 Channel 0 Vector High FFF7 TIM1 Channel 0 Vector Low IRD FFF8 PLL Vector High SFFF9 PLL Vector Low Mp SFFFA IRQ Vector High FFFB IRQ Vector Low
58. I O 209 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 16 3 2 Data Direction Register A Data direction register A DDRA determines whether each port A pin is an input or an output Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin a logic 0 disables the output buffer Address 0004 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 DDRA3 DDRA2 DDRA1 DDRAO Write Reset 0 0 0 0 0 0 0 0 Figure 16 3 Data Direction Register A DDRA DDRAS DDRAO Data Direction Register A Bits These read write bits control port A data direction Reset clears DDRAS DDRAQ configuring all port A pins as inputs 1 Corresponding port A pin configured as output 0 Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from O to 1 Figure 16 4 shows the port A I O logic Technical Data MC68HC908GR8 Rev 4 0 210 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc READ DDRA 0004 Input Output Ports I O Port A WRITE DDRA 0004 DDRAx RESET WRITE PTA 0000 PTAx VDD o INTERNAL DATA BUS j 2 x PTAPUEX gt o READ PTA 0000 INTERNAL
59. Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM O Registers 22 10 3 TIM Counter Modulo Registers NOTE MC68HC908GR8 Rev 4 0 The read write TIM modulo registers contain the modulo value for the TIM counter When the TIM counter reaches the modulo value the overflow flag TOF becomes set and the TIM counter resumes counting from 0000 at the next timer clock Writing to the high byte TMODH inhibits the TOF bit and overflow interrupts until the low byte TMODL is written Reset sets the TIM counter modulo registers Address T1MODH 0023 and T2MODH 002E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit15 14 18 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Unimplemented Figure 22 7 TIM Counter Modulo Register High TMODH Address TIMODL 0024 and T2MODL 002F Bit 7 6 5 4 3 2 1 Bit 0 Read Bit7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Unimplemented Figure 22 8 TIM Counter Modulo Register Low TMODL Reset the TIM counter before writing to the TIM counter modulo registers Technical Data MOTOROLA Timer Interface Module TIM 353 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM 22 10 4 TIM Counter Registers The two read only TIM counter registers contain the high
60. L POR RESET IS VECTOR BLANK YES NORMAL USER MODE MONITOR MODE EXECUTE MONITOR E CODE POR TRIGGERED YES Figure 15 2 Low Voltage Monitor Mode Entry Flowchart Enter monitor mode with pin configuration shown in Figure 15 1 by pulling RST low and then high The rising edge of RST latches monitor mode Once monitor mode is latched the values on the specified pins can change Once out of reset the MCU waits for the host to send eight security bytes See Security After the security bytes the MCU sends a break signal 10 consecutive logic Os to the host indicating that it is ready to receive a command NOTE The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin goes high to enter monitor mode properly In monitor mode the MCU uses different vectors for reset SWI software interrupt and break interrupt than those for user mode The alternate vectors are in the SFE page instead of the FF page and allow code execution from the internal monitor firmware instead of user code NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power on reset Pulling RST low will not exit monitor mode in this situation MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 195 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor RO
61. L L v v S XI lds IXI ec edS v ZXI E IXA HId cJ WMWI 3H c HNI HNI LI HNI LH HNI 3H c Hl c UHuld ogs ogs ogs ogs das ogs ogs ogs 198 vva VSN NG INN IH8 LL3S8 ILH3SHH c Z v S v LA Z Z L S v S XI lds IXI ec edS v ZXI E IXA HId c WMWI 3H 2 HNI FX Z dS p LXI EWANI WNNI amp uHa l3H dua c UHuld dino dNo dino dino diNO dino dNo dino Na S14 3990 03990 0399 X03909 vO399 0399 NHH 09109 04919949 L 4 v S v v 4 v v 9 S v v S v S XI lds IXI e edS v ZXI E IXA HId cJ WMWI 3H z HNI XI k lds IXI c HNI HNI jaa Z 134 Z Hla c Hld ans ans ans ans ans ans ans ans 39g ILH DIN SAN SAN XO3N VOAN DIN Vda O0L3S8 Ol3SHH 0 4 v S v v 4 L S v L L v v S asi d 336 J q36 a 2 a v 6 8 L 936 9 S v 4 L 0 asn XI LdS LXI cds exi 1X3 uia NINI HNI HNI XI kds LXI HNI HNI uia T3H uia uia Mowsy 1a sibay 101 u09 MM PPON pe y youeig uonejndiue ug MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU For More Information On This Product 155 Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU Technical Data MC68HC908GR8 Rev 4 0 156 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 11 1 Contents 11 2 Introduct
62. O Pin Mode to Read Write Read Write 0 x 1 Input Hi Z DDRB5 DDRBO Pin PTB5 PTBO 1 X Output DDRB5 DDRBO PTB5 PTBO PTB5 PTBO Notes 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect input MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O For More Information On This Product Go to www freescale com 215 Freescale Semiconductor Inc Input Output Ports 1 0 16 5 Port C Port C is a 2 bit general purpose bidirectional I O port Port C also has software configurable pullup devices if configured as an input port 16 5 1 Port C Data Register The port C data register PTC contains a data latch for each of the two port C pins Address 0002 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 PTC1 PTCO Write Reset Unaffected by reset Unimplemented Figure 16 9 Port C Data Register PTC PTC1 PTCO Port C Data Bits These read write bits are software programmable Data direction of each port C pin is under the control of the corresponding bit in data direction register C Reset has no effect on port C data NOTE PTC is not available in a 28 pin DIP and SOIC package Technical Data MC68HC908GR8 Rev 4 0 216 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports I O Port C 16 5 2
63. PTDO X 1 Output DDRD6 DDRDO PTD6 PTDO PTD6 PTDO Notes 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect input 4 O pin pulled up to Vpp by internal pullup device MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA For More Information On This Product Input Output Ports I O Go to www freescale com 223 Freescale Semiconductor Inc Input Output Ports 1 0 16 6 3 Port D Input Pullup Enable Register Technical Data The port D input pullup enable register PTDPUE contains a software configurable pullup device for each of the seven port D pins Each bit is individually configurable and requires that the data direction register DDRD bit be configured as an input Each pullup is automatically and dynamically disabled when a port bit s DDRD is configured for output mode Address S000F Bit 7 6 5 4 3 2 1 Bit 0 Read 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUES PTDPUE2 PTDPUE1 PTDPUEO Write Reset 0 0 0 0 0 0 0 0 Figure 16 16 Port D Input Pullup Enable Register PTDPUE PTDPUE6 PTDPUEO Port D Input Pullup Enable Bits These writeable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port D pin configured to have internal pullup 0 Corresponding port D pin has internal pullup disconnected MC68HC908GR8 Rev 4 0 224 Input Output Ports I O MOTOROLA
64. RE 229 17 3 Functional Description uuu acerba SCC eae oe 229 17 2 Introduction This section describes the 384 bytes of RAM random access memory 17 3 Functional Description Addresses 0040 through 01BF are RAM locations The location of the stack RAM is programmable The 16 bit stack pointer allows the stack to be anywhere in the 64K byte memory space NOTE For correct operation the stack pointer must point only to RAM locations Within page zero are 192 bytes of RAM Because the location of the stack RAM is programmable all page zero RAM locations can be used for I O control and user data or code When the stack pointer is moved from its reset location at 00FF out of page zero direct addressing mode instructions can efficiently access all page zero RAM locations Page zero RAM therefore provides ideal locations for frequently accessed global variables Before processing an interrupt the CPU uses five bytes of the stack to save the contents of the CPU registers NOTE For M6805 compatibility the H register is not stacked MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA RAM 229 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc During a subroutine call the CPU uses two bytes of the stack to store the return address The stack pointer decrements during pushes and increments during pulls NOTE Be careful when using nested subroutines The CPU may overwrite data i
65. RESET input pulse width low tIRL 125 ns IRQ interrupt pulse width low int 125 MET edge triggered IRQ interrupt pulse period tuk Note 8 lcyc 16 bit timer Input capture pulse width trytte ns Note 8 Input capture period triTL 7 Icyc Notes 1 Vss 0 Vdc timing shown with respect to 20 Vpp and 70 Vgs unless otherwise noted See Clock Generation Module Characteristics for more information No more than 1096 duty cycle deviation from 5096 Some modules may require a minimum frequency greater than dc for proper operation See appropriate table for this information 5 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset 6 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized 7 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized 8 The minimum period tj i or trj 7 should not be less than the number of cycles it takes to execute the interrupt service routine plus tcyc Roo m MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 369 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 9 Output High Voltage Characteristics 0 5 10 40
66. Registers is set and BCS cannot be set when PLLON is clear If the PLL is off PLLON 0 selecting CGMVCLK requires two writes to the PLL control register See Base Clock Selector Circuit PRE1 and PREO Prescaler Program Bits These read write bits control a prescaler that selects the prescaler power of two multiplier P See PLL Circuits and Programming the PLL PRE1 and PREO cannot be written when the PLLON bit is set Reset clears these bits NOTE The value of P is normally 0 when using a 32 768 kHz crystal as the reference Table 7 2 PRE 1 and PREO Programming PRE1 and PREO P Prescaler Multiplier 00 0 1 01 1 2 10 2 4 11 3 8 VPR1 and 0 VCO Power of Two Range Select Bits These read write bits control the VCO s hardware power of two range multiplier E that in conjunction with L See PLL Circuits Programming the PLL and PLL VCO Range Select Register controls the hardware center of range frequency fygs VPR1 VPRO cannot be written when the PLLON bit is set Reset clears these bits Table 7 3 VPR1 and VPRO Programming VCO Power of Two Range Multiplier 1 VPR1 and VPRO E 2 4 8 1 Do not program E to a value of 3 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 117 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 6
67. Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts 4 4 3 1 Interrupt Status Register 1 Address FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 Wrie R R R R R R R R Rest 0 0 0 0 0 0 0 0 R Reserved Figure 4 7 Interrupt Status Register 1 INT1 IF6 IF1 Interrupt Flags 6 1 These flags indicate the presence of interrupt requests from the sources shown in Table 4 2 1 Interrupt request present 0 No interrupt request present Bit 1 and Bit 0 Always read 0 4 4 3 2 Interrupt Status Register 2 Address FEO05 Bit 7 6 5 4 3 2 1 Bit 0 Read F14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Wrie R R R R R R R R Rest 0 0 0 0 0 0 0 0 R Reserved Figure 4 8 Interrupt Status Register 2 INT2 IF14 1F7 Interrupt Flags 14 7 These flags indicate the presence of interrupt requests from the sources shown in Table 4 2 1 Interrupt request present 0 No interrupt request present Technical Data MC68HC908GR8 Rev 4 0 76 Resets and Interrupts For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Resets and Interrupts Interrupts 4 4 3 3 Interrupt Status Register 3 Address FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read
68. SCI Status Register2 0017 8052 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SCI Data Register 0018 SCDR Write 17 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Read SCP1 SCPO R SCR2 SCR1 SCRO 0019 SCI Baud Rate Register Write SCBR Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 18 2 SCI I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 235 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 18 5 1 Data Format The SCI uses the standard non return to zero mark space data format illustrated in Figure 18 3 8 BIT DATA FORMAT PARITY BIT M IN SCC1 CLEAR BIT NEXT VB Bro Bri Kana Y ara Y arra Y ers Y are Y ar J STOP CBE 9 BIT DATA FORMAT BIT M IN SCC1 SET i NEXT VS BITO Y Brr1 f BIT2 Y Brra Brr4 BITS X Brre Y BIT7 X Bits STOP NBI Figure 18 3 SCI Data Formats 18 5 2 Transmitter Figure 18 4 shows the structure of the SCI transmitter The baud rate clock source for the SCI can be selected via the configuration bit SCIBDSRC Source selection values are shown in Figure 18 4 Technical Data MC68HC908GR8 Rev 4 0 236 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com SCIBDSRC FROM CONFIG2 SL SL
69. SF Sp PCH REL AD Ir f4 PC PC rel CBEQ opr rel PC lt PC 3 rel A M 00 DIR 31 ddrr 5 CBEQA opr rel PC lt PC 3 rel A M 00 IMM 41 lim 4 CBEQX stopr rel l PC PC 3 rel X M 00 liMM 51 lim 4 CBEQ opr X4 rel compare and Branch if Equal PC PC 3 rel A M 00 IX14 61 ffrr 5 CBEQ Xt rel PC c PC 2 rel A M 00 IX 71 r 4 CBEQ opr SP rel PC PC 4 rel A M 00 SP1 9E61 ffrr 6 CLC Clear Carry Bit C 0 10 INH 98 1 CLI Clear Interrupt Mask 10 0 INH 9A 2 CLR opr M lt 00 DIR 3F lad 3 CLRA A 00 INH 4F 1 CLRX X 00 INH 5F 1 CLRH Clear H 00 0 1 INH 8C 1 CLR opr X M 00 IX1 6F ff 3 CLR X M 00 IX 7F 2 CLR opr SP M lt 00 SP1 QEGF ff 4 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU For More Information On This Product Go to www freescale com 149 Freescale Semiconductor Inc Central Processing Unit CPU Table 10 1 Instruction Set Summary Continued Effect on o v Source CCR 0 58 Flo Operation Description 9o 60 S 0 Form o E 98 o o 2 VIHII NZC gsl l 6 CMP opr IMM Al ii 2 CMP opr DIR Bi dd 3 CMP opr EXT C1 hhll 4 CMP opr X IX2 D1 jeeff 4 CMP opr X Compare A wit
70. TIM module The TIM on this part is a 2 channel and a1 channel timer that provides a timing reference with input capture output compare and pulse width modulation functions Figure 22 1 is a block diagram of the TIM This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2 For further information regarding timers on M68HC08 family devices please consult the HC08 Timer Reference Manual TIMOBRM AD MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 335 For More Information On This Product Go to www freescale com 22 3 Features Freescale Semiconductor Inc Timer Interface Module TIM Features of the TIM include Three input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIM clock input with 7 frequency internal bus clock prescaler selection Free running or modulo up count operation Toggle any channel pin on overflow TIM counter stop and reset bits I O port bit s software configurable with pullup device s if configured as input port bit s 22 4 Pin Name Conventions Technical Data The text that follows describes both timers TIM1 and TIM2 The TIM input output I O pin names are T 1 2 CHO timer 1 channel O timer 2 channel 0 and T 1 CH1 timer channel 1 whe
71. Voltage Characteristics 3 3 Typical Supply Currents aua sss nuaau curd rd3 LAGLAG WA 376 ADC Characteristics 0c eee eee 378 5 0 V SPI CharacteristiS ost etd ede sess Sheena wneees 379 3 0 V SPI Characteristics sce rmm 380 Timer Interface Module Characteristics 383 Clock Generation Module Characteristics 383 Memory Characteristics 22 cs co cid eeese ce RR odes 385 Technical Data MOTOROLA Electrical Specifications 361 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 2 Absolute Maximum Ratings NOTE NOTE Technical Data Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it This device is not guaranteed to operate properly beyond the maximum ratings Refer to 5 0 V DC Electrical Characteristics for guaranteed operating conditions Table 23 1 Absolute Maximum Ratings Characteristic Symbol Value Unit Supply voltage Vpp 0 3 to 4 5 5 V Input voltage Vin Vss 0 3 to Vpp 0 3 V Maximum current per pin excluding Vpp Vss 15 mA and PTCO PTC1 Maximum current for pins PTCO PTC1 lPTCO PTO1 m ma Maximum current into Vpp Imvdd 150 mA Maximum current out of Vss Imvss 150 mA Storage temperature Tstg 55 to 150 C Note 1 Voltages referenced to Vss This device contains
72. a host computer via a standard RS 232 interface Simple monitor commands can access any memory address In monitor mode the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions All communication between the host computer and the MCU is through the PTAO pin A level shifting and multiplexing interface is required between PTAO and the host computer PTAO is used in a wired OR configuration and requires a pullup resistor 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users Technical Data MC68HC908GR8 Rev 4 0 190 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description 68HC08 e RST 0 1 uF VTST i SEE NOTE 3 RESET VECTORS FFFE 10 ko SEE NOTES 2 SFFFF cl swa AND3 uu IRQ Vi D DDA Wook CGMXFC 10k5 Ss AN 0 033 u S dl sws 08C1 6 30 pF 4 SEE NOTE 2 MC145407 bot fh L a OSC2 E pP ui qom ji swa PTA1 T Ly Co J sEE NOTE 2 32 768 kHz XTAL NIE 330ko D Vss 10 uF 10uF Vop 6 30 pF e ER i VssA DB25 7 Ez 2 Vop I 3 Vpp i Vppap VREFH 7 H A paaa CA 0 1 uF ES Vpp pons 9 Vbpo MC74HC125 E
73. and fpys P fvcuk 2 X N B xfgci f5us fvcik 4 7 Select the VCO s power of two range multiplier E according to Technical Data MOTOROLA Clock Generator Module CGMC 107 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC this table Frequency Range E 0 lt fycik lt 9 830 400 9 830 400 lt fyc x lt 19 660 800 1 19 660 800 lt fyc x lt 39 321 600 2 NOTE Do not program E to a value of 3 8 Select a VCO linear range multiplier L where foy 38 4 kHz f KG round EU 2 X from 9 Calculate and verify the adequacy of the VCO programmed center of range frequency fyps The center of range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL E fyrs Ex 2 Iinom For proper operation E E INOM X VRS VGLKI MO 10 Verify the choice of P R N E and L by comparing fyc to fyns and fyci pgs For proper operation fyc must be within the application s tolerance of fyc pgs and fyps must be as close as possible to fyc NOTE Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU 11 Program the PLL registers accordingly a In the PRE bits of the PLL control register PCTL program the binary equivalent of P b In the VPR bits of the PLL control register PCTL program the binary equivalent of E Techni
74. as VssAp Vssap should be tied to the same potential as Vss via separate traces See Analog to Digital Converter ADC 1 6 8 Port A Input Output I O Pins PTA3 KBD3 PTAO KBDO PTAS3 PTAO are special function bidirectional I O port pins Any or all of the port A pins can be programmed to serve as keyboard interrupt pins See Input Output Ports I O and External Interrupt IRQ These port pins also have selectable pullups when configured for input mode The pullups are disengaged when configured for output mode The pullups are selectable on an individual port bit basis When the port pins are configured for special function mode KBI pullups will be automatically engaged As long as the port pins are in special function mode the pullups will always be on 1 6 9 Port B I O Pins PTB5 AD5 PTBO ADO PTB5 PTBO are special function bidirectional I O port pins that can also be used for analog to digital converter ADC inputs See Input Output Ports I O and Analog to Digital Converter ADC There are no pullups associated with this port MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA General Description 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 6 10 Port C I O Pins PTC1 PTCO PTC1 PTCO are general purpose bidirectional I O port pins See Input Output Ports I O PTCO and PTC1 are only available on 32 pin QFP packages These por
75. been deasserted Technical Data MC68HC908GR8 Rev 4 0 146 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU Instruction Set Summary 10 8 Instruction Set Summary Table 10 1 provides a summary of the M68HC08 instruction set Table 10 1 Instruction Set Summary Effecton y v Source dt CCR a s f lv Operation Description o IS Io Form o E 9 9 o O gt HINZC 22 0 0 6 ADC opr IMM AQ ii 2 ADC opr DIR B9 dd 3 ADC opr EXT C9 hhll 4 ABC X Add with Carry A A M C t t t t e D9 lee 3 ADC X IX F9 2 ADC opr SP SP1 9EE9 ff 4 ADC opr SP SP2 9ED9 ee ff 5 ADD opr IMM AB lii 2 ADD opr DIR BB dd 3 ADD opr EXT CB hhil 4 ADD opr X 7 IX2 DB ff 4 ADD DEER Add without Carry A A M tjt tt EB f l3 ADD X IX FB 2 ADD opr SP SP1 9EEB f 4 ADD opr SP SP2 9EDB lee ff 5 AIS opr Add Immediate Value Signed to SP SP lt SP 16 M IMM A7 i 2 AIX opr Add Immediate Value Signed to H X H X H X 16 M IMM AF ii 2 AND opr IMM A4 ii 2 AND opr DIR B4 dd 3 AND opr EXT C4 hhi 4 AND opr X IX2 D4 leeff 4 AND oprX Logical AND A A 8 M tt pd E4 f 3 AND X IX F4 2 AND opr SP SP1 9EEA ff 4 AND opr SP SP2 9ED4
76. can read the SIM reset status register to clear the register after power on reset and to determine the source of any subsequent reset The register is initialized on powerup as shown with the POR bit set and all other bits cleared During a POR or any other internal reset the RST pin is pulled low After the pin is released it will be sampled 32 XCLK cycles later If the pin is not above a V at that time then the PIN bit in the SRSR may be set in addition to whatever other bits are set NOTE Only a read of the SIM reset status register clears all reset flags After multiple resets from different sources without reading the register multiple flags remain set Address SFE01 Bit 7 6 5 4 3 2 1 Bit 0 Read POR PIN COP ILOP ILAD 0 LVI 0 Write POR 1 0 0 0 0 0 0 0 Unimplemented Figure 4 3 SIM Reset Status Register SRSR POR Power On Reset Flag 1 Power on reset since last read of SRSR 0 Read of SRSR since last power on reset PIN External Reset Flag 1 External reset via RST pin since last read of SRSR 0 POR or read of SRSR since last external reset COP Computer Operating Properly Reset Bit 1 Last reset caused by timeout of COP counter 0 POR or read of SRSR MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts
77. circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that Vj and Vo be constrained to the range Vss Vin or Vout Vpp Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either Vss or Vpp MC68HC908GR8 Rev 4 0 362 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Functional Operating Range 23 3 Functional Operating Range Table 23 2 Functional Operation Range Characteristic Symbol Value Unit Operating temperature range TA 40 to 125 C 3 0 10 Operating voltage range Vpp 5000 V NOTE To ensure correct operation of the MCU under all operating conditions the user must write data 1C to address 0033 immediately after reset This is to ensure proper termination of an unused module within the MCU 23 4 Thermal Characteristics Table 23 3 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance SOIC 28 pin L 60 ow QFP 32 pin 95 O pin power dissipation Pio User Determined W Power dissipation Pp 3e vo e
78. com
79. compare or PWM operation Selects high low or toggling output on output compare Selects rising edge falling edge or any edge as the active input capture trigger Selects output toggling on TIM overflow e Selects 0 and 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation Address TISCO 0025 and T2SCO 0030 Bit 7 6 5 4 3 2 1 Bit 0 Read CHOF CHOIE MSOB MS0A ELSOB ELSOA TOVO CHOMAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 22 11 TIM Channel 0 Status and Control Register TSCO Address T1SC1 0028 Bit 7 6 5 4 3 2 1 Bit 0 Read CHIF 0 CHIIE MS1A ELS1B ELS1A TOV1 CHIMAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 22 12 TIM Channel 1 Status and Control Register TSC1 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 355 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM CHXF Channel x Flag Bit When channel x is an input capture channel this read write bit is set when an active edge occurs on the channel x pin When channel x is an output compare channel CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers When TIM CPU interrupt requests are enabled CHxIE 1 clear CHxF by reading TIM channel x status and control register with CHxF set and th
80. compare value in the TIM channel 0 registers initially controls the output on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows At each subsequent overflow the TIM channel registers 0 or 1 that control the output are the ones written to last TSCO controls and monitors the buffered output compare function and TIM channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 pin TCH1 is available as a general purpose I O pin In buffered output compare operation do not write new output compare values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered output compares MC68HC908GR8 Rev 4 0 342 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description 22 5 6 Pulse Width Modulation PWM By using the toggle on overflow feature with an output compare channel the TIM can generate a PWM signal The value in the TIM counter modulo registers determines the period of the PWM signal The channel pin toggles when the counter reaches the value in the TIM counter modulo registers The time between ov
81. effect on port B data AD5 ADO Analog to Digital Input Bits AD5 ADO are pins used for the input channels to the analog to digital converter module The channel select bits in the ADC status and control register define which port B pin will be used as an ADC input and overrides any control from the port I O logic by forcing that pin as the input to the analog circuitry NOTE Caremust be taken when reading port B while applying analog voltages to AD5 ADO pins If the appropriate ADC channel is not enabled excessive current drain may occur if analog voltages are applied to the PTBx ADx pin while PTB is read as a digital input Those ports not selected as analog input channels are considered digital I O ports NOTE PTB4 and 5 are not available in a 28 pin DIP and SOIC package MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 213 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 16 4 2 Data Direction Register B Data direction register B DDRB determines whether each port B pin is an input or an output Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin a logic 0 disables the output buffer Address 0005 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO Write Reset 0 0 0 0 0 0 0 0 Figure 16 7 Data Direction Regi
82. executes the software interrupt instruction SWI break interrupt A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers bus A set of wires that transfers logic signals bus clock The bus clock is derived from the CGMOUT output from the CGM The bus clock frequency fop is equal to the frequency of the oscillator output CGMXCLK divided by four byte A set of eight bits C The carry borrow bit in the condition code register The CPU08 sets the carry borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow Some logical operations and data manipulation instructions also clear or set the carry borrow bit as in bit test and branch instructions and shifts and rotates CCR See condition code register central processor unit CPU The primary functioning unit of any computer system The CPU controls the execution of instructions CGM See clock generator module CGM clear To change a bit from logic 1 to logic 0 the opposite of set clock A square wave signal used to synchronize events in a computer clock generator module CGM A module in the M68HC08 Family The CGM generates a base clock signal from which the system clocks are derived The CGM may include a crystal oscillator circuit and or phase locked loop PLL circuit
83. frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error 7 9 2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability These reaction times are not constant however Many factors directly and indirectly affect the acquisition time MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC The most critical parameter which affects the reaction times of the PLL is the reference frequency fppy This frequency is the input to the phase detector and controls how often the PLL makes corrections For stability the corrections must be small compared to the desired frequency so several corrections are required to reduce the frequency error Therefore the slower the reference the longer it takes to make these corrections This parameter is under user control via the choice of crystal frequency fyc and the R value programmed in the reference divider See PLL Circuits Programming the PLL and PLL Reference Divider Select Register Another critical parameter is the external filter network The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network Therefore the rate at which the
84. identical to the MC68HC908GR8 except that it has less Flash memory Only when there are differences from the MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the text MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA General Description 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 3 Features For convenience features have been organized to reflect Standard features of the MC68HC908GR8 Features of the CPU08 1 3 1 Standard Features of the MC68HC908GR8 High performance M68HC08 architecture optimized for C compilers Fully upward compatible object code with M6805 M146805 and M68HC05 Families 8 MHz internal bus frequency FLASH program memory security On chip programming firmware for use with host personal computer which does not require high voltage for entry In system programming System protection features Optional computer operating properly COP reset Low voltage detection with optional reset and selectable trip points for 3 0 V and 5 0 V operation Illegal opcode detection with reset Illegal address detection with reset Low power design fully static with stop and wait modes Standard low power modes of operation Wait mode Stop mode Master reset pin and power on reset POR 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH
85. in January 2002 to Rev 3 0 pub lished in February 2002 beck eke SA CRI RE ete de 406 Changes from Rev 1 0 published in April 2001 to Rev 2 0 pub lished In December 2001 weccacicisesecedeeieseicieaws 406 MC68HC908GR8 Rev 4 0 16 Table of Contents MOTOROLA For More information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Table d 4 1 4 2 5 1 5 2 7s 7 2 7 3 10 1 10 2 114 14 1 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 16 1 16 2 16 3 16 4 16 5 16 6 18 1 18 2 MC68HC908GR8 Rev 4 0 List of Tables Title Page Vector Addresses a 47 Interrupt SOMES ce kasd oe ciriciri eee CIEGO dee d e 70 Interrupt Source PISOS 65 ck chokes KARA NGABA Ke Ele 75 Mux Channel Select 0020 86 ADC Clock Divide APA 88 Numeric Example srir ra ee Re od Rn PECORI e od dd 109 PRE 1 and PREO Programming naaa aannaan 117 VPR1 and VPRO Programming iaces ker mac 117 Instruction Set Summary bs cick eer d pr OO We 147 Opcodo Map esses mmm Remi 155 Examples of protect start address 166 LVIOUT Bit Indication auium x mad gteeeet AR ACE 187 Monitor Mode Signal Requirements and Options 193 Mode Differences Louie d dede ra Re RC ROCA eO CORR Ge gea 196 Monitor Baud Rate Selection 0 197 READ Read Memory Command 199 WRITE Write Memory Comman
86. in register figures in this document reserved locations are marked with the word Reserved or with the letter R 2 5 Input Output I O Section Technical Data Most of the control status and data registers are in the zero page area of 50000 5003F Additional I O registers have these addresses FEO00 SIM break status register SBSR SFE01 SIM reset status register SRSR FE03 SIM break flag control register SBFCR FEO09 interrupt status register 1 INT1 FEOA interrupt status register 2 INT2 FEOB interrupt status register 3 INT3 FEO07 reserved FLASH test control register FLTCR SFE08 FLASH control register FLCR FEO09 break address register high BRKH SFEOA break address register low BRKL FEOB break status and control register BRKSCR FEOC LVI status register LVISR FF7E FLASH block protect register FLBPR Data registers are shown in Figure 2 2 and Table 2 1 is a list of vector locations MC68HC908GR8 Rev 4 0 36 Memory Map For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Freescale Semiconductor Inc Memory Map Input Output I O Section nG O Registers 64 Bytes i RAM 384 Bytes MC68HC908GR8 FLASH Memory EE00 7680 Bytes MC68HC908GR4 FLASH Memory 4096 Bytes FE00 SIM Break Status Register SBSR FE01 SIM Reset Status Register SRSR FE03 SIM Break Flag Control Register S
87. in the TIM2 channel 0 status and control register SPI CPU interrupt sources SPI receiver full bit SPRF The SPRF bit is set every time a byte transfers from the shift register to the receive data register The SPI receiver interrupt enable bit SPRIE enables SPRF CPU interrupt requests SPRF is in the SPI status and control register and SPRIE is in the SPI control register SPI transmitter empty SPTE The SPTE bit is set every time a byte transfers from the transmit data register to the shift register The SPI transmit interrupt enable bit SPTIE enables SPTE CPU interrupt requests SPTE is in the SPI status and control register and SPTIE is in the SPI control register Mode fault bit MODF The MODF bit is set in a slave SPI if the SS pin goes high during a transmission with the mode fault enable bit MODFEN set In a master SPI the MODF bit is set if the SS pin goes low at any time with the MODFEN bit set The error interrupt enable bit ERRIE enables MODF CPU interrupt requests MODF MODFEN and ERRIE are in the SPI status and control register MC68HC908GR8 Rev 4 0 72 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com 4 4 2 8 SCI Freescale Semiconductor Inc Resets and Interrupts Interrupts Overflow bit OVRF The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift regis
88. is falling edge sensitive only With MODEK clear a vector fetch or software clear immediately clears the keyboard interrupt request Reset clears the keyboard interrupt request and the MODEK bit clearing the interrupt request even if a keyboard interrupt pin stays at logic 0 The keyboard flag bit KEYF in the keyboard status and control register can be used to see if a pending interrupt exists The KEYF bit is not affected by the keyboard interrupt mask bit IMASKK which makes it useful in applications where polling is preferred To determine the logic level on a keyboard interrupt pin use the data direction register to configure the pin as an input and read the data register MC68HC908GR8 Rev 4 0 178 Keyboard Interrupt KBI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI Keyboard Initialization NOTE Setting a keyboard interrupt enable bit KBIEx forces the corresponding keyboard interrupt pin to be an input overriding the data direction register However the data direction register bit must be a logic O for software to read the pin 13 5 Keyboard Initialization When a keyboard interrupt pin is enabled it takes time for the internal pullup to reach a logic 1 Therefore a false interrupt can occur as soon as the pin is enabled To prevent a false interrupt on keyboard initialization 1 Mask keyboard interrupts by setting t
89. is longer than tMErase Min there is no erase disturb but it reduces the endurance of the FLASH memory 4 troy is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing HVEN to logic O tuy is defined as the cumulative high voltage programming time to the same row before next erase tyy must satisfy this condition tnvs thvh toos tpRog x 64 lt tuy max The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase program cycles 7 FLASH endurance is a function of the temperature at which erasure occurs Typical endurance degrades when the tem perature while erasing is less than 25 C 8 The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase program cycles The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified 10 Motorola performs reliability testing for data retention These tests are based on samples tested at elevated temperatures Due to the higher activation energy of the elevated test temperature calculated life tests correspond to more than 100 years of operation storage at 55 C O Cc co MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 385 For More Information On This Product Go to www freescale com Freescale Semiconducto
90. is selected as the base clock source See Base Clock Selector Circuit The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set 7 4 5 Manual and Automatic PLL Bandwidth Modes Technical Data The PLL can change the bandwidth or operational mode of the loop filter manually or automatically Automatic mode is recommended for most users In automatic bandwidth control mode AUTO 1 the lock detector automatically switches between acquisition and tracking modes Automatic bandwidth control mode also is used to determine when the VCO clock CGMVCLK is safe to use as the source for the base clock CGMOUT See PLL Bandwidth Control Register If PLL interrupts are enabled the software can wait for a PLL interrupt request and then check the LOCK bit If interrupts are disabled software can poll the LOCK bit continuously during PLL startup usually or at periodic intervals In either case when the LOCK bit is set the VCO clock is safe MC68HC908GR8 Rev 4 0 104 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description to use as the source for the base clock See Base Clock Selector Circuit If the VCO is selected as the source for the base clock and the LOCK bit is clear the PLL has suffered a severe noise hit and the software must take appropriate
91. lee ff 5 ASL opr DIR 38 ldd 4 ASLA INH 48 1 ASLX Arithmetic Shift Left n INH 58 1 ASL opr X Same as LSL Ch 0 aa KA KA KA Ina 68 f 4 ASL X b7 bO IX 78 3 ASL opr SP SP1 9E68 ff 5 ASR opr DIR 37 dd 4 ASRA INH 47 1 ASRX prey INH 57 1 ASR opr X Arithmetic Shift Right C i t i X1 67 lit 4 ASR opr X b7 bo IX 77 3 ASR opr SP SP1 9E67 ff 5 BCC rel Branch if Carry Bit Clear PC PC 2 rel CO 20 REL 24 jrr 3 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU For More Information On This Product Go to www freescale com 147 Central Processing Unit CPU Freescale Semiconductor Inc Table 10 1 Instruction Set Summary Continued Effect on o vo Source CCR 0 58 Flo Operation Description 9o o S a Form oO a o o H I N Z o9 2 2 S IF O O O DIR b0 11 dd 4 DIR b1 13 dd 4 DIR b2 15 dd 4 se DIR b3 17 dd 4 BCLR n opr Clear Bit n in M Mn 0 DIR b4 19 ldd 4 DIR bb 1B dd 4 DIR b6 1D dd 4 DIR b7 1F dd 4 BCS rel Branch if Carry Bit Set Same as BLO PC PC 2 rel C 2 1 SS REL 25 jrr 3 BEQ rel Branch if Equal PC e PC 2 rel Z 1 I REL 27 rr BGE opr Med Opera or Equal TO pc PC 2 rel N V 0 REL 90 Ir 3 B
92. main program to execute the instructions in the subroutine When the RTS instruction is executed the CPU returns to the main program where it left off synchronous Refers to logic circuits and operations that are synchronized by a common reference signal TIM See timer interface module TIM MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Glossary 403 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc timer interface module TIM A module used to relate events in a system to a point in time timer A module used to relate events in a system to a point in time toggle To change the state of an output from a logic O to a logic 1 or from a logic 1 to a logic O tracking mode Mode of low jitter PLL operation during which the PLL is locked on a frequency Also see acquisition mode two s complement A means of performing binary subtraction using addition techniques The most significant bit of a two s complement number indicates the sign of the number 1 indicates negative The two s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result unbuffered Utilizes only one register for data new data overwrites current data unimplemented memory location A memory location that is not used Writing to an unimplemented location has no effect Reading an unimplemented location returns an unpredictable va
93. no effect in slave mode Reset clears SPR1 and SPRO Table 20 4 SPI Master Baud Rate Selection SPR1 and SPRO Baud Rate Divisor BD 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate CGMOUT Baud rate 2x BD where CGMOUT base clock output of the clock generator module CGM BD baud rate divisor MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 327 For More Information On This Product Go to www freescale com 20 14 3 SPI Technical Data Freescale Semiconductor Inc Serial Peripheral Interface SPI Data Register The SPI data register consists of the read only receive data register and the write only transmit data register Writing to the SPI data register writes data into the transmit data register Reading the SPI data register reads data from the receive data register The transmit data and receive data registers are separate registers that can contain different values See Figure 20 2 Address 0012 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 RO Write T7 T6 T5 T4 T3 T2 Ti TO Reset R7 RO T7 TO Receive Transmit Data Bits Figure 20 15 SPI Data Register SPDR Indeterminate after reset NOTE Do not use read modify write instructions on the SPI data register since the register read is not the same as the register written MC68HC908GR8 Rev 4 0
94. of 128 256 or 50 22 5 7 Unbuffered PWM Signal Generation Technical Data NOTE Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation PWM The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period Also using a TIM overflow interrupt routine to write a new smaller pulse width value may cause the compare to be missed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x When changing to a shorter pulse width enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current pulse The interrupt routine has until the end of the PWM period to write the new value When changing to a longer pulse width enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current PWM period Writing a larger value
95. on o o Source CCR a Ela Operation Description 9o o S a Form oO o o H INZ TO 2 og m q4q 2 O0O Oo NEG opr M amp M 00 M DIR 30 dd 4 NEGA INH 40 1 NEGX SG 500 A INH 50 1 Negate Two s Complement X X 00 X tt NEG opr X IX1 60 ff 4 M e M 00 M NEG X M M 00 M IX 70 3 NEG opr SP B SP1 9E60 ff 5 NOP No Operation None INH 9D 1 NSA Nibble Swap A A A 3 0 A 7 4 INH 62 3 ORA opr IMM AA iii 2 ORA opr DIR BA dd 3 ORA opr EXT CA hhil 4 RA X IX2 DA SAK Inclusive OR A and M A c A M ejes sees Banag a ies ORA X IX FA 2 ORA opr SP SP1 9EEA ff 4 ORA opr SP SP2 9EDA ee ff 5 PSHA Push A onto Stack Push A SP SP 1 INH 87 2 PSHH Push H onto Stack Push H SP SP 1 INH 8B 2 PSHX Push X onto Stack Push X SP SP 1 INH 89 2 PULA Pull A from Stack SP lt SP 1 Pull A INH 86 2 PULH Pull H from Stack SP lt SP 1 Pull H INH 8A 2 PULX Pull X from Stack SP lt SP 1 Pull X INH 88 2 ROL opr DIR 39 dd 4 ROLA INH 49 1 ROLX BOE opr X Rotate Left through Carry Cia A t1 DA a tf a ROL X b7 bO IX 79 3 ROL opr SP SP1 9E69 ff 5 ROR opr DIR 36 dd 4 RORA INH 46 1 ROR oprX Rotate Right through Carry ma mc t t La e ff ROR X b7 bO IX 76 3 ROR opr SP SP1 9E66 ff 5 RSP Reset Stack Pointer SP FF INH 9C 1 SP SP 1 Pull
96. ore a EP oe di ko le RO UE RN 99 To E 6 oe koro eeee ON Gee eee 100 7 4 Functional Description 4 og os ta ee Sra d Pr n Roh dn 100 COMES 600 RTT 112 7 6 CGMC Registers nk bos hi eo KAB CR AE dC ede eta OR 114 E G0 0 000 VERTIT 123 7 8 Special Modes 44 244013 a Ce pde e ded 123 7 9 Acquisition Lock Time Specifications 125 This section describes the clock generator module The CGMC generates the crystal clock signal CGMXCLK which operates at the frequency of the crystal The CGMC also generates the base clock signal CGMOUT which is based on either the crystal clock divided by two or the phase locked loop PLL clock CGMVCLK divided by two In user mode CGMOUT is the clock from which the SIM derives the system clocks including the bus clock which is at a frequency of CGMOUT 2 In monitor mode PTC3 determines the bus clock The PLL is a fully functional frequency generator designed for use with crystals or ceramic resonators The PLL can generate an 8 MHz bus frequency using a 32 kHz crystal MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 99 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 3 Features Features of the CGMC include Phase locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low frequency crystal operation with low power ope
97. oscillator stabilization delay MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Power Modes 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes 3 6 Clock Generator Module CGM 3 6 1 Wait Mode 3 6 2 Stop Mode The CGM remains active in wait mode Before entering wait mode software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register PCTL Less power sensitive applications can disengage the PLL without turning it off Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL If the OSCSTOPEN bit in the CONFIG register is cleared default then the STOP instruction disables the CGM oscillator and phase locked loop and holds low all CGM outputs CGMXCLK CGMOUT and CGMINT If the STOP instruction is executed with the VCO clock CGMVCLK divided by two driving CGMOUT the PLL automatically clears the BCS bit in the PLL control register PCTL thereby selecting the crystal clock CGMXCLK divided by two as the source of CGMOUT When the MCU recovers from STOP the crystal clock divided by two drives CGMOUT and BCS remains clear If the OSCSTOPEN bit in the CONFIG register is set then the phase locked loop is shut off but the oscillator will continue to operate in stop mode 3 7 Computer Operating Properly Module COP 3 7 1 Wait Mode
98. prescaler divisor as shown in Table 18 6 Reset clears SCP1 and SCPO Table 18 6 SCI Baud Rate Prescaling SCP1 and SCPO Prescaler Divisor PD 00 1 01 3 10 4 11 13 SCR2 SCRO0 SCI Baud Rate Select Bits These read write bits select the SCI baud rate divisor as shown in Table 18 7 Reset clears SCR2 SCRO Table 18 7 SCI Baud Rate Selection SCR2 SCR1 Baud Rate and SCRO Divisor BD 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Technical Data MC68HC908GR8 Rev 4 0 266 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI O Registers Use this formula to calculate the SCI baud rate fBUS baud rate GF pp x BD where fBus bus frequency PD prescaler divisor BD baud rate divisor SCI BDSRC is an input to the SCI Normally it will be tied off low at the top level to select the bus clock as the clock source This makes the formula f BUS baud rate CT POX BD Table 18 8 shows the SCI baud rates that can be generated with a 4 9152 MHz bus clock MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 267 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI T
99. the maximum amount of time before the first timeout MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 279 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM The COP module is disabled if the RST pin or the IRQ pin is held at Vist while the MCU is in monitor mode The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin This prevents the COP from becoming disabled as a result of external noise During a break state Vist on the RST pin disables the COP module 19 4 2 3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions An illegal instruction sets the ILOP bit in the SIM reset status register SRSR and causes a reset If the stop enable bit STOP in the mask option register is logic 0 the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset The SIM actively pulls down the RST pin for all internal reset sources 19 4 2 4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR and resetting the MCU A data fetch from an unmapped address does not generate a reset The SIM actively pulls down the RST pin for
100. the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the POR bit in the SIM reset status register and clears all other bits in the register OSC1 N N M PoRRST N N N 4096 32 32 CYCLES CYCLES CYCLES a Bejat gt a CGMXCLK N NI Ng CGMOUT N N N RST PIN N N N INTERNAL N N N RESET 1 PORRST is an internally generated power on reset pulse Figure 4 2 Power On Reset Recovery 4 3 3 2 COP Reset A COP reset is an internal reset caused by an overflow of the COP counter A COP reset sets the COP bit in the system integration module SIM reset status register To clear the COP counter and prevent a COP reset write any value to the COP control register at location SFFFF MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts 4 3 3 3 Low Voltage Inhibit Reset A low voltage inhibit LVI reset is an internal reset caused by a drop in the power supply voltage to the LVI trip voltage Vrnipr An LVI reset e Holds the clocks to the CPU and modules inactive fo
101. the receiver Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Reset clears the RE bit 1 Receiver enabled 0 Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RWU Receiver Wakeup Bit This read write bit puts the receiver in a standby state during which receiver interrupts are disabled The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit Reset clears the RWU bit 1 Standby state 0 Normal operation SBK Send Break Bit Setting and then clearing this read write bit transmits a break character followed by a logic 1 The logic 1 after the break character guarantees recognition of a valid start bit If SBK remains set the transmitter continuously transmits break characters with no logic 1s between them Reset clears the SBK bit 1 Transmit break characters 0 No break characters being transmitted NOTE Do not toggle the SBK bit immediately after setting the SCTE bit Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 257 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 1
102. the slave SPI module must be set to logic 1 between bytes See Figure 20 12 Reset sets the CPHA bit SPWOM SPI Wired OR Mode Bit This read write bit disables the pullup devices on pins SPSCK MOSI and MISO so that those pins become open drain outputs 1 Wired OR SPSCK MOSI and MISO pins 0 Normal push pull SPSCK MOSI and MISO pins MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 323 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI SPE SPI Enable This read write bit enables the SPI module Clearing SPE causes a partial reset of the SPI See Resetting the SPI Reset clears the SPE bit 1 SPI module enabled 0 SPI module disabled SPTIE SPI Transmit Interrupt Enable This read write bit enables CPU interrupt requests generated by the SPTE bit SPTE is set when a byte transfers from the transmit data register to the shift register Reset clears the SPTIE bit 1 SPTE CPU interrupt requests enabled 0 SPTE CPU interrupt requests disabled 20 14 2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions Receive data register full Failure to clear SPRF bit before next byte is received overflow error Inconsistent logic level on SS pin mode fault error e Transmit data register empty The SPI status and control registe
103. the time between the last FLASH address programmed 11 to clearing PGM bit step 7 to step 10 must not exceed the maximum programming Wait for a time thyn time tpRoG max 12 Y Clear HVEN bit This row program algorithm assumes the row s to be programmed are initially erased Y 13 Wait for a time tcv T EN C End of programming J Figure 11 2 FLASH Programming Flowchart Technical Data MC68HC908GR8 Rev 4 0 164 Flash Memory MOTOROLA For More information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory FLASH Block Protection 11 8 1 FLASH Block Protect Register The FLASH block protect register FLBPR is implemented as a byte within the FLASH memory and therefore can only be written during a programming sequence of the FLASH memory The value in this register determines the starting location of the protected range within the FLASH memory Address SFF7E Bit 7 6 5 4 3 2 1 Bit 0 Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPRO Write Reset U U U U U U U U U Unaffected by reset Initial value from factory is 1 Write to this register is by a programming sequence to the FLASH memory Figure 11 3 FLASH Block Protect Register FLBPR BPR 7 0 FLASH Block Protect Bits These eight bits represent bits 13 6 of a 16 bit memory address Bits 15 14 are logic 1s and bits 5 0 are logic Os The re
104. to drive high voltages for program and erase operations in the array HVEN can only be set if either PGM 1 or ERASE 1 and the proper sequence for program or erase is followed 1 High voltage enabled to array and charge pump on 0 High voltage disabled to array and charge pump off MASS Mass Erase Control Bit Setting this read write bit configures the 8K byte FLASH array for mass erase operation 1 MASS erase operation selected 0 MASS erase operation unselected ERASE Erase Control Bit This read write bit configures the memory for erase operation ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Erase operation selected 0 Erase operation unselected MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Flash Memory 159 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory PGM Program Control Bit This read write bit configures the memory for program operation PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Program operation selected 0 Program operation unselected 11 5 FLASH Page Erase Operation Use this step by step procedure to erase a page 64 bytes of FLASH memory to read as logic 1 1 Set the ERASE bit and clear the MASS bit in the FLASH control register Read the FLASH block protect register e Write a
105. voltage changes for a given frequency error thus change in charge is proportional to the capacitance The size of the capacitor also is related to the stability of the PLL If the capacitor is too small the PLL cannot make small enough adjustments to the voltage and the system cannot lock If the capacitor is too large the PLL may not be able to adjust the voltage in a reasonable time See Choosing a Filter Also important is the operating voltage potential applied to Vppa The power supply potential alters the characteristics of the PLL A fixed value is best Variable supplies such as batteries are acceptable if they vary within a known range at very slow speeds Noise on the power supply is not acceptable because it causes small frequency errors which continually change the acquisition time of the PLL Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change The part operates as specified as long as these influences stay within the specified limits External factors however can cause drastic changes in the operation of the PLL These factors include noise injected into the PLL through the filter capacitor filter capacitor leakage stray impedances on the circuit board and even humidity or circuit board contamination Technical Data MC68HC908GR8 Rev 4 0 126 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com
106. 0 Read p Timer 2 Counter Modulo Bit 15 14 13 12 11 10 9 Bit 8 002E Register High T2MODH le Reset 1 1 1 1 1 1 1 1 Read f Timer 2 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 002F Register Low T2MODL Wie Reset 1 1 1 1 1 1 1 1 Timer 2 Channel 0 Status Read CHOF 0030 and Control Register Write 0 CHOIE MS0B MS0A ELSOB ELSOA TOVO CHOMAX T2SCO Reset 0 0 0 0 0 0 0 0 Timer2 Channel o N2 pit 45 14 13 12 1 10 9 Bit 8 0031 Write Register High T2CHOH Reset Indeterminate after reset Read f Timez Chamado BAT 6 5 4 3 2 1 Bito 0032 Write Register Low T2CHOL Reset Indeterminate after reset Read 0033 Unimplemented Write Reset 0 0 0 0 0 0 0 0 Read 0034 Unimplemented Write Reset Indeterminate after reset Read 0035 Unimplemented Write Reset Indeterminate after reset Unimplemented Figure 22 2 TIM I O Register Summary Sheet 2 of 2 22 5 1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin TCLK The prescaler generates seven clock rates from the internal bus clock The prescaler select bits PS 2 0 in the TIM status and control register select the TIM clock source Technical Data MC68HC908GR8 Rev 4 0 340 Timer Interface Module TIM For More Information On This Product Go to www freescale com MOTOROLA 22 5 2 Input Capture Freescale Semiconductor Inc Timer Interface Module TIM Functional De
107. 0 0 0 0 0 0 IF16 IF15 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 4 9 Interrupt Status Register 3 INT3 IF16 IF15 Interrupt Flags 16 15 This flag indicates the presence of an interrupt request from the source shown in Table 4 2 1 Interrupt request present 0 No interrupt request present Bits 7 2 Always read 0 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Technical Data MC68HC908GR8 Rev 4 0 78 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 5 1 Contents 5 2 Introduction Section 5 Analog to Digital Converter ADC 5 2 5 3 5 4 55 5 6 5 7 5 8 la cr aor ke Ead yel dopo hee b he olv AA PAA 79 pai o PAA AAP tt ot DOT iT 80 Functional Description ee Spa eor ee denn AK ELA 80 PE cix Rd E E KNANG AKA KA KALA d op UR GAAN 83 Low Power Modes Like dace wo x X ORE GREC he E POE 83 Le5 p p T NA AA E 83 8820 bA P ees 85 This section describes the 8 bit analog to digital converter ADC For further information regarding analog to digital converters on Motorola microcontrollers please consult the HC08 ADC Reference Manual ADCRM AD MC68HC908GR8 Rev 4 0
108. 0 5X A 1 gt X B SCP1 SCPO SCR1 SCR2 SCRO TRANSMITTER CPU INTERRUPT REQUEST Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description INTERNAL BUS PRE BAUD SCALER DIVIDER E SCI DATA REGISTER 11 BIT TRANSMIT SHIFT REGISTER 6 5 4 3 2 PE2 TxD t5 TXINV LL 2 e Ea m M 5 m PEN PARITY 9 uy lt PTY GENERATION 3 3 u x a TE amp m I a aj IH Cc ui Q E wa ma E T8 o o 2 E DMATE TRANSMITTER DMATE CONTROL LOGIC SCTIE SCTE SCTE mm DMATE E LOOPS SCTIE ENSCI TC TC la TE Tel TCIE Figure 18 4 SCI Transmitter 18 5 2 1 Character Length The transmitter can accommodate either 8 bit or 9 bit data The state of the M bit in SCI control register 1 SCC1 determines character length When transmitting 9 bit data bit T8 in SCI control register 3 SCC3 is the ninth bit bit 8 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 237 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 18 5 2 2 Character Transmission During an SCI transmission the transmit shift registe
109. 0 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC CGMC Registers 7 6 5 PLL VCO Range Select Register NOTE PMRS may be called PVRS on other HC08 derivatives The PLL VCO range select register PMRS contains the programming information required for the hardware configuration of the VCO Address S003A Bit 7 6 5 4 3 2 1 Bit 0 Read VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO Write Reset 0 1 0 0 0 0 0 0 Figure 7 8 PLL VCO Range Select Register PMRS VRS7 VRS0 VCO Range Select Bits These read write bits control the hardware center of range linear multiplier L which in conjunction with E see PLL Circuits Programming the PLL and PLL Control Register controls the hardware center of range frequency fyps VRS7 VRSO cannot be written when the PLLON bit in the PCTL is set See Special Programming Exceptions A value of 00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register PCTL See Base Clock Selector Circuit and Special Programming Exceptions Reset initializes the register to 40 for a default range multiply value of 64 NOTE The VCOrange select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 and such that the VCO clock cannot be selected as the source of the base clock B
110. 08GR8 Rev 4 0 28 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description MCU Block Diagram TINON AHLN3 SCOW HOLINOW 31ndON ALIWNOAS FINGOW 13634 NO H3MOd X1 031d QXu L31d 31HOd ss 0dld Losin ald ISOW 2dLd WOSdS EALd 10HOLLvOLd LHOLL SALd OHOZL 9GLd Q18Od quad oaviogLd sqv sald lt gt 4 ogawovid eaawevid CT FINGOW cd318I93H NOILdO ASYN JINON LHI1SI9AH NOILdO 9SVIN INGON HOLIMS SN VLVG FINGOW YOLINOW JINON 39V3H3 NI 1VH3Hdi43d 1viH3S 310n00N A143d0td ONILYHIdO HILNdNOO JINON 39V3U3 NI SNOILYIINANWWOO 1vIH3S e 3IndON 39V3W31NI H3IALL THNNVHO E FINGOW 3OV3H31NI H3IALL TANNVHO 2 JINON LA NHHILNI GYVOSAA LI8 Y JINON LIgIHNI 39YLI0A MO7 TYNG FINGOW Wadd Ld388 ITONIS 31ndON ASVEAWIL HHOHd snd IWNYSLNI a21nap dnjjnd pejeJ6ejur surejuoo Uld suid uod eAup 1uauno 1eufiip t uod indui ji eoi ep dnjjnd ui ejqeaniuoo e1eMjyos ase suog 4 4 YSSA a Vad HAMOd SSA kap 18344 OSSA hat HiH VAG 310100 HILHIANOO WLIDSIG OL SOTWNY 118 8 31na0W bul OHI TYN431X3 319NIS IINGON isu NOLLVHO3INI WALSAS HLNI Z T dO01 G3X4001 3SYHd 94XIN99 HOLVTIIOSO ZH 26 6980 LISO JINON HOLVU3N39 92019 SILAG 9 JOVdS HO103A HSV 13 YISN NOY Ni Nung 9NINNYHDOHd HSY74 Figure 1 1 MCU B
111. 0Ha d 4 v S v v 4 L L 4 v L L v S XI lds IXI ec edS ZXI E IXA HId cJ WMWI HNI Qq Xi e ani xid z qd 3H jyid c Uuld xaql xaql xaql xaq xaq xaql xdi xaql x dOls AOW AOW AOW AOW dla L13S8 Z13SH8 3 4 v S v v 4 k v v v S v S XI IXI c xI 1X3 HId c l3H HNI XI LH IidS j IXI c HNI LIHNI Hd cj l3H c Hld c UHuld asr asr asr asr asr usa dON ISL ISL ISL XLSL VISL ISL SNA 9H10d 99410849 a v S 9 S v v L 4 v L L v S XI IXI c ex E IXA E Ha c HNI HNI XI tb btdS IXI c HNI L HN L Hd Z 13Y d Ha 2 Ha dr dwr dvr dr dvr dSu HUTO ONI ONI ONI XONI VONI ONI OWd 9LASd 913SHH 2 4 v 4 L L S v L L v v S XI lds E IXI Z Zds v exl E IXA MUId Z NWI HNI HNI XI 2 ds t IXI HNI ZIHNI c Hd j134 c HId Z Ha ady ady ady ady ady ady ady ady 13S HHSd zNga ZN8G ZN8G XZN8G VZN8G ZN8G INg s4109 94190848 a 4 v S v v 4 4 4 v 9 S S v S XI lds j IXI Z Zds v exl E IXI MHUId Z NNI HNI HNI XI bt tdS IXI c HNI L HN LL Hd cH Z Ha Z Ha VHO VHO YHO VHO VHO YHO VHO VHO NO Hind 230 330 odd xoaa voga 330 Idd slasqd S13SHH v 4 v S v v E 4 4 4 S v L 5 v E v S XI lds IXI ec edS v ZXI E IXA HId c WMWI HNI L HNI XI H HidS j IXI c HNI HNI aa Z 134 Ha c uld JAV oav JAV JAV oav AV oav JAV 23s XHSd TOH TOH TOH X10H V IOH TOH SOHA vH10d 7HT10HA 6 4 v S v v 4 L 4 S v L L v E v S XI
112. 1 0 No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag clearing sequence Figure 18 13 shows the normal flag clearing sequence and an example of an overrun caused by a delayed flag clearing sequence The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read Byte 2 caused the overrun and is lost The next flag clearing sequence reads byte 3 in the SCDR instead of byte 2 In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun the flag clearing routine can check the OR bit in a second read of SCS1 after reading the data register NF Receiver Noise Flag Bit This clearable read only bit is set when the SCI detects noise on the PE1 RxD pin NF generates an NF CPU interrupt request if the NEIE bit in SCC is also set Clear the NF bit by reading SCS1 and then reading the SCDR Reset clears the NF bit 1 Noise detected 0 No noise detected FE Receiver Framing Error Bit This clearable read only bit is set when a logic O is accepted as the stop bit FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set Clear the FE bit by reading SCS1 with FE set and then reading the SCDR Reset clears the FE bit 1 Framing error detected 0 No framing error detected Technical Data MC68HC908GR8 Rev 4 0 262 Serial Communications Interf
113. 19 8 Interrupt Entry TM ices xad ue Fed dat enm Rn 283 19 9 Interrupt Recovery Timing 2 nr RR Rennen 283 19 10 Interrupt Processing carnea d KB RE RE RETAA ERE GRE 284 19 11 Interrupt Recognition Example aaee 285 19 12 Interrupt Status Register 1 INT1 naana 288 19 13 Interrupt Status Register 2 INT2 288 19 14 Interrupt Status Register 3 INT3 289 19 15 Wait Mode Entry TUNING 4 user dod ERAS E CR e 291 19 16 Wait Recovery from Interrupt or Break 291 19 17 Wait Recovery from Internal Reset 292 18 18 Stop Mode Entry TIMING 3 3 aa kana PG ERR CR Oe Roe es 293 19 19 Stop Mode Recovery from Interrupt or Break 293 19 20 SIM Break Status Register SBSR 294 19 21 SIM Reset Status Register SRSR 295 19 22 SIM Break Flag Control Register SBFCR 296 20 1 SPI I O Register Summary annann 299 20 2 SPI Module Block DIGONG KA KG dec oC e on 300 20 3 Full Duplex Master Slave Connections 301 20 4 Transmission Format CPHA 20 0 305 20 5 CPHA SS Timing s ssos rrr Ra kan ER Ine 305 20 6 Transmission Format CPHA 2 1 306 20 7 Transmission Start Delay Master 308 20 6 SPRF SPTE CPU Interrupt TIMING 44224 cane RR 309 20 9 Missed Read of Overflow Condition 311 20 10 Clearing SP
114. 2 PLL Bandwidth Control Register The PLL bandwidth control register PBWC Selects automatic or manual software controlled bandwidth control mode e Indicates when the PLL is locked e In automatic bandwidth control mode indicates when the PLL is in acquisition or tracking mode n manual operation forces the PLL into acquisition or tracking mode Address 0037 Bit 7 6 5 4 3 2 1 Bit 0 Read LOCK xm 0 0 0 0 AUTO ACQ R Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 7 5 PLL Bandwidth Control Register PBWC AUTO Automatic Bandwidth Control Bit This read write bit selects automatic or manual bandwidth control When initializing the PLL for manual operation AUTO 0 clear the ACQ bit before turning on the PLL Reset clears the AUTO bit 1 Automatic bandwidth control 0 Manual bandwidth control LOCK Lock Indicator Bit When the AUTO bit is set LOCK is a read only bit that becomes set when the VCO clock CGMVCLK is locked running at the programmed frequency When the AUTO bit is clear LOCK reads as logic O and has no meaning The write one function of this bit is reserved for test so this bit must always be written a 0 Reset clears the LOCK bit Technical Data MC68HC908GR8 Rev 4 0 118 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
115. 3 Address SFE06 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 116 115 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 14 Interrupt Status Register 3 INT3 Bits 7 2 Always read 0 116 115 Interrupt Flags 16 15 These flags indicate the presence of an interrupt request from the source shown in Table 19 3 1 Interrupt request present 0 No interrupt request present 19 6 2 Reset All reset sources always have equal and highest priority and cannot be arbitrated 19 6 3 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output See Timer Interface Module TIM The SIM puts the CPU into the break state by forcing it to the SWI vector location Refer to the break interrupt subsection of each module to see how each module is affected by the break state MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 289 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 6 4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit BCFE in the SIM break flag control regist
116. 3 Voltage Hysteresis Protection Technical Data Once the LVI has triggered by having Vpp fall below V7pjpp the LVI will maintain a reset condition until Vpp rises above the rising trip point voltage Vrgipn This prevents a condition in which the MCU is continually entering and exiting reset if Vpp is approximately equal to VTniPr VTRIPR is greater than Vrpipr by the hysteresis voltage Vyys MC68HC908GR8 Rev 4 0 186 Low Voltage Inhibit LVI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI LVI Status Register 14 4 4 LVI Trip Selection The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5V or 3V protection NOTE The microcontroller is guaranteed to operate at a minimum supply voltage The trip point Vrgipe 5 V or Vrgipe 8 V may be lower than this See Electrical Specifications for the actual trip point voltages 14 5 LVI Status Register The LVI status register LVISR indicates if the Vpp voltage was detected below the V7pjpr level Address SFEOC Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 3 LVI Status Register LVISR LVIOUT LVI Output Bit This read only flag becomes set when the Vpp voltage falls below the VTnipr trip voltage See Table 14 1 Reset clears the LVI
117. 4 kHz times a linear factor L and a power of two factor E or L x 25 fyoy CGMRCLK is the PLL reference clock a buffered version of CGMXCLK CGMRCLK runs at a frequency fac and is fed to the PLL through a programmable modulo reference divider which divides fac by a factor R The divider s output is the final reference clock CGMRDV running at a frequency fppy faci K R With an external crystal 30 KHz 100 kHz always set R 1 for specified performance With an external high frequency clock source use R to divide the external frequency to between 30 kHz and 100 kHz The VCO s output clock CGMVCLK running at a frequency fyc k is fed back through a programmable prescale divider and a programmable modulo divider The prescaler divides the VCO clock by a power of two factor P and the modulo divider reduces the VCO clock by a factor N The dividers output is the VCO feedback clock CGMVDV running at a frequency fypy fyci KAN x 2P See Programming the PLL for more information The phase detector then compares the VCO feedback clock CGMVDV with the final reference clock CGMRDV A correction pulse is generated based on the phase difference between the two signals The loop filter then slightly alters the DC voltage on the external capacitor connected to CGM XFC based on the width and direction of the correction pulse The filter can make fast or slow corrections depending on its mode described in Acquisition an
118. 48 Central Processing Unit CPU For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Central Processing Unit CPU Table 10 1 Instruction Set Summary Continued Instruction Set Summary Effect on o o Source 7 CCR 0 58 Flo Operation Description 9o 60 S 0 Form o 3 9 8 o o S HINZC 2s o BNE rel Branch if Not Equal PC PC 2 rel Z 0 REL 26 jrr 3 BPL rel Branch if Plus PC PC 2 rel N 0 22 2 s REL 2A r 3 BRA rel Branch Always PC lt PC 2 rel REL 20 rr 3 DIR bO 01 ddrr 5 DIR b1 03 ddrr 5 DIR b2 05 ddrr 5 BRCLR n opr rel Branch if Bit n in M Clear PC e PC 3 rel Mn 0 t DIR pa HS naba pa DIR b5 OB ddrr 5 DIR b6 OD ddrr 5 DIR b7 OF ddrr 5 BRN rel Branch Never PC PC 2 REL 21 jrr 3 DIR b0 00 ddrr 5 DIR b1 02 ddrr 5 DIR b2 04 ddrr 5 BRSET n opr rel Branch if Bit n in M Set PC e PC 3 rel Mn 1 DIR ba ric uq DIR b5 OA ddrr 5 DIR b6 OC ddm 5 DIR b7 OE ddrr 5 DIR b0 10 ldd 4 DIR b1 12 dd 4 DIR b2 14 dd 4 ar DIR b3 16 dd 4 BSET n opr Set Bit nin M Mn c 1 7 7 7 DIR b4 18 ldd 4 DIR b5 1A dd 4 DIR b6 1C ldd 4 DIR b7 1E dd 4 PC PC 2 push PCL BSR rel Branch to Subroutine E
119. 6 Keyboard Initialization 14 2 rr ERE ROCA EORR ER 179 Low Power Modes cirea aed 4 eR A ewes RC Ro de o o 180 Keyboard Module During Break Interrupts 180 VO REJSTES 181 The keyboard interrupt module KBI provides four independently maskable external interrupts MC68HC908GR8 Rev 4 0 Four keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Hysteresis buffers Programmable edge only or edge and level interrupt sensitivity Exit from low power modes I O input output port bit s software configurable with pullup device s if configured as input port bit s Technical Data MOTOROLA Keyboard Interrupt KBI 175 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI 13 4 Functional Description Writing to the KBIE3 KBIEO bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin Enabling a keyboard interrupt pin also enables its internal pullup device A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request A keyboard interrupt is latched when one or more keyboard pins goes low after all were high The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt fthe keyboard interrupt is edge sensit
120. 8 9 3 SCI Control Register 3 SCI control register 3 e Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables these interrupts Receiver overrun interrupts Noise error interrupts Framing error interrupts e Parity error interrupts Address 0015 Bit 7 6 5 4 3 2 1 Bit 0 Read R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write Reset U U 0 0 0 0 0 0 Unimplemented U Unaffected Figure 18 11 SCI Control Register 3 SCC3 R8 Received Bit 8 When the SCI is receiving 9 bit characters R8 is the read only ninth bit bit 8 of the received character R8 is received at the same time that the SCDR receives the other 8 bits When the SCI is receiving 8 bit characters R8 is a copy of the eighth bit bit 7 Reset has no effect on the R8 bit T8 Transmitted Bit 8 When the SCI is transmitting 9 bit characters T8 is the read write ninth bit bit 8 of the transmitted character T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register Reset has no effect on the T8 bit Technical Data MC68HC908GR8 Rev 4 0 258 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI O Registers DMARE DMA Receive Enable Bit CAUTION The DMA modu
121. 8 pin DIP target head adapter M68TC08GR8FA32 32 pin QFP target head adapter M68TQS032SAG1 32 pin TQ socket with guides M68TQP032SA1 32 pin TQPACK MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Ordering Information 393 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ordering Information Technical Data MC68HC908GR8 Rev 4 0 394 Ordering Information MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Glossary A See accumulator A accumulator A An 8 bit general purpose register in the CPU08 The CPUOS uses the accumulator to hold operands and results of arithmetic and logic operations acquisition mode A mode of PLL operation during startup before the PLL locks on a frequency Also see tracking mode address bus The set of wires that the CPU or DMA uses to read and write memory locations addressing mode The way that the CPU determines the operand address for an instruction The M68HC08 CPU has 16 addressing modes ALU See arithmetic logic unit ALU arithmetic logic unit ALU The portion of the CPU that contains the logic circuitry to perform arithmetic logic and manipulation operations on operands asynchronous Refers to logic circuits and operations that are not synchronized by a common referenc
122. 95 Vssap 0 Vde VREFH 5 0 Vdc 10 VREFL 0 2 Source impedances greater than 10 kQ adversely affect internal RC charging time during input sampling 3 Zero input full scale reading requires sufficient decoupling measures for accurate conversions 4 The external system error caused by input leakage current is approximately equal to the product of R source and input current Technical Data MC68HC908GR8 Rev 4 0 378 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 5 0 V SPI Characteristics 23 13 5 0 V SPI Characteristics Diagram istic Symbol Min Max Unit Number Characteristic y Operating frequency Master fop m fop 128 fop 2 MHz Slave fop s DC fop MHz Cycle time 1 Master tcyc m 2 128 lcyc Slave lcvc s 1 lcyc 2 Enable lead time ll ead S 1 Es teyc 3 Enable lag time tLag S 1 TE loyc Clock SPSCK high time 4 Master tsckH M toyo 25 64 tcyc ns Slave tsckH S 1 2 lcyc 25 ns Clock SPSCK low time 5 Master tscKL M teye 25 64 tcyc ns Slave 15CKL S 1 2 loyc 25 ns Data setup time inputs 6 Master tsu M 30 ns Slave tsU s 30 ns Data hold time inputs 7 Master tH M 30 ns Slave tH s 30 ns Access time slave 8 CPHA 0 lA CPO 0 40 ns CPHA 1 tA CP1 0 40 ns 9 Disable time slave lpis s 40 ns Da
123. A BUS PN WU READ DDRBx a WRITE DDRBx EORR DISABLE RESET 5 t WRITE PTB em PTBx T 1 ri PTBx 3 1 ADC CHANNEL x READ PTBx l AN N7 ADC DATA REGISTER DISABLE NN YQ ADC Y INTERRUPT ADC VapN CHANNEL 88 af LOGIC SELECT EN ESEG boc CLOCK CGMXCLK CLOCK BUS CLOCK p GENERATOR ADIV2 ADIVO ADICLK Figure 5 1 ADC Block Diagram 5 4 1 ADC Port I O Pins PTB5 ATD5 PTBO ATDO are general purpose I O input output pins that share with the ADC channels The channel select bits define which ADC channel port pin will be used as the input signal The ADC overrides the port I O logic by forcing that pin as input to the ADC The remaining ADC channels port pins are controlled by the port I O logic and can be used as general purpose I O Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC Read of a port pin in use by the ADC will return a logic 0 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Analog to Digital Converter ADC 81 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC 5 4 2 Voltage Conversion NOTE When the input voltage to the ADC equals Vpepp the ADC converts the signal to FF full scale If t
124. AX 0025 and Control Register Write 0 TISCO Reset 0 0 0 0 0 0 0 0 ee Bit 15 14 13 12 11 10 9 Bit 8 Timer 1 Channel 0 P l 0026 Register High TICHOH Me Reset Indeterminate after reset hci Bit 7 6 5 4 3 2 1 Bit 0 Timer 1 ChannelO l 0027 Register Low TICHOL tte Reset Indeterminate after reset t One time writeable register after each reset except LVIBORS bit LVIBORS bit is only reset via POR power on reset Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 4 of 8 Technical Data MC68HC908GR8 Rev 4 0 42 Memory Map MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read CHIF 0 Timer 1 Channel 1 Status CHIIE MS1A ELS1B ELS1A TOV1 CHIMAX 0028 and Control Register Write 0 TISCT Reset 0 0 0 0 0 0 0 0 id Bit 15 14 13 12 11 10 9 Bit 8 Timer 1 Channel 1 P l 0029 Register High T1CH1H te Reset Indeterminate after reset ka Bit 7 6 5 4 3 2 1 Bit 0 Timer 1 Channel 1 l l 002A Register Low T1CH1L NAG Reset Indeterminate after reset kg BAL TOIE TSTOP i PS2 PS1 PS0 Timer 2 Status and Control 002B Re
125. B2 ATD2 MC68HC908GR8 Rev 4 0 86 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC O Registers Table 5 1 Mux Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCHO Input Select 0 0 0 1 1 PTB3 ATD3 0 0 1 0 0 PTB4 ATD4 0 0 1 0 1 PTB5 ATD5 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved l l l l l Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 VREFH 1 1 1 1 0 VREFL 1 1 1 1 1 ADC power off NOTE If an unknown channel is selected it should be made clear what value the user will read from the ADC Data Register unknown or reserved is not specific enough 5 8 2 ADC Data Register One 8 bit result register ADC data register ADR is provided This register is updated each time an ADC conversion completes Address S0003D Bit 7 6 5 4 3 2 1 Bit 0 Read AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 5 3 ADC Data Register ADR MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Analog to Digital Converter ADC 87 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC 5 8 3 ADC Clock Register The ADC clock register ADCLK selects the clock frequency for th
126. BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register Therefore a write to the SPDR in break mode with the BCFE bit cleared has no effect The SPI module has five I O pins and shares four of them with a parallel I O port They are e MISO Data received e MOSI Data transmitted e SPSCK Serial clock SS Slave select e CGND Clock ground internally connected to Vss The SPI has limited inter integrated circuit I C capability requiring software support as a master in a single master environment To MC68HC908GR8 Rev 4 0 318 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor I
127. BFCR FE09 Interrupt Status Register 1 INT1 SFEOA Interrupt Status Register 2 INT2 FEOB Interrupt Status Register 3 INT3 Figure 2 1 Memory Map MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 37 For More Information On This Product Go to www freescale com Note FFF6 FFFD contains 8 security bytes Technical Data Freescale Semiconductor Inc Memory Map FE08 FE09 FEOA FEOB FEOC FEOD l FEOF FE10 l SFE1F FE20 l FF55 FF56 l FF7D FF7E FF7F J FFDB FFDC l FFFE FFFF FLASH Control Register FLCR Break Address Register High BRKH Break Address Register Low BRKL Break Status and Control Register BRKSCR LVI Status Register LVISR Reserved 3 Bytes Unimplemented 16 Bytes Reserved for Compatibility with Monitor Code for A Family Parts Monitor ROM 310 Bytes Unimplemented 40 Bytes FLASH Block Protect Register FLBPR Unimplemented 93 Bytes FLASH Vectors 36 Bytes inluding SFFFF Low byte of reset vector when read COP Control Register COPCTL Figure 2 1 Memory Map Continued MC68HC908GR8 Rev 4 0 38 Memory Map For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Memory Map Input Output I O Section
128. Bit This read write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests Reset clears the SCRIE bit 1 SCRF enabled to generate CPU interrupt 0 SCRF not enabled to generate CPU interrupt ILIE Idle Line Interrupt Enable Bit This read write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests Reset clears the ILIE bit 1 IDLE enabled to generate CPU interrupt requests 0 IDLE not enabled to generate CPU interrupt requests TE Transmitter Enable Bit Setting this read write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PE2 TxD pin If software clears the TE bit the transmitter completes any transmission in progress before the PE2 TxD returns to the idle Technical Data MC68HC908GR8 Rev 4 0 256 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI O Registers condition logic 1 Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted Reset clears the TE bit 1 Transmitter enabled 0 Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this read write bit enables
129. C3 enables OR to generate SCI error CPU interrupt requests Noise flag NF The NF bit is set when the SCI detects noise on incoming data or break characters including start data and stop bits The noise error interrupt enable bit NEIE in SCC3 enables NF to generate SCI error CPU interrupt requests MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 249 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Framing error FE The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit The framing error interrupt enable bit FEIE in SCC3 enables FE to generate SCI error CPU interrupt requests Parity error PE The PE bit in SCS1 is set when the SCI detects a parity error in incoming data The parity error interrupt enable bit PEIE in SCC3 enables PE to generate SCI error CPU interrupt requests 18 6 Low Power Modes 18 6 1 Wait Mode 18 6 2 Stop Mode Technical Data The WAIT and STOP instructions put the MCU in low power consumption standby modes The SCI module remains active after the execution of a WAIT instruction In wait mode the SCI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consum
130. CH1 a A ou CHF MS1A CH1IE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TSC may generically refer to both T1SC and T2SC NOTE will be available in both TIM1 and TIM2 Technical Data In Figure 22 1 channel1 will only be available in TIM1 while channel 0 MC68HC908GR8 Rev 4 0 338 Timer Interface Module TIM For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Timer Interface Module TIM Functional Description Figure 22 2 summarizes the timer registers Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Tini Status anetContie oe lro PS PS1 PSO 0020 Write 0 TRST Register T1SC Reset 0 0 1 0 0 0 0 0 f Read Bit1 14 1 12 11 1 Bit 0021 Timer 1 Counter Register ue Lo s High T1CNTH gh TICNTH not 0 0 0 0 0 0 0 0 Read Bit7 4 2 1 Bit 0022 Timer 1 Counter Register We us Low TICNTL Reset 0 0 0 0 0 0 0 0 Read 2 Timer 1 Counter Modulo Bit 15 14 13 12 11 10 9 Bit 8 0023 Register High TIMODH Pe PEE Reset 1 1 1 1 1 1 1 1 Read 0024 Timer 1 Counter Modulo tie Bit 7 6 5 4 3 2 1 Bit 0 Register Low TI MODL Reset 1 1 1 1 1 1 1 1 Timer 1 Channel 0 Status Read CHOF 0025 and Control Register Write 0
131. CK one for CPOL 0 and another for CPOL 1 The diagram may be interpreted as a master or slave timing diagram since the serial clock SPSCK master in slave MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 305 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI out MISO and master out slave in MOSI pins are directly connected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MISO output only when its slave select input SS is at logic 0 so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose l O not affecting the SPI See Mode Fault Error When CPHA 1 the master begins driving its MOSI pin on the first SPSCK edge Therefore the slave uses the first SPSCK edge as a start transmission signal The SS pin can remain low between transmissions This format may be preferable in systems having only one master and only one slave driving the MISO data line SPSCK CYCLE FOR REFERENCE SPSCK CPOL 0 T ITNA IN IN IN IN IN FN SPSCK CPOL 1 NA SA NA NA SA SAAN FROM MASTER MAR Mss y Bre B175 B174 B113 Y erra 6171 X
132. CR is described here Address 0003C Bit 7 6 5 4 3 2 1 Bit 0 Read COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCHO Write IDMAS Reset 0 0 0 1 1 1 1 1 Figure 5 2 ADC Status and Control Register ADSCR COCO IDMAS Conversions Complete Interrupt DMA Select Bit When the AIEN bit is a logic O the COCO IDMAS is a read only bit which is set each time a conversion is completed except in the continuous conversion mode where it is set after the first conversion This bit is cleared whenever the ADSCR is written or whenever the ADR is read If the AIEN bit is a logic 1 the COCO IDMAS is a read write bit which selects either CPU or DMA to service the ADC interrupt request Reset clears this bit 1 Conversion completed AIEN 0 DMA interrupt AIEN 1 0 Conversion not completed AIEN 0 CPU interrupt AIEN 1 CAUTION Because the MC68HC908GR8 does NOT have a DMA module the IDMAS bit should NEVER be set when AIEN is set Doing so will mask ADC interrupts and cause unwanted results MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Analog to Digital Converter ADC 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC NOTE Technical Data AIEN ADC Interrupt Enable Bit When this bit is set an interrupt is generated at the end of an ADC conversion The interrupt signal is cleared w
133. CS 1 if the VCO range select bits are all clear The PLL VCO range select register must be programmed correctly Incorrect programming can result in failure of the PLL to achieve lock MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 6 6 PLL Reference Divider Select Register NOTE PMDS may be called PRDS on other HC08 derivatives The PLL reference divider select register PMDS contains the programming information for the modulo reference divider Address 003B Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 RDS3 RDS2 RDS1 RDSO Write Reset 0 0 0 0 0 0 0 1 Unimplemented Figure 7 9 PLL Reference Divider Select Register PMDS RDS3 RDS0 Reference Divider Select Bits These read write bits control the modulo reference divider that selects the reference division factor R See PLL Circuits and Programming the PLL RDS7 RDSO cannot be written when the PLLON bit in the PCTL is set A value of 00 in the reference divider select register configures the reference divider the same as a value of 01 See Special Programming Exceptions Reset initializes the register to 01 for a default divide value of 1 NOTE The reference divider select bits have built in protection such that they cannot be written when the PLL is on
134. CS2 e SCl data register SCDR e SCl baud rate register SCBR 18 9 1 SCI Control Register 1 SCI control register 1 e Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method e Controls idle character detection e Enables parity function Controls parity type Technical Data MC68HC908GR8 Rev 4 0 252 Serial Communications Interface SCI For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Serial Communications Interface SCI O Registers Address 0013 Bit 7 6 5 4 3 2 1 Bit 0 Read LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write Reset 0 0 0 0 0 0 0 0 Figure 18 9 SCI Control Register 1 SCC1 LOOPS Loop Mode Select Bit This read write bit enables loop mode operation In loop mode the PE1 RxD pin is disconnected from the SCI and the transmitter output goes into the receiver input Both the transmitter and the receiver must be enabled to use loop mode Reset clears the LOOPS bit 1 Loop mode enabled 0 Normal operation enabled ENSCI Enable SCI Bit This read write bit enables the SCI and the SCI baud rate generator Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts Reset clears the ENSCI bit 1 SCI enabled 0 SCI disabled TXINV Transmit Inversion Bit
135. Clock Generator Module CGMC CGMC Registers 1 VCO frequency correct or locked 0 VCO frequency incorrect or unlocked ACQ Acquisition Mode Bit When the AUTO bit is set ACQ is a read only bit that indicates whether the PLL is in acquisition mode or tracking mode When the AUTO bit is clear ACQ is a read write bit that controls whether the PLL is in acquisition or tracking mode In automatic bandwidth control mode AUTO 1 the last written value from manual operation is stored in a temporary location and is recovered when manual operation resumes Reset clears this bit enabling acquisition mode 1 Tracking mode 0 Acquisition mode 7 6 3 PLL Multiplier Select Register High The PLL multiplier select register high PMSH contains the programming information for the high byte of the modulo feedback divider Address 0038 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 MUL11 MUL10 MUL9 MUL8 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 7 6 PLL Multiplier Select Register High PMSH MUL11 MUL8 Multiplier Select Bits These read write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N See PLL Circuits and Programming the PLL A value of 0000 in the multiplier select registers configures the modulo feedback divider the same as a value of 0001 Reset initializes the registers to 0040 for a default multiply value o
136. Conventions iaces x m R04 e Re 299 vixi f hAKAWAGNALEENGHEEA DAANAN KAG 314 SELL NOON S ka oe e ded KB BAEK E PAR LA 321 SPI Master Baud Rate Selection 327 Timebase Rate Selection for OSC1 32 768 kHz 341 Pin Name Conventions ssa d GB KAKA CR OX REOR RC RR e 336 Prescaler Selection iu raa acea evaded Kec exe cadsienwn cow s 351 Mode Edge and Level Selection 358 Absolute Maximum Ratings llllslsuss 362 Functional Operation Range a 363 Thermal Characteristics occ aa ka se hex rra mam anes 363 5 0V DC Electrical Characteristics 364 3 0 V DC Electrical Characteristics 366 5 0 V Control TIMIN uua dx Rex RARE qe tees HALIKA 368 sapakin BU au dde de do a ORE RC RA edd dod 369 Timer Interface Module Characteristics 383 CGM Component Specifications 383 MC Order PINES au 6b iid PG diario bode ob bed ee 392 Development Tool Kits aaa saa mam sh a Re rens 393 Development Tool Components 393 MC68HC908GR8 Rev 4 0 18 List of Tables MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Figure Title 1 31 MCU Block Diagram 1 2 QFP Pin Assignments cuis sax o RR Rd 1 3 DIP And SOIC Pin Assignments 1 4 Power Supply Bypass
137. D 10 o2 E PTAO L Vbpo 10 ka Hang PTBO PTB1 10 ka S Notes 1 SW2 SW3 and SW4 Position C Enter monitor mode using external oscillator SW2 SW3 and SWA4 Position D Enter monitor mode using external XTAL and internal PLL 2 See Monitor Mode Signal Requirements and Options for IRQ voltage level requirements Figure 15 1 Monitor Mode Circuit MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 191 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON The monitor code has been updated from previous versions to allow enabling the PLL to generate the internal clock provided the reset vector is blank when the device is being clocked by a low frequency crystal This addition which is enabled when IRQ is held low out of rest is intended to support serial communication programming at 9600 baud in monitor mode by stepping up the external frequency assumed to be 32 768 kHz by a fixed amount to generate the desired internal frequency 2 4576 MHz Since this feature is enabled only when IRQ is held low out of reset it cannot be used when the reset vector is not blank because entry into monitor mode in this case requires Vst on IRQ 15 4 1 Entering Monitor Mode Technical Data Table 15 1 shows the pin conditions for entering monitor mode As specified in the table monitor mode may be entered after a power on reset POR and will a
138. DETECT LOGIC Figure 12 1 IRQ Module Block Diagram Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 IRQF 0 mase iidne IRQ Status and Control Sip Register INTSCR We ACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 2 IRQ I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA External Interrupt IRQ 169 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 12 5 IRQ1 Pin Technical Data A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch A vector fetch software clear or reset clears the IRQ latch If the MODE bit is set the IRQ1 pin is both falling edge sensitive and low level sensitive With MODE set both of the following actions must occur to clear IRQ e Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the latch Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register INTSCR The ACK bit is useful in applications that poll the IRQ1 pin and require software to clear the IRQ latch Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACK does not affect subsequent transitions on the IRQ1 pin A falling edge that occurs after writing to the ACK bit another interrupt request If the IRQ mask bit
139. Data Register 0000 PTA Write Reset Unaffected by reset Read 0 0 PTB5 PTB4 PTB3 PTB2 PTB1 PTBO 0001 Port B Data Register Write PTB Reset Unaffected by reset Read 0 0 0 0 0 0 Port C Data Register PTC1 PTCO S0002 PTC Write Reset Unaffected by reset Read 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTDO 0003 Port D Data Register Write PTD Reset Unaffected by reset Read 0 0 0 0 acti DDRA3 DDRA2 DDRA1 DDRAO Data Direction Register A 0004 DDRA Write Reset 0 0 0 0 0 0 0 0 Read 0 0 acti DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO Data Direction Register B 0005 DDRB Write Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 Data Direction Register C DDRC1 DDRCO 0006 DDRC Write Reset 0 0 0 0 0 0 0 0 Read 0 gogo Data Direction RegisterD Write DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO DDRD Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 1 I O Port Register Summary Technical Data MC68HC908GR8 Rev 4 0 206 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Addr Register Name Read Port E Data Register 0008 PTE Reset Read Data Direction Register E 000C DDRE Reset Read Port A Input Pullup Enable S000D meister PTAPUE Reset Read Port C Input Pullup Enable 000E Register PTCPUE Reset Read Port D Input Pullup
140. E 8 POSSIBLE START POINTS TO SPDR BUS CLOCK EARLIEST SPSCK INTERNAL CLOCK 32 LATEST WRITE 32 POSSIBLE START POINTS TO SPDR BUS CLOCK EARLIEST SPSCK INTERNAL CLOCK 128 LATEST 128 POSSIBLE START POINTS Figure 20 7 Transmission Start Delay Master Technical Data MC68HC908GR8 Rev 4 0 308 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Queuing Transmission Data 20 7 Queuing Transmission Data The double buffered transmit data register allows a data byte to be queued and transmitted For an SPI configured as a master a queued data byte is transmitted immediately after the previous transmission has completed The SPI transmitter empty flag SPTE indicates when the transmit data buffer is ready to accept new data Write to the transmit data register only when the SPTE bit is high Figure 20 8 shows the timing associated with doing back to back transmissions with the SPI SPSCK has CPHA CPOL 1 0 WRITE TO SPDR D 1 GJ Y SPTE SPSCK CPHA CPOL 1 0 MOSI NSB BIT BIT BIT BIT BIT BIT LSBIMSB BIT BIT BIT BIT BIT BIT SB MSB BIT BIT BIT 815 418 211 6 51413 2 1 61514 BYTE 1 BYTE2 BYTE3 SPRF READ SPSCR DN READ SPDR DIN 1 D CPU WRITES BYTE 1 TO SPDR CLEARING SPTE BIT D CPU READS SPDR CLEARING SPRF BIT BYTE 1 TRANSFERS FROM TRANS
141. E bit and before asserting the HVEN bit When the FLBPR is programmed with all Os the entire memory is protected from being programmed and erased When all the bits are erased all 1s the entire memory is accessible for program and erase When bits within the FLBPR are programmed they lock a block of memory with address ranges as shown in FLASH Block Protect Register Once the FLBPR is programmed with a value other than SFF any erase or program of the FLBPR or the protected block of FLASH memory is prohibited The FLBPR itself can be erased or programmed only with an external voltage Ver present on the IRQ pin This voltage also allows entry from reset into the monitor mode MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Flash Memory 163 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory Set PGM bit Algorithm for programming a row 32 bytes of FLASH memory Y Read the FLASH block protect register Y Write any data to any FLASH address within the row address range desired Y Wait for a time thy Y Set HVEN bit Y Wait for a time togs oa A Y Write data to the FLASH address to be programmed Y Wait for a time tprog Completed programming this row Y NOTE 10 Clear PGM bit The time between each FLASH address change step 7 to step 7 or Y
142. FE bit enabled 0 SCI error CPU interrupt requests from FE bit disabled MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 259 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI PEIE Receiver Parity Error Interrupt Enable Bit This read write bit enables SCI receiver CPU interrupt requests generated by the parity error bit PE See SCI Status Register 1 Reset clears PEIE 1 SCI error CPU interrupt requests from PE bit enabled 0 SCI error CPU interrupt requests from PE bit disabled 18 9 4 SCI Status Register 1 SCI status register 1 SCS1 contains flags to signal these conditions Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error e Parity error Address 0016 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTE TC SCRF IDLE OR NF FE PE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 18 12 SCI Status Register 1 SCS1 SCTE SCI Transmitter Empty Bit This clearable read only bit is set when the SCDR transfers a character to the transmit shift register SCTE can generate an SCI transmitter CPU interrupt request When the SCTIE bit in SCC2 is set SCTE generates an SCI transmitter CPU interrupt req
143. FLASH address programmed to clearing PGM bit must not exceed the maximum programming time tpnoc max This program sequence is repeated throughout the memory until all data is programmed Technical Data MC68HC908GR8 Rev 4 0 162 Flash Memory MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc Flash Memory FLASH Block Protection Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order shown other unrelated operations may occur between the steps Do not exceed tpgoc maximum See Memory Characteristics 11 8 FLASH Block Protection NOTE Due to the ability of the on board charge pump to erase and program the FLASH memory in the target application provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction This protection is done by using of a FLASH Block Protect Register FLBPR The FLBPR determines the range of the FLASH memory which is to be protected The range of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory FFFF When the memory is protected the HVEN bit cannot be set in either ERASE or PROGRAM operations In performing a program or erase operation the FLASH block protect register must be read after setting the PGM or ERAS
144. Freescale Semiconductor Inc Break Module BRK 6 4 Functional Description When the internal address bus matches the value written in the break address registers the break module issues a breakpoint signal to the CPU The CPU then loads the instruction register with a software interrupt instruction SWI after completion of the current CPU instruction The program counter vectors to SFFFC and SFFFD FEFC and SFEFD in monitor mode The following events can cause a break interrupt to occur ACPU generated address the address in the program counter matches the contents of the break address registers Software writes a logic 1 to the BRKA bit in the break status and control register When a CPU generated address matches the contents of the break address registers the break interrupt begins after the CPU completes its current instruction A return from interrupt instruction RTI in the break routine ends the break interrupt and returns the MCU to normal operation Figure 6 1 shows the structure of the break module IAB15 IAB8 BREAK ADDRESS REGISTER HIGH 8 BIT COMPARATOR 8 BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB15 IABO CONTROL BREAK IAB7 IABO Figure 6 1 Break Module Block Diagram Technical Data MC68HC908GR8 Rev 4 0 92 Break Module BRK MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Functio
145. Freescale Semiconductor Inc Clock Generator Module CGMC Acquisition Lock Time Specifications 7 9 3 Choosing a Filter MC68HC908GR8 Rev 4 0 As described in Parametric Influences on Reaction Time the external filter network is critical to the stability and reaction time of the PLL The PLL is also dependent on reference frequency and supply voltage Either of the filter networks in Figure 7 10 is recommended when using a 32 768 kHz reference crystal In low cost applications where stability and reaction time of the PLL is not critical this filter network can be replaced by a single capacitor CGMXFC Vssa Figure 7 10 PLL Filter Technical Data MOTOROLA Clock Generator Module CGMC 127 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Technical Data MC68HC908GR8 Rev 4 0 128 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 8 1 Contents 8 2 Introduction Section 8 Configuration Register CONFIG EX NUN i do Ri ER eae eer ER or RR CE OR CR 129 8 3 Functional Description oaa ecd care RR RR Ran ce o een 129 This section describes the configuration registers CONFIG1 and CONFIG2 The configuration registers enable or disable these options e Stop mode recovery time 32 CGMXCLK cycles or
146. G retu saaana a a uS Did id dd 189 Functional Description cee eee eee 190 co jo MIC NAB Ake HELEN NPA SLA GA 202 Section 16 Input Output Ports I O dg IMPIDE 205 nii c AA AAP AP 205 PO AA AP AA AY 209 AA AA dade x as dU Qs 6 dea 3 aca d 213 FOE Saan AA PAANAN ERR AA donde 4k AM 216 POK AKAPAD AHA BAKA KAADANGKALNHE BAGA EA KI 220 MC68HC908GR8 Rev 4 0 12 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 15 SINS os en RA he KABAGAL KAMA NG GAWA BALA LA BABA 229 IE MUG ears dta 4t era CARCER I Re dE Edo son NG AA 229 17 3 F ncglons Description uoossszssuaeancbebRERSULSA ERE ARRA 229 Section 18 Serial Communications Interface SCI Pel COMGE AA AA E aDlIqRuE 231 15 2 Introduction APA 231 lgo AA AA AA AA ees 232 18 4 Pin Name Conventions liliis 233 18 5 Functional Description 2s 20scicrcieseasceeseeesdaciwe 233 18 6 Low Power Modes nananana 250 18 7 SCI During Break Module Interrupts 251 18 8 VO Signals aaa cb dicecdceataseeenesbdunnacees 251 189 FORES AA AA AT 252 Section 19 System Integration Module SIM 19 1 LOB Se ee KAG GT se REV En did udi KIT di ands 271 192 WOOO ews dia dris aea esa d RS Rb dO Ls ip aae d 271 19 3 SIM Bus Clock Control and Generation 275 19 4 Reset and System Initialization 276 195 SIM
147. GMXCLK CGMOUT RST IAB Freescale Semiconductor Inc System Integration Module SIM Reset and System Initialization The internal reset signal is asserted The SIM enables CGMOUT e Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator The RST pin is driven low during the oscillator stabilization time The POR bit of the SIM reset status register SRSR is set and all other bits in the register are cleared Sie CA 08 P NE E y FFFE j FFFF PER 3 Figure 19 7 POR Recovery 19 4 2 2 Computer Operating Properly COP Reset An input to the SIM is reserved for the COP reset signal The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register SRSR The SIM actively pulls down the RST pin for all internal reset sources To prevent a COP module timeout write any value to location FFFF Writing to location FFFF clears the COP counter and bits 12 through 4 of the SIM counter The SIM counter output which occurs at least every 213 24 CGMXCLK cycles drives the COP counter The COP should be serviced as soon as possible out of reset to guarantee
148. GT opr Cnn E Than Signed pc PC 2 rel Z N V 0 REL 92 m l3 BHCC rel Branch if Half Carry Bit Clear PC PC 2 rel H 20 i REL 28 jrr 3 BHCS rel Branch if Half Carry Bit Set PC PC 2 rel H 1 Eee REL 29 jrr 3 BHI rel Branch if Higher PC e PC 2 rel C 2 0 REL 22 m 3 BHS rel udi as BEC or Same PC PC 2 rel C 0 lt 2 TREES 24 r 13 BIH rel Branch if IRQ Pin High PC PC 2 rel IRQ 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC PC 2 rel IRQ 0 REL 2E frr 3 BIT opr IMM A5 lii 2 BIT opr DIR B5 dd 3 BIT opr EXT C5 hhll 4 BIT opr X Jha IX2 DS jeeff 4 BIT oprX Bit Test A amp M 7x E5 f 3 BIT X IX F5 2 BIT opr SP SP1 9EE5 ff 4 BIT opr SP SP2 9ED5 ee ff 5 BLE opr eod Ope ander or Equal To PG e PC 2 rel Z NO V 1 REL 93 r 3 BLO rel Branch if Lower Same as BCS PC PC 2 rel C 2 1 Shae Eza REL 25 rr 3 BLS rel Branch if Lower or Same PC PC 2 rel C 2 2 1 Ee REL 23 jrr 3 BLT opr Branch if Less Than Signed Operands PC c PC 2 rel N O V 1 REL 91 Irr 3 BMC rel Branch if Interrupt Mask Clear PC PC 2 rel I 20 ma Ka ka aa REL 2C rr 3 BMI rel Branch if Minus PC PC 2 rel N 1 Slee REL 2B ir 3 BMS rel Branch if Interrupt Mask Set PC PO 2 rel 1 2 1 a Shae REL 2D jr 3 Technical Data MC68HC908GR8 Rev 4 0 1
149. Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 9 Computer Operating Properly COP 9 1 Contents 9 2 Introduction mr MINORUM onde 66 bs PA KG KAG KAKA ee th ae 93 Functional Description saaa Rx 94 OT rcrum 95 COP Control Register a na mmm RREERERERA 96 WCU AA AA ER OR de ede 9 7 Monitor Mode a e te coisa d re ER EAR ee RR dene 9 8 Low Power Modes L sususs 9 9 COP Module During Break Mode The computer operating properly COP module contains a free running counter that generates a reset if allowed to overflow The COP module helps software recover from runaway code Prevent a COP reset by clearing the COP counter periodically The COP module can be disabled through the COPD bit in the CONFIG register 9 3 Functional Description Figure 9 1 shows the structure of the COP module MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Computer Operating Properly COP For More Information On This Product Go to www freescale com 133 Freescale Semiconductor Inc Computer Operating Properly COP STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPEN FROM SIM COP DISABLE FROM CONFIG RESET COPCTL WRITE COP RATE SEL e FROM CONFIG Technical Data CGMXCLK D 12 BIT COP PRESCALER RESET CIRCUIT COPCTL WRITE NOTE RESET STATUS REGISTER CLEAR ALL STAGES LEAR STAGES 5 12
150. ILOP Illegal Opcode Reset Bit 1 Last reset caused by an illegal opcode 0 POR or read of SRSR ILAD Illegal Address Reset Bit 1 Last reset caused by an opcode fetch from an illegal address 0 POR or read of SRSR LVI Low Voltage Inhibit Reset Bit 1 Last reset caused by low power supply voltage 0 POR or read of SRSR 4 4 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event An interrupt does not stop the operation of the instruction being executed but begins when the current instruction completes its operation 4 4 1 Effects An interrupt e Saves the CPU registers on the stack At the end of the interrupt the RTI instruction recovers the CPU registers from the stack so that normal processing can resume Sets the interrupt mask bit to prevent additional interrupts Once an interrupt is latched no other interrupt can take precedence regardless of its priority Loads the program counter with a user defined vector address Technical Data MC68HC908GR8 Rev 4 0 66 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Interrupts 5 CONDITION CODE REGISTER fo 0000 9 UNSTACKING ORDER a A U N 00FF DEFAULT ADDRESS ON RESET High byte of index register is not stacked Figure 4 4 Interrupt Stacking Order After every i
151. IMASK is clear the CPU loads the program counter with the vector address at locations SFFFA and FFFB Return of the IRQ1 pin to logic 1 As long as the IRQ1 pin is at logic O IRQ remains active The vector fetch or software clear and the return of the IRQ1 pin to logic 1 may occur in any order The interrupt request remains pending as long as the IRQ1 pin is at logic 0 A reset will clear the latch and the MODE control bit thereby clearing the interrupt even if the pin stays low If the MODE bit is clear the IRQ1 pin is falling edge sensitive only With MODE clear a vector fetch or software clear immediately clears the IRQ latch MC68HC908GR8 Rev 4 0 170 External Interrupt IRQ MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc External Interrupt IRQ IRQ Module During Break Interrupts The IRQF bit in the INTSCR register can be used to check for pending interrupts The IRQF bit is not affected by the IMASK bit which makes it useful in applications where polling is preferred Use the BIH or BIL instruction to read the logic level on the IRQ1 pin When using the level sensitive interrupt trigger avoid false interrupts by masking interrupt requests in the interrupt routine 12 6 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register SBFCR enables software to clear the latch during the break state See
152. IRQ latch ACK always reads as logic 0 Reset clears ACK IMASK IRQ Interrupt Mask Bit Writing a logic 1 to this read write bit disables IRQ interrupt requests Reset clears IMASK 1 IRQ interrupt requests disabled 0 IRQ interrupt requests enabled Technical Data MC68HC908GR8 Rev 4 0 172 External Interrupt IRQ MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ IRQ Status and Control Register MODE IRQ Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ1 pin Reset clears MODE 1 IRQ1 interrupt requests on falling edges and low levels 0 IRQ1 interrupt requests on falling edges only MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA External Interrupt IRQ 173 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ Technical Data MC68HC908GR8 Rev 4 0 174 External Interrupt IRQ MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 13 1 Contents 13 2 Introduction 13 3 Features 13 2 13 3 13 4 13 5 13 6 13 7 13 8 Section 13 Keyboard Interrupt KBI Laga he KG ere od dopo ep ew oe die de dob AA 175 E 05 e KK KAPA T TOTO DT TT TIT ee 175 Functional Description uuu iere e Sac d Rr e EORR RR 17
153. If monitor mode was entered with Vpp on IRQ then the divide by ratio is also set at 1024 If monitor mode was entered with Ves on IRQ then the internal PLL steps up the external frequency presumed to be 32 768 kHz to 2 4576 MHz These latter two conditions for monitor mode entry require that the reset vector is blank Table 15 3 lists external frequencies required to achieve a standard baud rate of 9600 BPS Other standard baud rates can be accomplished using proportionally higher or lower frequency generators If using a crystal as the clock source be aware of the upper frequency limit that the internal clock module can handle See 5 0 V Control Timing and 3 0 V Control Timing for this limit Table 15 3 Monitor Baud Rate Selection External IRA Internal Baud Rate Frequency Frequency BPS 9 8304 MHz Vist 2 4576 MHz 9600 9 8304 MHz Vpp 2 4576 MHz 9600 32 768 kHz Vss 2 4576 MHz 9600 The monitor ROM firmware uses these commands e READ read memory WRITE write memory e TREAD indexed read e WRITE indexed write e READSP read stack pointer e RUN run user program MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 197 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON The monitor ROM firmware echoes each received byte back to the PTAO pin for error checking An 11 bit delay at the end of each co
154. KF RPF ha N Lu Em B ua M Epi WAKE eg wn 5 um WAKEUP gall ange ES ILTY ros 5 E r zi 5 REE PEN PARITY gt R8 eE zy CHECKING E5R IDLE i ILIE NG DMARE SCRF SCRIE SENE DMARE SCRF SCRIE DMARE URP OR ead ORIE ORIE NF T RA NEIE EE mc FE FE je FEIE Bara PE PE ha BEE PEIE Figure 18 5 SCI Receiver Block Diagram Technical Data MC68HC908GR8 Rev 4 0 242 Serial Communications Interface SCI For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description 18 5 3 3 Data Sampling The receiver samples the PE1 RxD pin at the RT clock rate The RT clock is an internal signal with a frequency 16 times the baud rate To adjust for baud rate mismatch the RT clock is resynchronized at the following times see Figure 18 6 After every start bit After the receiver detects a data bit change from logic 1 to logic 0 after the majority of data bit samples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic O To locate the start bit data recovery logic does an asynchronous search for a logic O preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 kag START BIT ma LSB PE1 RxD tftt tt ttt START BIT START BIT DATA SAM
155. M MON Table 15 2 summarizes the differences between user mode and monitor mode Table 15 2 Mode Differences Functions Modes Reset Reset Break Break SWI SWI Vector Vector Vector Vector Vector Vector High Low High Low High Low User SFFFE SFFFF SFFFC SFFFD SFFFC SFFFD Monitor SFEFE FEFF FEFC FEFD FEFC SFEFD 15 4 2 Data Format Communication with the monitor ROM is in standard non return to zero NRZ mark space data format Transmit and receive baud rates must be identical NEXT Bit erro B1 BiT2 YBrs y era ers BIT 6 Br 7 STOP Bir NON Figure 15 3 Monitor Data Format 15 4 3 Break Signal A start bit logic 0 followed by nine logic O bits is a break signal When the monitor receives a break signal it drives the PTAO pin high for the duration of two bits and then echoes back the break signal MISSING STOP BIT pp 4 r 2 STOP BIT DELAY BEFORE ZERO ECHO A TEE KO KI teks KA Ko KENT V V Kok K2 3 KA KS KENT Figure 15 4 Break Transaction Technical Data MC68HC908GR8 Rev 4 0 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com 196 15 4 4 Baud Rate 15 4 5 Commands Freescale Semiconductor Inc Monitor ROM MON Functional Description The communication baud rate is controlled by the crystal frequency upon entry into monitor mode The divide by ratio is 1024
156. MCU may enter two low power modes wait mode and stop mode They are common to all HC08 MCUs and are entered through instruction execution This section describes how each module acts in the low power modes MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Power Modes 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes 3 2 1 Wait Mode 3 2 2 Stop Mode The WAIT instruction puts the MCU in a low power standby mode in which the CPU clock is disabled but the bus clock continues to run Power consumption can be further reduced by disabling the LVI module and or the timebase module through bits in the CONFIG register See Configuration Register CONFIG Stop mode is entered when a STOP instruction is executed The CPU clock is disabled and the bus clock is disabled if the OSCSTOPENB bit in the CONFIG register is at a logic 0 See Configuration Register CONFIG 3 3 Analog to Digital Converter ADC 3 3 1 Wait Mode 3 3 2 Stop Mode Technical Data The ADC continues normal operation during wait mode Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting ADCH4 ADCHO bits in the ADC status and control register before executing the WAIT instruction The ADC module is inactive after the execution of a STOP instruction Any pendi
157. MIT DATA CPU WRITES BYTE 3 TO SPDR QUEUEING BYTE REGISTER TO SHIFT REGISTER SETTING SPTE BIT 3 AND CLEARING SPTE BIT 8 SECOND INCOMING BYTE TRANSFERS FROM SHIFT D AA QUEUEING BYTES REGISTER TO RECEIVE DATA REGISTER SETTING SPRF BIT 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO RECEIVE DATA REGISTER SETTING REGISTER TO SHIFT REGISTER SETTING SPTE BIT SPRF BIT 0 CPU READS SPSCR WITH SPRF BIT SET 8 BYTE 2 TRANSFERS FROM TRANSMIT DATA 2 CPU READS SPDR CLEARING SPRF BIT REGISTER TO SHIFT REGISTER SETTING SPTE BIT 6 CPU READS SPSCR WITH SPRF BIT SET Figure 20 8 SPRF SPTE CPU Interrupt Timing The transmit data buffer allows back to back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer Also if no new data is written to the data buffer the last value contained in the shift register is the next data word to be transmitted MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 309 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI For an idle master or idle slave that has no data loaded into its transmit buffer the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register This allows the user to queue up a 16 bit value to send For
158. O Register Addresses 298 20 5 Functional Description oua ka xAR RE RE EE drach 299 20 6 Transmission Formats a KA ada dsc sed Er ce we 303 20 7 Queuing Transmission Data a 309 20 8 Eror LOUER s cud dod EROR e dO OR Capi p eos 310 20 9 1000300 010004 12 0222 2 07171 177 1501001 2 eke ees 314 20 10 Resetting the SPI nn 2 2264 ce NAKA RR RR mms 316 20 11 Low Power Modes 4 42014 cieeeeeteecdeerescieieoes 317 20 12 SPI During Break Interrupts 002200 eee 318 20 13 VO mer T cT 318 20 14 I O Registers 0 0000 eee 322 20 2 Introduction This section describes the serial peripheral interface SPI module which allows full duplex synchronous serial communications with peripheral devices MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 297 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 3 Features Features of the SPI module include e Full duplex operation e Master and slave modes e Double buffered operation with separate transmit and receive registers e Four master mode frequencies maximum bus frequency 2 e Maximum slave mode frequency bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts SPRF SPI receiver full SPTE SPI transmitter empty Mode fault error flag with CPU interrupt capability
159. O controls and monitors the buffered PWM function and TIM channel 1 status and control register TSC1 is unused While the MSOB bit is set the channel 1 pin TCH1 is available as a general purpose l O pin In buffered PWM signal generation do not write new pulse width values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered PWM signals 22 5 9 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals use the following initialization procedure 1 In the TIM status and control register TSC a Stop the TIM counter by setting the TIM stop bit TSTOP b Resetthe TIM counter and prescaler by setting the TIM reset bit TRST 2 Inthe TIM counter modulo registers TMODH TMODL write the value for the required PWM period 3 Inthe TIM channel x registers TCHxH TCHXxL write the value for the required pulse width 4 In TIM channel x status and control register TSCx MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 345 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM NOTE 22 6 Interrupts Technical Data a Write 0 1 for unbuffered output compare or PWM signals or 1 0 for buffered out
160. OUT bit Table 14 1 LVIOUT Bit Indication Vpp LVIOUT Vpp gt VTRIPR 0 Vpp lt VTRIPF 1 VIRIPF Vpp lt VTRIPR Previous value MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Voltage Inhibit LVI 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI 14 6 LVI Interrupts The LVI module does not generate interrupt requests 14 7 Low Power Modes The STOP and WAIT instructions put the MCU in low power consumption standby modes 14 7 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the L VI module can generate a reset and bring the MCU out of wait mode 14 7 2 Stop Mode If enabled in stop mode LVISTOP set the LVI module remains active in stop mode If enabled to generate resets the L VI module can generate a reset and bring the MCU out of stop mode Technical Data MC68HC908GR8 Rev 4 0 188 Low Voltage Inhibit LVI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 15 1 Contents 15 2 Introduction 15 3 Features 15 2 15 3 15 4 15 5 Section 15 Monitor ROM MON BUTS co oie dod doe ACE OR AA 189 ES I ETLTTItT TO OTT AA T TT Io 189 Functional Description 74 irr re Sa d Rr Rare RN 190 ON td ee bp ied eee NA T T T TT S 202 This section descri
161. Overflow error flag with CPU interrupt capability Programmable wired OR mode 2C inter integrated circuit compatibility O input output port bit s software configurable with pullup device s if configured as input port bit s 20 4 Pin Name Conventions and I O Register Addresses The text that follows describes the SPI The SPI I O pin names are SS slave select SPSCK SPI serial clock CGND clock ground MOSI master out slave in and MISO master in slave out The SPI shares four I O pins with four parallel I O ports Technical Data MC68HC908GR8 Rev 4 0 298 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Functional Description The full names of the SPI I O pins are shown in Table 20 1 The generic pin names appear in the text that follows Table 20 1 Pin Name Conventions SPI Generic MISO MOSI SS SPSCK CGND Pin Names Full SPI PTD2 ATD1 PTDO AT Pi Neves SPI PTDI ATDO PTD3 ATD11 Veg 20 5 Functional Description Figure 20 1 summarizes the SPI I O registers and Figure 20 2 shows the structure of the SPI module Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read DMAS cO i So a A SPRIE SPMSTR POL PHA PWOM PE PTIE 0010 SPI Control Register Write SPCR Reset 0 0 1
162. P Figure 1 3 DIP And SOIC Pin Assignments 1 6 Pin Functions Descriptions of the pin functions are provided here 1 6 1 Power Supply Pins Vpp and Vss Vpp and Vgs are the power supply and ground pins The MCU operates from a single power supply Fast signal transitions on MCU pins place high short duration current demands on the power supply To prevent noise problems take special care to provide power supply bypassing at the MCU as Figure 1 4 shows Place the C1 bypass capacitor as close to the MCU as possible Use a high frequency response ceramic capacitor for C1 C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA General Description 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Vpp NOTE Component values shown represent typical applications Figure 1 4 Power Supply Bypassing 1 6 2 Oscillator Pins OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on chip oscillator circuit See Clock Generator Module CGMC 1 6 3 External Reset Pin RST A logic O on the RST pin forces the MCU to a known startup state RST is bidirectional allowing a reset of the entire system Itis driven low when any internal reset source is asserted This pin contains an internal pullup resistor that is a
163. PAKA Aa Ud Rap EEEREN Oa p ui 137 Low Power Modes npa RR ORC RR nes eae da 137 COP Module During Break Mode 137 Section 10 Central Processing Unit CPU oic APAPAP ee ee ee on 139 BOON ssr esama 3 der decade Emend ba bodes 139 PARO KARANGALANG LK AADABENTEEGNH SAL cick ceewet 139 CPU registers ee 140 Arithmeticfogic unit ALU 0 Naa ma nkaka erm 145 Low power modes ellen 145 CPU during break InlelrUplS cocoaocecese rere crea dd 146 Instruction Set Summary 0c eee eee eee 147 peod Musae Bbdesdasirbhes CKieRtbeecmreructeRs 154 MC68HC908GR8 Rev 4 0 10 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 13 1 132 13 3 13 4 13 5 MC68HC908GR8 Rev 4 0 Table of Contents Section 11 Flash Memory sog O TTTT 157 Libet 2 RESTITIT I SIT T T ee 1 fo cil ol D 157 F nctional DesorBlIell 4d a ici cha rrini ie aed 157 FLASH Control Register CREER CORO RR 159 FLASH Page Erase Operation 20 5 160 FLASH Mass Erase QOperation aa 161 FLASH Program Read Operation Llssss 162 FLASH Block Protecliblh su doo ede ed deere CODE KA 163 al Ce heed rrr 166 STOF LEE fies ce dd KIN BAKA EA OUR be reser cu bead 166 Section 12 External Interrupt IRQ ARAMA NAA are ere nn PP 167 Lire o UT eae T 167 PORN d Dae E
164. PLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK RTCLOCK rr rr rr rr STATE C amp amp C c c ctc URS Y VY VV YY Figure 18 6 Receiver Data Sampling E a a a a a T NO s O OMN EFEEEREEEE C C Cr Cr C C C RT8 RT RT RT RT RT RT RT RT RT1 RT2 RT3 RT4 To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Table 18 2 summarizes the results of the start bit verification samples MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 243 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Serial Communications Interface SCI Table 18 2 Start Bit Verification RT3 RT5 and RT7 Samples Haras Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 Start bit verification is not successful if any two of the three verification samples are logic 1s If start bit verification is not successful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 18 3 summarizes the results of the data
165. PLLIE i PLLON BCS PRE1 PREO VPR1 VPRO PLL Control Register 0036 PCTL Write Reset 0 0 1 0 0 0 0 0 Read T LOCK Wa 0 0 0 0 A PLL Bandwidth Control Mind Register PBWC e Reset 0 0 0 0 0 0 0 0 sd 0 i MUL11 MUL10 MULI MUL8 PLL Multiplier Select High a 30998 Register PMSH Wit Reset 0 0 0 0 0 0 0 0 ie MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MULO 0039 PLL Multiplier Select Low Write Register PMSL Reset 0 1 0 0 0 0 0 0 Figure 7 3 CGMC I O Register Summary Technical Data MC68HC908GR8 Rev 4 0 114 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC CGMC Registers Read VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO 003A PLL VCO Select Range Write Register PMRS Reset 0 1 0 0 0 0 0 0 ika i RDS3 RDS2 RDS1 RDSO PLL Reference Divider 0038 Select Register PMDS Mt Reset 0 0 0 0 0 0 0 1 Unimplemented R Reserved NOTES 1 When AUTO 0 PLLIE is forced clear and is read only 2 When AUTO 0 PLLF and LOCK read as clear 3 When AUTO 1 ACQ is read only 4 When PLLON 0 or VRS7 VRSO 0 BCS is forced clear and is read only 5 When PLLON 1 the PLL programming register is read only 6 When BCS 1 PLLON is forced set and is read only Figure 7 3 CGMC I O Register Summary 7 6 1 PLL Control Registe
166. PU READS BYTE 2 IN SPDR CLEARING SPRF BIT 4 BYTE 2 SETS SPRF BIT BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED BYTE 4 IS LOST Figure 20 9 Missed Read of Overflow Condition In this case an overflow can be missed easily Since no more SPRF interrupts can be generated until this OVRF is serviced it is not obvious that bytes are being lost as more transmissions are completed To prevent this either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit Figure 20 10 illustrates this process Generally to avoid this second SPSCR read enable the OVRF to the CPU by setting the ERRIE bit MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 311 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI BYTE 1 BYTE2 BYTE 3 BYTE 4 SPI RECEIVE COMPLETE o o o ju SPRF OVRF READ sr NOO NO NO we je e READ SPOR NO o NG We 1 BYTE 1 SETS SPRF BIT CPU READS BYTE 2 IN SPDR CLEARING SPRF BIT 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR 9 CPU READS SPSCR AGAIN 3 CPU READS BYTE 1 IN SPDR TS EPEe ODER CLEARING SPRE BIT CPU READS BYTE 2 SPDR CPU READS SPSCR AGAIN SEARING OVREB Lr TO CHECK OVRF BIT 11
167. PUE 16 17 Port E Data Register PTE 16 18 Data Direction Register E DDRE 16 19 Port E siio MM KAL EHE R AA 18 1 SCI Module Block Diagram 18 2 SCI I O Register Summary 183 SUI Da Formal io 22 diei cR ER PES 18 4 SCI Transmitter annaa p hah d Eum arde ee 18 5 SCI Receiver Block Diagram 18 6 Receiver Data Sampling 18 7 Slow CAE PME IBB FastDala AAP RO bee ey bo 8 eee ee ee ere 18 10 SCI Control Register 2 SCC2 18 11 SCI Control Register 3 SCC3 18 12 SCI Status Register 1 SCS1 18 13 Flag Clearing Sequence 18 14 SCI Status Register 2 SCS2 18 15 SCI Data Register SCDR 18 16 SCI Baud Rate Register SCBR 19 1 SIM Block Diagram xa ka KA KG KA 19 2 SIM I O Register Summary 18 9 SCI Control Register 1 MC68HC908GR8 Rev 4 0 List of Figures Technical Data MOTOROLA List of Figures For More Information On This Product Go to www freescale com 21 Freescale Semiconductor Inc List of Figures Technical Data 19 3 COM Clock SB APP E AA 275 19 4 External Reset Timing ps na sa se KA KR KEAN AKA KA KA AKA 277 19 5 Internal Reset Timing L04 caasa herr RR xn 278 19 6 Sources of Internal Reset AA 278 19 7 POT ca KA ER AERE RE ORC OR AKA me CR AK 279
168. RF When OVRF Interrupt Is Not Enabled 312 20 11 SPI Interrupt Request Generation 315 2045 CPHAISS Timing osouuszoceorez2ep kerzdda ee ra di 320 20 13 SPI Control Register SPCR a 322 20 14 SPI Status and Control Register SPSCR 325 20 15 SPI Data Register SPDR cocoa rr Rt RS 328 21 1 Timebase Block Diagram 00 0200000 ee 330 21 2 Timebase Control Register TBCR 331 Er TIM Blook Diagram APA PAA 338 MC68HC908GR8 Rev 4 0 22 List of Figures MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures 22 2 TIM I O Register Summary AK KAG KAG BREAK Rua hes 339 22 3 PWM Period and Pulse Width 343 22 4 TIM Status and Control Register TSC 349 22 5 TIM Counter Registers High TCNTH 352 22 6 TIM Counter Registers Low TCNTL 352 22 7 TIM Counter Modulo Register High TMODH 353 22 8 TIM Counter Modulo Register Low TMODL 353 22 9 TIM Counter Register High TCNTH 354 22 10 TIM Counter Register Low TCNTL 354 22 11 TIM Channel 0 Status and Control Register TSCO 355 22 12 TIM Channel 1 Status and Control Register TSC1 355 22 13 CHXMAX Laltahoy cueuacecunsukAuRu RR Eur n Rn Eun 359 22 14 TIM Channel O Regist
169. ROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Transmission Formats SPSCK CYCLE FOR REFERENCE SPSCK CPOL 0 SPSCK CPOL 1 Lh VA VE VUE Ld NV V FRoM MAE MINA MSB y Bre y Brrs 8114 y rra y Br jy err y cse WAN MISO AA FROM SLAVE MSB BITE Y BIT 5 Y BIT4 Y Biv Y BIT2 Y Bir 1 Y LSB is SS TO SLAVE CAPTURE STROBE A A A A A Figure 20 4 Transmission Format CPHA 0 MISOMOS Y BYTE 1 y BYTE 2 y BYTE 3 y MASTERSS e HETA T SLAVE SS T CPHA 1 Figure 20 5 CPHA SS Timing When CPHA 0 for a slave the falling edge of SS indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data Once the transmission begins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the falling edge of SS Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission 20 6 3 Transmission Format When CPHA 1 Figure 20 6 shows an SPI transmission in which CPHA is logic 1 The figure should not be used as a replacement for data sheet parametric information Two waveforms are shown for SPS
170. RRE E See ERG EG ERA 19 Section 1 General Description 25 Section 2 Memory Map eeeeese 35 Section 3 Low Power Modes 49 Section 4 Resets and Interrupts 61 Section 5 Analog to Digital Converter ADC 79 Section 6 Break Module BRK 91 Section 7 Clock Generator Module CGMC 99 Section 8 Configuration Register CONFIG 129 Section 9 Computer Operating Properly COP 133 Section 10 Central Processing Unit CPU 139 Section 11 Flash Memory 157 Section 12 External Interrupt IRQ 167 Section 13 Keyboard Interrupt KBI 175 Section 14 Low Voltage Inhibit LVI 183 Section 15 Monitor ROM MON 189 Section 16 Input Output Ports I O 205 MC68HC908GR8 Rev 4 0 Technical Data For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc List of Paragraphs Section 17 RAM cap a pA KAEN NAKAKA ULA DNA 229 Section 18 Serial Communications Interface SCI 231 Section 19 System Integration Module SIM 271 Section 20 Serial Peripheral Interface SPI 297 Section 21 Timebase Module TBM 329 Section 22 Timer Interface Module TIM 335 Section 23 Electrical Specifications 361 Se
171. RU 9 ad oe bk Eds kb ded qq NO ER 167 Functional Descriplio 24 404 sa sock dee dates OR e 168 ODA NGANGA epe AA 170 IRQ Module During Break Interrupts 171 IRQ Status and Control Register 172 Section 13 Keyboard Interrupt KBI AA ua acce Kama di kak raider Rub LEAK bha na salad 175 HIN asco KG BK IKA bONERSPAEQGE PEOSS E NAKA 175 FOU OE aka BG kB paaa m Ida pb had pa mabisa 175 F nctional Description sasa kaa kA R KING BG dccus roc PR 176 Keyboard Initialization llle 179 Technical Data MOTOROLA Table of Contents 11 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Table of Contents 13 6 13 7 13 8 14 1 14 2 14 3 14 4 14 5 14 6 14 7 15 1 15 2 15 3 15 4 15 5 16 1 16 2 16 3 16 4 16 5 16 6 Low Power Modes a aded op ae cde FER ROC OL e en 180 Keyboard Module During Break Interrupts 180 PUP Ga ua d dp doo Ordered doll d ao bee doo orb d 181 Section 14 Low Voltage Inhibit LVI GIES AA PAA AA APP 183 NI iro PRIME PA DALA EK KYA UNAWAAN PONE 183 AA AA 183 Functional Description uiua use uk Rad e ded nana ERR caus 184 LOT Stats FOGG ceuacaassinabasue p AKA LUKAB AGA SANG 187 LIPAD MCCC 188 Low Power MOIS nc ca LG BK NGANGA AHAB EEe CET ET 188 Section 15 Monitor ROM MON Pu APAN AA AA 189 Mr DOUCEOIL aue den dX oed ex dd Rr m eme ed maa malag 189 EOD PA
172. Resets the TIM counter e Prescales the TIM counter clock Address T1SC 0020 and T2SC 002B Bit 7 6 5 4 3 2 1 Bit 0 Read TOF 0 0 TOIE TSTOP PS2 PS1 PSO Write 0 TRST Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 22 4 TIM Status and Control Register TSC MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 349 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM TOF TIM Overflow Flag Bit This read write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic O to TOF If another TIM overflow occurs before the clearing sequence is complete then writing logic 0 to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a logic 1 to TOF has no effect 1 TIM counter has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIM overflow interrupts enabled 0 TIM overflow interrupts disabled TSTOP TIM Stop Bit This read write bit stops the TIM counter Counting resumes whe
173. SP SP1 9E6D ff 4 TSX Transfer SP to H X H X SP 1 INH 95 2 TXA Transfer X to A A X i INH 9F 1 TXS Transfer H X to SP SP e H X 1 7 INH 94 2 A Accumulatorn Any bit C Carry borrow bitopr Operand one or two bytes CCRCondition code registerPC Program counter ddDirect address of operandPCH Program counter high byte dd rrDirect address of operand and relative offset of branch instructionPCL Program counter low byte DDbDirect to direct addressing modeREL Relative addressing mode DIRDirect addressing moderel Relative program counter offset byte DIX Direct to indexed with post increment addressing moderr Relative program counter offset byte ee ffHigh and low bytes of offset in indexed 16 bit offset addressingSP 1 Stack pointer 8 bit offset addressing mode EXTExtended addressing modeSP2 Stack pointer 16 bit offset addressing mode ff Offset byte in indexed 8 bit offset addressingSP Stack pointer H Half carry bitU Undefined H Index register high byteV Overflow bit hh IIHigh and low bytes of operand address in extended addressingX Index register low byte Interrupt maskZ Zero bit ii Immediate operand byte amp Logical AND IMDImmediate source to direct destination addressing mode Logical OR IMMImmediate addressing mode Logical EXCLUSIVE OR INHInherent addressing mode Contents of IXIndexed no offset addressing mode Negation two s complement IX Indexed no offset post increment addressing mo
174. SPI module When the SPI enable bit SPE is clear the SPI module is disabled and the PTDO SS pin is available for general purpose I O Data direction register D DDRD does not affect the data direction of port D pins that are being used by the SPI module However the DDRD bits always determine whether reading port D returns the states of the latches or the states of the pins See Table 16 5 SS Slave Select The PTDO SS pin is the slave select input of the SPI module When the SPE bit is clear or when the SPI master bit SPMSTR is set the PTDO SS pin is available for general purpose I O When the SPI is enabled the DDRBO bit in data direction register B DDRB has no effect on the PTDO SS pin MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 221 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 16 6 2 Data Direction Register D Data direction register D DDRD determines whether each port D pin is an input or an output Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin a logic 0 disables the output buffer Address 0007 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO Write Reset 0 0 0 0 0 0 0 0 Figure 16 14 Data Direction Register D DDRD DDRD6 DDRDO Data Direction Register D Bits These rea
175. SPMSTR when MODF 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave When CPHA 0 a MODF occurs if a slave is selected SS is at logic 0 and later unselected SS is at logic 1 even if no SPSCK is sent to that MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 313 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI NOTE 20 9 Interrupts Technical Data slave This happens because SS at logic 0 indicates the start of the transmission MISO ariven out with the value of MSB for CPHA 0 When CPHA 1 a slave can be selected and then later unselected with no transmission occurring Therefore MODF does not occur since a transmission was never begun In a slave SPI MSTR 0 the MODF bit generates an SPI receiver error CPU interrupt request if the ERRIE bit is set The MODF bit does not clear the SPE bit or reset the SPI in any way Software can abort the SPI transmission by clearing the SPE bit of the slave A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state Also the slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmission Toclear the MODF flag read the SPSCR with the MODF bit set and then write to the SPCR register This entire clearing mechanism must occur with no MODF condit
176. Serial Communications Interface SCI Technical Data MC68HC908GR8 Rev 4 0 270 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 19 1 Contents 19 2 Introduction Section 19 System Integration Module SIM 18 2 19 3 19 4 19 5 19 6 19 7 19 8 La liga UE AA AA AA 271 SIM Bus Clock Control and Generation 275 Reset and System lInitialization 276 PAL AA AA AA da M od 281 Exception SO ci de dod APA AA AA 282 Low Power Modes MR 290 pa Le PO AA APA AA EE 293 This section describes the system integration module SIM Together with the CPU the SIM controls all MCU activities A block diagram of the SIM is shown in Figure 19 1 Table 19 1 is a summary of the SIM input output I O registers The SIM is a system state controller that coordinates CPU and exception timing The SIM is responsible for MC68HC908GR8 Rev 4 0 Bus clock generation and control for CPU and peripherals Stop wait reset break entry and recovery Internal clock control Master reset control including power on reset POR and COP timeout Interrupt control Acknowledge timing Arbitration control timing Technical Data MOTOROLA System Integration Module SIM 271 For More Information On This Product Go to www freescale com Freescale Se
177. T When the MCU recovers from STOP the crystal clock divided by two drives CGMOUT and BCS remains clear If the OSCSTOPENB bit in the CONFIG register is set then the phase locked loop is shut off but the oscillator will continue to operate in stop mode 7 8 3 CGMC During Break Interrupts Technical Data The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect the PLLF bit during the break state write a logic O to the BCFE bit With BCFE at logic O its default state software can read and write the PLL control register during the break state without affecting the PLLF bit MC68HC908GR8 Rev 4 0 124 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Acquisition Lock Time Specifications 7 9 Acquisition Lock Time Specifications The acquisition and lock times of the PLL are in many applications the most critical PLL design parameters Proper design and use of the PLL ens
178. TD2 MOSI 3 DDRD3 PTD3 SPSCK 4 DDRD4 PTDA T1CHO 5 DDRD5 T PTD5 T1CH1 6 DDRD6 PTD6 T2CHO TIM2 E 0 DDREO sel PTEO TxD 1 DDRE1 PTE1 RxD MC68HC908GR8 Rev 4 0 208 Input Output Ports I O For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Input Output Ports I O Port A 16 3 PortA Port A is an 4 bit special function port that shares all four of its pins with the keyboard interrupt KBI module Port A also has software configurable pullup devices if configured as an input port 16 3 1 Port A Data Register The port A data register PTA contains a data latch for each of the four port A pins Address 0000 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 PTA3 PTA2 PTA1 PTAO Write Reset Unaffected by reset Alamat KBD3 KBD2 KBD1 KBDO Function Figure 16 2 Port A Data Register PTA PTA3 PTAO Port A Data Bits These read write bits are software programmable Data direction of each port A pin is under the control of the corresponding bit in data direction register A Reset has no effect on port A data KBD3 KBDO Keyboard Inputs The keyboard interrupt enable bits KBIE3 KBIEO in the keyboard interrupt control register KBICR enable the port A pins as external interrupt pins See Keyboard Interrupt KBI MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports
179. TERNAL PTCx Figure 16 11 Port C I O Circuit When bit DDRCx is a logic 1 reading address 0002 reads the PTCx data latch When bit DDRCx is a logic O reading address 0002 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 16 4 summarizes the operation of the port C pins Table 16 4 Port C Pin Functions Accesses to DDRC Accesses to PTC PTCPUE Bit DDRC Bit PTC Bit 1 0 Pin Mode Read Write Read Write 1 0 x Input Vpp DDRC1 DDRCO Pin PTC1 PTCOO 0 0 X Input Hi zZ DDRC1 DDRCO Pin PTC1 PTCO X 1 X Output DDRC1 DDRCO PTC1 PTCO PTC1 PTCO Notes 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect input 4 I O pin pulled up to Vpp by internal pullup device Technical Data MC68HC908GR8 Rev 4 0 218 Input Output Ports I O For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Input Output Ports I O Port C 16 5 3 Port C Input Pullup Enable Register The port C input pullup enable register PTCPUE contains a software configurable pullup device for each of the two port C pins Each bit is individually configurable and requires that the data direction register DDRC bit be configured as an input Each pullup is automatically and dynamically disabled when a p
180. Technical Data MOTOROLA Analog to Digital Converter ADC 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC 5 3 Features Features of the ADC module include Six channels with multiplexed input Linear successive approximation with monotonicity e 8 bit resolution Single or continuous conversion e Conversion complete flag or conversion complete interrupt Selectable ADC clock 5 4 Functional Description NOTE Technical Data The ADC provides six pins for sampling external sources at pins PTB5 ATD5 PTBO ATDO An analog multiplexer allows the single ADC converter to select one of six ADC channels as ADC voltage in Vapin VapiN is converted by the successive approximation register based analog to digital converter When the conversion is completed ADC places the result in the ADC data register and sets a flag or generates an interrupt See Figure 5 1 References to DMA direct memory access and associated functions are only valid if the MCU has a DMA module If the MCU has no DMA any DMA related register bits should be left in their reset state for expected MCU operation MC68HC908GR8 Rev 4 0 80 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Functional Description INTERNAL DAT
181. The TIM is inactive in stop mode The STOP instruction does not affect register states or the state of the TIM counter TIM operation resumes when the MCU exits stop mode after an external interrupt 3 14 Timebase Module TBM 3 14 1 Wait Mode 3 14 2 Stop Mode Technical Data The timebase module remains active after execution of the WAIT instruction In wait mode the timebase register is not accessible by the CPU If the timebase functions are not required during wait mode reduce the power consumption by stopping the timebase before enabling the WAIT instruction The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register The timebase module can be used in this mode to generate a periodic wakeup from stop mode If the oscillator has not been enabled to operate in stop mode the timebase module will not be active during stop mode In stop mode the timebase register is not accessible by the CPU If the timebase functions are not required during stop mode reduce the power consumption by stopping the timebase before enabling the STOP instruction MC68HC908GR8 Rev 4 0 56 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com 3 15 Exiting Wait Mode Freescale Semiconductor Inc Low Power Modes Exiting Wait Mode These events restart the CPU clock
182. US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http www motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating
183. Vppa AAN t T Voo RB 5 T CBYP RS As 0 01 uF GR 0 1 uF 0 033 UE I iI e e xi C1 Te C2 ES Note Filter network in box can be replaced with a 0 47 uF capacitor but will degrade stability Figure 7 2 CGMC External Connections MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 5 I O Signals The following paragraphs describe the CGMC I O signals 7 5 1 Crystal Amplifier Input Pin OSC1 The OSC1 pin is an input to the crystal oscillator amplifier 7 5 2 Crystal Amplifier Output Pin OSC2 The OSC2 pin is the output of the crystal oscillator inverting amplifier 7 5 3 External Filter Capacitor Pin CGMXFC NOTE The CGMXFC pin is required by the loop filter to filter out phase corrections An external filter network is connected to this pin See Figure 7 2 To prevent noise problems the filter network should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the network 7 5 4 PLL Analog Power Pin VppA NOTE Vppa is a power pin used by the analog portions of the PLL Connect the VppA pin to the same voltage potential as the Vpp pin Route VppA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 7
184. Write Reset 0 0 0 0 0 0 0 0 Figure 6 5 Break Address Register Low BRKL 6 6 3 Break Status Register The break status register SBSR contains a flag to indicate that a break caused an exit from wait mode The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt Address SFE00 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 1 0 0 BW 0 Write R R R R R R NOTE R Reset 0 0 0 1 0 0 0 0 Note Writing a logic 0 clears BW R Reserved Figure 6 6 SIM Break Status Register SBSR Technical Data MC68HC908GR8 Rev 4 0 96 Break Module BRK MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Break Module Registers BW Break Wait Bit This read write bit is set when a break interrupt causes an exit from wait mode Clear BW by writing a logic O to it Reset clears BW 1 Break interrupt during wait mode 0 No break interrupt during wait mode BW can be read within the break interrupt routine The user can modify the return address on the stack by subtracting 1 from it The following code is an example This code works if the H register was stacked in the break interrupt routine Execute this code at the end of the break interrupt routine HIBYTE EQU 5 LOBYTE EQU 6 If not BW do RTI BRCLR BW BSR RETURN See if wait mode or stop mo
185. a a zn Disabled set in monitor Z Z Z 1 DNA code Vpr Enters user mode will encounter or Vist FFFF OFF X X X Enabled X an illegal address GND reset Vpp Voo Not or or SFFFF OFF X X X Enabled X Enters user mode GND Vrsr Notes 1 External clock is derived by a 32 768 kHz crystal or a 9 8304 MHz off chip oscillator 2 PTAO 1 if serial communication PTAO X if parallel communication 3 PTA1 0 gt serial PTA1 1 parallel communication for security code entry 4 DNA does not apply X don t care If entering monitor mode with Vrsr applied on IRQ condition set 1 the CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1 input directly generates internal bus clocks In this case the OSC1 signal must have a 50 duty cycle at maximum bus frequency If entering monitor mode without high voltage applied on IRQ condition set 2 or 3 where applied voltage is either Vpp or Vss then all port B pin MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON For More Information On This Product Go to www freescale com 193 Freescale Semiconductor Inc Monitor ROM MON NOTE Technical Data requirements and conditions are not in effect This is to reduce circuit requirements when performing in circuit programming If the reset vector is blank and monitor mode is entered the chip will see an additional reset cycle after the initial POR rese
186. able 18 8 SCI Baud Rate Selection Examples SCP1 and Prescaler SCR2 SCR1 Baud Rate Baud Rate SCPO Divisor PD and SCRO Divisor BD fgus 4 9152 MHz 00 1 000 1 76 800 00 1 001 2 38 400 00 1 010 4 19 200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25 600 01 3 001 2 12 800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19 200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 Technical Data MC68HC908GR8 Rev 4 0 268 Serial Communications Interface SCI For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Serial Communications Interface SCI Table 18 8 SCI Baud Rate Selection Examples SCP1 and Prescaler SCR2 SCR1 Baud Rate Baud Rate SCPO Divisor PD and SCRO Divisor BD fgus 4 9152 MHz 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 Technical Data MC68HC908GR8 Rev 4 0 269 Serial Communications Interface SCI For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc
187. ables the timebase Timebase may be turned off to reduce power consumption when its function is not necessary The counter can be initialized by clearing and then setting this bit Reset clears the TBON bit 1 Timebase enabled 0 Timebase disabled and the counter initialized to Os The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2 TBRO When the timebase counter chain rolls over the TBIF flag is set If the TBIE bit is set enabling the timebase interrupt the counter chain overflow will generate a CPU interrupt request Interrupts must be acknowledged by writing a logic 1 to the TACK bit MC68HC908GR8 Rev 4 0 332 Timebase Module TBM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timebase Module TBM Low Power Modes 21 7 Low Power Modes 21 7 1 Wait Mode 21 7 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The timebase module remains active after execution of the WAIT instruction In wait mode the timebase register is not accessible by the CPU If the timebase functions are not required during wait mode reduce the power consumption by stopping the timebase before enabling the WAIT instruction The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCSTOPEN bit i
188. ace SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI NORMAL FLAG CLEARING SEQUENCE I O Registers o o 7 o ll ll ll Il ll ll LL LL LL LL LL LL a ao ao tc tc a O O O O O O i BYTE 1 BYTE 2 y BYTE 3 BYTE 4 A READ SCS1 READ SCS1 a READ SCS1 E SCRF 1 SCRF 1 SCRF 1 OR 0 OR 0 OR 0 READ SCDR READ SCDR READ SCDR BYTE 1 BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE e T ou lo bn Be a Ba 2 HO oO 95 HO BYTE 1 BYTE 2 y BYTE 3 BYTE 4 A A READ SCS1 E READ SCS1 SCRF 1 SCRF 1 OR 0 OR 1 READ SCDR READ SCDR BYTE 1 BYTE 3 Figure 18 13 Flag Clearing Sequence PE Receiver Parity Error Bit This clearable read only bit is set when the SCI detects a parity error in incoming data PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set Clear the PE bit by reading SCS1 with PE set and then reading the SCDR Reset clears the PE bit 1 Parity error detected 0 No parity error detected MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI For More Information On This Product Go to www freescale com 263 Freescale Semiconductor Inc Serial Communications Interface SCI 18 9 5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions Break character detected
189. action depending on the application See Interrupts for information and precautions on using interrupts The following conditions apply when the PLL is in automatic bandwidth control mode The ACQ bit see PLL Bandwidth Control Register is a read only indicator of the mode of the filter See Acquisition and Tracking Modes The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance See Acquisition Lock Time Specifications for more information e TheLOCK bit is a read only indicator of the locked state of the PLL The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance See Acquisition Lock Time Specifications for more information e CPU interrupts can occur if enabled PLLIE 1 when the PLL s lock condition changes toggling the LOCK bit See PLL Control Register The PLL also may operate in manual mode AUTO 0 Manual mode is used by systems that do not require an indicator of the lock condition for proper operation Such systems typically operate well below fgysmax The following conditions apply when in manual mode e ACQ is a writable control bit that controls the mode of the filter Before turning on the PLL in manual mode the ACQ bit must be clear Before entering tracking mode ACQ 1 software must wait a given time taco see Acqu
190. ail No dc loads Less than 100 pF on all outputs Cj 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects wait Ipp Measured with PLL and LVI enabled 5 Stop Ipp is measured with OSC1 Ves 6 Stop Ipp with TBM enabled is measured using an external square wave clock source fosc 32 8 KHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs All inputs configured as inputs Pullups and pulldowns are disabled Maximum is highest voltage that POR is guaranteed Maximum is highest voltage that POR is possible 0 If minimum Vpp is not reached before the internal POR reset is released RST must be driven low externally until minimum Vpp is reached Co N QO CA MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 367 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Electrical Specifications 23 7 5 0 V Control Timing Table 23 6 5 0 V Control Timing Characteristic Symbol Min Max Unit Frequency of operation Crystal option fosc 32 100 kHz External clock option dc 32 8 MHz Internal operating frequency fop 82 MHz Internal clock period 1 fop toye 122 ns RESET input pulse width low tiRL 50 ns IRQ interrupt pulse width low in 50 u edge triggered IRQ interrupt pulse period tuk Note 8 lcyc 16 bit timer Input capture pulse
191. ain valid until the CPU writes a different value or until power is turned off RC circuit A circuit consisting of capacitors and resistors having a defined time constant read To copy the contents of a memory location to the accumulator register A circuit that stores a group of bits reserved memory location A memory location that is used only in special factory test modes Writing to a reserved location has no effect Reading a reserved location returns an unpredictable value reset To force a device to a known condition ROM Read only memory A type of memory that can be read but cannot be changed written The contents of ROM must be specified before manufacturing the MCU SCI See serial communication interface module SCI serial Pertaining to sequential transmission over a single line Technical Data MC68HC908GR8 Rev 4 0 402 Glossary MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Glossary serial communications interface module SCI A module in the M68HC08 Family that supports asynchronous communication serial peripheral interface module SPI A module in the M68HC08 Family that supports synchronous communication set To change a bit from logic O to logic 1 opposite of clear shift register A chain of circuits that can retain the logic levels logic 1 or logic O written to them and that can shift the
192. ak Module IBEX E46 93 9 bel de CR OR ere ee RR de 51 Central Processor Unit CPU uua ak d EROR Rea 51 Clock Generator Module CGM 00 005 52 Computer Operating Properly Module COP 52 External Interrupt Module IRQ 2a maa awake rr en 53 Keyboard Interrupt Module KBI 53 Low Voltage Inhibit Module LVI 54 Serial Communications Interface Module SCI 54 Serial Peripheral Interface Module SPI 55 Timer Interface Module TIM1 and TIM2 55 Timebase Module TBM wawasak ak kA RA atest ox Rn 56 Exiting Wat Mode APAPAP 57 BANGA CU Moder oda dI iced bod RUIN C ACE ERU de dede den 58 Section 4 Resets and Interrupts DERE a doe R6 doe dob deo E OPE de Beat Fed e EGRE rH ean 61 Lir s Doi RENT AA AA AA EP 61 ics METTE a 61 AA cbe d 4308 PAKA bdo EE 66 Section 5 Analog to Digital Converter ADC a AA AA 79 Introduction AA 79 MC68HC908GR8 Rev 4 0 8 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 3 5 4 6 5 5 6 5 7 5 8 6 1 6 2 6 3 6 4 6 5 6 6 7 1 za 7 3 7 4 Es 7 6 Fa 7 8 19 MC68HC908GR8 Rev 4 0 Table of Contents FeO ee a h SA 80 Functional Description sssri Liked BREN EXPE Oba ads 80 LOIS ee T TTE TTL T 83 Low Power eS sod UC HERE CR FREER OO HR kaa 83 pL SIC a da ica eh acd did da
193. akes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW lug PERIOD Y Y Y PTEx TCHx A 1 i A OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE CHxMAX Figure 22 13 CHxMAX Latency 22 10 6 TIM Channel Registers These read write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function The state of the TIM channel registers after reset is unknown In input capture mode MSxB MSxA 0 0 reading the high byte of the TIM channel x registers TCHxH inhibits input captures until the low byte TCHxL is read In output compare mode MSxB MSxA z 0 0 writing to the high byte of the TIM channel x registers TCHxH inhibits output compares until the low byte TCHxL is written MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 359 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Address T1CHOH 0026 and T2CHOH 0031 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 22 14 TIM Channel 0 Register High TCHOH Address T1CHOL 0027 and T2CHOL 0032
194. al reset signal R W Read write signal MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 273 For More information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW SIM Break Status Register R R R R R R R FE00 SBSR Write NOTE Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears SBSW Read POR PIN COP ILOP ILAD MODRST LVI 0 SIM Reset Status Register SFE01 SRSR Write POR 1 0 0 0 0 0 0 0 Read SFEO2 SIM Upper Byte Address Write R R R R R R R R Register SUBAR Reset Read FE03 SIM Break Flag Control Write BCFE R R R R R R R Register SBFCR Reset 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 SFE09 Interrupt Status Register 1 Write R R R R R R R R INT1 Reset 0 0 0 0 0 0 0 0 Read IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 SFEOA Interrupt Status Register 2 Write R R R R R R R R INT2 Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 IF16 IF15 FEOB Interrupt Status Register 3 Write R R R R R R R R INT3 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 19 2 SIM I O Register Summary Technical Data MC68HC908GR8 Rev 4 0 274 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freesc
195. al tuning capacitance Co 6 2x CL 40 pF Feedback bias resistor Rp 10 10 22 MQ Series resistor Rs 330 330 470 kQ Notes 1 Fundamental mode crystals only 2 Consult crystal manufacturer s data MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 383 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 16 2 CGM Electrical Specifications Description Symbol Min Typ Max Unit Operating voltage Vpp 2 7 5 5 V Operating temperature T 40 25 125 C Crystal reference frequency fRcLK 30 32 768 100 kHz Range nominal multiplier fNoM 38 4 kHz VCO center of range frequency fvrs 38 4 k 40 0M Hz Medium voltage VCO center of range frequency fyrs 38 4 k 40 0 M Hz VCO range linear range multiplier L 1 255 VCO power of two range multiplier 2E 1 4 VCO multiply factor N 1 4095 VCO prescale multiplier 2P 1 1 8 Reference divider factor R 1 1 15 VCO operating frequency fvcLK 38 4 k 40 0 M Hz Bus operating frequency fBus 8 2 MHz Bus frequency medium voltage fBus 4 1 MHz Manual acquisition time ll ock 50 ms Automatic lock time ll ock 50 ms fRCLK X PLL jitter fj 0 0 02596 Hz x 2P N 4 bei qus frequency fost de S 32 8 M Hz Ea input frequency take 30k 15M Hz Notes 1 5 0 V 1096 Vp
196. ale Semiconductor Inc System Integration Module SIM SIM Bus Clock Control and Generation 19 3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU The system clocks are generated from an incoming clock CGMOUT as shown in Figure 19 3 This clock can come from either an external oscillator or from the on chip PLL See Clock Generator Module CGMC OSCILLATOR OSC CGMXCLK TO TIMTB15A ADC SIM SIMOSCEN OSCSTOPENB gt FROM a MEME CONFIG CGMRCLK SIM COUNTER IT12 TO REST emet Yeu OF CHIP omer BUS CLOCK IT23 PHASE LOCKED LOOP PLL GENERATORS SLE Figure 19 3 CGM Clock Signals 19 3 1 Bus Timing In user mode the internal bus frequency is either the crystal oscillator output CGMXCLK divided by four or the PLL output CGMVCLK divided by four See External Interrupt IRQ MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 275 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 3 2 Clock Startup from POR or LVI Reset When the power on reset module or the low voltage inhibit module generates a reset the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed The RST pi
197. ale com 20 5 1 Master Mode NOTE Freescale Semiconductor Inc Serial Peripheral Interface SPI Functional Description The following paragraphs describe the operation of the SPI module The SPI operates in master mode when the SPI master bit SPMSTR is set Configure the SPI modules as master or slave before enabling them Enable the master SPI before enabling the slave SPI Disable the slave SPI before disabling the master SPI See SPI Control Register Only a master SPI module can initiate transmissions Software begins the transmission from a master SPI module by writing to the transmit data register If the shift register is empty the byte immediately transfers to the shift register setting the SPI transmitter empty bit SPTE The byte begins shifting out on the MOSI pin under the control of the serial clock See Figure 20 3 MASTER MCU SLAVE MCU SHIFT REGISTER SHIFT REGISTER BAUD RATE Figure 20 3 Full Duplex Master Slave Connections GENERATOR MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 301 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 5 2 Slave Mode Technical Data The SPR1 and SPRO bits control the baud rate generator and determine the speed of the shift register See SPI Status and Control Register Through the SPSCK pin the baud rate genera
198. all internal reset sources 19 4 2 5 Low Voltage Inhibit LVI Reset Technical Data The low voltage inhibit module LVI asserts its output to the SIM when the Vpp voltage falls to the LVI p pp voltage The LVI bit in the SIM reset status register SRSR is set and the external reset pin RST is held low while the SIM counter counts out 4096 CGMXCLK cycles Sixty four CGMXCLK cycles later the CPU is released from reset to allow the reset vector sequence to occur The SIM actively pulls down the RST pin for all internal reset sources MC68HC908GR8 Rev 4 0 280 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM SIM Counter 19 4 2 6 Monitor Mode Entry Module Reset MODRST 19 5 SIM Counter The monitor mode entry module reset MODRST asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are blank 00 See Entering Monitor Mode When MODRST gets asserted an internal reset occurs The SIM actively pulls down the RST pin for all internal reset sources The SIM counter is used by the power on reset module POR and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus IBUS clocks The SIM counter also serves as a prescaler for the computer operating properly module COP The SIM counter overflow supplies the c
199. an already active slave the load of the shift register cannot occur until the transmission is completed This implies that a back to back write to the transmit data register is not possible The SPTE indicates when the next write can occur 20 8 Error Conditions 20 8 1 Overflow Error Technical Data The following flags signal SPI error conditions e Overflow OVRF Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit The new byte does not transfer to the receive data register and the unread byte still can be read OVRF is in the SPI status and control register Mode fault error MODF The MODF bit indicates that the voltage on the slave select pin SS is inconsistent with the mode of the SPI MODF is in the SPI status and control register The overflow flag OVRF becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs The bit 1 capture strobe occurs in the middle of SPSCK cycle 7 See Figure 20 4 and Figure 20 6 If an overflow occurs all data received after the overflow and before the OVHREF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit SPRF The unread data that transferred to the receive data register before the overflow occurred can still be read Therefore an overflow error always indicates the loss of
200. an bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations FFF6 FFFD Locations FFF6 FFFD contain user defined data Do not leave locations FFF6 FFFD blank For security reasons they should be programmed even if they are not used for vectors During monitor mode entry the MCU waits after the power on reset for the host to send the eight security bytes on pin PTAO If the received bytes match those at locations SFFF6 SFFFD the host bypasses the security feature and can read all FLASH locations and execute code from FLASH Security remains bypassed until a power on reset occurs If the reset was not a power on reset security remains bypassed and security code entry is not required See Figure 15 8 MC68HC908GR8 Rev 4 0 202 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc Monitor ROM MON Security lt oe um pon 24 BUS CYCLES pat AAA 4 4096 32 CGMXCLK CYCLES la 256 BUS CYCLES MINIMUM S a co g Lu Lu Lu S E E E gt gt gt Q e a a O FROM HOST PAD N JW a DEI Ute CLE NEED eo FROM MCU Oo Oo o o I I I x L O O o 5 g Lu w NT a QN m 2 Lu Lu LLI T x ka pa m e a 3 NOTES o 1 Echo delay 2 bit times 2 Data return delay 2 bit times 4 Wait 1 bit time before sending next byte Figure 15 8 Mon
201. and load the program counter with the reset vector or with an interrupt vector MC68HC908GR8 Rev 4 0 External reset A logic O on the RST pin resets the MCU and loads the program counter with the contents of locations SFFFE and SFFFF External interrupt A high to low transition on an external interrupt pin IRQ pin loads the program counter with the contents of locations SFFFA and FFFB IRQ pin Break interrupt A break interrupt loads the program counter with the contents of FFFC and FFFD Computer operating properly module COP reset A timeout of the COP counter resets the MCU and loads the program counter with the contents of SFFFE and FFFF Low voltage inhibit module LVI reset A power supply voltage below the Virip voltage resets the MCU and loads the program counter with the contents of locations SFFFE and FFFF Clock generator module CGM interrupt A CPU interrupt request from the phase locked loop PLL loads the program counter with the contents of FFF8 and FFF9 Keyboard module KBI interrupt A CPU interrupt request from the KBI module loads the program counter with the contents of FFDE and FFDF Timer 1 interface module TIM1 interrupt A CPU interrupt request from the TIM1 loads the program counter with the contents of FFF2 and SFFF3 TIM1 overflow FFF4 and FFF5 TIM1 channel 1 SFFF6 and SFFF7 TIM1 channel 0 Timer 2 interface module TIM2 interrupt
202. and low bytes of the value in the TIM counter Reading the high byte TCNTH latches the contents of the low byte TCNTL into a buffer Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read Reset clears the TIM counter registers Setting the TIM reset bit TRST also clears the TIM counter registers NOTE Ifyou read TCNTH during a break interrupt be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt Otherwise TCNTL retains the value latched during the break Address T1CNTH 0021 and T2CNTH 002C Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 9 TIM Counter Register High TCNTH Address T1CNTL 0022 and T2CNTL 002D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 10 TIM Counter Register Low TCNTL Technical Data MC68HC908GR8 Rev 4 0 354 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM O Registers 22 10 5 TIM Channel Status and Control Registers Each of the TIM channel status and control registers Flags input captures and output compares e Enables input capture and output compare interrupts Selects input capture output
203. and more detail about CPU architecture 10 6 Low power modes The WAIT and STOP instructions put the MCU in low power consumption standby modes MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU 10 6 1 WAIT mode The WAIT instruction clears the interrupt mask bit in the condition code register enabling interrupts After exit from WAIT mode by interrupt the bit remains clear After exit by reset the bit is set e Disables the CPU clock 10 6 2 STOP mode The STOP instruction clears the interrupt mask bit in the condition code register enabling external interrupts After exit from STOP mode by external interrupt the bit remains clear After exit by reset the bit is set e Disables the CPU clock After exiting STOP mode the CPU clock begins running after the oscillator stabilization delay 10 7 CPU during break interrupts If the break module is enabled a break interrupt causes the CPU to execute the software interrupt instruction SWI at the completion of the current CPU instruction See Break Module BRK The program counter vectors to SFFFC SFFFD SFEFC SFEFD in monitor mode A return from interrupt instruction RTI in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has
204. appear in the text of this section Table 18 1 Pin Name Conventions Generic Pin Names RxD TxD Full Pin Names PE1 RxD PE0 TxD 18 5 Functional Description Figure 18 1 shows the structure of the SCI module The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The transmitter and receiver of the SCI operate independently although they use the same baud rate generator During normal operation the CPU monitors the status of the SCI writes the data to be transmitted and processes received data The baud rate clock source for the SCI can be selected via the configuration bit SCIBDSRC of the CONFIG2 register 001E Source selection values are shown in Figure 18 1 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 233 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI INTERNAL BUS SCI DATA SCI DATA REGISTER REGISTER RECEIVE i z E z E z E S z E TRANSMIT
205. ard interrupt requests to bring the MCU out of wait mode MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Power Modes 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes 3 9 2 Stop Mode The keyboard module remains active in stop mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode 3 10 Low Voltage Inhibit Module LVI 3 10 1 Wait Mode 3 10 2 Stop Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of wait mode If enabled the LVI module remains active in stop mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of stop mode 3 11 Serial Communications Interface Module SCI 3 11 1 Wait Mode Technical Data The SCI module remains active in wait mode Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction MC68HC908GR8 Rev 4 0 54 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com 3 11 2 Stop Mode Freescale Semiconductor Inc Low Power Modes Serial Peripheral Interface Module
206. as read from the SCI data register The overrun interrupt enable bit ORIE enables OR to generate SCI error CPU interrupt requests OR is in SCI status register 1 ORIE is in SCI control register 3 Technical Data MOTOROLA Resets and Interrupts 73 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Noise flag NF NF is set when the SCI detects noise on incoming data or break characters including start data and stop bits The noise error interrupt enable bit NEIE enables NF to generate SCI error CPU interrupt requests NF is in SCI status register 1 NEIE is in SCI control register 3 Framing error bit FE FE is set when a logic 0 occurs where the receiver expects a stop bit The framing error interrupt enable bit FEIE enables FE to generate SCI error CPU interrupt requests FE is in SCI status register 1 FEIE is in SCI control register 3 Parity error bit PE PE is set when the SCI detects a parity error in incoming data The parity error interrupt enable bit PEIE enables PE to generate SCI error CPU interrupt requests PE is in SCI status register 1 PEIE is in SCI control register 3 4 4 2 9 KBDO KBDA Pins A logic O on a keyboard interrupt pin latches an external interrupt request 4 4 2 10 ADC Analog to Digital Converter When the AIEN bit is set the ADC module is capable of generating a CPU interrupt after each ADC conv
207. ata available in SCDR 0 Data not available in SCDR IDLE Receiver ldle Bit MC68HC908GR8 Rev 4 0 This clearable read only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR After the receiver is enabled it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit Also after the IDLE bit has been cleared a valid character must again set the SCRF bit before an idle condition can set the IDLE bit Reset clears the IDLE bit 1 Receiver input idle 0 Receiver input active or idle since the IDLE bit was cleared Technical Data MOTOROLA Serial Communications Interface SCI 261 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI OR Receiver Overrun Bit This clearable read only bit is set when software fails to read the SCDR before the receive shift register receives the next character The OR bit generates an SCI error CPU interrupt request if the ORIE bitin SCC3 is also set The data in the shift register is lost but the data already in the SCDR is not affected Clear the OR bit by reading SCS1 with OR set and then reading the SCDR Reset clears the OR bit 1 Receive shift register full and SCRF
208. atch the operating Vpp See Electrical Specifications for the LVI s voltage trip points for each of the modes 1 LVI operates in 5V mode 0 LVI operates in 3V mode SSREC Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay 1 Stop mode recovery after 32 CGMXCLK cycles 0 Stop mode recovery after 4096 CGMXCLKC cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery If using an external crystal oscillator do not set the SSREC bit NOTE When the LVISTOP is enabled the system stabilization time for power on reset and long stop recovery both 4096 CGMXCLK cycles gives a delay longer than the enable time for the LVI There is no period where the MCU is not protected from a low power condition However when using the short stop recovery configuration option the 32 CGMXCLK delay is less than the LVI s turn on time and there exists a period in startup where the LVI is not protecting the MCU STOP STOP Instruction Enable Bit STOP enables the STOP instruction 1 STOP instruction enabled 0 STOP instruction treated as illegal opcode COPD COP Disable Bit COPD disables the COP module See Computer Operating Properly COP 1 COP module disabled 0 COP module enabled Technical Data MC68HC908GR8 Rev 4 0 132 Configuration Register CONFIG MOTOROLA For More Information On This Product
209. ated external interrupt pin IRQ1 e IRQ interrupt control bits Hysteresis buffer e Programmable edge only or edge and level interrupt sensitivity e Automatic interrupt acknowledge Internal pullup resistor MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA External Interrupt IRQ 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 12 4 Functional Description Technical Data A logic O applied to the external interrupt pin can latch a CPU interrupt request Figure 12 1 shows the structure of the IRQ module Interrupt signals on the IRQ1 pin are latched into the IRQ latch An interrupt latch remains set until one of the following actions occurs e Vector fetch A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch e Software clear Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register INTSCR Writing a logic 1 to the ACK bit clears the IRQ latch e Reset A reset automatically clears the interrupt latch The external interrupt pin is falling edge triggered and is software configurable to be either falling edge or falling edge and low level triggered The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ1 pin When an interrupt pin is edge triggered only the interrupt r
210. ation Module SIM Exception Control condition code register and if the corresponding interrupt enable bit is set the SIM proceeds with interrupt processing otherwise the next instruction is fetched and executed If more than one interrupt is pending at the end of an instruction execution the highest priority interrupt is serviced first Figure 19 11 demonstrates what happens when two interrupts are pending If an interrupt is pending upon exit from the original interrupt service routine the pending interrupt is serviced before the LDA instruction is executed CLI gt LDA FF BAGO 3 INT1 PSHH I INT1 INTERRUPT SERVICE ROUTINE INT PSHH EE I INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 19 11 Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions However in the case of the INT1 RTI prefetch this is a redundant operation NOTE To maintain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode software should save the H register and then restore it prior to exiting the routine MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 285 For More Information On This Product Go to www freescale com Freescale Semiconducto
211. bes the monitor ROM MON and the monitor mode entry methods The monitor ROM allows complete testing of the MCU through a single wire interface with a host computer Monitor mode entry can be achieved without use of the higher test voltage VrsT as long as vector addresses FFFE and FFFF are blank thus reducing the hardware requirements for in circuit programming Features of the monitor ROM include MC68HC908GR8 Rev 4 0 Normal user mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark space non return to zero NRZ communication with host computer Execution of code in RAM or FLASH Technical Data MOTOROLA Monitor ROM MON 189 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON FLASH memory security feature e FLASH memory programming interface Enhanced PLL phase locked loop option to allow use of external 32 768 kHz crystal to generate internal frequency of 2 4576 MHz 310 byte monitor ROM code size FE20 to FF55 e Monitor mode entry without high voltage Vrsr if reset vector is blank FFFE and FFFF contain FF Standard monitor mode entry if high voltage Vrsr is applied to IRQ 15 4 Functional Description The monitor ROM receives and executes commands from a host computer Figure 15 1 shows an example circuit used to enter monitor mode and communicate with
212. bit samples Table 18 3 Data Bit Recovery RT8 RT9 and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 MC68HC908GR8 Rev 4 0 244 Serial Communications Interface SCI For More Information On This Product Go to www freescale com MOTOROLA NOTE Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description The RT8 RT9 and RT10 samples do not affect start bit verification If any or all of the RT8 RT9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 18 4 summarizes the results of the stop bit samples Table 18 4 Stop Bit Recovery RT8 RT9 and RT10 Framing Noise Flag Samples Error Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 18 5 3 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character it sets the framing error bit FE in SCS1 A break character also sets the FE bit because a break character has no stop bit The FE bit is set at the same time that the SCRF bit is set 18 5 3 5 Baud Rate Tolerance A tra
213. cal Data MC68HC908GR8 Rev 4 0 108 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description c Inthe PLL multiplier select register low PMSL and the PLL multiplier select register high PMSH program the binary equivalent of N d In the PLL VCO range select register PMRS program the binary coded equivalent of L e Inthe PLL reference divider select register PMDS program the binary coded equivalent of R Table 7 1 provides numeric examples numbers are in hexadecimal notation Table 7 1 Numeric Example fBus RCLK N PE L 2 0 MHz 32 768 kHz F5 0 0 D1 2 4576 MHz 32 768 kHz 12C 0 1 80 2 5 MHz 32 768 kHz 132 0 1 83 4 0 MHz 32 768 kHz 1E9 0 1 D1 4 9152 MHz 32 768 kHz 258 0 2 80 5 0 MHz 32 768 kHz 263 0 2 82 7 3728 MHz 32 768 kHz 384 0 2 CO 8 0 MHz 32 768 kHz 3D1 0 2 DO 7 4 7 Special Programming Exceptions The programming method described in Programming the PLL does not account for three possible exceptions A value of 0 for R N or L is meaningless when used in the equations given To account for these exceptions e AOvalueforRorN is interpreted exactly the same as a value of 1 e A0 value for L disables the PLL and prevents its selection as the source for the base clock See Base Clock Selector Circuit MC68HC908GR8
214. ce of IREAD or IWRITE commands can access a block of memory sequentially over the full 64K byte memory map Table 15 8 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Data Returns incremented stack pointer value SP 1 in high byte low Returned byte order Opcode SOC Command Sequence FROM HOST SP SP J READSP READSP HIGH LOW ECHO RETURN Table 15 9 RUN Run User Program Command Description Executes PULH and RTI instructions Operand None Data NG ag Returned Opcode 28 Command Sequence FROM HOST RUN RUN ECHO MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 201 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON 15 5 Security Technical Data NOTE The MCU executes the SWI and PSHH instructions when it enters monitor mode The RUN command tells the MCU to execute the PULH and RTI instructions Before sending the RUN command the host can modify the stacked CPU registers to prepare to run the host program The READSP command returns the incremented stack pointer value SP 1 The high and low bytes of the program counter are at addresses SP 5 and SP 6 Figure 15 7 Stack Pointer at Monitor Mode Entry A security feature discourages unauthorized reading of FLASH locations while in monitor mode The host c
215. cifications Typical Supply Currents lt a o 1 15 A jnre de 1 10 1 05 5 5 V E 3 6 V 1 0 1 2 3 4 5 6 7 8 9 fbus MHz Figure 23 15 Typical Stop Mode lpp with all Modules Disabled 40 C to 125 C MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 377 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 12 ADC Characteristics Characteristic Symbol Min Max Unit Comments 27 55 Vppap Should be tied i to the same potential V V Supply voltage VDDAD DD Vpp V 8s Vp via separate min max traces Input voltages VADIN 0 VDDAD V VADIN lt VREFH Resolution Bap 8 8 Bits Absolute accuracy VREFL 0 V VppAD VREFH Aap t1 LSB Includes quantization 5V t 1095 taic 1 f tested ADC internal clock ADIC 0 5 048 Zz only at 1 MHz VREFH VDDAD Conversion range Rap VeeeL VnEFH V VREFL VssAD Power up time tADPU 16 taic cycles Conversion time tapc 16 17 taic cycles t an 2 t mE AIC Sample time ADS 5 Cycles Zero input reading ZADI 00 01 Hex Vin VREFL Full scale reading Fapi FE FF Hex ViN VREFH Input capacitance Capi 20 8 pF Not tested Input leakage A m 4 uA Port B Notes 1 Vpp 5 0 Vdc 1095 Vss 0 Vdc VDDAD 5 0 Vdc 10
216. control register 4 4 2 5 TIM1 TIM1 CPU interrupt sources MC68HC908GR8 Rev 4 0 TIM1 overflow flag TOF The TOF bit is set when the TIM1 counter value rolls over to 0000 after matching the value in the TIM1 counter modulo registers The TIM1 overflow interrupt enable bit TOIE enables TIM1 overflow CPU interrupt requests TOF and TOIE are in the TIM1 status and control register TIM1 channel flags CH1F CHOF The CHXxF bit is set when an input capture or output compare occurs on channel x The channel x interrupt enable bit CHxIE enables channel x TIM1 CPU interrupt requests CHxF and CHxIE are in the TIM1 channel x status and control register Technical Data MOTOROLA Resets and Interrupts 71 For More Information On This Product Go to www freescale com 4 4 2 6 TIM2 4 4 2 7 SPI Technical Data Freescale Semiconductor Inc Resets and Interrupts TIM2 CPU interrupt sources TIM2 overflow flag TOF The TOF bit is set when the TIM2 counter value rolls over to 0000 after matching the value in the TIM2 counter modulo registers The TIM2 overflow interrupt enable bit TOIE enables TIM2 overflow CPU interrupt requests TOF and TOIE are in the TIM2 status and control register TIM2 channel flag CHOF The CHOF bit is set when an input capture or output compare occurs on channel 0 The channel 0 interrupt enable bit CHOIE enables channel 0 TIM2 CPU interrupt requests CHOF and CHOIE are
217. cse JO FROM MISO QN MSB Y Bite Y Bits Y BIT 4 Y BIT3 X BIT2 X BIT1 LSB SS TO SLAVE CAPTURE STROBE A A A A A A Technical Data Figure 20 6 Transmission Format CPHA 1 MC68HC908GR8 Rev 4 0 306 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Transmission Formats When CPHA 1 for a slave the first edge of the SPSCK indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data Once the transmission begins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission 20 6 4 Transmission Initiation Latency When the SPI is configured as a master SPMSTR 1 writing to the SPDR starts a transmission CPHA has no effect on the delay to the start of the transmission but it does affect the initial state of the SPSCK signal When CPHA 0 the SPSCK signal remains inactive for the first half of the first SPSCK cycle When CPHA 1 the first SPSCK cycle begins with an e
218. ction 24 Mechanical Specifications 387 Section 25 Ordering Information 391 AIO oo na ees Sh he ee eee AA AA 395 Revision History issus xs EORR CROACIE EO o ern 405 MC68HC908GR8 Rev 4 0 6 List of Paragraphs MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Table of Contents List of Paragraphs Table of Contents List of Tables List of Figures Section 1 General Description C EE rrr 25 D Oca 3 eed du dad a ORE EA APR 25 13 a doas EDdcdueasARd dde dax AE dieux d dd 26 1 4 MODDING x eso ae RR ed orari e Een Rua 28 15 PN Lom da dai ada d ZR RAS AD od dido e BA n 30 Lo Pim FUNCIONS EDIT 31 ET IG GRAN 9 ux arce kA ded dete dopo ORE KNA 35 22 NG TT 35 2 3 Unimplemented Memory Locations 35 2 4 Reserved Memory Locations a 36 25 Input Output 1 0 Section soak asks KA KGG Re o ER eo 36 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Table of Contents 7 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Table of Contents 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 4 1 4 2 4 3 4 4 5 1 5 2 Section 3 Low Power Modes COMENGE PTT 49 PU de ERA UOI Ren ADIP ER EA GA Uhd 49 Analog to Digital Converter ADC aa 50 Bre
219. d 199 IREAD Indexed Read Command aaa 200 IWRITE Indexed Write Command 200 READSP Read Stack Pointer Command 201 RUN Run User Program Command LLus 201 Port Control Register Bits Summary 208 Port PD PODES cs PAK kx HR weep KG uc e 211 Fart B Pin PINONG eed Ra Ra NAGA BAWAL DAA Dha 215 Port C PIN FUNCIONS iuuenem eR dmm deos 218 Port D Pin Funcions eae se KA der eK REPRE qa UR ewe 223 Fort E Pin FOOCROUS Lou 0 ces NBA K KAN Ed NGA ads Rue 227 Pin Name Conventions cece eee eee 233 Start Bit NAPAPA 244 Technical Data MOTOROLA List of Tables 17 For More information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables 18 3 18 4 18 5 18 6 18 7 18 8 19 1 19 2 19 3 19 4 20 1 20 2 20 3 20 4 21 7 22 1 ded 22 3 23 1 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23 9 25 1 25 2 25 3 Technical Data Dala BE HG M LS ia kA UE EROR d oor a AG 244 Stop Bit ey MEM 245 Character Format Selection 2 2 0055 255 SCI Baud Rate Prescaling i ng sad ka RR Rer RR 266 SCI Baud Hate Selection a kr hr NG 266 SCI Baud Rate Selection Examples 268 Signal Name Conventions sssaaa RR n onde 273 PIN Bit Set PAPA AA 277 BUM SOURS 44 NG KAL BK am eanu ed e dr x dores 286 sa REE O caduco 64 10 FE dE ioa S lob Voce deed 293 Pin Name
220. d Tracking Modes The value of the external capacitor and the reference frequency determine the speed of the corrections and the stability of the PLL The lock detector compares the frequencies of the VCO feedback clock CGMVDV and the final reference clock CGMRDV Therefore the speed of the lock detector is directly proportional to the final reference MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 103 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC frequency fgpy The circuit determines the mode of the PLL and the lock condition based on this comparison 7 4 4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes Acquisition mode In acquisition mode the filter can make large frequency corrections to the VCO This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency When in acquisition mode the ACQ bit is clear in the PLL bandwidth control register See PLL Bandwidth Control Register Tracking mode In tracking mode the filter makes only small corrections to the frequency of the VCO PLL jitter is much lower in tracking mode but the response to noise is also slower The PLL enters tracking mode when the VCO frequency is nearly correct such as when the PLL
221. d as a slave the SS pin is always configured as an input It cannot be used as a general purpose I O regardless of the state of the MODFEN control bit However the MODFEN bit can still prevent the state of the SS from creating a MODF error See SPI Status and Control Register A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state The slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmission MC68HC908GR8 Rev 4 0 320 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI O Signals When an SPI is configured as a master the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK See Mode Fault Error For the state of the SS pin to set the MODF flag the MODFEN bit in the SPSCK register must be set If the MODFEN bit is low for an SPI master the SS pin can be used as a general purpose I O under the control of the data direction register of the shared I O port With MODFEN high it is an input only pin to the SPI regardless of the state of the data direction register of the shared I O port The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register See Table 20 3 Table 20 3 SPI Configuration
222. d write bits control port D data direction Reset clears DDRD6 DDRD O configuring all port D pins as inputs 1 Corresponding port D pin configured as output 0 Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from O to 1 Figure 16 15 shows the port D I O logic Technical Data MC68HC908GR8 Rev 4 0 222 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Z N READ DDRD 0007 Input Output Ports I O WRITE DDRD 0007 Port D DDRDx RESET WRITE PTD 0003 PTDx INTERNAL DATA BUS PTOPUEx ed READ PTD 0003 U pj O x INTERNAL PULLUP DEVICE Figure 16 15 Port D I O Circuit When bit DDRDx is a logic 1 reading address 0003 reads the PTDx data latch When bit DDRDx is a logic O reading address 0003 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 16 5 summarizes the operation of the port D pins Table 16 5 Port D Pin Functions Accesses to DDRD Accesses to PTD PTDPUE Bit DDRD Bit PTD Bit 1 0 Pin Mode Read Write Read Write 1 0 x Input Vpp DDRDE DDRDO Pin PTDE PTD0 0 0 Input Hi Z DDRD6 DDRDO Pin PTD6
223. de was exited by break TST LOBYTE SP If RETURNLO is not 0 BNE DOLO then just decrement low byte DEC HIBYTE SP Else deal with high byte also DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Break Module BRK 97 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK 6 6 4 Break Flag Control Register The break flag control register SBFCR contains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 6 7 SIM Break Flag Control Register SBFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break Technical Data MC68HC908GR8 Rev 4 0 98 Break Module BRK MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 7 1 Contents 7 2 Introduction Section 7 Clock Generator Module CGMC o Ai cl eoe
224. de Immediate value IX DIndexed with post increment to direct addressing mode Sign extend IX1Indexed 8 bit offset addressing mode Loaded with IX1 Indexed 8 bit offset post increment addressing mode If IX2Indexed 16 bit offset addressing mode Concatenated with MMemory location Set or cleared N Negative bit Not affected 10 9 Opcode Map See Table 10 2 Technical Data MC68HC908GR8 Rev 4 0 154 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU dew epoodo 2Z 01 eiqer suogonisui pexepul Jejulod 4oe s 104 4 q 1d apow Buissaippy salig jo jequnN YIA jueuleJou 150d pexepu eug xId 19eug pexepu q xI djuowauy epoodo 013SYA 0 euiroepexeH ui epoodo jo eig MOT UUM 19SJO ex g L pexepu LXI oeuiq ejeipeuu ANI paiq paiq ad S9 oo S ueujeJou 1S0g JOSHO NA 9 pexepu ZXI pepuex4 1X3 891 UYIIMIOSJO ON pexepu XI SHO 49 8 pexepu LXI paid ula jewjoapexaH ui epoodo jo ei4g yH 0 JesyO Ng 9 4e1utod YIS ZdS 19SJJO ON pexepu XI jeipoww WNI asn 19SyJO 49 8 e utog YIS LAS nl y 134 jueJeuu HNI XI lds IXI e edS v ZXI E IXA E Ha c WMWI HNI L HNI XI k kds j IXI c HNI LIHNI HG Z 134 Ha c Uuld XLS XLS XLS XLS XLS XLS XLS XIV VXL LIVM H10 H10 419 x410 v40 419 HId ZH104 Z41
225. dge on the SPSCK line from its inactive to its active level The SPI clock rate selected by SPR1 SPRO0 affects the delay from the write to SPDR and the start of the SPI transmission See Figure 20 7 The internal SPI clock in the master is a free running derivative of the internal MCU clock To conserve power it is enabled only when both the SPE and SPMSTR bits are set SPSCK edges occur halfway through the low time of the internal MCU clock Since the SPI clock is free running it is uncertain where the write to the SPDR occurs relative to the slower SPSCK This uncertainty causes the variation in the initiation delay shown in Figure 20 7 This delay is no longer than a single SPI bit time That is the maximum delay is two MCU bus cycles for DIV2 eight MCU bus cycles for DIV8 32 MCU bus cycles for DIV32 and 128 MCU bus cycles for DIV128 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 307 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI WRITE ro Sron INITIATION DELAY BUS MOSI MSB BIT 6 BIT5 SPSCK CPHA 1 SPSCK CPHA 0 J SPSCK CYCLE m NUMBER Baa See 3 pia DELAY FROM WRITE SPDR TO TRANSFER BEGIN r WRITE TO SPDR CLOCK SPSCK INTERNAL CLOCK 2 EARLIEST m 2 POSSIBLE START POINTS WRITE LATE TO SPDR BUS CLOCK EARLIEST SPSCK INTERNAL CLOCK 8 LATEST WRIT
226. dicate that a break caused an exit from stop mode or wait mode Address SFE00 Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW R R R R R R R Write Note Reset 0 0 0 0 0 0 0 0 R Reserved Note 1 Writing a logic 0 clears SBSW Figure 19 20 SIM Break Status Register SBSR SBSW SIM Break Stop Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt Clear SBSW by writing a logic O to it Reset clears SBSW 1 Stop mode or wait mode was exited by break interrupt 0 Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine The user can modify the return address on the stack by subtracting one from it The following code is an example of this Writing 0 to the SBSW bit clears it This code works if the H register has been pushed onto the stack in the break Service routine software This code should be executed at the end of the break Service routine software HIBYTE EQU 5 LA LOBYTE EQU 6 If not SBSW do RTI BRCLR SBSW SBSR RETURN See if wait mode or stop mode was exited by break TST LOBYTE SP If RETURNLO is not zero BNE DOLO then just decrement low byte Technical Data MC68HC908GR8 Rev 4 0 294 System Integration Module SIM MOTOROLA For More Information On This Product Go to www fr
227. difficult for unauthorized users Technical Data MC68HC908GR8 Rev 4 0 26 General Description MOTOROLA For More Information On This Product Go to www freescale com MC68HC908GR8 Rev 4 0 Freescale Semiconductor Inc General Description Features 7680 bytes of on chip FLASH memory on the MC68HC908GR8 and 4096 bytes of on chip FLASH memory on the MC68HC908GR4 with in circuit programming capabilities of FLASH program memory 384 bytes of on chip random access memory RAM Serial peripheral interface module SPI Serial communications interface module SCI One 16 bit 2 channel timer TIM1 and one 16 bit 1 channel timer TIM2 interface modules with selectable input capture output compare and PWM capability on each channel e 6 channel 8 bit successive approximation analog to digital converter ADC BREAK module BRK to allow single breakpoint setting during in circuit debugging Internal pullups on IRQ and RST to reduce customer system cost e Clock generator module with on chip 32 kHz crystal compatible PLL phase lock loop e Up to 21 general purpose input output I O pins including 19 shared function I O pins Up to two dedicated I O pins depending on package choice e Selectable pullups on inputs only on ports A C and D Selection is on an individual port bit basis During output mode pullups are disengaged High current 10 mA sink 10 mA source capability on all po
228. ds 145 CPU during break interrupts sonus RR xra kenn 146 Instruction Set Summary xis casxesasadadra rm acria en 147 Gpcode APA Re E ub ded TREE NER 154 The M68HC08 CPU central processor unit is an enhanced and fully object code compatible version of the M68HC05 CPU The CPU08 Reference Manual Motorola document order number CPU08RM AD contains a description of the CPU instruction set addressing modes and architecture 10 3 Features MC68HC908GR8 Rev 4 0 Object code fully upward compatible with M68HC05 Family 16 bit stack pointer with stack manipulation instructions 16 bit index register with x register manipulation instructions 8 MHz CPU internal bus frequency Technical Data MOTOROLA Central Processing Unit CPU 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU 64K byte program data memory space e 16 addressing modes Memory to memory data moves without using accumulator Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions e Enhanced binary coded decimal BCD data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64K bytes Low power stop and wait modes 10 4 CPU registers Figure 10 1 shows the five CPU registers CPU registers are not part of the memory map
229. ductor Inc Electrical Specifications 23 6 3 0 V DC Electrical Characteristics Table 23 5 3 0 V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Output high voltage ILoad 0 6 MA all 1 0 pins Vou Voges u u V ILoad 74 0 MA all I O pins Vou Vpop 1 0 E V ILoad 74 0 mA pins PTCO PTC1 only Vou Vpp 0 5 E V Maximum combined lo for port C port E loH1 30 mA port PTDO PTD3 Maximum combined loj for port PTD4 PTD6 lou 30 mA port A port B Maximum total loj for all port pins lour zd 60 mA Output low voltage ILoad 0 5 MA all 1 0 pins VoL B u d T ILoad 6 0 MA all I O pins VoL a 10 V ILoad 10 0 mA pins PTCO PTC1 only VoL 0 8 V Maximum combined lo for port C port E lout 30 mA port PTDO PTDS3 Maximum combined lo for port PTD4 PTD6 loro EC S 30 mA port A port B Maximum total lo for all port pins lott a m 60 mA Input high voltage All ports IRQs RESET Vin 0 7 x Vpp Vpp V OSC1 0 8 x Vpp Input low voltage All ports IRQs RESET VIL Vss 0 3 x Vpp V OSC1 0 2 x Vpp Vpp Supply current Run lop 4 5 8 mA wait 1 65 4 mA Stop 85 C 1 3 uA Stop 585 C pa 3 6 uA Stop with TBM enabled 9 12 20 uA Stop with LVI and TBM enabled 200 300 uA I O ports Hi Z leakage current liL 10 uA Input current lin 1 uA Technical Data MC68HC908GR8 Rev 4 0 366 Elec
230. e ADC Address 0003E Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 ADIV2 ADIV1 ADIVO ADICLK Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 5 4 ADC Clock Register ADCLK ADIV2 ADIVO ADC Clock Prescaler Bits ADIV2 ADIVO form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC clock Table 5 2 shows the available clock configurations The ADC clock should be set to approximately 1 MHz Table 5 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADIVO ADC Clock Rate 0 0 0 ADC input clock 1 0 0 1 ADC input clock 2 0 1 0 ADC input clock 4 0 1 1 ADC input clock 8 1 X X ADC input clock 16 X don t care ADICLK ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock Reset selects CGMXCLK as the ADC clock source Technical Data MC68HC908GR8 Rev 4 0 88 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC O Registers If the external clock CGMXCLK is equal to or greater than 1 MHz CGMXCLK can be used as the clock source for the ADC If CGMXCLK is less than 1 MHz use the PLL generated bus clock as the clock source As long as the internal ADC clock is at approximately 1 MHz correct operatio
231. e IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode 13 7 Keyboard Module During Break Interrupts Technical Data The system integration module SIM controls whether the keyboard interrupt latch can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state To allow software to clear the keyboard interrupt latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect the latch during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state writing to the keyboard acknowledge bit ACKK in the keyboard status and control register during the break state has no effect See Keyboard Status and Control Register MC68HC908GR8 Rev 4 0 180 Keyboard Interrupt KBI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI O Registers 13 8 I O Registers These registers control and monitor operation of the keyboard module e Keyboard status and control register INTKBSCR Keyboard interrupt enable register INTKBIER 13 8 1 Keyboard Status and Control Register The keyboard status and control register Flags keyboard interrupt req
232. e mask option register MOR most significant bit MSB The leftmost digit of a binary number multiplexer A device that can select one of a number of inputs and pass the logic level of that input on to the output N The negative bit in the condition code register of the CPU08 The CPU sets the negative bit when an arithmetic operation logical operation or data manipulation produces a negative result nibble A set of four bits half of a byte Technical Data MC68HC908GR8 Rev 4 0 400 Glossary MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Glossary object code The output from an assembler or compiler that is itself executable machine code or is suitable for processing to produce executable machine code opcode A binary code that instructs the CPU to perform an operation open drain An output that has no pullup transistor An external pullup device can be connected to the power supply to provide the logic 1 output voltage operand Data on which an operation is performed Usually a statement consists of an operator and an operand For example the operator may be an add instruction and the operand may be the quantity to be added oscillator A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference OTPROM One time programmable read only memory A nonvolatil
233. e the default will revert back to 3V mode after each POR If the Vpp supply is below the 5V mode trip voltage but above the 3V mode trip voltage when POR is released the part will operate because Vp pr defaults to 3V mode after a POR So in a 5V system care must be taken to ensure that Vpp is above the 5V mode trip voltage after POR is released If the user requires 5V mode and sets the LVI5OR3 bit after a POR while the Vpp supply is not above the Vrgipg for 5V mode the MCU will immediately go into reset The LVI in this case will hold the part in reset until either Vpp goes above the rising 5V trip point Vrpjpp which will release reset or Vpp decreases to approximately O V which will re trigger the POR and reset the trip point to 3V operation MC68HC908GR8 Rev 4 0 184 Low Voltage Inhibit LVI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI Functional Description LVISTOP LVIPWRD LVI5OR3 and LVIRSTD are in the configuration register MOR1 See Configuration Register CONFIG for details of the LVI s configuration bits Once an LVI reset occurs the MCU remains in reset until Vpp rises above a voltage Vtpipr which causes the MCU to exit reset See Low Voltage Inhibit LVI Reset for details of the interaction between the SIM and the LVI The output of the comparator controls the state of the LVIOUT flag in the LVI status register LVISR
234. e Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 TxD SCI Transmit Data Output The PTEO TxD pin is the transmit data output for the SCI module When the enable SCI bit ENSCI is clear the SCI module is disabled and the PTE0 TxD pin is available for general purpose I O See Serial Communications Interface SCI 16 7 2 Data Direction Register E Data direction register E DDRE determines whether each port E pin is an input or an output Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin a logic 0 disables the output buffer Address S000C Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 DDRE1 DDREO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 18 Data Direction Register E DDRE DDRE1 and DDREO Data Direction Register E Bits These read write bits control port E data direction Reset clears DDRE1 and DDREO configuring all port E pins as inputs 1 Corresponding port E pin configured as output 0 Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from O to 1 Figure 16 19 shows the port E I O logic Technical Data MC68HC908GR8 Rev 4 0 226 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale c
235. e frequency and amplitude of CGMXCLK can be unstable at startup 7 5 9 CGMC Base Clock Output CGMOUT CGMOUT is the clock output of the CGMC This signal goes to the SIM which generates the MCU clocks CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency CGMOUT is software programmable to be either the oscillator output CGMXCLK divided by two or the VCO clock CGMVCLK divided by two 7 5 10 CGMC CPU Interrupt CGMINT CGMINT is the interrupt signal generated by the PLL lock detector MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 113 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 6 CGMC Registers These registers control and monitor operation of the CGMC e PLL control register PCTL See PLL Control Register e PLL bandwidth control register PBWC See PLL Bandwidth Control Register PLL multiplier select register high PMSH See PLL Multiplier Select Register High PLL multiplier select register low PMSL See PLL Multiplier Select Register Low PLL VCO range select register PMRS See PLL VCO Range Select Register PLL reference divider select register PMDS See PLL Reference Divider Select Register Figure 7 3 is a summary of the CGMC registers Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 id
236. e frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master Therefore the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed MC68HC908GR8 Rev 4 0 302 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc Serial Peripheral Interface SPI Transmission Formats When the master SPI starts a transmission the data in the slave shift register begins shifting out on the MISO pin The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission Otherwise the byte already in the slave shift register shifts out on the MISO pin Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission When the clock phase bit CPHA is set the first edge of SPSCK starts a transmission When CPHA is clear the falling edge of SS starts a transmission See Transmission Formats SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge 20 6 Transmission Formats Du
237. e signal baud rate The total number of bits transmitted per unit of time BCD See binary coded decimal BCD binary Relating to the base 2 number system binary number system The base 2 number system having two digits O and 1 Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels low and high The binary digits O and 1 can be interpreted to correspond to the two digital voltage levels binary coded decimal BCD A notation that uses 4 bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number For example 234 decimal 0010 0011 0100 BCD bit A binary digit A bit has a value of either logic O or logic 1 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Glossary 395 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc branch instruction An instruction that causes the CPU to continue processing at a memory location other than the next sequential address break module A module in the M68HC08 Family The break module allows software to halt program execution at a programmable point in order to enter a background routine breakpoint A number written into the break address registers of the break module When a number appears on the internal address bus that is the same as the number in the break address registers the CPU
238. e time slave lpis s 50 ns Data valid time after enable edge 10 Master tym 60 ns Slave tv s 60 ns Data hold time outputs after enable edge 11 Master tHo M 0 ns Slave tHO s 0 ns Notes 1 Numbers refer to dimensions in Figure 23 16 and Figure 23 17 2 All timing is shown with respect to 2096 Vpp and 7096 Vpp unless noted 100 pF load on all SPI pins 3 Time to data active from high impedance state 4 Hold time to high impedance state 5 With 100 pF on all SPI pins Technical Data MC68HC908GR8 Rev 4 0 380 Electrical Specifications For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Electrical Specifications 3 0 V SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH a O gt SPSCK OUTPUT 5 cPoL 0 NOTE a Da SPSCK OUTPUT 5 POL 2 NOTE lt 4 MISO INPUT MSB IN MOSI OUTPUT Note This first clock edge is generated internally but is not seen at the SPSCK pin a SPI Master Timing CPHA 0 SS E INPUT SS PIN OF MASTER HELD HIGH a 1 SPSCK OUTPUT 5 CPOL 0 4 NOTE SPSCK OUTPUT 5 CPOL 1 4 NOTE MISO INPUT OUTPUT MASTER LSB OUT Note This last clock edge is generated internally but is not seen at the SPSCK pin b SPI Master Timing CPHA 1 Figure 23 16 SPI Master Timing MC68HC908GR8 Rev 4 0 Technical Data
239. e type of memory that cannot be reprogrammed overflow A quantity that is too large to be contained in one byte or one word page zero The first 256 bytes of memory addresses 0000 00FF parity An error checking scheme that counts the number of logic 1s in each byte transmitted In a system that uses odd parity every byte is expected to have an odd number of logic 1s In an even parity system every byte should have an even number of logic 1s In the transmitter a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity A parity checker in the receiver counts the number of logic 1s in each byte The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s PC See program counter PC peripheral A circuit not under direct CPU control phase locked loop PLL A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal PLL See phase locked loop PLL pointer Pointer register An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand and therefore points to the operand polarity The two opposite logic levels logic 1 and logic 0 which correspond to two different voltage levels Vp and Vas polling Periodically reading a status bit to monitor the condition of a periphe
240. ears the SIM counter see SIM Counter but an external reset does not Each of the resets sets a corresponding bit in the SIM reset status register SRSR See SIM Registers 19 4 4 External Pin Reset The RST pin circuit includes an internal pullup device Pulling the asynchronous RST pin low halts all processing The PIN bit of the SIM reset status register SRSR is set as long as RST is held low for a minimum of 67 CGMXCLK cycles assuming that neither the POR nor the LVI was the source of the reset See Table 19 2 for details Figure 19 4 shows the relative timing Table 19 2 PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR LVI 4163 4096 64 3 All others 67 64 3 CGMOUT RST e CPE Ere Figure 19 4 External Reset Timing 19 4 2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals The internal reset signal IRST continues to be asserted for an additional 32 cycles See Figure 19 5 An internal reset can be caused by an illegal address illegal opcode COP timeout LVI or POR See Figure 19 6 NOTE For LVI or POR resets the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low The i
241. eatures of the SCI module include e Full duplex operation Standard mark space non return to zero NRZ format e 32 programmable baud rates e Programmable 8 bit or 9 bit character length e Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Programmable transmitter output polarity Two receiver wakeup methods Idle line wakeup Address mark wakeup e nterrupt driven operation with eight interrupt flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection Hardware parity checking e 1 16 bit time noise detection Configuration register bit SCIBDSRC to allow selection of baud rate clock source Technical Data MC68HC908GR8 Rev 4 0 232 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Pin Name Conventions 18 4 Pin Name Conventions The generic names of the SCI I O pins are e RxD receive data e TxD transmit data SCI I O input output lines are implemented by sharing parallel I O port pins The full name of an SCI input or output reflects the name of the shared port pin Table 18 1 shows the full names and the generic names of the SCI I O pins The generic pin names
242. echnical Data MC68HC908GR8 Rev 4 0 59 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes Technical Data MC68HC908GR8 Rev 4 0 60 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 4 Resets and Interrupts 4 1 Contents 4 2 aaa TNT EET TTL 61 4 3 Foo curasse dere d c dO bU RR ee ee ee LO EROR EE NAA 61 a NS oii oe epee d e DE dE OR ORE 9 Rr abet 66 4 2 Introduction Resets and interrupts are responses to exceptional events during program execution A reset re initializes the MCU to its startup condition An interrupt vectors the program counter to a service routine 4 3 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user defined memory location 4 3 1 Effects A reset Immediately stops the operation of the instruction being executed Initializes certain control and status bits Loads the program counter with a user defined reset vector address from locations SFFFE and FFFF Selects CGMXCLK divided by four as the bus clock MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 61 For More Information On This Product Go to www freescale com 4 3 2 External Reset 4 3 3 Internal Reset Freescale Semiconducto
243. ed 363 Maximum operating temperature increased to 125 C Electrical 376 377 Maximum temperature increased to 125 C in titles of figures 23 Specifications 13 23 14 and 23 15 383 Maximum operating temperature increaed to 125 C Drenng 391 New section added Information Changes from Rev 1 0 published in April 2001 to Rev 2 0 published in December 2001 Section Page in Rev 2 0 Description of change The blank state of the reset vectors F FFE and FFFF was incorrectly defined as 00 and is now FF This affects several places in the Monitor ROM MON section The information was previously described in an addendum See details below Monitor ROM 190 Penultimate bullet of features list MON 192 Final sentence of first paragraph Each list item in Entering Monitor Mode section 193 Third column of Table 15 1 Timebase Module ens TBM 329 Several changes for clarification Finer imanaoa 335 Several changes for clarification Module TIM 9 Electrical 385 Typical column added to table Typical values added for FLASH Specifications row program endurance and FLASH data retention time Technical Data MC68HC908GR8 Rev 4 0 406 Revision History MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH
244. eescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description SCI receiver full bit SCRF The idle line type bit ILTY determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit NOTE With the WAKE bit clear setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately 18 5 3 9 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver e SCl receiver full SCRF The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR SCRF can generate a receiver CPU interrupt request Setting the SCI receive interrupt enable bit SCRIE in SCC2 enables the SCRF bit to generate receiver CPU interrupts e Idle input IDLE The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the PE1 RxD pin The idle line interrupt enable bit ILIE in SCC2 enables the IDLE bit to generate CPU interrupt requests 18 5 3 10 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests Receiver overrun OR The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR The previous character remains in the SCDR and the new character is lost The overrun interrupt enable bit ORIE in SC
245. eescale com Freescale Semiconductor Inc System Integration Module SIM DEC HIBYTE SP Else deal with high byte too DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI 19 8 2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared Clear the SIM reset status register by reading it A power on reset sets the POR bit and clears all other bits in the register Address SFE01 Bit 7 6 5 4 3 2 1 Bit 0 Read POR PIN COP ILOP ILAD MODRST LVI 0 Write Reset 1 0 0 0 0 0 0 0 Unimplemented Figure 19 21 SIM Reset Status Register SRSR POR Power On Reset Bit 1 Last reset caused by POR circuit 0 Read of SRSR PIN External Reset Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode Reset Bit 1 Last reset caused by an illegal opcode 0 POR or read of SRSR Technical Data MC68HC908GR8 Rev 4 0 295 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM ILAD Illegal Address Reset Bit opcode fetches only 1 Last reset caused by an opc
246. emains set until a vector fetch software clear or reset occurs When an interrupt pin is both falling edge and low level triggered the interrupt remains set until both of the following occur e Vector fetch or software clear Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1 As long as the pin is low the interrupt request remains pending A reset will clear the latch and the MODE control bit thereby clearing the interrupt even if the pin stays low When set the IMASK bit in the INTSCR mask all external interrupt requests A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear MC68HC908GR8 Rev 4 0 168 External Interrupt IRQ MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ Functional Description NOTE The interrupt mask I in the condition code register CCR masks all interrupt requests including external interrupt requests ACK RESET D gt 2 TO CPU FOR m VECTOR BIL BIH i FETCH INSTRUCTIONS a VDD lt z INTERNAL V 2 PULLUP Kag IRQF m DEVICE Rat n INTERRUPT REQUEST NC HIGH TO MODE VOLTAGE SELECT
247. en writing a logic O to CHxF If another interrupt request occurs before the clearing sequence is complete then writing logic 0 to CHxF has no effect Therefore an interrupt request cannot be lost due to inadvertent clearing of CHxF Reset clears the CHxF bit Writing a logic 1 to CHxF has no effect 1 Input capture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIM CPU interrupt service requests on channel x Reset clears the CHxIE bit 1 Channel x CPU interrupt service requests enabled 0 Channel x CPU interrupt service requests disabled MSxB Mode Select Bit B This read write bit selects buffered output compare PWM operation MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers Setting MSOB disables the channel 1 status and control register and reverts TCH1 to general purpose l O Reset clears the MSxB bit 1 Buffered output compare PWM operation enabled 0 Buffered output compare PWM operation disabled MSxA Mode Select Bit A When ELSxB A z 00 this read write bit selects either input capture operation or unbuffered output compare PWM operation See Table 22 3 1 Unbuffered output compare PWM operation Technical Data MC68HC908GR8 Rev 4 0 356 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com NOTE Fre
248. entre of leads when formed parallel M 0 15 4 Dimension B does not include mould protrusion G 2 54 BSC N 0 51 1 02 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Mechanical Specifications 389 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 24 5 28 Pin SOIC Case 751F 14PL E B P IGBlo25 M B M LE MAA 4 de 77 Seating Plane Dim Min Max Notes Dim Min Max A 17 80 18 05 J 0 229 0 317 B 7 40 7 60 1 Dimensions A and B are datums and T is a datum surface K 0 127 0 292 C 2 35 2 65 2 Dimensioning and tolerancing per ANSI Y14 5M 1982 M 0 8 3 All dimensions in mm D 0 35 049 4 Dimensions A and B do not include mould protrusion P 10 05 10 55 F 0 41 0 90 5 Maximum mould protrusion is 0 15 mm per side R 0 25 0 75 G 1 27 BSC m Technical Data MC68HC908GR8 Rev 4 0 390 Mechanical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Se
249. equence SENT TO MONITOR ADDRESS VADDRESSV ADDRESS ADDRES JA READ READ HIGH HIGH LOW LOW DATA ECHO RETURN Table 15 5 WRITE Write Memory Command Description Write byte to memory Operand 2 byte address in high byte low byte order low byte followed by data byte Dala None Returned Opcode 49 Command Sequence FROM HOST ADDRESS ADDRES J ware WRITE HERI baa ECHO MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 199 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Technical Data Table 15 6 IREAD Indexed Read Command Description Read next 2 bytes in memory from last address accessed Operand 2 byte address in high byte low byte order Data Returns contents of next two addresses Returned Opcode SIA Command Sequence FROM HOST f IREAD IREAD DATA DATA ECHO d RETURN Table 15 7 IWRITE Indexed Write Command Description Write to last address accessed 1 Operand Single data byte Data None Returned Opcode 19 Command Sequence ECHO MC68HC908GR8 Rev 4 0 200 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description A sequen
250. er SBFCR Protecting flags in break mode ensures that set flags will not be cleared while in break mode This protection allows registers to be freely read and written during break mode without losing status flag information Setting the BCFE bit enables the clearing mechanisms Once cleared in break mode a flag remains cleared even when break mode is exited Status flags with a 2 step clearing mechanism for example a read of one register followed by the read or write of another are protected even when the first step is accomplished prior to entering break mode Upon leaving break mode execution of the second step will clear the flag as normal 19 7 Low Power Modes 19 7 1 Wait Mode Technical Data Executing the WAIT or STOP instruction puts the MCU in a low power consumption mode for standby situations The SIM holds the CPU in a non clocked state The operation of each of these modes is described in the following subsections Both STOP and WAIT clear the interrupt mask 1 in the condition code register allowing interrupts to occur In wait mode the CPU clocks are inactive while the peripheral clocks continue to run Figure 19 15 shows the timing for wait mode entry A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred In wait mode the CPU clocks are inactive
251. er data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 18 7 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles 3 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit character with no errors is 154 147 154 x 100 4 54 For a 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles MC68HC908GR8 Rev 4 0 246 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description With the misaligned character shown in Figure 18 7 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 3 RT cycles 163 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 9 bit character with no errors is 170 163 1100 4 12 170 18 5 3 7 Fast Data Tolerance Figure 18 8 shows how much a fast received character can be misaligned without causing a noise error or a framing error The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data sa
252. er High TCHOH 360 22 15 TIM Channel O Register Low TCHOL 360 22 16 TIM Channel 1 Register High TCH1H 360 22 17 TIM Channel 1 Register Low TCH1iL 360 23 1 Typical High Side Driver Characteristics Port PTA3 PTAO Vpp 4 5 Vdc LLsluuss 370 23 2 Typical High Side Driver Characteristics Port PTA3 PTAD Vpn 2 7 VOC oc na naa KAG AKA n naan 370 23 3 Typical High Side Driver Characteristics Port PTCH PTOO Vpp 4 5 YAO ci naaa kA 371 23 4 Typical High Side Driver Characteristics Port PTCI PTCO Vpp 2 7 VJ asawa kaaa aaa n Re 371 23 5 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 5 5 Vdc 372 23 6 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 2 7 Vdc 372 23 7 Typical Low Side Driver Characteristics Poit PTAS PTAO Vpp 5 5 Vdo naana KA esse RR 373 23 8 Typical Low Side Driver Characteristics Pot PTAS PTAO Vpn 27 VOC das ees naaa ver ERAS 373 23 9 Typical Low Side Driver Characteristics Port PTC1 PTCO Vpp 4 5 VdB ci saka esr kr teda 374 23 10 Typical Low Side Driver Characteristics Port PTCT FTOD Vpp 2 7 VB s acoccsases s Ras 374 23 11 Typical Low Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 5 5 Vdc 375 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA L
253. erflows is the period of the PWM signal As Figure 22 3 shows the output compare value in the TIM channel registers determines the pulse width of the PWM signal The time between overflow and output compare is the pulse width Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1 Program the TIM to set the pin if the state of the PWM pulse is logic O The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8 bit PWM signal is variable in 256 increments Writing SOOFF 255 to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 See TIM Status and Control Register OVERFLOW OVERFLOW OVERFLOW 4 PERIOD a gt a PULSE WIDTH Y Y PTEx TCHx A A A OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 22 3 PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output The pulse width of an 8 bit PWM signal is variable in 256 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 343 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM increments Writing 50080 128 to the TIM channel registers produces a duty cycle
254. error PE PEIE SCI receiver full SCRF SCRIE SCI input idle IDLE ILIE io ka a SCI transmitter empty SCTE SCTIE IF13 13 FFE2 FFE3 SCI transmission complete TC TCIE Keyboard pin KEYF IMASKK IF 14 14 FFDE FFDF ADC conversion complete COCO AIEN IF15 15 FFDE FFDF Timebase TBIF TBIE IF16 16 FFDC FFDD Note 1 The bit in the condition code register is a global mask for all interrupt sources except the SWI instruction 2 0 highest priority Technical Data MC68HC908GR8 Rev 4 0 70 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com 4 421 SW I Instruction Freescale Semiconductor Inc Resets and Interrupts Interrupts The software interrupt instruction SWI causes a non maskable interrupt NOTE A software interrupt pushes PC onto the stack An SWI does not push PC 1 as a hardware interrupt does 4 4 2 2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software programmable break point 4 4 2 3 IRQ Pin A logic 0 on the IRQ1 pin latches an external interrupt request 4 4 2 4 CGM The CGM can generate a CPU interrupt request every time the phase locked loop circuit PLL enters or leaves the locked state When the LOCK bit changes state the PLL flag PLLF is set The PLL interrupt enable bit PLLIE enables PLLF CPU interrupt requests LOCK is in the PLL bandwidth control register PLLF is in the PLL
255. errupts Interrupts FROM RESET BREA INTERRUPT NO YES YES NO IRQ YES INTERRUPT NO CGM YES INTERRUPT NO 2 OTHER yes lt INTERRUPTS gt gt STACK CPU REGISTERS SET BIT LOAD PC WITH INTERRUPT VECTOR NO RTI YES INSTRUCTION gt UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 4 6 Interrupt Processing MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts 4 4 2 Sources The sources in Table 4 1 can generate CPU interrupt requests Table 4 1 Interrupt Sources Source Flag Mask ING a Priority rud Reset None None None 0 SFFFE SFFFF SWI instruction None None None 0 FFFC FFFD IRQ pin IRQF IMASK1 IF1 1 SFFFA SFFFB CGM PLL PLLF PLLIE IF2 2 FFF8 FFF9 TIM1 channel 0 CHOF CHOIE IF3 3 FFF6 FFF7 TIM1 channel 1 CH1F CH1IE IF4 4 FFF4 FFF5 TIM1 overflow TOF TOIE IF5 5 FFF2 FFF3 TIM2 channel 0 CHOF CHOIE IFG 6 FFFO FFF 1 TIM2 overflow TOF TOIE IF8 8 FFEC FFED SPI receiver full SPRF SPRIE SPI overflow OVRF ERRIE IF9 9 FFEA FFEB SPI mode fault MODF ERRIE SPI transmitter empty SPTE SPTIE IF10 10 FFE8 FFE9 SCI receiver overrun OR ORIE SCI noise fag NF NEIE SCI framing error FE FEIE Hi ka a SCI parity
256. ersion The COCO IDMAS bit is not used as a conversion complete flag when interrupts are enabled 4 4 2 11 TBM Timebase Module The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2 TBRO When the timebase counter chain rolls over the TBIF flag is set If the TBIE bit is set enabling the timebase interrupt the counter chain overflow will generate a CPU interrupt request Interrupts must be acknowledged by writing a logic 1 to the TACK bit Technical Data MC68HC908GR8 Rev 4 0 74 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Interrupts 4 4 3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources Table 4 2 summarizes the interrupt sources and the interrupt status register flags that they set The interrupt status registers can be useful for debugging Table 4 2 Interrupt Source Flags Interrupt Source Interrupt Status Register Flag Reset SWI instruction IRQ pin IF1 CGM PLL IF2 TIM1 channel 0 IF3 TIM1 channel 1 IF4 TIM1 overflow IF5 TIM2 channel 0 IF6 Reserved IF7 TIM2 overflow IF8 SPI receive IF9 SPI transmit IF10 SCI error IF11 SCI receive IF12 SCI transmit IF13 Keyboard IF14 ADC conversion complete IF15 Timebase IF16 MC68HC908GR8
257. escale Semiconductor Inc Timer Interface Module TIM O Registers 0 Input capture operation When ELSxB A 00 this read write bit selects the initial output level of the TCHx pin See Table 22 3 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high Before changing a channel function by writing to the MSxB or MSxA bit set the TSTOP and TRST bits in the TIM status and control register TSC ELSxB and ELSxA Edge Level Select Bits MC68HC908GR8 Rev 4 0 When channel x is an input capture channel these read write bits control the active edge sensing logic on channel x When channel x is an output compare channel ELSxB and ELSxA control the channel x output behavior when an output compare occurs When ELSxB and ELSxA are both clear channel x is not connected to port D and pin PTDx TCHx is available as a general purpose I O pin Table 22 3 shows how ELSxB and ELSxA work Reset clears the ELSxB and ELSxA bits Technical Data MOTOROLA Timer Interface Module TIM 357 For More Information On This Product Go to www freescale com Technical Data NOTE NOTE Freescale Semiconductor Inc Timer Interface Module TIM Table 22 3 Mode Edge and Level Selection 00 Input capture 11 MSxB MSxA ELSxB ELSxA Mode Configuration Pin under port control AG sg initial output level high Output preset NG 00 Pin under port control initial output l
258. ev 4 0 82 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Interrupts 5 4 5 Accuracy and Precision 5 5 Interrupts The conversion process is monotonic and has no missing codes When the AIEN bit is set the ADC module is capable of generating CPU interrupts after each ADC conversion A CPU interrupt is generated if the COCO IDMAS bit is at logic 0 If COCO IDMAS bit is set a DMA interrupt is generated The COCO IDMAS bit is not used as a conversion complete flag when interrupts are enabled 5 6 Low Power Modes 5 6 1 Wait Mode 5 6 2 Stop Mode The WAIT and STOP instruction can put the MCU in low power consumption standby modes The ADC continues normal operation during wait mode Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting ADCH4 ADCHO bits in the ADC status and control register before executing the WAIT instruction The ADC module is inactive after the execution of a STOP instruction Any pending conversion is aborted ADC conversions resume when the MCU exits stop mode after an external interrupt Allow one conversion cycle to stabilize the analog circuitry 5 7 I O Signals The ADC module has six pins shared with port B PTB5 AD5 PTBO ATDO MC68HC908GR8
259. evel low 00 01 Capture on rising edge only 00 10 Capture on falling edge only Capture on rising or falling edge 01 01 Toggle output on compare Output 01 10 compare or Clear output on compare PWM 01 11 Set output on compare 1X 01 Buffered Toggle output on compare 1X 10 output Clear output on compare compare or 1X 11 buffered PWM Set output on compare Before enabling a TIM channel register for input capture operation make sure that the PTD TCHx pin is stable for at least two bus clocks TOVx Toggle On Overflow Bit When channel x is an output compare channel this read write bit controls the behavior of the channel x output when the TIM counter overflows When channel x is an input capture channel TOVx has no effect Reset clears the TOVx bit 1 Channel x pin toggles on TIM counter overflow 0 Channel x pin does not toggle on TIM counter overflow When TOVx is set a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time MC68HC908GR8 Rev 4 0 358 For More Information On This Product Timer Interface Module TIM Go to www freescale com MOTOROLA Freescale Semiconductor Inc Timer Interface Module TIM O Registers CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1 setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As CHxMAX Latency shows the CHxMAX bit t
260. execution of a WAIT instruction In wait mode the SPI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode If SPI module functions are not required during wait mode reduce power consumption by disabling the SPI module before executing the WAIT instruction To exit wait mode when an overflow condition occurs enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit ERRIE See Interrupts The SPI module is inactive after the execution of a STOP instruction The STOP instruction does not affect register conditions SPI operation resumes after an external interrupt If stop mode is exited by reset any transfer in progress is aborted and the SPI is reset MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 317 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 12 SPI During Break Interrupts 20 13 I O Signals Technical Data The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See System Integration Module SIM To allow software to clear status bits during a break interrupt write a logic 1 to the
261. f 64 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC NOTE The multiplier select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 PMSH 7 4 Unimplemented Bits These bits have no function and always read as logic Os 7 6 4 PLL Multiplier Select Register Low The PLL multiplier select register low PMSL contains the programming information for the low byte of the modulo feedback divider Address 0038 Bit 7 6 5 4 3 2 1 Bit 0 Read MUL7 MUL6 MUL5 MULA MUL3 MUL2 MUL1 MULO Write Reset 0 1 0 0 0 0 0 0 Figure 7 7 PLL Multiplier Select Register Low PMSL MUL7 MULO Multiplier Select Bits These read write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier N See PLL Circuits and Programming the PLL MUL7 MULO cannot be written when the PLLON bit in the PCTL is set A value of 0000 in the multiplier select registers configures the modulo feedback divider the same as a value of 0001 Reset initializes the register to 40 for a default multiply value of 64 NOTE The multiplier select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 Technical Data MC68HC908GR8 Rev 4 0 12
262. f CGMXCLK is not guaranteed to be 50 and depends on external factors including the crystal and related external components An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit Connect the external clock to the OSC1 pin and let the OSC2 pin float 7 4 2 Phase Locked Loop Circuit PLL 7 4 3 PLL Circuits Technical Data The PLL is a frequency generator that can operate in either acquisition mode or tracking mode depending on the accuracy of the output frequency The PLL can change between acquisition and tracking modes either automatically or manually The PLL consists of these circuits e Voltage controlled oscillator VCO Reference divider Frequency prescaler Modulo VCO frequency divider Phase detector Loop filter e Lock detector MC68HC908GR8 Rev 4 0 102 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise including supply and CGM XFC noise The VCO frequency is bound to a range from roughly one half to twice the center of range frequency fyps Modulating the voltage on the CGM XFC pin changes the frequency within this range By design fyps is equal to the nominal center of range frequency fuoy 38
263. freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI Technical Data If the MODEK bit is set the keyboard interrupt pins are both falling edge and low level sensitive and both of the following actions must occur to clear a keyboard interrupt request e Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the interrupt request Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register INTKBSCR The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins A falling edge that occurs after writing to the ACKK bit latches another interrupt request If the keyboard interrupt mask bit IMASKK is clear the CPU loads the program counter with the vector address at locations FFDE and FFDF Return of all enabled keyboard interrupt pins to logic 1 As long as any enabled keyboard interrupt pin is at logic O the keyboard interrupt remains set The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order If the MODEK bit is clear the keyboard interrupt pin
264. from the CGMOUT output from the CGM The CPU clock frequency is equal to the frequency of the oscillator output CGMXCLK divided by four CPU cycles A CPU cycle is one period of the internal bus clock normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal The length of time required to execute an instruction is measured in CPU clock cycles CPU registers Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map The CPU always has direct access to the information in these registers The CPU registers in an M68HC08 are A 8 bit accumulator H X 16 bit index register SP 16 bit stack pointer PC 16 bit program counter e CCR condition code register containing the V H I N Z and C bits CSIC customer specified integrated circuit cycle time The period of the operating frequency teyc 1 fop decimal number system Base 10 numbering system that uses the digits zero through nine MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Glossary 397 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc direct memory access module DMA A M68HC08 Family module that can perform data transfers between any two CPU addressable locations without CPU intervention For transmitting or receiving blocks of data to or from peripherals DMA transfers are faster
265. fter the stop bit avoids false idle character recognition but requires properly synchronized transmissions Reset clears the ILTY bit 1 Idle character bit count begins after stop bit 0 Idle character bit count begins after start bit PEN Parity Enable Bit This read write bit enables the SCI parity function See Table 18 5 When enabled the parity function inserts a parity bit in the most significant bit position See Figure 18 3 Reset clears the PEN bit 1 Parity function enabled 0 Parity function disabled PTY Parity Bit This read write bit determines whether the SCI generates and checks for odd parity or even parity See Table 18 5 Reset clears the PTY bit 1 Odd parity 0 Even parity Technical Data MC68HC908GR8 Rev 4 0 254 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI O Registers NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error Table 18 5 Character Format Selection Control Bits Character Format M PEN and Start Data Parity Stop Character PTY Bits Bits Bits Length 0 OX 1 8 None 1 10 bits 1 OX 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 18 9 2 SCI Control Register 2 SCI control re
266. ge location MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU 10 4 3 Stack pointer SP NOTE The stack pointer is a 16 bit register that contains the address of the next location on the stack During a reset the stack pointer is preset to 00FF The reset stack pointer RSP instruction sets the least significant byte to SFF and does not affect the most significant byte The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack In the stack pointer 8 bit offset and 16 bit offset addressing modes the stack pointer can function as an index register to access data on the stack The CPU uses the contents of the stack pointer to determine the conditional address of the operand Reset 0 0 0 0 0 0 O O 1 1 1 1 1 1 1 1 Figure 10 4 Stack pointer SP The location of the stack is arbitrary and may be relocated anywhere in RAM Moving the SP out of page zero 50000 to 00FF frees direct address page zero space For correct operation the stack pointer must point only to RAM locations 10 4 4 Program counter PC Technical Data The program counter is a 16 bit register that contains the address of the next instruction or operand to be fetched Normally the progra
267. ge during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit Port D shares three of its pins with the TIM There is an optional TCLK which can be used as an external clock input to the TIM prescaler but is not available on this MCU The three TIM channel I O pins are T1CHO T1CH1 and T2CHO as described in Pin Name Conventions Each channel I O pin is programmable independently as an input capture pin or an output compare pin T1CHO and T2CHO can be configured as buffered output compare or buffered PWM pins MC68HC908GR8 Rev 4 0 348 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM O Registers 22 10 I O Registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TSC may generically refer to both T1SC AND T2SC These I O registers control and monitor operation of the TIM e TIM status and control register TSC e TIM control registers TCNTH TONTL e TIM counter modulo registers TMODH TMODL e TIM channel status and control registers TSCO TSC1 e TIM channel registers TCHOH TCHOL TCH1H TCH1L 22 10 1 TIM Status and Control Register The TIM status and control register TSC Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter e
268. gister T2SC Write 0 TRST Reset 0 0 1 0 0 0 0 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Timer 2 Counter Register 002C High T2CNTH Write Reset 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 Timer 2 Counter Register 002D Low T2CNTL Write Reset 0 0 0 0 0 0 0 0 er Bit 15 14 13 12 11 10 9 Bit 8 i j 002E Timer 2 Counter Modulo Write Register High T2MODH Reset 1 1 1 1 1 1 1 1 Pid Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Counter Modulo l l 002F Register Low T2MODL tte Reset 1 1 1 1 1 1 1 1 i Read CHOF Timer 2 Channel 0 Status l CHOIE MS0B MS0A ELSOB ELSOA TOVO CHOMAX 0030 and Control Register Write 0 T2SCO Reset 0 0 0 0 0 0 0 0 ki Bit 15 14 13 12 11 10 9 Bit 8 i j 0031 Timer 2 Channel 0 Write Register High T2CHOH Reset Indeterminate after reset Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 5 of 8 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 43 For More Information On This Product Go to www freescale com Addr 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B Freescale Semiconductor Inc Memory Map Register Name Read Timer 2 Channel 0 Write Register Low T2CHOL Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read Write Reset Read PLL Control Register PCTL PLL Bandwid
269. gister 2 Enables the following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests e Enables the transmitter e Enables the receiver Enables SCI wakeup e Transmits SCI break characters MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 255 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Address S0014 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 18 10 SCI Control Register 2 SCC2 SCTIE SCI Transmit Interrupt Enable Bit This read write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests Reset clears the SCTIE bit 1 SCTE enabled to generate CPU interrupt 0 2 SCTE not enabled to generate CPU interrupt TCIE Transmission Complete Interrupt Enable Bit This read write bit enables the TC bit to generate SCI transmitter CPU interrupt requests Reset clears the TCIE bit 1 TC enabled to generate CPU interrupt requests 0 TC not enabled to generate CPU interrupt requests SCRIE SCI Receive Interrupt Enable
270. gned branch instructions BGT BGE BLE and BLT use the overflow flag 1 Overflow 0 No overflow H Half carry flag MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU 143 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor 1 Carry between bits 3 and 4 0 No carry between bits 3 and 4 Interrupt mask When the interrupt mask is set all maskable CPU interrupts are disabled CPU interrupts are enabled when the interrupt mask is cleared When a CPU interrupt occurs the interrupt mask is set automatically after the CPU registers are saved on the stack but before the interrupt vector is fetched 1 Interrupts disabled 0 Interrupts enabled NOTE To maintain M6805 compatibility the upper byte of the index register H is not stacked automatically If the interrupt service routine modifies H then the user must stack and unstack H using the PSHH and PULH instructions After the bit is cleared the highest priority interrupt request is serviced first A return from interrupt RTI instruction pulls
271. h M A M t It11 1 IX1 E1 f 3 CMP X IX F1 2 CMP opr SP SP1 9EE1 ff 4 CMP opr SP SP2 9ED1 eeff 5 COM opr M c M FF M DIR 33 dd 4 COMA A lt A FF M INH 43 1 COMX X X FF M la INH 53 1 COM oprX Complement One s Complement M M SFF M 0 O OR xi 63 f 4 COM X M lt M SFF M IX 73 3 COM opr SP M lt M FF M SP1 9E63 ff 5 CPHX opr LY wi 3 IMM 65 jiiii 1 3 CPHX opr Compare H X with M H X M M 1 ti j t ot d DIR 75 Idd 4 CPX opr IMM A3 fii 2 CPX opr DIR B3 dd 3 CPX opr EXT C3 hhll 4 CPX X IX2 D3 jee ff 4 CPX oprX Compare X with M X M t It11 1 IX1 E3 f 3 CPX opr X IX F3 2 CPX opr SP SP1 9EE3 ff 4 CPX opr SP SP2 9ED3 Jee ff 5 DAA Decimal Adjust A Ajo U 2 2 3 INH 72 2 A A 1 or M M 1 or X X 1 5 DBNZ opr rel PC lt PC 3 rel result 0 DIR 3B ddrr 3 DBNZA rel PC lt PC 2 rel result 0 INH 4B rr 3 DBNZX rel Decrement and Branch if Not Zero PC c PC 2 rel result 0 INH 5B ir 5 DBNZ opr X rel PC lt PC 3 rel result 0 IX1 6B frr 4 DBNZ X rel PC lt PC 2 rel result 0 IX 7B rr 6 DBNZ opr SP rel PC c PC 4 rel result 0 SP1 9E6B ff rr DEC opr M M 1 DIR 3A dd 4 DECA Ac A 1 INH 4A 1 DECX X X 1 INH 5A 1 DEC opr X Decrement M c M 1 t ix 6A f 4 DEC X Me M 1 IX 7A 3 DEC opr SP Me M 1 SP1 9E6A ff 5 Ae H A X DIV Div
272. haracter Reception During an SCI reception the receive shift register shifts characters in from the PE1 RxD pin The SCI data register SCDR is the read only buffer between the internal data bus and the receive shift register After a complete character shifts into the receive shift register the data portion of the character transfers to the SCDR The SCI receiver full bit SCRF in SCI status register 1 SCS1 becomes set indicating that the received byte can be read If the SCI receive interrupt enable bit SCRIE in SCC2 is also set the SCRF bit generates a receiver CPU interrupt request MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 241 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI INTERNAL BUS SCIBDSRC SCR1 FROM CONFIG2 SCP SCR SCP0 m SCRO PRE SL 0 gt X A SL 1 gt X B BAUD SCALER DIVIDER DATA d 11 BIT SCI DATA REGISTER RECEIVE SHIFT REGISTER r START PE1 RxD RECOVERY 7 6 5 4 3 2 1 ALLO B
273. he IMASKK bit in the keyboard status and control register 2 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3 Write to the ACKK bit in the keyboard status and control register to clear any false interrupts 4 Clear the IMASKK bit An interrupt signal on an edge triggered pin can be acknowledged immediately after enabling the pin An interrupt signal on an edge and level triggered interrupt pin must be acknowledged after a delay that depends on the external load Another way to avoid a false interrupt is 1 Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A 2 Write logic 1s to the appropriate port A data register bits 3 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Keyboard Interrupt KBI 179 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI 13 6 Low Power Modes 13 6 1 Wait Mode 13 6 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The keyboard module remains active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode The keyboard module remains active in stop mode Clearing th
274. he input voltage equals Vpepr the ADC converts it to 00 Input voltages between Vggr and Vpger are a straight line linear conversion All other input voltages will result in FF if greater than Vnggg Inside the ADC module the reference voltage Veer His connected to the ADC analog power Vppap and Vpepy is connected to the ADC analog ground Vppap Therefore the ADC input voltage should not exceed the analog supply voltages For operation Vppap should be tied to the same potential as Vpp via separate traces 5 4 3 Conversion Time 5 4 4 Conversion Technical Data Conversion starts after a write to the ADSCR One conversion will take between 16 and 17 ADC clock cycles The ADIVx and ADICLK bits should be set to provide a 1 MHz ADC clock frequency 16 to17 ADC cycles Conversion time a ADC frequency Number of bus cycles conversion time x bus frequency In continuous conversion mode the ADC data register will be filled with new data after each conversion Data from the previous conversion will be overwritten whether that data has been read or not Conversions will continue until the ADCO bit is cleared The COCO IDMAS bit is set after the first conversion and will stay set until the next write of the ADC status and control register or the next read of the ADC data register In single conversion mode conversion begins with a write to the ADSCR Only one conversion occurs between writes to the ADSCR MC68HC908GR8 R
275. he voltage on the V pin and can force a reset when the Vpp voltage falls below the LVI trip falling voltage Vrmipr 14 3 Features Features of the LVI module include Programmable LVI reset Selectable LVI trip voltage e Programmable stop mode operation MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Voltage Inhibit LVI 183 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI 14 4 Functional Description NOTE NOTE Technical Data Figure 14 1 shows the structure of the LVI module The LVI is enabled out of reset The LVI module contains a bandgap reference circuit and comparator Clearing the LVI power disable bit LVIPWRD enables the LVI to monitor Vpp voltage Clearing the LVI reset disable bit LVIRSTD enables the LVI module to generate a reset when Vpp falls below the trip point voltage Vrpipr Setting the LVI enable in stop mode bit LVISTOP enables the LVI to operate in stop mode Setting the LVI 5V or 3V trip point bit LVISOR3 enables V rpjpr to be configured for 5V operation Clearing the LVI5OR3 bit enables V7pjpp to be configured for 3V operation The actual trip points are shown in Electrical Specifications After a power on reset POR the LVI s default mode of operation is 3 V If a 5V system is used the user must set the LVI5OR3 bit to raise the trip point to 5V operation Note that this must be done after every POR sinc
276. hen the data register is read or the status control register is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disabled ADCO ADC Continuous Conversion Bit When this bit is set the ADC will convert samples continuously and update the ADR register at the end of each conversion Only one conversion is completed between writes to the ADSCR when this bit is cleared Reset clears the ADCO bit 1 Continuous ADC conversion 0 One ADC conversion ADCH4 ADCHO ADC Channel Select Bits ADCH4 ADCHO form a 5 bit field which is used to select one of 16 ADC channels Only six channels AD5 ADO are available on this MCU The channels are detailed in Table 5 1 Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal See Table 5 1 The ADC subsystem is turned off when the channel select bits are all set to 1 This feature allows for reduced power consumption for the MCU when the ADC is not being used Recovery from the disabled state requires one conversion cycle to stabilize The voltage levels supplied from internal reference nodes as specified in Table 5 1 are used to verify the operation of the ADC converter both in production test and for user applications Table 5 1 Mux Channel Select ADCHA ADCHS3 ADCH2 ADCH1 ADCHO Input Select 0 0 0 0 0 PTBO ATDO 0 0 0 0 1 PTB1 ATD1 0 0 0 1 0 PT
277. his read only flag bit is set when the timebase counter has rolled Over 1 Timebase interrupt pending 0 Timebase interrupt not pending TBR2 TBRO Timebase Rate Selection These read write bits are used to select the rate of timebase interrupts as shown in Table 21 1 Table 21 1 Timebase Rate Selection for OSC1 32 768 kHz MC68HC908GR8 Rev 4 0 TBR2 TBR1 TBRO Divider Timebase Interrupt Rate Hz ms 0 0 0 32 768 1 1000 0 1 8192 4 250 0 1 0 2048 16 62 5 0 1 1 128 256 3 9 1 0 0 64 512 2 1 0 1 32 1024 1 1 0 16 2048 0 5 1 1 1 8 4096 0 24 Technical Data MOTOROLA Timebase Module TBM For More information On This Product Go to www freescale com 331 Freescale Semiconductor Inc Timebase Module TBM NOTE 21 6 Interrupts Technical Data Do not change TBR2 TBR0 bits while the timebase is enabled TBON 1 TACK Timebase ACKnowledge The TACK bit is a write only bit and always reads as 0 Writing a logic 1 to this bit clears TBIF the timebase interrupt flag bit Writing a logic 0 to this bit has no effect 1 Clear timebase interrupt flag 0 No effect TBIE Timebase Interrupt Enabled This read write bit enables the timebase interrupt when the TBIF bit becomes set Reset clears the TBIE bit 1 Timebase interrupt enabled 0 Timebase interrupt disabled TBON Timebase Enabled This read write bit en
278. i z 5 es HY 05 oa 85 HE 35 40 3 3 2 3 4 3 6 3 8 4 0 4 2 VoH V Vou gt Vpp 0 8 V loH 2 0 mA Vou gt Vpp 1 5V lou 10 0 mA Figure 23 1 Typical High Side Driver Characteristics Port PTA3 PTAO Vpp 4 5 Vdc 0 5 nu 40 pa A 25 S 54 X 85 25 1 3 1 5 1 7 1 9 2 1 2 3 2 5 Vou V Vou gt Vpp 0 3 V loH 0 6 mA Vou gt Vpp 1 0V lon 4 0 mA Figure 23 2 Typical High Side Driver Characteristics Port PTA3 PTAO Vpp 2 7 Vdc Technical Data MC68HC908GR8 Rev 4 0 370 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Output High Voltage Characteristics 0 5 10 Fa 15 40 NA mo AE a mI ik 25 P 05 Xx 85 30 35 40 3 3 2 34 3 6 38 40 4 2 Vou V Vou gt Vpp 0 8 V lop 10 0 mA Figure 23 3 Typical High Side Driver Characteristics Port PTC1 PTCO Vpp 4 5 Vdc 0 5 x o 40 ps k 25 151 X X 85 T ee adel 25 1 3 1 5 1 7 1 9 2 1 2 3 2 5 Vou V Vou gt Vpp 0 5 V loH 4 0 mA Figure 23 4 Typical High Side Driver Characteristics Port PTC1 PTCO Vpp 2 7 Vdc MC68HC908GR8 Rev 4 0 Technical
279. i do dod d AA 83 7 7 5 KABABA KALAN ETE PETE E A ANAN ASA 85 Section 6 Break Module BRK cca AA AA AA 91 WO nes AKA TKB AKNG KB rm 91 3 7 AR AA AA EA 91 F ngti nal Description pada KK AKA cranes BARB dz edes aa 92 Low Power Modes 0 waa GAT RALA KANA RR Gd KNA LL ALENG 94 Break Module Registers a 94 Section 7 Clock Generator Module CGMC o ca Ems 99 Lick AAP AY 99 o AA AA AA T 100 Functional Description cies 100 LP pi AA AAP iei 112 CGMC Registers nuaa annaa 114 MCC 14 ows eke dente nA dese E aa bh NAUNA 123 Special Modes 0000 e eee ees 123 Acquisition Lock Time Specifications 125 Technical Data MOTOROLA Table of Contents 9 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Table of Contents 8 1 8 2 8 3 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 Section 8 Configuration Register CONFIG a AA AA RAP AA AA AA 129 aa a AA AA 129 F nctional DesperDllell 44 paaa KAKA KA REROE ordo da dn 129 Section 9 Computer Operating Properly COP dolo CMT AA M rm 133 BODEN yes diet ook ew AO dope Ace Jie Feld dh EP NI 133 Functional Description z4 msa dc ay RC E dasa WG KA Ra 133 EL SEHE Lc EROR EROR eee d eld 135 COP Control Register aad KG BA C ed d e 136 PIO 65 vae ho RC E EROR Ee dn KA RO UR p n 136 Monitor ONES KE
280. ide H Remainder INH 52 7 EOR opr IMM A8 iii 2 EOR opr DIR B8 dd 3 EOR opr EXT C8 hhll 4 EOR opr X F IX2 D8 leeff 4 EOR oprX Exclusive OR M with A A A M 0 t t ixi E8 f 3 EOR X IX F8 2 EOR opr SP SP1 9EE8 ff 4 EOR opr SP SP2 9ED8 Jee ff 5 Technical Data MC68HC908GR8 Rev 4 0 150 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU Table 10 1 Instruction Set Summary Continued Instruction Set Summary Effecton y Source CCR a Ela Form Operation Description o 29 S 9 O o H INZC 32 8 8 3a INC opr M e M 41 DIR 3C dd 4 INCA A A 1 INH 4C 1 INCX X e X 1 INH 5C 1 INC opr X Increment M e M 1 t i7 ni 6C ff 4 INC X M e M 1 IX 7C 3 INC opr SP M e M 1 SP1 9E6C ff 5 JMP opr DIR BC dd 2 JMP opr EXT CC hhll 3 JMP opr X Jump PC lt Jump Address IxX2 DC jeeff 4 JMP opr X IX1 EC ff 3 JMP X IX FC 2 ISR opr PG Gg POs ane iA ora ext co hi 5 us SP amp Sit Ja opr X Jump to Subroutine Push PGH SP SP 1 NG ED ce ff E JSR X PC lt Unconditional Address Ig EB 4 LDA opr IMM A6 ii 2 LDA opr DIR B6 dd 3 LDA opr EXT C6 hhi 4 LDA op
281. in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same PWM period In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 096 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value MC68HC908GR8 Rev 4 0 344 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM Functional Description 22 5 8 Buffered PWM Signal Generation NOTE Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCHO pin The TIM channel registers of the linked pair alternately control the pulse width of the output Setting the MSOB bit in TIM channel 0 status and control register TSCO links channel 0 and channel 1 The TIM channel 0 registers initially control the pulse width on the TCHO pin Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period At each subsequent overflow the TIM channel registers 0 or 1 that control the pulse width are the ones written to last TSC
282. ine Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode To prevent inadvertently turning off the COP with a STOP instruction a configuration option is available that disables the STOP instruction When the STOP bit in the configuration register has the STOP instruction disabled execution of a STOP instruction results in an illegal opcode reset 9 9 COP Module During Break Mode The COP is disabled during a break interrupt when V7g7 is present on the RST pin MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Computer Operating Properly COP 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly COP Technical Data MC68HC908GR8 Rev 4 0 138 Computer Operating Properly COP MOTOROLA For More information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 10 Central Processing Unit CPU 10 1 Contents 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 2 Introduction BOUE cob eed dopo ep ee oe dee de dos dea e void i 139 oe ewe Rede ER AU ap eR ed 0C NAK ORO HERE GER 139 88 SANG 00 TP AA PAPA 140 Arithmetic logic unit ALU 42 aa seek KPA e hr 145 Low power modes Lus Dese uoa RO ER EU ER eee da
283. ing 2 1 Memory DIIS KR A I EROR CR ERI o 2 2 Control Status and Data Registers 4 1 Internal Reset Timing 4 2 Power On Reset Recovery 4 3 SIM Reset Status Register SRSR 4 4 Interrupt Stacking Order 4 5 Interrupt Recognition Example 4 6 Interrupt Processing 4 7 Interrupt Status Register 1 INT1 4 8 Interrupt Status Register 2 INT2 4 9 Interrupt Status Register 3 INT3 5 1 ADC Block Diagram a 5 2 ADC Status and Control Register ADSCR 5 3 ADC Data Register ADR 5 4 ADC Clock Register ADCLK 6 1 Break Module Block Diagram 6 2 I O Register Summary 6 3 Break Status and Control Register BRKSCR 6 4 Break Address Register High BRKH 6 5 Break Address Register Low BRKL 6 6 SIM Break Status Register SBSR 6 7 SIM Break Flag Control Register SBFCR 7 1 GGMG Block Diagram 2 2 ces an akaaaaawawwn 7 2 CGMC External Connections 7 3 CGMC I O Register Summary MC68HC908GR8 Rev 4 0 List of Figures Technical Data MOTOROLA List of Figures For More Information On This Product Go to www freescale com 19 Technical Data Freescale Semiconductor Inc List of Figures 7 4 7 5 FLL
284. inimize stop current all pins configured as inputs should be driven to a logic 1 or logic 0 MC68HC908GR8 Rev 4 0 292 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM SIM Registers CPUSTOP IAB STOP ADDR STOPADDR 1 SAME SAME y IDB PREVIOUS DATA NEXT OPCODE SAME SAME RW Note Previous data can be operand data or the STOP opcode depending on the last instruction Figure 19 18 Stop Mode Entry Timing Bi STOP RECOVERY PERIOD CGMXCLK INT BREAK a IAB STOP 1 ror stop 2 sp jJ sp 1 f sp 2 sp 3 y Figure 19 19 Stop Mode Recovery from Interrupt or Break 19 8 SIM Registers The SIM has three memory mapped registers Table 19 4 shows the mapping of these registers Table 19 4 SIM Registers Address Register Access Mode FEO0 SBSR User FE01 SRSR User SFE03 SBFCR User MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 293 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 8 1 SIM Break Status Register The SIM break status register SBSR contains a flag to in
285. interrupt requests on falling edges and low levels 0 Keyboard interrupt requests on falling edges only 13 8 2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin Address 001B Bit 7 6 5 4 3 2 1 Bit 0 Read KBIE3 KBIE2 KBIE1 KBIEO Write Reset 0 0 0 0 Figure 13 4 Keyboard Interrupt Enable Register INTKBIER KBIES3 KBIEO Keyboard Interrupt Enable Bits Each of these read write bits enables the corresponding keyboard interrupt pin to latch interrupt requests Reset clears the keyboard interrupt enable register 1 PTAx pin enabled as keyboard interrupt pin 0 PTAx pin not enabled as keyboard interrupt pin Technical Data MC68HC908GR8 Rev 4 0 182 Keyboard Interrupt KBI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 14 Low Voltage Inhibit LVI 14 1 Contents Ta WMI de bh ec edo kh odo ie de obe YO HIC RR d 183 143 JEN EL cis der dep deca dE CARD EORR AAP 183 144 Functional Description ean setewenees 184 14 5 LVI Status Register saa AG KK RR EC RO oe AR 187 150 Te AOS 52 045 dere KG ROCCO E OR ed eot bn a OR 188 14 7 Low Power Modes Lia eaa eor KARERA KKK SAGA 188 14 2 Introduction This section describes the low voltage inhibit LVI module which monitors t
286. ion Section 11 Flash Memory Na BG s arrihen rr kee vola aoo diede lo HERS eee 157 11 3 Functional Description 24 ABAKA KAB PK KAWA KA Ra 157 114 FLASH Control Regislet 0 ap ka RR EY ene de 158 11 5 FLASH Page Erase Operation aaa 160 11 6 FLASH Mass Erase Operation 2 161 11 7 FLASH Program Read Operation 162 11 8 FLASH Block PIDIGOBODL Lice doe pa CR RA RR RR RR 163 DLE e EE E E quss sca diti dx RU ER 166 11 10 STOP Mode iiir pem ed KG die aca ato at UR d d db woe deat 166 This section describes the operation of the embedded FLASH memory This memory can be read programmed and erased from a single external supply The program erase and read operations are enabled through the use of an internal charge pump 11 3 Functional Description The FLASH memory is an array of 7 680 bytes for the MC68HC908GHR8 or 4 096 bytes for the MC68HC908GR4 with an additional 36 bytes of user vectors and one byte used for block protection An erased bit reads as logic 1 and a programmed bit reads as a logic 0 The program and erase operations are facilitated through control bits in the Flash Control MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Flash Memory 157 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory Register FLCR Details for these operations appear later in this section The FLASH is organized internally a
287. ion existing or else the flag is not cleared Four SPI status flags can be enabled to generate CPU interrupt requests Table 20 2 SPI Interrupts Flag Request SPTE SPI transmitter CPU interrupt request Transmitter empty DMAS 0 SPTIE 1 SPE 1 SPRF SPI receiver CPU interrupt request Receiver full DMAS 0 SPRIE 1 OVRF Overflow SPI receiver error interrupt request ERRIE 1 MODF Mode fault SPI receiver error interrupt request ERRIE 1 MC68HC908GR8 Rev 4 0 314 Serial Peripheral Interface SPI MOTOROLA For More information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Interrupts Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF The clearing mechanism for the SPTE flag is always just a write to the transmit data register The SPI transmitter interrupt enable bit SPTIE enables the SPTE flag to generate transmitter CPU interrupt requests provided that the SPI is enabled SPE 1 The SPI receiver interrupt enable bit SPRIE enables the SPRF bit to generate receiver CPU interrupt requests regardless of the state of the SPE bit See Figure 20 11 The error interrupt enable bit ERRIE enables both the MODF and OVHREF bits to generate a receiver error CPU interrupt request The mode fault enable bit MODFEN can prevent the MODF flag fr
288. ions cannot be performed by code being executed from the FLASH memory While these operations must be performed in the order shown other unrelated operations may occur between the steps MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Flash Memory 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory 11 7 FLASH Program Read Operation Programming of the FLASH memory is done on a row basis A row consists of 32 consecutive bytes starting from addresses XX00 XX20 XX40 XX60 XX80 XXAO0 SXXCO and XXEO Use this step by step procedure to program a row of FLASH memory Figure 11 2 is a flowchart representation 1 po cp GC gx puo Set the PGM bit This configures the memory for program operation and enables the latching of address and data for programming Read from the FLASH block protect register Write any data to any FLASH address within the row address range desired Wait for a time thys min 10us Set the HVEN bit Wait for a time tpgs min Sus Write data to the FLASH address to be programmed Wait for a time tprog min 30s Repeat step 7 and 8 until all the bytes within the row are programmed Clear the PGM bit Wait for a time tnyh min Sus Clear the HVEN bit After time toy min 1us the memory can be accessed in read mode again The time between each FLASH address change or the time between the last
289. isition Lock Time Specifications after turning on the PLL by setting PLLON in the PLL control register PCTL MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC e Software must wait a given time tA after entering tracking mode before selecting the PLL as the clock source to CGMOUT BCS 1 The LOCK bit is disabled e CPU interrupts from the CGMC are disabled 7 4 6 Programming the PLL The following procedure shows how to program the PLL NOTE The round function in the following equations means that the real number should be rounded to the nearest integer number 1 Choose the desired bus frequency fpyspes 2 Calculate the desired VCO frequency four times the desired bus frequency fveLkpes 4X fBUSDES 3 Choose a practical PLL crystal reference frequency fac and the reference clock divider R Typically the reference crystal is 32 768 kHz and R 1 Frequency errors to the PLL are corrected at a rate of fac K R For stability and lock time reduction this rate must be as fast as possible The VCO frequency must be an integer multiple of this rate The relationship between the VCO frequency fyc x and the reference frequency frac ix is 2PN fvck Rp acu P the power of two multiplier and N the range multiplier are integer
290. ist of Figures 23 For More information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Technical Data 23 12 Typical Low Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 2 7 Vdc 375 23 13 Typical Operating IDD with All Modules Turned On m dicor o le AA AA 376 23 14 Typical Wait Mode IDD with all Modules Disabled im 0 tiom le rn 376 23 15 Typical Stop Mode IDD with all Modules Disabled A0 TE t0 125 C a eie s d deir a d RS APA 377 23 16 SPI Master Timing aucucescecunasat dw d dteeuwchabas 381 23 17 SEINS ob ipd o AA REOR oed 382 MC68HC908GR8 Rev 4 0 24 List of Figures MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 1 1 Contents 1 2 Introduction Section 1 General Description Da a PR G6 aet qd dod V aos pale e Ro qp ER E een 25 1S POOR ertir E PENE EREE RE EEE E EA 26 a AB LAPAT 28 1 5 PN AWA KAMA GG ur ER Fol ia KPA 30 LE Sela oe 6s Fb hs 0 a Se AGA AA 31 The MC68HC908GR8 is a member of the low cost high performance M68HC08 Family of 8 bit microcontroller units MCUs All MCUs in the family use the enhanced M68HC08 central processor unit CPUOS and are available with a variety of modules memory sizes and types and package types This document also describes the MC68HC908GR4 The MC68HC908GR4 is a device
291. it SCIBDSRC controls the clock source used for the SCI The setting of this bit affects the frequency at which the SCI operates 1 Internal data bus clock used as clock source for SCI 0 External oscillator used as clock source for SCI COPRS COP Rate Select Bit COPRS selects the COP timeout period Reset clears COPRS See Computer Operating Properly COP 1 COP timeout period 213 24 CGMXCLK cycles 0 COP timeout period 219 2 CGMXCLK cycles LVISTOP LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear setting the LVISTOP bit enables the LVI to operate during stop mode Reset clears LVISTOP See Stop Mode 1 LVI enabled during stop mode 0 LVI disabled during stop mode LVIRSTD LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module See Low Voltage Inhibit LVI 1 LVI module resets disabled 0 LVI module resets enabled LVIPWRD LVI Power Disable Bit LVIPWRD disables the LVI module See Low Voltage Inhibit LVI 1 LVI module power disabled 0 LVI module power enabled MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Configuration Register CONFIG 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration Register CONFIG LVI50R3 LVI 5V or 3V Operating Mode Bit LVI50R3 selects the voltage operating mode of the LVI module See Low Voltage Inhibit LVI The voltage mode selected for the LVI should m
292. itor Mode Entry Timing Upon power on reset if the received bytes of the security code do not match the data at locations FFF6 FFFD the host fails to bypass the security feature The MCU remains in monitor mode but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset After receiving the eight security bytes from the host the MCU transmits a break character signifying that itis ready to receive a command The MCU does not transmit a break character until after the host sends the eight security bytes To determine whether the security code entered is correct check to see if bit 6 of RAM address 40 is set If it is then the correct security code has been entered and FLASH can be accessed MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 203 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON If the security sequence fails the device can be reset and brought up in monitor mode to attempt another entry After failing the security sequence the FLASH mode can also be bulk erased by executing an erase routine that was downloaded into internal RAM The bulk erase operation clears the security code locations so that all eight security bytes become SFF blank Technical Data MC68HC908GR8 Rev 4 0 204 Monitor ROM MON MOTOROLA For More Information On This Product Go to
293. ive only a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low To prevent losing an interrupt request on one pin because another pin is still low software can disable the latter pin while it is low e If the keyboard interrupt is falling edge and low level sensitive an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled Technical Data MC68HC908GR8 Rev 4 0 176 Keyboard Interrupt KBI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI Functional Description INTERNAL BUS ECTOR FETC DECODER TO PULLUP ENABLE KEYBOARD INTERRUPT A REQUEST KEYBOARD IMASKK O ne INTERRUPT FF MODEK i TO PULLUP ENABLE Figure 13 1 Keyboard Module Block Diagram Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 KEYF 0 Keyboard Status IMASKK MODEK 001A and Control Register Write ACKK INTKBSCR Reset 0 0 0 0 0 0 0 0 Read 001B Keyboard Interrupt Enable Write KBIE3 KBIE2 KBIE1 KBIEO Register INTKBIER i Reset 0 0 0 0 Unimplemented Figure 13 2 I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Keyboard Interrupt KBI 177 For More Information On This Product Go to www
294. l Data MC68HC908GR8 Revision History Contents BOOTE c pe e edet od ee Ae Ge de e qeu n apo C 405 Changes from Rev 3 0 published in February 2002 to Rev 4 0 published in June 2002 Xa aa aaa md uut saisie Rm 405 Changes from Rev 2 0 published in January 2002 to Rev 3 0 pub lished in ka AN AA cidi kikina 406 Changes from Rev 1 0 published in April 2001 to Rev 2 0 pub lished in December 2001 0 0 sa kwawa Rr mmn 406 Introduction This section contains the revision history for the MC68HC908GR8 technical data book Changes from Rev 3 0 published in February 2002 to Rev 4 0 published in June 2002 Section Page in Rev 3 0 Description of change All references to the ROM MC68HCO8GR8 removed Appendix A removed 363 Maximum junction temperature increased to 140 C 364 Input High Voltage for OSC1 changed Electrical Stop Ipp for temperatures gt 85 C added Specifications Input High Voltage for OSC1 changed 366 Input Low Voltage for OSC1 changed Stop Ipp for temperatures gt 85 C added MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Revision History For More Information On This Product Go to www freescale com 405 Freescale Semiconductor Inc Revision History Changes from Rev 2 0 published in January 2002 to Rev 3 0 published in February 2002 Section Page in Rev 3 0 Description of change All references to the ROM MC68HCO8GR8 removed Appendix A remov
295. lds IXI e edS v ZXI E IXA HId c WMWI HNI L HNI XI H HidS j IXI Z HNI LIHNI eld c d3H Ha c Uuld Ho HOI uod Hoa Ho HO HOI uod 010 x1Nd ISI ISI ISI X1S1 VIS1 ISI OOH8 v13S8 v1HSHH 8 v E S v v 4 L 4 S v L k v v S XI lds IXI ec edS v ex E IXA HId c WNWI HNI L HNI XI k kds j IXI Z HNI L HNI eld Z 134 ua c UHuld VLS YLS VIS VIS VLS VIS VIS SIV XYL VHSd usv usv HSY XUSV VUSV usv O3H u198 u1Oug Z 4 v S v v 4 L 4 S v L L v v S XI lds j IXI Z Zds v exl E IXA MUId Z NWI HNI XI E kds IXI Z HNI L HN LI Hd cH d Hla Z Ha val val vaq val val val val val vind YOu YOu YOu XHOH VHOH YOu aNg Lasd 13SHH 9 4 v S v v 4 4 S v L L v v S XI lds j IXI Z Zds v ZXI E IXA MUId Z NNI HNI HNI Hua c WAI HG c NNI HI c lH cua va Llig lia Lid Lid lia lia lia lla XSL Vd XHdO XHdO XHQ1 XHQ1 XHLS sod 2H10d cu 10ug8 S 4 v S v v 4 4 L v v v v S XI lds IXI ez edS v cxi 1x3 efa Z WWI HNI L HNI XI L idS f IXI 2 HNI HNI IG cj 13H cH c HI GNV GNV GNV GNV GNV GNV GNV GNV SXL dVL us us1 us1 Xus1 Vus Ysl 394g eLasd ZLIsHd v 4 v S v v 4 4 4 E S v L L v v E XI lds IXI e edS v ZXI E IXA E Ha c WMWI T134 z HNI XI LH HidS IXI c HNI LIHNI HG c d3H ua c Uuld XdO XdO XdO XdO XdO XdO XdO XdO ad IMS NOO NOO NOO XINOO VINOO NOO sid t9109 kUTO0Hd v S v v 4 6 S v
296. le is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 DMA not enabled to service SCI receiver DMA service requests generated by the SCHRF bit SCI receiver CPU interrupt requests enabled 0 DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled DMATE DMA Transfer Enable Bit CAUTION The DMA module is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 SCTE DMA service requests enabled SCTE CPU interrupt requests disabled 0 SCTE DMA service requests disabled SCTE CPU interrupt requests enabled ORIE Receiver Overrun Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit OR 1 SCI error CPU interrupt requests from OR bit enabled 0 SCI error CPU interrupt requests from OR bit disabled NEIE Receiver Noise Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the noise error bit NE Reset clears NEIE 1 SCI error CPU interrupt requests from NE bit enabled 0 SCI error CPU interrupt requests from NE bit disabled FEIE Receiver Framing Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the framing error bit FE Reset clears FEIE 1 SCI error CPU interrupt requests from
297. llow communication at 9600 baud provided one of the following sets of conditions is met 1 If FFFE and FFFF contain values not cared The external clock is 9 8304 MHz RQ Vrs1 PLL off 2 If FFFE and FFFF contain SFF blank state The external clock is 9 8304 MHz EN RQ Vpp this can be implemented through the internal IRQ pullup PLL off 3 If FFFE and FFFF contain FF blank state The external clock is 32 768 kHz crystal IRQ Vss this setting initiates the PLL to boost the external 32 768 kHz to an internal bus frequency of 2 4576 MHz MC68HC908GR8 Rev 4 0 192 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description Table 15 1 Monitor Mode Signal Requirements and Options For Serial Communication d FFFE External Bus IRQ RESET SFFFF PLL PTBO PTB1 Clock CGMOUT Freq COP BS Comment PTAO PTA1 Rate 9 x enn X X X x x 0 0 Disabled X ge Do operation unn reset goes high Vpp 0 9600 PTBO and PTB1 9 8304 4 9152 2 4576 n voltages only Vist va X OFF 1 0 MHz MHz MHz Disabled Siti required i TST IRQ Vrgr 0 9600 External frequency 9 8304 4 9152 2 4576 ti Vpp Vpp FFFF OFF X X Disabled always divided by 0 9600 PLL enabled BCS GND Voo SFFFF ON X X m
298. lock Diagram SILAG 01 NOY HOLINOIN SILAG v8 WV HISN SILAG960F HSV14 HISN 7HI806 H89I N SILAG 0897 HSV 1H HISN 8H9806 H89IN SILAG 79 SHALSIOAY SNLVLS ANY TOHINOO nv LINN SHILSI93H 0I9O72ILINHLIHY Nd fid9 800H89N Technical Data MC68HC908GR8 Rev 4 0 General Description 29 For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc General Description 1 5 Pin Assignments e g o 003 85082 oO OS Sk EE N e RST H O PTA2 KBD2 PTEO TxD PTA1 KBD1 PTE1 RxD PTAO KBDO IRQ Vssap VREFL PTDO SS Vppap VREFH PTD1 MISO PTB5 AD5 PTD2 MOSI PTB4 AD4 PTD3 SPSCK PTB3 AD3 PTD4 T1CHO PTD5 T1CH1 PTD6 T2CHO PTBO ADO PTB1 AD1 PTB2 AD2 NOTE Ports PTB4 PTB5 PTCO and PTC1 are available only with the QFP Figure 1 2 QFP Pin Assignments Technical Data MC68HC908GR8 Rev 4 0 30 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Pin Functions CGMXFC 1 Vssa OSC2 2 VDpA OSC1 3 PTA3 KBD3 RST 4 PTA2 KBD2 PTEO TxD 5 PTA1 KBD1 PTE1 RxD 6 PTAO KBDO IRQ 7 Vssap VREFL PTDO SS 8 VDDAD VREFH PTD1 MISO 9 PTB3 AD3 PTD2 MOSI 10 PTB2 AD2 PTD3 SPSCK 11 PTB1 AD1 Vss 12 PTBO ADO View 13 PTD6 T2CHO PTD4 T1CHO 14 PTD5 T1CH1 NOTE Ports PTB4 PTB5 PTCO and PTC1 are available only with the QF
299. lock for the COP module The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK 19 5 1 SIM Counter During Power On Reset The power on reset module POR detects power applied to the MCU At power on the POR circuit asserts the signal PORRST Once the SIM is initialized it enables the clock generation module CGM to drive the bus clock state machine 19 5 2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery The STOP instruction clears the SIM counter After an interrupt break or reset the SIM senses the state of the short stop recovery bit SSREC in the mask option register If the SSREC bit is a logic 1 then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles This is ideal for applications using canned oscillators that do not require long startup times from stop mode External crystal applications should use the full stop recovery time that is with SSREC cleared MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 281 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 5 3 SIM Counter and Reset States External reset has no effect on the SIM counter See Stop Mode for details The SIM counter is free running after all reset states See Active Resets from Internal Sources for counter control and in
300. logic levels to the right or left through adjacent circuits in the chain signed A binary number notation that accommodates both positive and negative numbers The most significant bit is used to indicate whether the number is positive or negative normally logic O for positive and logic 1 for negative The other seven bits indicate the magnitude of the number software Instructions and data that control the operation of a microcontroller software interrupt SWI An instruction that causes an interrupt and its associated vector fetch SPI See serial peripheral interface module SPI stack A portion of RAM reserved for storage of CPU register contents and subroutine return addresses stack pointer SP A 16 bit register in the CPU08 containing the address of the next available storage location on the stack start bit A bit that signals the beginning of an asynchronous serial transmission status bit A register bit that indicates the condition of a device stop bit A bit that signals the end of an asynchronous serial transmission subroutine A sequence of instructions to be used more than once in the course of a program The last instruction in a subroutine is a return from subroutine RTS instruction At each place in the main program where the subroutine instructions are needed a jump or branch to subroutine JSR or BSR instruction is used to call the subroutine The CPU leaves the flow of the
301. lue Executing an opcode at an unimplemented location causes an illegal address reset V The overflow bit in the condition code register of the CPU08 The CPUOS sets the V bit when a two s complement overflow occurs The signed branch instructions BGT BGE BLE and BLT use the overflow bit variable A value that changes during the course of program execution VCO See voltage controlled oscillator vector A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset voltage controlled oscillator VCO A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input waveform A graphical representation in which the amplitude of a wave is plotted against time wired OR Connection of circuit outputs so that if any output is high the connection point is high word A set of two bytes 16 bits write The transfer of a byte of data from the CPU to a memory location X The lower byte of the index register H X in the CPU08 Z The zero bit in the condition code register of the CPU08 The CPUOS sets the zero bit when an arithmetic operation logical operation or data manipulation produces a result of 00 Technical Data MC68HC908GR8 Rev 4 0 404 Glossary MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technica
302. lways activated even when the reset pin is pulled low See Resets and Interrupts 1 6 4 External Interrupt Pin IRQ IRQ is an asynchronous external interrupt pin This pin contains an internal pullup resistor that is always activated even when the reset pin is pulled low See External Interrupt IRQ 1 6 5 CGM Power Supply Pins VppA and Vssa VppA and Vssa are the power supply pins for the analog portion of the clock generator module CGM Decoupling of these pins should be as per the digital supply See Clock Generator Module CGMC Technical Data MC68HC908GR8 Rev 4 0 32 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Pin Functions 1 6 6 External Filter Capacitor Pin CGMXFC CGMXFC is an external filter capacitor connection for the CGM See Clock Generator Module CGMC 1 6 7 Analog Power Supply Reference Pins VppAp Vngru and Vssap VRerL Vppap and Vssap are the power supply pins for the analog to digital converter Decoupling of these pins should be as per the digital supply NOTE Vggrgy is the high reference supply for the ADC The Vggre signal is internally connected with Vppap and have the same potential as Vppap Vppap should be tied to the same potential as Vpp via separate traces Vngr is the low reference supply for the ADC The Vpepj pin is internally connected with Vss4p and has the same potential
303. m counter automatically increments to the next sequential memory location every time an instruction or operand is fetched Jump branch and interrupt operations load the program counter with an address other than that of the next sequential location MC68HC908GR8 Rev 4 0 142 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU CPU registers During reset the program counter is loaded with the reset vector address located at FFFE and FFFF The vector address is the address of the first instruction to be executed after exiting the reset state Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Read PC Write Reset Loaded with vector from FFFE and FFFF Figure 10 5 Program counter PC 10 4 5 Condition code register CCR The 8 bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed Bits 6 and 5 are set permanently to 1 The following paragraphs describe the functions of the condition code register Bit 7 6 5 4 3 2 1 Bit 0 Read CCR V 1 1 H l N Z C Write Reset X 1 1 X 1 X X X X Indeterminate Figure 10 6 Condition code register CCR V Overflow flag The CPU sets the overflow flag when a two s complement overflow occurs The si
304. miconductor Inc System Integration Module SIM Vector address generation e CPU enable disable timing Modular architecture expandable to 128 interrupt sources Table 19 1 shows the internal signal names used in this section MODULE STOP MODULE WAIT CPU STOP FROM CPU CPU WAIT FROM CPU SIMOSCEN TO CGM SIM COUNTER COP CLOCK CGMXCLK FROM CGM CGMOUT FROM CGM STOP WAIT CONTROL INTERNAL CLOCKS Y CONTROL CLOCK GENERATORS INTERNAL PULLUP DEVICE LVI FROM LVI MODULE ILLEGAL OPCODE FROM CPU ILLEGAL ADDRESS FROM ADDRESS MAP DECODERS COP FROM COP MODULE RESET PIN LOGIC INTERRUPT CONTROL INTERRUPT SOURCES AND PRIORITY DECODE gt CPU INTERFACE Figure 19 1 SIM Block Diagram Technical Data MC68HC908GR8 Rev 4 0 272 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Introduction Table 19 1 Signal Name Conventions Signal Name Description CGMXCLK Buffered version of OSC1 from clock generator module CGM CGMVCLK PLL output CGMOUT PLL based or OSC1 based clock output from CGM module Bus clock CGMOUT divided by two IAB Internal address bus IDB Internal data bus PORRST Signal from the power on reset module to the SIM IRST Intern
305. miconductor Inc Technical Data MC68HC908GR8 25 1 Contents 25 2 Introduction Section 25 Ordering Information 25 2 nUOONOGHDIE uu Eu d aod a dace ie dotado aue Er deed eee ew Roe 391 25 9 MG Order NIIDOIS ko a eara GG WG BAKA AGANE RR 392 25 4 Development Fools npa Ra acr hr deen tees 393 This section contains instructions for ordering the MC68HC908GR8 and MC68HC908GR4 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Ordering Information 391 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ordering Information 25 3 MC Order Numbers Table 25 1 MC Order Numbers Operating MC Order Number Temperature Range C MC68HC908GR8CP 40 to 85 MC68HC908GR8CFA 40 to 85 MC68HC908GR8CDW 40 to 85 MC68HC908GR8VFA 40 to 105 MC68HC908GR8VP 40 to 105 MC68HC908GR8VDW 40 to 105 MC68HC908GR8MFA 40 to 125 MC68HC908GR8MP 40 to 125 MC68HC908GR8MDW 40 to 125 Production Parts MC68HC908GR4CP 40 to 85 MC68HC908GR4CFA 40 to 85 MC68HC908GR4CDW 40 to 85 MC68HC908GR4VFA 40 to 105 MC68HC908GR4VP 40 to 105 MC68HC908GR4VDW 40 to 105 MC68HC908GR4MFA 40 to 125 MC68HC908GR4MP 40 to 125 MC68HC908GR4MDW 40 to 125 MC908GR8CFAR2 40 to 85 MC908GR8CDWR2 40 to 85 MC908GR8VFAR2 40 to 105 MC908GR8VDWR2 40 to 105 MC908GR8MFAR2
306. mmand allows the host to send a break character to cancel the command A delay of two bit times occurs before each echo and before READ IREAD or READSP data is returned The data returned by a read command appears after the echo of the last byte of the command NOTE Wait one bit time after each echo before sending the next byte FROM HOST ER ADDRESS ES ADDRESS A 5 READ A HIGH HIGH A LOW LOW DATA 4 ECHO RETURN Notes 1 Echo delay 2 bit times 2 Data return delay 2 bit times 3 Cancel command delay 11 bit times 4 Wait 1 bit time before sending next byte Figure 15 5 Read Transaction ADDRESS VADDRESS VADDRESSV ADDRESS J wame J mame Gs Sra 51 Cum aa pm 3 1 3 1 t 3 1 3 1 1 2 3 ECHO Notes 1 Echo delay 2 bit times Cancel command delay 11 bit times 3 Wait 1 bit time before sending next byte Figure 15 6 Write Transaction Technical Data MC68HC908GR8 Rev 4 0 198 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description A brief description of each monitor mode command is given in Table 15 4 through Table 15 9 Table 15 4 READ Read Memory Command Description Read byte from memory Operand 2 byte address in high byte low byte order Data Returned Opcode S4A Returns contents of specified address Command S
307. module 116 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 287 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 6 1 4 Interrupt Status Register 1 Address SFE04 Bit 7 6 5 4 3 2 1 Bit 0 Read l6 I5 l4 I3 l2 i 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 12 Interrupt Status Register 1 INT1 16 11 Interrupt Flags 1 6 These flags indicate the presence of interrupt requests from the sources shown in Table 19 3 1 Interrupt request present 0 No interrupt request present Bit O and Bit 1 Always read 0 19 6 1 5 Interrupt Status Register 2 Address SFE05 Bit 7 6 5 4 3 2 1 Bit 0 Read 114 113 112 111 110 19 18 I7 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 13 Interrupt Status Register 2 INT2 114 17 Interrupt Flags 14 7 These flags indicate the presence of interrupt requests from the sources shown in Table 19 3 1 Interrupt request present 0 No interrupt request present Technical Data MC68HC908GR8 Rev 4 0 288 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control 19 6 1 6 Interrupt Status Register
308. mples at RT8 RT9 and RT10 STOP NDLE OR NEXT CHARACTER RECEIVER t t t AA NG AE AA a r mr c cr cr cr cr c mr it it Pe kc k Ek k DATA SAMPLES Figure 18 8 Fast Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 18 8 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 160 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 8 bit character with no errors is 154 160 x 100 3 90 154 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 247 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI For a 9 bit character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 18 8 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles 176 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is s x100 3
309. n TSTOP is cleared Reset sets the TSTOP bit stopping the TIM counter until software clears the TSTOP bit 1 TIM counter stopped 0 TIM counter active NOTE Donotset the TSTOP bit before entering wait mode if the TIM is required to exit wait mode TRST TIM Reset Bit Setting this write only bit resets the TIM counter and the TIM prescaler Setting TRST has no effect on any other registers Counting resumes from 50000 TRST is cleared automatically after the TIM counter is reset and always reads as logic 0 Reset clears the TRST bit 1 Prescaler and TIM counter cleared 0 No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of 0000 Technical Data MC68HC908GR8 Rev 4 0 350 Timer Interface Module TIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PS2 PSO0 Prescaler Select Bits Timer Interface Module TIM O Registers These read write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 22 2 shows Reset clears the PS 2 0 bits Table 22 2 Prescaler Selection PS2 PS0 TIM Clock Source 000 Internal bus clock 1 001 Internal bus clock 2 010 Internal bus clock 4 011 Internal bus clock 8 100 Internal bus clock 16 101 Internal bus clock 32 110 Internal bus clock 64
310. n can be guaranteed 1 Internal bus clock 0 External clock CGMXCLK ADC input clock frequency _ 4 MHz ADIV2 ADIVO MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Analog to Digital Converter ADC 89 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ADC Technical Data MC68HC908GR8 Rev 4 0 90 Analog to Digital Converter ADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 6 1 Contents 6 2 Introduction 6 3 Features 6 2 6 3 6 4 6 5 6 6 Section 6 Break Module BRK Modua AG Ead TAK eee he ke ERE RE NAA 91 iol ES ch Fo eked REE EEO E TEA 91 Functional Description iuusacse ee Spa eor Pep 92 Low Power Modes 6 gc Ka GANG KA KAB REA RE REA RR oe om 94 Break Module Registers a 94 This section describes the break module The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program Features of the break module include MC68HC908GR8 Rev 4 0 Accessible input output I O registers during the break interrupt CPU generated break interrupts Software generated break interrupts COP disabling during break interrupts Technical Data MOTOROLA Break Module BRK 91 For More Information On This Product Go to www freescale com
311. n is driven low by the SIM during this entire period The IBUS clocks start upon completion of the timeout 19 3 3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt break or reset the SIM allows CGMXCLK to clock the SIM counter The CPU and peripheral clocks do not become active until after the stop delay timeout This timeout is selectable as 4096 or 32 CGMXCLK cycles See Stop Mode In wait mode the CPU clocks are inactive The SIM also produces two sets of clocks for other modules Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode 19 4 Reset and System Initialization Technical Data The MCU has these reset sources e Power on reset module POR External reset pin RST Computer operating properly module COP Low voltage inhibit module LVI e Illegal opcode e Illegal address All of these resets produce the vector SFFFE SFFFF SFEFE SFEFF in monitor mode and assert the internal reset signal IRST IRST causes all registers to be returned to their default values and all modules to be returned to their reset states MC68HC908GR8 Rev 4 0 276 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Reset and System Initialization An internal reset cl
312. n serial communication mask 1 A logic circuit that forces a bit or group of bits to a desired state 2 A photomask used in integrated circuit fabrication to transfer an image onto silicon mask option A optional microcontroller feature that the customer chooses to enable or disable mask option register MOR An EPROM location containing bits that enable or disable certain MCU features MCU Microcontroller unit See microcontroller memory location Each M68HC08 memory location holds one byte of data and has a unique address To store information in a memory location the CPU places the address of the location on the address bus the data information on the data bus and asserts the write signal To read information from a memory location the CPU places the address of the location on the address bus and asserts the read signal In response to the read signal the selected memory location places its data onto the data bus memory map A pictorial representation of all memory locations in a computer system microcontroller Microcontroller unit MCU A complete computer system including a CPU memory a clock oscillator and input output I O on a single integrated circuit modulo counter A counter that can be programmed to count to any number from zero to its maximum possible modulus monitor ROM A section of ROM that can execute commands from a host computer for testing purposes MOR Se
313. n the CONFIG register The timebase module can be used in this mode to generate a periodic wakeup from stop mode If the oscillator has not been enabled to operate in stop mode the timebase module will not be active during STOP mode In stop mode the timebase register is not accessible by the CPU If the timebase functions are not required during stop mode reduce the power consumption by stopping the timebase before enabling the STOP instruction MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timebase Module TBM 333 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timebase Module TBM Technical Data MC68HC908GR8 Rev 4 0 334 Timebase Module TBM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 22 1 Contents 22 2 Introduction 22 2 22 3 22 4 22 5 22 6 22 7 22 8 ze 22 10 Section 22 Timer Interface Module TIM Bro UI cs dor deed dob ep ee ee dee de oh ea e c ER OR 335 oc i0 MEE Y NY T TT TT TT TS DOT ee TOt OTT KA 336 Pin Name Conventions auis ere pa AR rr Ron Rem 336 Functional Description can aae xe REA RR es 337 a TENET A Bae hw oa E T Oe ee ae ws 346 Low Power Modes sic sam KA kan Re RERO R3 KAKA 347 TIM During Break Interrupts onnaa KR GG KAG 348 LAS a AA AA AA 348 PO Registers UPC MR 349 This section describes the timer interface
314. n the RAM during a subroutine or during the interrupt stacking operation Technical Data MC68HC908GR8 Rev 4 0 230 RAM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 18 Serial Communications Interface SCI 18 1 Contents 182 GEN oi 6b bed ied od ao AE de ee Heke dO d 231 134 1 00 232 18 4 Pin Name Convention iocos ise e rar rh Ra n 233 18 5 Functional Description pa are RRERERATA T A Rear 233 18 6 Low Power Modes 22 a ks ue RO RR ERR RE Rn 250 18 7 SCI During Break Module Interrupts 251 18 8 BO ERU i pido o dp b i QU ee led edo dI bo 251 18 9 PO PSI ei diee xdi abdo aca eee E UAR RF AG 252 18 2 Introduction This section describes the serial communications interface SCI module which allows high speed asynchronous communications with peripheral devices and other MCUs NOTE References to DMA direct memory access and associated functions are only valid if the MCU has a DMA module This MCU does not have the DMA function Any DMA related register bits should be left in their reset state for normal MCU operation MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 231 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 18 3 Features F
315. nal Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 1 0 0 BW 0 SIM Break Status Register FE00 SBSR Write R R R R R R NOTE R Reset 0 0 0 1 0 0 0 0 bis BCFE R R R R R R R SIM Break Flag Control SEEDS Register SBFCR We Reset 0 ea Bit 15 14 13 12 11 10 9 Bit 8 Break Address Register Pl I SFE09 High BRKH Write Reset 0 0 0 0 0 0 0 0 bs Bit 7 6 5 4 3 2 1 Bit 0 Break Address Register _ l l FEOA Low BRKL Write Reset 0 0 0 0 0 0 0 0 Read BAKE mana 0 0 0 0 0 0 Break Status and Control SFEOB Register BRKSCR MI Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears BW Unimplemented R Reserved Figure 6 2 I O Register Summary 6 4 1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state 6 4 2 CPU During Break Interrupts The CPU starts a break interrupt by Loading the instruction register with the SWI instruction e Loading the program counter with FFFC and SFFFD FEFC and FEFD in monitor mode MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Break Module BRK 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK The break interrupt begins after completion of the CPU instruction in progress If the b
316. nal reflects the state of the COP rate select bit COPRS in the configuration register See Configuration Register CONFIG 9 5 COP Control Register The COP control register is located at address FFFF and overlaps the reset vector Writing any value to FFFF clears the COP counter and starts a new timeout period Reading location FFFF returns the low byte of the reset vector Address FFFF Bit 7 6 5 4 3 2 1 Bit 0 Read Low byte of reset vector Write Clear COP counter Reset Unaffected by reset Figure 9 2 COP Control Register COPCTL 9 6 Interrupts The COP does not generate CPU interrupt requests Technical Data MC68HC908GR8 Rev 4 0 136 Computer Operating Properly COP MOTOROLA For More Information On This Product Go to www freescale com 9 7 Monitor Mode Freescale Semiconductor Inc Computer Operating Properly COP Monitor Mode When monitor mode is entered with Vrgz on the IRQ pin the COP is disabled as long as V st remains on the IRQ pin or the RST pin When monitor mode is entered by having blank reset vectors and not having Vrsr on the IRQ pin the COP is automatically disabled until a POR occurs 9 8 Low Power Modes 9 8 1 Wait Mode 9 8 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The COP remains active during wait mode To prevent a COP reset during wait mode periodically clear the COP counter in a CPU interrupt rout
317. nalog to Digital Status and Control Register Write ADSCR Read Write Reset Read Write Reset Read Unimplemented Write Analog to Digital Data Register ADR Analog to Digital Input Clock Register ADCLK Reset Read Write Reset Note Writing a logic 0 clears SBSW Read Write POR Read Unimplemented Write SBSR SRSR Reset Read Write Reset Read Write Reset Read Write Reset SIM Break Flag Control Register SBFCR INT1 INT2 Memory Map Input Output I O Section Read Reset Bit 7 6 5 4 3 2 1 Bit 0 COCO B AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCHO 0 0 0 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO R R R R R R R R Indeterminate after reset 0 ADIV2 ADIV1 ADIVO ADICLK R R R R 0 0 0 0 0 0 0 0 SBSW R R R R R R R NOTE 0 0 0 0 0 0 0 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 BCFE R R R R R R R 0 IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 7 of 8 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Memory Map 45 For More Information On This Product Go to www freescale c
318. nc Serial Peripheral Interface SPI O Signals communicate with 1 C peripherals MOSI becomes an open drain output when the SPWOM bit in the SPI control register is set In 1 C communication the MOSI and MISO pins are connected to a bidirectional pin from the I C peripheral and through a pullup resistor to Vpp 20 13 1 MISO Master In Slave Out MISO is one of the two SPI module pins that transmits serial data In full duplex operation the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin Slave output data on the MISO pin is enabled only when the SPI is configured as a slave The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0 To support a multiple slave system a logic 1 on the SS pin puts the MISO pin in a high impedance state When enabled the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I O port 20 13 2 MOSI Master Out Slave In MOSI is one of the two SPI module pins that transmits serial data In full duplex operation the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin When enabled the SPI controls data direction of the MOSI pin rega
319. ng conversion is aborted ADC conversions resume when the MCU exits stop mode after an external interrupt Allow one conversion cycle to stabilize the analog circuitry MC68HC908GR8 Rev 4 0 50 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes Break Module BRK 3 4 Break Module BRK 3 4 1 Wait Mode If enabled the break module is active in wait mode In the break routine the user can subtract one from the return address on the stack if the BW bit in the break status register is set 3 4 2 Stop Mode The break module is inactive in stop mode A break interrupt causes exit from stop mode and sets the BW bit in the break status register The STOP instruction does not affect break module register states 3 5 Central Processor Unit CPU 3 5 1 Wait Mode The WAIT instruction Clears the interrupt mask bit in the condition code register enabling interrupts After exit from wait mode by interrupt the bit remains clear After exit by reset the bit is set e Disables the CPU clock 3 5 2 Stop Mode The STOP instruction Clears the interrupt mask bit in the condition code register enabling external interrupts After exit from stop mode by external interrupt the bit remains clear After exit by reset the bit is set e Disables the CPU clock After exiting stop mode the CPU clock begins running after the
320. nsmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit Then a noise error occurs If more than one of the samples is outside the stop bit a framing error occurs In most applications the baud rate MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 245 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI tolerance is much more than the degree of misalignment that is likely to occur As the receiver samples an incoming character it resynchronizes the RT clock on any valid falling edge within the character Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times 18 5 3 6 Slow Data Tolerance Technical Data Figure 18 7 shows how much a slow received character can be misaligned without causing a noise error or a framing error The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 MSB y STOP RECEIVER t t t GO PA p e ph p p fx V2 ao e C tr tc tC tC Cc Cc EE E E E t E E E DATA SAMPLES Figure 18 7 Slow Data For an 8 bit charact
321. nstruction the CPU checks all pending interrupts if the bit is not set If more than one interrupt is pending when an instruction is done the highest priority interrupt is serviced first In the example shown in Figure 4 5 if an interrupt is pending upon exit from the interrupt service routine the pending interrupt is serviced before the LDA instruction is executed MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Resets and Interrupts 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts CLI BACKGROUND PE LA SEE ROUTINE P INT1 PSHH I INT1 INTERRUPT SERVICE ROUTINE INT2 PSHH _ l INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 4 5 Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions However in the case of the INT1 RTI prefetch this is a redundant operation NOTE To maintain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode save the H register and then restore it prior to exiting the routine Technical Data MC68HC908GR8 Rev 4 0 68 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Int
322. nstructions are expressed by programmers as assembly language mnemonics A CPU interprets an opcode and its associated operand s and instruction interrupt A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine interrupt request A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine O See input output I 0 IRQ See external interrupt module IRQ Jitter Short term signal instability latch A circuit that retains the voltage level logic 1 or logic O written to it for as long as power is applied to the circuit latency The time lag between instruction completion and data movement least significant bit LSB The rightmost digit of a binary number logic 1 A voltage level approximately equal to the input power voltage Vpj logic 0 A voltage level approximately equal to the ground voltage Vss low byte The least significant eight bits of a word low voltage inhibit module LVI A module in the M68HCO08 Family that monitors power supply voltage MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Glossary 399 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LVI See low voltage inhibit module LVI M68HC08 A Motorola family of 8 bit MCUs mark space The logic 1 logic 0 convention used in formatting data i
323. nternal reset signal MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 277 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM then follows the sequence from the falling edge of RST shown in Figure 19 5 IRST RST RST PULLED LOW BY MCU t 32 CYCLES 4 32 CYCLES CGMXCLK T T J o AA vecrom wor Figure 19 5 Internal Reset Timing The COP reset is asynchronous to the bus clock ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST J gt INTERNAL RESET LVI POR Figure 19 6 Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU 19 4 2 1 Power On Reset When power is first applied to the MCU the power on reset module POR generates a pulse to indicate that power on has occurred The external reset pin RST is held low while the SIM counter counts out 4096 CGMXCLK cycles Sixty four CGMXCLK cycles later the CPU and memories are released from reset to allow the reset vector sequence to Occur At power on these events occur e A POR pulse is generated Technical Data MC68HC908GR8 Rev 4 0 278 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com OSC1 PORRST C
324. ny data to any FLASH address within the page address range desired Wait for a time thys min 10us Set the HVEN bit Wait for a time tErase min 1ms Clear the ERASE bit Wait for a time tyyp min 5us Clear the HVEN bit P RO Jr b SON SUE ds After a time t c typ 1us the memory can be accessed again in read mode NOTE While these operations must be performed in the order shown other unrelated operations may occur between the steps Technical Data MC68HC908GR8 Rev 4 0 160 Flash Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory FLASH Mass Erase Operation 11 6 FLASH Mass Erase Operation NOTE Use this step by step procedure to erase entire FLASH memory to read as logic 1 1 e oo qe NG gr oc Set both the ERASE bit and the MASS bit in the FLASH control register Read from the FLASH block protect register Write any data to any FLASH address within the FLASH memory address range Wait for a time tays min 10us Set the HVEN bit Wait for a time tMErase min 4ms Clear the ERASE bit Wait for a time t yp min 100us Clear the HVEN bit After a time t min 1s the memory can be accessed again in read mode When in Monitor mode with security sequence failed Monitor ROM MON write to the FLASH block protect register instead of any FLASH address Programming and erasing of FLASH locat
325. o Ty unless otherwise noted Typical values reflect average measurements at midpoint of voltage range 25 C only Run operating Ipp measured using external square wave clock source fog 32 8 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs C 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects run Ipp Measured with all modules enabled 4 Wait Ipp measured using external square wave clock source fog 32 8 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs Cj 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects wait Ipp Measured with PLL and LVI enabled 5 Stop Ipp is measured with OSC1 Ves 6 Stop Ipp with TBM enabled is measured using an external square wave clock source fosc 32 8 KHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs All inputs configured as inputs Pullups and pulldowns are disabled Port B leakage is specified in ADC Characteristics Maximum is highest voltage that POR is guaranteed Maximum is highest voltage that POR is possible 0 If minimum Vpp is not reached before the internal POR reset is released RST must be driven low externally until minimum Vpp is reached Ww N zoom c MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 365 For More Information On This Product Go to www freescale com Freescale Semicon
326. ode fetch from an illegal address 0 POR or read of SRSR MODRST Monitor Mode Entry Module Reset Bit 1 Last reset caused by monitor mode entry when vector locations FFFE and FFFF are 00 after POR while IRQ Vpp 0 POR or read of SRSR LVI Low Voltage Inhibit Reset Bit 1 Last reset caused by the LVI circuit 0 POR or read of SRSR 19 8 3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state Address SFE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 19 22 SIM Break Flag Control Register SBFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break Technical Data MC68HC908GR8 Rev 4 0 296 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 20 Serial Peripheral Interface SPI 20 1 Contents 20 2 na TG Li qoi Fe Hh eee NUR ene e oe RO I oO 297 20 9 EI 0o e knee kets ce he he S 298 20 4 Pin Name Conventions and I
327. oftware clears the ENSCI bit in SCI control register 1 SCC1 the transmitter and receiver relinquish control of the port E pins 18 5 2 3 Break Characters Technical Data Writing a logic 1 to the send break bit SBK in SCC2 loads the transmit shift register with a break character A break character contains all logic Os and has no start stop or parity bit Break character length depends on the M bit in SCC1 As long as SBK is at logic 1 transmitter logic MC68HC908GR8 Rev 4 0 238 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be Receiving a break character has these effects on SCI registers Sets the framing error bit FE in SCS1 Sets the SCI receiver full bit SCRF in SCS1 e Clears the SCI data register SCDR e Clears the R8 bit in SCC3 Sets the break flag bit BKF in SCS2 e Ma
328. oftware does not read the byte in the receive data register before the next full byte enters the shift register In an overflow condition the byte already in the receive data register is unaffected and the byte that shifted in last is lost Clear the OVREF bit by reading the SPI status and control register with OVRF set and then reading the receive data register Reset clears the OVRF bit 1 Overflow 0 No overflow MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 325 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Technical Data MODF Mode Fault Bit This clearable read only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set In a master SPI the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set Clear the MODF bit by reading the SPI status and control register SPSCR with MODF set and then writing to the SPI control register SPCR Reset clears the MODF bit 1 SS pin at inappropriate logic level 0 SS pin at appropriate logic level SPTE SPI Transmitter Empty Bit This clearable read only flag is set each time the transmit data register transfers a byte into the shift register SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the SPTIE bit in the SPI control register is set also Do not write
329. om Freescale Semiconductor Inc Input Output Ports I O Port E PTEx Z w READ DDRE 000C rat o WRITE DDRE 000C a DDREx lt RESET lt Q 3 PTEx ao Lu FH z READ PTE 0008 rat Figure 16 19 Port E I O Circuit When bit DDREx is a logic 1 reading address 0008 reads the PTEx data latch When bit DDREx is a logic O reading address 0008 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 16 6 summarizes the operation of the port E pins Table 16 6 Port E Pin Functions Accesses to DDRE Accesses to PTE DDRE Bit PTE Bit I O Pin Mode Read Write Read Write 0 x Input Hi Z DDRE1 DDREO Pin PTE1 PTEO 1 X Output DDRE1 DDREQ PTE1 PTEO PTE1 PTEO Notes 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect input MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O For More Information On This Product Go to www freescale com 227 Freescale Semiconductor Inc Input Output Ports l O Technical Data MC68HC908GR8 Rev 4 0 228 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 17 RAM 17 1 Contents 172 BG d 6 inr Hd qr ao dile de eo ee d
330. om Freescale Semiconductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 IF16 IF15 geogr TRIS NE Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 T R R R R R R R R FLASH Test Control SEED Register FLTCR Pte Reset 0 0 0 0 0 0 0 0 mae HVEN MASS ERASE PGM FLASH Control Register SFE08 FLCR Write Reset 0 0 0 0 0 0 0 0 ia Bit 15 14 13 12 11 10 9 Bit 8 Break Address Register PI l SFE09 High BRKH Write Reset 0 0 0 0 0 0 0 0 a Bit 7 6 5 4 3 2 1 Bit 0 Break Address Register l SFEOA Low BRKL Write Reset 0 0 0 0 0 0 0 0 Read DUKE BEA 0 0 0 0 0 0 Break Status and Control SFEOB Register BRKSCR MI Reset 0 0 0 0 0 0 0 0 Read LVIOUT 0 0 0 0 0 0 0 LVI Status Register FEOC LVISR Write Reset 0 0 0 0 0 0 0 0 Read FLASH Block Protect BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPRO FF7E t Write Register FLBPR Reset U U U U U U U U Read Low byte of reset vector COP Control Register z FFFF COPCTL Write Writing clears COP counter any value Reset Unaffected by reset 1 Non volatile FLASH register Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 8 of 8 Technical Data MC68HC908GR8 Rev 4 0 46 Memory Map MOTOROLA
331. om being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver error CPU interrupt requests NOT AVAILABLE SPI TRANSMITTER CPU INTERRUPT REQUEST SPTE SPTIE SPE NOT AVAILABLE DMAS hd SPRIE SPRF 5m RECEIVER ERROR CPU INTERRUPT REQUEST ERRIE J H MODF Y OVRF Figure 20 11 SPI Interrupt Request Generation MC68HC908GR8 Rev 4 0 Technical Data Serial Peripheral Interface SPI 315 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI The following sources in the SPI status and control register can generate CPU interrupt requests e SPI receiver full bit SPRF The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register If the SPI receiver interrupt enable bit SPRIE is also set SPRF generates an SPI receiver error CPU interrupt request e SPItransmitter empty SPTE The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register If the SPI transmit interrupt enable bit SPTIE is also set SPTE generates an SPTE CPU interrupt request 20 10 Resetting the SPI Any system reset completely resets the SPI Partial resets occur whenever the SPI enable bit SPE is lo
332. onductor Inc Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 000A Unimplemented Write Reset 0 0 0 0 0 0 0 0 Read 000B Unimplemented Write Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 Sapeti BORED Data Direction Register E 000C DDRE Write Reset 0 0 0 0 0 0 0 0 id PTAPUE3 PTAPUE2 PTAPUE1 PTAPUEO 000D Port A Input Pullup Enable Write Register PTAPUE Reset 0 0 0 0 0 0 0 0 3 PTCPUE1 PTCPUEO Port C Input Pullup Enable S000 Register PTCPUE te Reset 0 0 0 0 0 0 0 0 Read 0 Port D Input Pullup Enable me PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUEO S000F Register PTDPUE We Reset 0 0 0 0 0 0 0 0 idi SPRIE me SPMSTR CPOL CPHA SPWOM SPE SPTIE 0010 SPI Control Register Write SPCR Reset 0 0 1 0 1 0 0 0 Read SPRF OVRF MODF SPTE 0011 Write Register SPSCR Reset 0 0 0 0 1 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SPI Data Register 0012 SPDR Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset a LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0013 SCI Control Register 1 Write SCC1 Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 2 of 8 Technical Data MC68HC908GR8 Rev 4 0 40 Memory Ma
333. onductor Inc Serial Communications Interface SCI O Registers 18 9 6 SCI Data Register The SCI data register SCDR is the buffer between the internal data bus and the receive and transmit shift registers Reset has no effect on data in the SCI data register Address 0018 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 RO Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Figure 18 15 SCI Data Register SCDR R7 T RO TO Receive Transmit Data Bits Reading address 0018 accesses the read only received data bits R7 RO Writing to address 0018 writes the data to be transmitted T7 TO Reset has no effect on the SCI data register NOTE Do not use read modify write instructions on the SCI data register 18 9 7 SCI Baud Rate Register The baud rate register SCBR selects the baud rate for both the receiver and the transmitter Address 50019 Bit 7 6 5 4 3 2 1 Bit 0 Read SCP1 SCPO R SCR2 SCR1 SCRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 18 16 SCI Baud Rate Register SCBR MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 265 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI SCP1 and SCPO SCI Baud Rate Prescaler Bits These read write bits select the baud rate
334. or read modify write operation on the PLL control register clears the PLLF bit PLLON PLL On Bit This read write bit activates the PLL and enables the VCO clock CGMVCLK PLLON cannot be cleared if the VCO clock is driving the base clock CGMOUT BCS 1 See Base Clock Selector Circuit Reset sets this bit so that the loop can stabilize as the MCU is powering up 1 PLL on 0 PLL off BCS Base Clock Select Bit This read write bit selects either the crystal oscillator output CGMXCLK or the VCO clock CGMVCLK as the source of the CGMC output CGMOUT CGMOUT frequency is one half the frequency of the selected clock BCS cannot be set while the PLLON bit is clear After toggling BCS it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other During the transition CGMOUT is held in stasis See Base Clock Selector Circuit Reset clears the BCS bit 1 CGMVCLK divided by two drives CGMOUT 0 CGMXCLK divided by two drives CGMOUT NOTE PLLON and BCS have built in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off Therefore PLLON cannot be cleared when BCS Technical Data MC68HC908GR8 Rev 4 0 116 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC CGMC
335. ort bit s DDRC is configured for output mode Address 000E Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 PTCPUE1 PTCPUEO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 12 Port C Input Pullup Enable Register PTCPUE PTCPUE1 PTCPUEO Port C Input Pullup Enable Bits These writeable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port C pin configured to have internal pullup 0 Corresponding port C pin internal pullup disconnected MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 219 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports 1 0 16 6 Port D Port D is an 7 bit special function port that shares four of its pins with the serial peripheral interface SPI module and three of its pins with two timer interface TIM1 and TIM2 modules Port D also has software configurable pullup devices if configured as an input port 16 6 1 Port D Data Register The port D data register PTD contains a data latch for each of the seven port D pins Address 0003 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTDO Write Reset Unaffected by reset P emate T2CH0 T1cH1 TicHo SPSCK mosi miso 88 Function Figure 16 13 Port D Data Register PTD PTD6 PTDO Port
336. other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola and 4 are registered trademarks of Motorola Inc DigitalDNA is a trademark of Motorola Inc Motorola Inc 2002 MC68HC908GR8 Rev 4 0 Technical Data 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Rev 4 0 4 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 List of Paragraphs List of ParagraphS asian PAA Re RR Ra a di 5 Table of COIS a4 dca EET AUR EV ICI ICD ERA C 7 LIBI OF T2DIBS ss G8 069454605 eR ROCA EROR Re 17 List Of FIQUIES isa 00 aaa kRR
337. p 2 3 0 V 1096 Vpp 3 Deviation of average bus frequency over 2 ms N VCO multiplier Technical Data MC68HC908GR8 Rev 4 0 384 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Memory Characteristics 23 17 Memory Characteristics Characteristic Symbol Min Typ Max Unit RAM data retention voltage VRDR 1 3 V FLASH program bus clock frequency 1 MHz FLASH read bus clock frequency fread 32k 8 4M Hz FLASH page erase time tErase 1 ms FLASH mass erase time tMErase 4 ms FLASH PGM ERASE to HVEN set up time tavs 10 us FLASH high voltage hold time tnvh 5 us FLASH high voltage hold time mass erase tnvhi 100 us FLASH program hold time togs 5 us FLASH program time tPRoG 30 40 us FLASH return to read time tan 1 us FLASH cumulative program HV period tuy 4 ms FLASH row erase endurance 10k 100k Cycles FLASH row program endurance 9 10k 100k Cycles FLASH data retention time 10 10019 ma Years Notes 1 fReaq is defined as the frequency range for which the FLASH memory can be read 2 If the page erase time is longer than tErase Min there is no erase disturb but it reduces the endurance of the FLASH memory 3 If the mass erase time
338. p MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output I O Section Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 dodi SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCI Control Register2 0014 SCC2 Write Reset 0 0 0 0 0 0 0 0 pa T8 DMARE DMATE ORIE NEIE FEIE PEIE SCI Control Register 3 0015 8003 Write Reset U U 0 0 0 0 0 0 Read SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 0016 SCS1 Write Reset 1 1 0 0 0 0 0 0 Read BKF RPF SCI Status Register2 0017 6CS2 Write Reset 0 0 0 0 0 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SCI Data Register 0018 SCDR Write T7 T6 T5 T4 T3 T2 Ti TO Reset Unaffected by reset re SCP1 SCPO R SCR2 SCR1 SCRO SCI Baud Rate Register 0019 SCBR Write Reset 0 0 0 0 0 0 0 0 Keyboard Status Read 0 0 0 0 KEYF 0 SRE MODE 001A and Control Register Write ACKK NTKBSCR Reset 0 0 0 0 0 0 0 0 Pa KBIE3 KBIE2 KBIE1 KBIEO 001B Keyboard Interrupt Enable Write Register INTKBIER Reset 0 0 0 0 CEDE TBR2 TBR1 TBRO TBIE TBON R Time Base Module Control 001C Register TBCR Write TACK Reset 0 0 0 0 0 0 0 0 Read 0 0 0 0 IRQF1 0 magi MODEL IRQ Status and Control 001D Register INTSCR
339. parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 MC68HC908GR8 D For More Information On This Product Go to www freescale
340. ping the TIM before executing the WAIT instruction The TIM is inactive after the execution of a STOP instruction The STOP instruction does not affect register conditions or the state of the TIM counter TIM operation resumes when the MCU exits stop mode after an external interrupt MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 347 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM 22 8 TIM During Break Interrupts 22 9 I O Signals Technical Data A break interrupt stops the TIM counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot chan
341. pins lott a m 100 mA Input high voltage All ports IRQs RESET Vin 0 7 x Vpp Vpp V OSC1 0 8 x Vpp Input low voltage V V E All ports IRQs RESET OSC1 IL ss Na porq v Vpp Supply current Run IDD 15 20 mA Wait 4 8 mA Stop 85 C 3 5 uA Stop gt 85 C 5 10 uA Stop with TBM enabled PP 20 35 uA Stop with LVI and TBM enabled m 300 500 uA I O ports Hi Z leakage current liL 10 uA Input current lin 1 uA Technical Data MC68HC908GR8 Rev 4 0 364 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 5 0 V DC Electrical Characteristics Table 23 4 5 0V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Pullup resistors as input only Ports PTAS KBDS PTAO KBDO PTC1 PTCO Rey 20 45 65 kQ PTD6 T2CHO PTDO SS Capacitance Cout 12 Ports as input or output Cin m 8 Br Monitor mode entry voltage Vist Vpp 2 5 8 V Low voltage inhibit trip falling voltage target VTRIPF 3 85 4 25 4 50 V Low voltage inhibit trip rising voltage target VTRIPR 3 95 4 35 4 60 V pode eee D hysteresis target Nive 100 mV POR rearm voltage VpoR 0 100 mV POR reset voltage VPORRST 0 700 800 mV POR rise time ramp rate RpoR 0 035 V ms Notes 1 Vpp 5 0 Vde 10 Vgs 0 Vdc T4 T t
342. ption by disabling the module before executing the WAIT instruction Refer to Low Power Modes for information on exiting wait mode The SCI module is inactive after the execution of a STOP instruction The STOP instruction does not affect SCI register states SCI module operation resumes after an external interrupt Because the internal clock is inactive during stop mode entering stop mode during an SCI transmission or reception results in invalid data Refer to Low Power Modes for information on exiting stop mode MC68HC908GR8 Rev 4 0 250 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI SCI During Break Module Interrupts 18 7 SCI During Break Module Interrupts 18 8 I O Signals The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains cleared when the MCU exits the break state To protect status bits during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state software can read and write I O registers during
343. put compare or PWM signals to the mode select bits MSxB MSxA See Table 22 3 b Write 1 to the toggle on overflow bit TOVx c Write 1 0 to clear output on compare or 1 1 to set output on compare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 22 3 In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 096 duty cycle generation and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value 5 Inthe TIM status control register TSC clear the TIM stop bit TSTOP Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation The TIM channel 0 registers TCHOH TCHOL initially control the buffered PWM output TIM status control register 0 TSCRO controls and monitors the PWM signal from the linked channels Clearing the toggle on overflow bit TOVx inhibits output toggles on TIM overflows Subsequent output compares try to force the output to a state itis already in and have no effect The result is a 096 duty cycle output Setting the channel x maximum duty cycle bit CHxMAX and setting the TOVXx bit generates a 100 duty cycle output See TIM Channel Status and
344. r The PLL control register PCTL contains the interrupt enable and flag bits the on off switch the base clock selector bit the prescaler bits and the VCO power of two range selector bits Address 0036 Bit 7 6 5 4 3 2 1 Bit 0 Read PLLF PLLIE PLLON BCS PRE1 PREO VPR1 VPRO Write Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 7 4 PLL Control Register PCTL PLLIE PLL Interrupt Enable Bit This read write bit enables the PLL to generate an interrupt request when the LOCK bit toggles setting the PLL flag PLLF When the AUTO bit in the PLL bandwidth control register PBWC is clear PLLIE cannot be written and reads as logic 0 Reset clears the PLLIE bit MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 115 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 1 PLL interrupts enabled 0 PLL interrupts disabled PLLF PLL Interrupt Flag Bit This read only bit is set whenever the LOCK bit toggles PLLF generates an interrupt request if the PLLIE bit also is set PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register PBWC is clear Clear the PLLF bit by reading the PLL control register Reset clears the PLLF bit 1 Change in lock condition 0 No change in lock condition NOTE Do not inadvertently clear the PLLF bit Any read
345. r Inc Electrical Specifications Technical Data MC68HC908GR8 Rev 4 0 386 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 24 Mechanical Specifications 24 1 Contents ELE MUR ca doce Kl ol X E KP e dee de oe qol a M ER 387 24 3 32 Pin LQFP Case B73A a wawa rra rn 388 244 28 PinPDIP Case 712 33 paw naa pawa aa ren 389 24 5 28 Pin SOIC Case 751F 0 390 24 2 Introduction The MC68HC908GR8 is available in these packages e 32 pin low profile quad flat pack LQFP e 28 pin dual in line package PDIP e 28 pin small outline package SOIC The package information contained in this section is the latest available at the time of this publication To make sure that you have the latest package specifications contact one of the following Local Motorola Sales Office e World Wide Web at http www motorola com semiconductors Follow World Wide Web on line instructions to retrieve the current mechanical specifications MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Mechanical Specifications 387 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 24 3 32 Pin LQFP Case 873A p A 4X a sas A 0 20 0 008 aB T U z 32 25 ry EG
346. r Inc Resets and Interrupts A logic 0 applied to the RST pin for a time tjp generates an external reset An external reset sets the PIN bit in the SIM reset status register Sources Power on reset POR Computer operating properly COP Low power reset circuits Illegal opcode Illegal address All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices The MCU is held in reset for an additional 33 CGMXCLK cycles after releasing the RST pin PULLED LOW BY MCU RST PIN E I 32 CYCLES gt 32 CYCLES CGMXCLK N R INTERNAL N N RESET 4 3 3 1 Power On Reset Technical Data Figure 4 1 Internal Reset Timing A power on reset is an internal reset caused by a positive transition on the Vpp pin Vpp atthe POR must go completely to O V to reset the MCU This distinguishes between a reset and a POR The POR is not a brown out detector low voltage detector or glitch detector MC68HC908GR8 Rev 4 0 62 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Resets A power on reset e Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles Drives the RST pin low during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after
347. r Inc System Integration Module SIM 19 6 1 2 SWI Instruction The SWI instruction is a non maskable instruction that causes an interrupt regardless of the state of the interrupt mask bit in the condition code register NOTE Asoftware interrupt pushes PC onto the stack A software interrupt does not push PC 1 as a hardware interrupt does 19 6 1 3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources Table 19 3 summarizes the interrupt sources and the interrupt status register flags that they set The interrupt status registers can be useful for debugging Table 19 3 Interrupt Sources er Interrupt Status Priority Interrupt Source Register Flag Highest Reset Technical Data MC68HC908GR8 Rev 4 0 286 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control Table 19 3 Interrupt Sources Priority Interrupt Source a Fan SWI instruction IRQ pin H PLL I2 TIM1 channel 0 I3 TIM1 channel 1 l4 TIM1 overflow I5 TIM2 channel 0 l6 Reserved I7 TIM2 overflow I8 SPI receiver full I9 SPI transmitter empty 110 SCI receive error 114 SCI receive 112 SCI transmit 113 Keyboard 114 ADC conversion complete 115 Lowest Timebase
348. r Inc Timebase Module TBM 21 4 Functional Description NOTE This module is designed for a 32 768 kHz oscillator This module can generate a periodic interrupt by dividing the crystal frequency CGMXCLK The counter is initialized to all Os when TBON bit is cleared The counter shown in Figure 21 1 starts counting when the TBON bit is set When the counter overflows at the tap selected by TBR2 TBRO the TBIF bit gets set If the TBIE bit is set an interrupt request is sent to the CPU The TBIF flag is cleared by writing a 1 to the TACK bit The first time the TBIF flag is set after enabling the timebase module the interrupt is generated at approximately half of the overflow period Subsequent events occur at the exact period CGMXCLK TBMINT Figure 21 1 Timebase Block Diagram Technical Data MC68HC908GR8 Rev 4 0 330 Timebase Module TBM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timebase Module TBM Timebase Register Description 21 5 Timebase Register Description The timebase has one register the TBCR which is used to enable the timebase interrupts and set the rate Address S001C Bit 7 6 5 4 3 2 1 Bit 0 Read TBIF 0 TBR2 TBR1 TBRO TBIE TBON Reserved Write TACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 21 2 Timebase Control Register TBCR TBIF Timebase Interrupt Flag T
349. r X hha _ IX2 D6 j eeff 4 LDA opr X Load A from M Ac M tit IX1 E6 f 3 LDA X IX F6 2 LDA opr SP SP1 9EE6 ff 4 LDA opr SP SP2 9ED6 ee ff 5 LDHX opr 3 3 _ IMM 45 iiijj 3 LDHX opr Load H X from M H X MM 1 i iii DIR 55 Idd 4 LDX opr IMM AE ji 2 LDX opr DIR BE dd 3 LDX opr EXT CE hhll 4 LDX opr X Tl la IX2 DE leeff 4 LDX opr X Load X from M X M tit 1X4 EE li 3 LDX X IX FE 2 LDX opr SP SP1 9EEE f 4 LDX opr SP SP2 9EDE lee ff 5 LSL opr DIR 38 dd H LSLA lt _ lt INH 48 LSLX Logical Shift Left pla lt 0 hahaha INH 58 1 LSL oprX Same as ASL b7 b a LS pi ff 4 LSL X LSL oprSP SP1 9E68 tf 5 LSR opr DIR 34 dd 4 LSRA INH 44 1 LSR oprX Logical Shift Right 0 8 C PAPA ka t NP e ile 1 LSR X b7 bo IX 74 3 LSR opr SP SP1 9E64 ff 5 oy EG i M pestination M source SE ae E di ga 3 MOV stopr opr ove f 17154 EC liMD 6E lidd 4 MOV Xz opr H X H X 1 IX D DIX IX D 7E dd 4 MUL Unsigned multiply KA X x A 0 0 INH 42 5 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU 151 For More Information On This Product Go to www freescale com Central Processing Unit CPU Freescale Semiconductor Inc Table 10 1 Instruction Set Summary Continued Effect
350. r also contains bits that perform these functions Enable error interrupts Enable mode fault error detection e Select master SPI baud rate Technical Data MC68HC908GR8 Rev 4 0 324 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI O Registers Address 0011 Bit 7 6 5 4 3 2 1 Bit 0 Read SPRF OVRF MODF SPTE ERRIE MODFEN SPR1 SPRO Write Reset 0 0 0 0 1 0 0 0 Unimplemented Figure 20 14 SPI Status and Control Register SPSCR SPRF SPI Receiver Full Bit This clearable read only flag is set each time a byte transfers from the shift register to the receive data register SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also During an SPRF CPU interrupt the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register Reset clears the SPRF bit 1 Receive data register full 0 Receive data register not full ERRIE Error Interrupt Enable Bit This read write bit enables the MODF and OVRF bits to generate CPU interrupt requests Reset clears the ERRIE bit 1 MODF and OVRF can generate CPU interrupt requests 0 MODF and OVRF cannot generate CPU interrupt requests OVRF Overflow Bit This clearable read only flag is set if s
351. r an oscillator stabilization delay of 4096 CGMXCLK cycles after the power supply voltage rises to VTRIPF Drives the RST pin low for as long as Vpp is below Vrpipr and during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the LVI bit in the SIM reset status register 4 3 3 4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set An illegal opcode reset sets the ILOP bit in the SIM reset status register If the stop enable bit STOP in the mask option register is a logic O the STOP instruction causes an illegal opcode reset 4 3 3 5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address An illegal address reset sets the ILAD bit in the SIM reset status register A data fetch from an unmapped address does not generate a reset Technical Data MC68HC908GR8 Rev 4 0 64 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Resets 4 3 4 SIM Reset Status Register This read only register contains flags to show reset sources All flag bits are automatically cleared following a read of the register Reset service
352. r of the CPU08 This bit indicates a carry from the low order four bits of the accumulator value to the high order four bits The half carry bit is required for binary coded decimal arithmetic operations The decimal adjust accumulator DAA instruction uses the state of the H and C bits to determine the appropriate correction factor hexadecimal Base 16 numbering system that uses the digits 0 through 9 and the letters A through F high byte The most significant eight bits of a word Technical Data MC68HC908GR8 Rev 4 0 398 Glossary MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Glossary illegal address An address not within the memory map illegal opcode A nonexistent opcode The interrupt mask bit in the condition code register of the CPU08 When is set all interrupts are disabled index register H X A 16 bit register in the CPU08 The upper byte of H X is called H The lower byte is called X In the indexed addressing modes the CPU uses the contents of H X to determine the effective address of the operand H X can also serve as a temporary data storage location input output I O Input output interfaces between a computer system and the external world A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal instructions Operations that a CPU can perform I
353. r shifts a character out to the PE2 TxD pin The SCI data register SCDR is the write only buffer between the internal data bus and the transmit shift register To initiate an SCI transmission 1 Enable the SCI by writing a logic 1 to the enable SCI bit ENSCI in SCI control register 1 SCC1 2 Enable the transmitter by writing a logic 1 to the transmitter enable bit TE in SCI control register 2 SCC2 3 Clear the SCI transmitter empty bit by first reading SCI status register 1 SCS1 and then writing to the SCDR 4 Repeat step 3 for each subsequent transmission At the start of a transmission transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s After the preamble shifts out control logic transfers the SCDR data into the transmit shift register A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register A logic 1 stop bit goes into the most significant bit position The SCI transmitter empty bit SCTE in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register The SCTE bit indicates that the SCDR can accept new data from the internal data bus If the SCI transmit interrupt enable bit SCTIE in SCC2 is also set the SCTE bit generates a transmitter CPU interrupt request When the transmit shift register is not transmitting a character the PE2 TxD pin goes to the idle condition logic 1 If at any time s
354. rX IX2 DF leeff 4 STX opr X Store X in M M e X t IX1 EF ff 3 STX X IX FF 2 STX opr SP SP1 9EEF ff 4 STX opr SP SP2 9EDF Jee ff 5 SUB opr IMM AO iii 2 SUB opr DIR BO dd 3 SUB opr EXT CO hhll 4 SUB opr X IX2 DO jeeff 4 SUB opr X Subtract A A M t i1 IX1 EO 3 SUB X IX FO 2 SUB opr SP SP1 9EEO ff 4 SUB opr SP SP2 9EDO eeff 5 PC lt PC 1 Push PCL SP SP 1 Push PCH SP SP 1 Push X SWI Software Interrupt SP SP 1 Push CCR 1 INH 83 9 SP e SP 1 1 lt 1 PCH Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAP Transfer A to CCR CCR c A tl3l3 3 INH 84 2 TAX Transfer A to X X c A i 7 INH 97 1 TPA Transfer CCR to A A amp CCR INH 85 1 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU For More information On This Product Go to www freescale com 153 Freescale Semiconductor Inc Central Processing Unit CPU Table 10 1 Instruction Set Summary Continued Effecton 5 Source e CCR a S flo Operation Description 9o o S 9 Form 99 8 glo o 2 VH IINZC gsl l 6 TST opr DIR 3D dd 3 TSTA INH 4D 1 INH 5D 1 TST opr x Test for Negative or Zero A 00 or x 00 or M 00 0 i Bp lge le TST X IX 7D 2 TST opr
355. ral device port A set of wires for communicating with off chip devices MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Glossary 401 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc prescaler A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1 2 1 8 1 10 etc program A set of computer instructions that cause a computer to perform a desired operation or operations program counter PC A 16 bit register in the CPU08 The PC register holds the address of the next instruction or operand that the CPU will use pull An instruction that copies into the accumulator the contents of a stack RAM location The stack RAM address is in the stack pointer pullup A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply pulse width The amount of time a signal is on as opposed to being in its off state pulse width modulation PWM Controlled variation modulation of the pulse width of a signal with a constant frequency push An instruction that copies the contents of the accumulator to the stack RAM The stack RAM address is in the stack pointer PWM period The time required for one complete cycle of a PWM waveform RAM Random access memory All RAM locations can be read or written by the CPU The contents of a RAM memory location rem
356. ration and high output frequency resolution Programmable prescaler for power of two increases in frequency Programmable hardware voltage controlled oscillator VCO for low jitter operation Automatic bandwidth control mode for low jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Configuration register bit to allow oscillator operation during stop mode 7 4 Functional Description The CGMC consists of three major submodules Crystal oscillator circuit The crystal oscillator circuit generates the constant crystal frequency clock CGMXCLK Phase locked loop PLL The PLL generates the programmable VCO frequency clock CGMVCLK Base clock selector circuit This software controlled circuit selects either CGMXCLK divided by two or the VCO clock CGMVCLK divided by two as the base clock CGMOUT The SIM derives the system clocks from either CGMOUT or CGMXCLK Figure 7 1 shows the structure of the CGMC Technical Data MC68HC908GR8 Rev 4 0 100 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description OSCILLATOR OSC Do CGMXCLK e e gt Mare p TO SIM TIMTB15A ADC SIMOSCEN FROM SIM OSCSTOPENB FROM CONFIG OSC2 PHASE LOCKED LOOP PLL
357. rdless of the state of the data direction register of the shared I O port MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 319 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 13 3 SPSCK Serial Clock The serial clock synchronizes data transmission between master and slave devices In a master MCU the SPSCK pin is the clock output In a slave MCU the SPSCK pin is the clock input In full duplex operation the master and slave MCUs exchange a byte of data in eight serial clock cycles When enabled the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I O port 20 13 4 SS Slave Select Technical Data NOTE The SS pin has various functions depending on the current state of the SPI For an SPI configured as a slave the SS is used to select a slave For CPHA 0 the SS is used to define the start of a transmission See Transmission Formats Since it is used to indicate the start of a transmission the SS must be toggled high and low between each byte transmitted for the CPHA 0 format However it can remain low between transmissions for the CPHA 1 format See Figure 20 12 MISO MOSI y BYTE 1 y BYTE 2 y BYTE 3 MASTERSS s L BASS E a SLAVE SS CPHA 1 Figure 20 12CPHA SS Timing When an SPI is configure
358. re 1 is used to indicate TIM1 and 2 is used to indicate TIM2 The two TIMs share three I O pins with three port D I O port pins The full names of the TIM I O pins are listed in Table 22 1 The generic pin names appear in the text that follows Table 22 1 Pin Name Conventions TIM Generic Pin Names T 1 2 CHO T 1 2 CH1 Full TIM TIM1 PTD4 ATD12 TBLCK PTD5 T1CH1 Pin Names TIM2 PTD6 ATD14 TACLK MC68HC908GR8 Rev 4 0 336 Timer Interface Module TIM For More Information On This Product Go to www freescale com MOTOROLA NOTE NOTE Freescale Semiconductor Inc Timer Interface Module TIM Functional Description References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TCHO may refer generically to T1CHO and T2CHO and TCH will refer to T1CH1 The Timer Interface Module in MC68HC908GR8 is constructed by TIM1 which is contained channel 0 and 1 and TIM2 which is contained channel 0 only 22 5 Functional Description NOTE References to TCLK and external TIM clock input are only valid if the MCU has an external TCLK pin If the MCU has no external TCLK pin the TIM module must use the internal bus clock prescaler selections Figure 22 1 shows the structure of the TIM The central component of the TIM is the 16 bit TIM counter that can operate as a free running counter or a modulo up counter The TIM counter pro
359. reak address register match occurs on the last cycle of a CPU instruction the break interrupt begins immediately 6 4 3 TIMI and TIM2 During Break Interrupts A break interrupt stops the timer counters 6 4 4 COP During Break Interrupts The COP is disabled during a break interrupt when V g7 is present on the RST pin 6 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 6 5 1 Wait Mode If enabled the break module is active in wait mode In the break routine the user can subtract one from the return address on the stack if SBSW is set See Low Power Modes Clear the BW bit by writing logic O to it 6 5 2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register 6 6 Break Module Registers These registers control and monitor operation of the break module Break status and control register BRKSCR Break address register high BRKH Technical Data MC68HC908GR8 Rev 4 0 94 Break Module BRK MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Break Module Registers Break address register low BRKL SIM break status register SBSR SIM break flag control register SBFCR 6 6 1 Break Status and Control Register The break status and control register BRKSCR contains break module enable and status bits Address SFEOE
360. ring an SPI transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock synchronizes shifting and sampling on the two serial data lines A slave select line allows selection of an individual slave SPI device slave devices that are not selected do not interfere with SPI bus activities On a master SPI device the slave select line can optionally be used to indicate multiple master bus contention 20 6 1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock SPSCK phase and polarity using two bits in the SPI control register SPCR The clock polarity is specified by the CPOL control bit which selects an active high or low clock and has no significant effect on the transmission format MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 303 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI NOTE The clock phase CPHA control bit selects one of two fundamentally different transmission formats The clock phase and polarity should be identical for the master SPI device and the communicating slave device In some cases the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements Before writing to the CPOL bit or the CPHA bit di
361. rnal Connections Technical Data In its typical configuration the CGMC requires up to nine external components Five of these are for the crystal oscillator and two or four are for the PLL The crystal oscillator is normally connected in a Pierce oscillator configuration as shown in Figure 7 2 Figure 7 2 shows only the logical representation of the internal components and may not represent actual circuitry The oscillator configuration uses five components Crystal X4 Fixed capacitor C e Tuning capacitor C can also be a fixed capacitor e Feedback resistor Rp Series resistor Rs MC68HC908GR8 Rev 4 0 110 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description The series resistor Rs is included in the diagram to follow strict Pierce oscillator guidelines Refer to the crystal manufacturer s data for more information regarding values for C1 and C2 Figure 7 2 also shows the external components for the PLL e Bypass capacitor Cpyp Filter network Routing should be done with great care to minimize signal cross talk and noise See CGM Component Specifications for capacitor and resistor values SIMOSCEN OSCSTOPENB FROM CONFIG 1 A Do CGMXCLK j M OSC1 OSC2 CGMXFC Vssa
362. rt pins e Higher current 15 mA sink source capability on PTCO PTC1 e Timebase module with clock prescaler circuitry for eight user selectable periodic real time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external 32 kHz crystal e Oscillator stop mode enable bit OSCSTOPENB in the CONFIG register to allow user selection of having the oscillator enabled or disabled during stop mode Technical Data MOTOROLA General Description 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 4 bit keyboard wakeup port 32 pin quad flat pack QFP or 28 pin plastic dual in line package DIP or 28 pin small outline integrated circuit SOIC Specific features of the MC68HC908GR8 in 28 pin DIP and 28 pin SOIC are Port B is only 4 bits PTBO PTB3 4 channel ADC module No Port C bits 1 3 2 Features of the CPU08 Features of the CPU08 include Enhanced HC05 programming model Extensive loop control functions 16 addressing modes eight more than the HC05 16 bit index register and stack pointer Memory to memory data transfers Fast 8 x 8 multiply instruction Fast 16 8 divide instruction Binary coded decimal BCD instructions Optimization for controller applications Efficient C language support 1 4 MCU Block Diagram Figure 1 1 shows the structure of the MC68HC908GR8 Technical Data MC68HC9
363. s In cases where desired bus frequency has some tolerance choose fpc x to a value determined either by other module requirements such as modules which are clocked by CGMXCLK cost requirements or ideally as high as the specified range Technical Data MC68HC908GR8 Rev 4 0 106 Clock Generator Module CGMC MOTOROLA For More Information On This Product Go to www freescale com MC68HC908GR8 Rev 4 0 Freescale Semiconductor Inc Clock Generator Module CGMC Functional Description allows See Electrical Specifications Choose the reference divider R 1 After choosing N and P the actual bus frequency can be determined using equation in 2 above When the tolerance on the bus frequency is tight choose fpc to an integer divisor of fsyspgs and R 1 If fac cannot meet this requirement use the following equation to solve for R with practical choices of fac x and choose the fpc that gives the lowest R f f R round Rya EMSPES image aes FROLK FRCLK 4 Select a VCO frequency multiplier N R xf E rouna vemoss RCLK Reduce N R to the lowest possible R 5 If Nis Nmax use P 0 If N gt Nmax choose P using this table Current N Value P Oe NSN ix 0 Nmax SN SNimay X2 1 Nmax X2 lt N lt N mnax X4 2 Naay 4 NSN ag KO 3 Then recalculate N Rxf N round d P facuk X 6 Calculate and verify the adequacy of the VCO and bus frequencies fyc
364. s a 8192 word by 8 bit CMOS page erase byte 8 bit program Embedded Flash Memory Each page consists of 64 bytes The page erase operation erases all words within a page A page is composed of two adjacent rows The address ranges for the user memory and vectors are as follows e E000 FDFF user memory for the MC68HC908GR8 EEO00 FDFF user memory for the MC68HC908GR4 e FF7E FLASH block protect register e SFE08 FLASH control register e FFDC FFFF these locations are reserved for user defined interrupt and reset vectors Programming tools are available from Motorola Contact your local Motorola representative for more information NOTE A security feature prevents viewing of the FLASH contents 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users Technical Data MC68HC908GR8 Rev 4 0 158 Flash Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory FLASH Control Register 11 4 FLASH Control Register The FLASH control register FLCR controls FLASH program and erase operations Address SFE08 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 HVEN MASS ERASE PGM Write Reset 0 0 0 0 0 0 0 0 Figure 11 1 FLASH Control Register FLCR HVEN High Voltage Enable Bit This read write bit enables the charge pump
365. s at logic 1 See SCI Control Register 1 18 5 2 6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter e SCl transmitter empty SCTE The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register SCTE can generate a transmitter CPU interrupt request Setting the SCI transmit interrupt enable bit SCTIE in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests Transmission complete TC The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated The transmission complete interrupt enable bit TCIE in SCC2 enables the TC bit to generate transmitter CPU interrupt requests 18 5 3 Receiver Figure 18 5 shows the structure of the SCI receiver 18 5 3 1 Character Length The receiver can accommodate either 8 bit or 9 bit data The state of the M bit in SCI control register 1 SCC1 determines character length When receiving 9 bit data bit R8 in SCI control register 2 SCC2 is the ninth bit bit 8 When receiving 8 bit data bit R8 is a copy of the eighth bit bit 7 Technical Data MC68HC908GR8 Rev 4 0 240 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description 18 5 3 2 C
366. sable the SPI by clearing the SPI enable bit SPE 20 6 2 Transmission Format When CPHA 0 Technical Data Figure 20 4 shows an SPI transmission in which CPHA is logic 0 The figure should not be used as a replacement for data sheet parametric information Two waveforms are shown for SPSCK one for CPOL 0 and another for CPOL 1 The diagram may be interpreted as a master or slave timing diagram since the serial clock SPSCK master in slave out MISO and master out slave in MOSI pins are directly connected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MISO output only when its slave select input SS is at logic O so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose l O not affecting the SPI See Mode Fault Error When CPHA 0 the first SPSCK edge is the MSB capture strobe Therefore the slave must begin driving its data before the first SPSCK edge and a falling edge on the SS pin is used to start the slave data transmission The slave s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 20 5 MC68HC908GR8 Rev 4 0 304 Serial Peripheral Interface SPI MOTO
367. scale Semiconductor Inc System Integration Module SIM 19 7 2 Stop Mode Technical Data NOTE NOTE e ab JC nA nog C IDB SA6Y A6 46 E A N RST CGMXCLK Figure 19 17 Wait Recovery from Internal Reset In stop mode the SIM counter is reset and the system clocks are disabled An interrupt request from a module can cause an exit from stop mode Stacking for interrupts begins after the selected stop recovery time has elapsed Reset or break also causes an exit from stop mode The SIM disables the clock generator module outputs CGMOUT and CGMXCLK in stop mode stopping the CPU and peripherals Stop recovery time is selectable using the SSREC bit in the mask option register MOR If SSREC is set stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 This is ideal for applications using canned oscillators that do not require long startup times from stop mode External crystal applications should use the full stop recovery time by clearing the SSREC bit A break interrupt during stop mode sets the SIM break stop wait bit SBSW in the SIM break status register SBSR The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery It is then used to time the recovery period Figure 19 18 shows stop mode entry timing To m
368. scription With the input capture function the TIM can capture the time at which an external event occurs When an active edge occurs on the pin of an input capture channel the TIM latches the contents of the TIM counter into the TIM channel registers TCHxH TCHXxL The polarity of the active edge is programmable Input captures can generate TIM CPU interrupt requests 22 5 3 Output Compare With the output compare function the TIM can generate a periodic pulse with a programmable polarity duration and frequency When the counter reaches the value in the registers of an output compare channel the TIM can set clear or toggle the channel pin Output compares can generate TIM CPU interrupt requests 22 5 4 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in Output Compare The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods For example writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period Also using a TIM overflow interrupt routine to write a new smaller output compare value may cause the compare to be mis
369. sed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the output compare value on channel x MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 341 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Interface Module TIM When changing to a smaller value enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current output compare pulse The interrupt routine has until the end of the counter overflow period to write the new value When changing to a larger output compare value enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine The TIM overflow interrupt occurs at the end of the current counter overflow period Writing a larger value in an output compare interrupt routine at the end of the current pulse could cause two output compares to occur in the same counter overflow period 22 5 5 Buffered Output Compare NOTE Technical Data Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCHO pin The TIM channel registers of the linked pair alternately control the output Setting the MSOB bit in TIM channel 0 status and control register TSCO links channel 0 and channel 1 The output
370. special registers containing one time writeable latches after each reset Upon a reset the CONFIG registers default to predetermined settings as shown in Figure 8 1 and Figure 8 2 Address 001E Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 OSC SCIBD STOPEN SRC Write B Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 8 1 Configuration Register 2 CONFIG2 Address 001F Bit 7 6 5 4 3 2 1 Bit 0 Read LVIP COPRS LVISTOP LVIRSTD LVI50R3 SSREC STOP COPD Write WRD Reset 0 0 0 0 See Note 0 0 0 Note LVI5OR3 bit is only reset via POR power on reset Figure 8 2 Configuration Register 1 CONFIG1 Technical Data MC68HC908GR8 Rev 4 0 130 Configuration Register CONFIG MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration Register CONFIG Functional Description OSCSTOPENB Oscillator Stop Mode Enable Bar Bit OSCSTOPENB enables the oscillator to continue operating during stop mode Setting the OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode This is useful for driving the timebase module to allow it to generate periodic wakeup while in stop mode See Clock Generator Module CGM subsection Stop Mode 1 Oscillator enabled to operate during stop mode 0 Oscillator disabled during stop mode default SCIBDSRC SCI Baud Rate Clock Source B
371. ster B DDRB DDRB5 DDRBO Data Direction Register B Bits These read write bits control port B data direction Reset clears DDRB5 DDRB0 configuring all port B pins as inputs 1 Corresponding port B pin configured as output 0 Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from O to 1 NOTE Forthose devices packaged in a 28 pin DIP and SOIC package PTB5 4 are not connected Set DDRB5 4 to a 1 to configure PTB5 4 as outputs Figure 16 8 shows the port B I O logic Technical Data MC68HC908GR8 Rev 4 0 214 Input Output Ports I O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports I O Port B Z w READ DDRB 0005 9 WRITE DDRB 0005 m DDRBx lt RESET lt Q d WRITE PTB 0001 z PTBx PTBx ao Lu FH z READ PTB 0001 rat Figure 16 8 Port B I O Circuit When bit DDRBx is a logic 1 reading address 0001 reads the PTBx data latch When bit DDRBx is a logic O reading address 0001 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 16 3 summarizes the operation of the port B pins Table 16 3 Port B Pin Functions Accesses DDRB Accesses to PTB DDRB Bit PTB Bit
372. sultant 16 bit address is used for specifying the start address of the FLASH memory for block protection The FLASH is protected from this start address to the end of FLASH memory at FFFF With this mechanism the protect start address can be XX00 XX40 XX80 and XXCO 64 bytes page boundaries within the FLASH memory 16 bit memory address Start address of FLASH block protect 1 1 L FiBPRwhe 0 0 0 0 0 0 Figure 11 4 FLASH Block Protect Start Address MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Flash Memory 165 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory 11 9 Wait 11 10 STOP Mode Technical Data Mode NOTE Examples of protect start address Table 11 1 Examples of protect start address BPR 7 0 Start of Address of Protect Range 80 The entire FLASH memory is protected 81 1000 0001 E040 1110 0000 0100 0000 82 1000 0010 E080 1110 0000 1000 0000 and so on FE 1111 1110 FF80 1111 1111 1000 0000 FF The entire FLASH memory is not protected Note The end address of the protected range is always FFFF Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly but there will not be any memory activity since the CPU is inactive The WAIT instruction sho
373. t Once the part has been programmed the traditional method of applying a voltage Vrsr to IRQ must be used to enter monitor mode The COP module is disabled in monitor mode based on these conditions f monitor mode was entered as a result of the reset vector being blank condition set 2 or 3 the COP is always disabled regardless of the state of IRQ or RST If monitor mode was entered with Vrg7 on IRQ condition set 1 then the COP is disabled as long as V sr is applied to either IRQ or RST The second condition states that as long as Vrsr is maintained on the IRQ pin after entering monitor mode or if Vrgz is applied to RST after the initial reset to get into monitor mode when V7g7 was applied to IRQ then the COP will be disabled In the latter situation after VrsT is applied to the RST pin Vrgz can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode Figure 15 2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just 1 x Vpp voltage is applied to the IRQ pin An external oscillator of 9 8304 MHz is required for a baud rate of 9600 as the internal bus frequency is automatically set to the external frequency divided by four MC68HC908GR8 Rev 4 0 194 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description
374. t pins also have selectable pullups when configured for input mode The pullups are disengaged when configured for output mode The pullups are selectable on an individual port bit basis 1 6 11 Port D I O Pins PTD6 T2CHO PTDO SS PTD6 PTDO are special function bidirectional I O port pins PTDS PTDO can be programmed to be serial peripheral interface SPI pins while PTD6 PTD4 can be individually programmed to be timer interface module TIM1 and TIM2 pins See Timer Interface Module TIM Serial Peripheral Interface SPI and Input Output Ports I O These port pins also have selectable pullups when configured for input mode The pullups are disengaged when configured for output mode The pullups are selectable on an individual port bit basis When the port pins are configured for special function mode SPI TIM1 TIM2 pullups can be selectable on an individual port pin basis 1 6 12 Port E I O Pins PTE1 RxD PTE0 TxD Technical Data NOTE PTE1 PTEO are special function bidirectional l O port pins These pins can also be programmed to be serial communications interface SCI pins See Serial Communications Interface SCI and Input Output Ports 1 O Any unused inputs and I O ports should be tied to an appropriate logic level either Vpp or Vss Although the I O ports of the MC68HC908GHR8 do not require termination termination is recommended to reduce the possibility of electro static discharge damage MC68HC908GR8
375. t subroutine Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly 9 4 I O Signals The following paragraphs describe the signals shown in Figure 9 1 9 4 1 CGMXCLK CGMXCLK is the crystal oscillator output signal CGMXCLK frequency is equal to the crystal frequency 9 4 2 STOP Instruction The STOP instruction clears the COP prescaler 9 4 3 COPCTL Write Writing any value to the COP control register COPCTL see COP Control Register clears the COP counter and clears bits 12 through 5 of the prescaler Reading the COP control register returns the low byte of the reset vector 9 4 4 Power On Reset The power on reset POR circuit clears the COP prescaler 4096 CGMXCLK cycles after power up 9 4 5 Internal Reset An internal reset clears the COP prescaler and the COP counter MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Computer Operating Properly COP 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Computer Operating Properly COP 9 4 6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus A reset vector fetch clears the COP prescaler 9 4 7 COPD COP Disable The COPD signal reflects the state of the COP disable bit COPD in the configuration register See Configuration Register CONFIG 9 4 8 COPRS COP Rate Select The COPRS sig
376. ta valid time after enable edge 10 Master tym 50 ns Slave tvs 50 ns Data hold time outputs after enable edge 11 Master tHo M 0 ns Slave tH0 s 0 ns Notes 1 Numbers refer to dimensions in Figure 23 16 and Figure 23 17 2 All timing is shown with respect to 20 Vpp and 70 Vpp unless noted 100 pF load on all SPI pins 3 Time to data active from high impedance state 4 Hold time to high impedance state 5 With 100 pF on all SPI pins MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 379 For More Information On This Product Go to www freescale com Electrical Specifications Freescale Semiconductor Inc 23 14 3 0 V SPI Characteristics Diagram F 3 istic Symbol Min Max Unit Norbert Characteristic y Operating frequency Master foP M fop 1 28 fop 2 MHz Slave fop s DC fop MHz Cycle time 1 Master lcvc M 2 128 lcyc Slave lcvc s 1 toye 2 Enable lead time ll ead s 1 teyc 3 Enable lag time li ag s 1 leyc Clock SPSCK high time 4 Master tscKH M toyo 735 64 toyo ns Slave 15CKH S 1 2 loyc 35 ns Clock SPSCK low time 5 Master tsckL M teye 35 64 toye ns Slave tsckL s 1 2 lcyc 35 ns Data setup time inputs 6 Master tsu M 40 ns Slave tsus 40 ns Data hold time inputs 7 Master tH m 40 ns Slave tH s 40 ns Access time slave 9 8 CPHA 0 tA CPO 0 50 ns CPHA 1 tA CP1 0 50 ns 9 Disabl
377. ter The error interrupt enable bit ERRIE enables OVRF CPU interrupt requests OVRF and ERRIE are in the SPI status and control register SCI CPU interrupt sources MC68HC908GR8 Rev 4 0 SCI transmitter empty bit SCTE SCTE is set when the SCI data register transfers a character to the transmit shift register The SCI transmit interrupt enable bit SCTIE enables transmitter CPU interrupt requests SCTE is in SCI status register 1 SCTIE is in SCI control register 2 Transmission complete bit TC TC is set when the transmit shift register and the SCI data register are empty and no break or idle character has been generated The transmission complete interrupt enable bit TCIE enables transmitter CPU interrupt requests TC is in SCI status register 1 TCIE is in SCI control register 2 SCI receiver full bit SCRF SCRF is set when the receive shift register transfers a character to the SCI data register The SCI receive interrupt enable bit SCRIE enables receiver CPU interrupts SCRF is in SCI status register 1 SCRIE is in SCI control register 2 Idle input bit IDLE IDLE is set when 10 or 11 consecutive logic 1s shift in from the RxD pin The idle line interrupt enable bit ILIE enables IDLE CPU interrupt requests IDLE is in SCI status register 1 ILIE is in SCI control register 2 Receiver overrun bit OR OR is set when the receive shift register shifts in a new character before the previous character w
378. ternal reset recovery sequences 19 6 Exception Control Normal sequential program execution can be changed in three different ways Interrupts Maskable hardware CPU interrupts Non maskable software interrupt instruction SWI Reset Breakinterrupts 19 6 1 Interrupts At the beginning of an interrupt the CPU saves the CPU register contents on the stack and sets the interrupt mask bit to prevent additional interrupts At the end of an interrupt the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume Figure 19 8 shows interrupt entry timing Figure 19 9 shows interrupt recovery timing Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing The arbitration result is a constant that the CPU uses to determine which vector to fetch Once an interrupt is latched by the SIM no other interrupt can take precedence regardless of priority until the latched interrupt is serviced or the bit is cleared See Figure 19 10 Technical Data MC68HC908GR8 Rev 4 0 282 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM Exception Control MODULE INTERRUPT J IBIT IAB J pummy J SP sp 1 sP 2 sP s sP 4 VECTH vEcTL JSTARTADDR y IDB DUMMY PC 1 7 0 PC 1 15 8
379. ternal interrupt A high to low transition on an external interrupt pin loads the program counter with the contents of locations FFFA and FFFB IRQ pin FFDE and FFDF keyboard interrupt pins MC68HC908GR8 Rev 4 0 58 Low Power Modes MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes Low voltage inhibit LVI reset A power supply voltage below the LVlirip voltage resets the MCU and loads the program counter with the contents of locations FFFE and FFFF Break interrupt A break interrupt loads the program counter with the contents of locations SFFFC and SFFFD e Timebase module TBM interrupt A TBM interrupt loads the program counter with the contents of locations FFDC and SFFDD when the timebase counter has rolled over This allows the TBM to generate a periodic wakeup from stop mode Upon exit from stop mode the system clocks begin running after an oscillator stabilization delay A 12 bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt The short stop recovery bit SSREC in the configuration register controls the oscillator stabilization delay during stop recovery Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles NOTE Use the full stop recovery time SSREC 0 in applications that use an external crystal T
380. th Control Write Register PBWC Reset Read Write Reset Read Write Reset Read Write Reset Read PLL Multiplier Select High Register PMSH PLL Multiplier Select Low Register PMSL PLL VCO Select Range Register PMRS PLL Reference Divider Write Select Register PMDS Reset Figure 2 2 Control Status and Data Registers Sheet 6 of 8 Technical Data Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Indeterminate after reset 0 0 0 0 0 0 0 0 Indeterminate after reset Indeterminate after reset PLLF PLLIE PLLON BCS PRE1 PREO VPR1 VPRO 0 0 1 0 0 0 0 0 LOCK P 0 0 0 0 AUTO ACQ R 0 0 0 0 0 0 0 0 0 0 0 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MULA MUL3 MUL2 MUL1 MULO 0 1 0 0 0 0 0 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRSO 0 1 0 0 0 0 0 0 0 0 0 0 RDS3 RDS2 RDS1 RDSO 0 0 0 0 0 0 0 1 Unimplemented R Reserved U Unaffected MC68HC908GR8 Rev 4 0 44 Memory Map For More Information On This Product Go to www freescale com MOTOROLA Addr 003C 003D 003E 003F FE00 SFE01 FE02 FE03 SFE09 SFEOA SIM Break Status Register SIM Reset Status Register Interrupt Status Register 1 Interrupt Status Register 2 Freescale Semiconductor Inc Register Name A
381. the CPU registers from the stack and restores the interrupt mask from the stack After any reset the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction CLI Technical Data MC68HC908GR8 Rev 4 0 144 Central Processing Unit CPU MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Central Processing Unit CPU Arithmetic logic unit ALU N Negative flag The CPU sets the negative flag when an arithmetic operation logic operation or data manipulation produces a negative result setting bit 7 of the result 1 Negative result 0 Non negative result Z Zero flag The CPU sets the zero flag when an arithmetic operation logic operation or data manipulation produces a result of 00 1 Zero result 0 Non zero result C Carry borrow flag The CPU sets the carry borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow Some instructions such as bit test and branch shift and rotate also clear or set the carry borrow flag 1 Carry out of bit 7 0 No carry out of bit 7 10 5 Arithmetic logic unit ALU The ALU performs the arithmetic and logic operations defined by the instruction set Refer to the CPU08 Reference Manual Motorola document number CPUOS8RM AD for a description of the instructions and addressing modes
382. the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit Port E shares two of its pins with the SCI module The two SCI I O pins are e PE2 TxD Transmit data e PE1 RxD Receive data 18 8 1 PE2 TxD Transmit Data The PE2 TxD pin is the serial data output from the SCI transmitter The SCI shares the PE2 TxD pin with port E When the SCI is enabled the PE2 TxD pin is an output regardless of the state of the DDREO bit in data direction register E DDRE MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 251 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 18 8 2 PE1 RxD Receive Data The PE1 RxD pin is the serial data input to the SCI receiver The SCI shares the PE1 RxD pin with port E When the SCI is enabled the PE1 RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E DDRE 18 9 I O Registers These I O registers control and monitor SCI operation e SCI control register 1 SCC1 e SCl control register 2 SCC2 e SCl control register 3 SCC3 e SCI status register 1 SCS1 e SCI status register 2 S
383. tics 370 Output Low Voltage Characteristics 373 Typical Supply Currents eek xx wx ERREUR 376 ADC Characteristics Leid aae RO Rd OR ORC RR ee RR 378 5 0 Y SPI Characteristics Loue kr RETE a AER ERR 378 3 0 V SPI Characteristics o BAKER ERE RE E 380 Timer Interface Module Characteristics 383 Technical Data MOTOROLA Table of Contents 15 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc Table of Contents 23 16 Clock Generation Module Characteristics 383 23 17 Memory Characteristics kak NABA BEA KAEN 385 24 1 24 2 24 3 24 4 24 5 25 1 25 2 25 3 25 4 Section 24 Mechanical Specifications COMES ases AA PAPA TAPA 387 NI aua edades sea Rerum ERE ESAE ERE ER 387 32 Pin LQFP Case 87SA 2 aka hr RE 388 28 Pin PDIP Case VT IU uuu dudu RR Ac HK Maa a dd 389 28 Pin SOIC Case 751F eck cede aced ewes ese kaka 390 Section 25 Ordering Information Contents 46 5 ak ee mx RE Rok me or eee ee aaa 391 MONGHE waaa T CY EO IO TO TOO ANAL ILA TT 391 MC Order Numbers esee 392 Development Tools ssa a aa wa e codU eA rue PRAEEST 393 Glossary Revision History JR DRE RET DIT TT IIT 405 Introduction l l 405 Changes from Rev 3 0 published in February 2002 to Rev 4 0 published in June 2002 Loss unu de eerta Re hee 405 Changes from Rev 2 0 published
384. to the SPI data register unless the SPTE bit is high During an SPTE CPU interrupt the CPU clears the SPTE bit by writing to the transmit data register Reset sets the SPTE bit 1 Transmit data register empty 0 Transmit data register not empty MODFEN Mode Fault Enable Bit This read write bit when set to 1 allows the MODF flag to be set If the MODF flag is set clearing the MODFEN does not clear the MODF flag If the SPI is enabled as a master and the MODFEN bit is low then the SS pin is available as a general purpose I O If the MODFEN bit is set then this pin is not available as a general purpose I O When the SPI is enabled as a slave the SS pin is not available as a general purpose I O regardless of the value of MODFEN See SS Slave Select If the MODFEN bit is low the level of the SS pin does not affect the operation of an enabled SPI configured as a master For an enabled SPI configured as a slave having MODFEN low only prevents the MODF flag from being set It does not affect any other part of SPI operation See Mode Fault Error MC68HC908GR8 Rev 4 0 326 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI O Registers SPR1 and SPRO SPI Baud Rate Select Bits In master mode these read write bits select one of four baud rates as shown in Table 20 4 SPR1 and SPRO have
385. tor of the master also controls the shift register of the slave peripheral As the byte shifts out on the MOSI pin of the master another byte shifts in from the slave on the master s MISO pin The transmission ends when the receiver full bit SPRF becomes set At the same time that SPRF becomes set the byte from the slave transfers to the receive data register In normal operation SPRF signals the end of a transmission Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register Writing to the SPI data register clears the SPTE bit The SPI operates in slave mode when the SPMSTR bit is clear In slave mode the SPSCK pin is the input for the serial clock from the master MCU Before a data transmission occurs the SS pin of the slave SPI must be at logic 0 SS must remain low until the transmission is complete See Mode Fault Error In a slave SPI module data enters the shift register under the control of the serial clock from the master SPI module After a byte enters the shift register of a slave SPI it transfers to the receive data register and the SPRF bit is set To prevent an overflow condition slave software then must read the receive data register before another full byte enters the shift register The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed which is twice as fast as the fastest master SPSCK clock that can be generated Th
386. trical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 3 0 V DC Electrical Characteristics Table 23 5 3 0 V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Pullup resistors as input only Ports PTAS KBD37 PTAO KBDO PTC1 PTCO Rpy 20 45 65 kQ PTD6 T2CHO PTDO SS Capacitance Cout 12 Ports as input or output Cin E 8 pF Monitor mode entry voltage VIST Vpp 2 5 8 V Low voltage inhibit trip falling voltage target VTRIPF 2 35 2 60 2 70 V Low voltage inhibit trip rising voltage target VTRIPR 2 45 2 66 2 80 V E vindi hysteresis target Vive u 60 mV POR rearm voltage 9 VpoR 0 100 mV POR reset voltage VPORRST 0 700 800 mV POR rise time ramp rate RpoR 0 02 V ms Notes 1 Vpp 3 0 Vdc 10 Vgs 0 Vdc T4 T to Ty unless otherwise noted Typical values reflect average measurements at midpoint of voltage range 25 C only Run operating Ipp measured using external square wave clock source fosc 16 4 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs C 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects run Ipp Measured with all modules enabled 4 Wait Ipp measured using external square wave clock source fog 16 4 MHz All inputs 0 2 V from r
387. uest In normal Technical Data MC68HC908GR8 R ev 4 0 260 Serial Communications Interface SCI MOTO For More information On This Product Go to www freescale com ROLA Freescale Semiconductor Inc Serial Communications Interface SCI O Registers operation clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR Reset sets the SCTE bit 1 SCDR data transferred to transmit shift register 0 SCDR data not transferred to transmit shift register TC Transmission Complete Bit This read only bit is set when the SCTE bit is set and no data preamble or break character is being transmitted TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set TC is automatically cleared when data preamble or break is queued and ready to be sent There may be up to 1 5 transmitter clocks of latency between queueing data preamble and break and the transmission actually starting Reset sets the TC bit 1 No transmission in progress 0 Transmission in progress SCRF SCI Receiver Full Bit This clearable read only bit is set when the data in the receive shift register transfers to the SCI data register SCRF can generate an SCI receiver CPU interrupt request When the SCRIE bit in SCC2 is set SCRF generates a CPU interrupt request In normal operation clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR Reset clears SCRF 1 Received d
388. uests e Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity Address 001A Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 3 Keyboard Status and Control Register INTKBSCR Bits 7 4 Not used These read only bits always read as logic Os KEYF Keyboard Flag Bit This read only bit is set when a keyboard interrupt is pending Reset clears the KEYF bit 1 Keyboard interrupt pending 0 No keyboard interrupt pending MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Keyboard Interrupt KBI 181 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keyboard Interrupt KBI ACKK Keyboard Acknowledge Bit Writing a logic 1 to this write only bit clears the keyboard interrupt request ACKK always reads as logic 0 Reset clears ACKK IMASKK Keyboard Interrupt Mask Bit Writing a logic 1 to this read write bit prevents the output of the keyboard interrupt mask from generating interrupt requests Reset clears the IMASKK bit 1 Keyboard interrupt requests masked 0 Keyboard interrupt requests not masked MODEK Keyboard Triggering Sensitivity Bit This read write bit controls the triggering sensitivity of the keyboard interrupt pins Reset clears MODEK 1 Keyboard
389. uld not be executed while performing a program or erase operation on the FLASH otherwise the operation will discontinue and the FLASH will be on Standby Mode Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly but there will not be any memory activity since the CPU is inactive The STOP instruction should not be executed while performing a program or erase operation on the FLASH otherwise the operation will discontinue and the FLASH will be on Standby Mode Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum MC68HC908GR8 Rev 4 0 166 Flash Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 12 External Interrupt IRQ 12 1 Contents DM WNC 20 bb KPA od ene be de be ORO HER CR 167 123 PELA cio cece KAKA KABAN BABENG NAKA ES 167 12 4 Functional Description mma AK AREA UR RR 168 125 UU GB RANA KAWA a Rn KA ee Ree ACA KA GN ER A 170 12 6 IRQ Module During Break Interrupts 171 12 7 IRQ Status and Control Register 172 12 2 Introduction The IRQ external interrupt module provides a maskable interrupt input 12 3 Features Features of the IRQ module include A dedic
390. ures the highest stability and lowest acquisition lock times 7 9 1 Acquisition Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time within specified tolerances of the system to a step input In a PLL the step input occurs when the PLL is turned on or when it suffers a noise hit The tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change Therefore the reaction time is constant in this definition regardless of the size of the step input For example consider a system with a 5 percent acquisition time tolerance If a command instructs the system to change from 0 Hz to 1 MHz the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz Fifty kHz 5 of the 1 MHz step input If the system is operating at 1 MHz and suffers a 100 kHz noise hit the acquisition time is the time taken to return from 900 kHz to 1 MHz 5 kHz Five kHz 5 of the 100 kHz step input Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances Therefore the acquisition or lock time varies according to the original error in the output Minor errors may not even be registered Typical PLL applications prefer to use this definition because the system requires the output
391. vides the timing reference for the input capture and output compare functions The TIM counter modulo registers TMODH TMODL control the modulo value of the TIM counter Software can read the TIM counter value at any time without affecting the counting sequence The TIM channels per timer are programmable independently as input capture or output compare channels If a channel is configured as input capture then an internal pullup device may be enabled for that channel See Port D Input Pullup Enable Register MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 337 For More Information On This Product Go to www freescale com INTERNAL TCLK ace PRESCALER TSTOP INTERNAL BUS lt Freescale Semiconductor Inc Timer Interface Module TIM TRST 16 BIT COUNTER 16 BIT COMPARATOR TMODH TMODL CHANNEL 0 16 BIT COMPARATOR TCHOH TCHOL 16 BIT LATCH CHANNEL 1 16 BIT COMPARATOR TCH1H TCH1L 16 BIT LATCH NOTE PRESCALER SELECT PS2 PS1 PSO Figure 22 1 TIM Block Diagram gt TOF INTER RUPT TOIE LOGIC TOVO NG J CHOMAX T 1 2 CHO t 9 CHOF MSOA CHOIE MS0B 69 TOV1 ELS1B ELS1A CH1MAX T 1
392. w Whenever SPE is low the following occurs The SPTE flag is set e Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared making it ready for a new complete transmission All the SPI port logic is defaulted back to being general purpose O These items are reset only by a system reset All control bits in the SPCR register All control bits in the SPSCR register MODFEN ERRIE SPR1 and SPRO The status flags SPRF OVRF and MODF By not resetting the control bits when SPE is low the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission Technical Data MC68HC908GR8 Rev 4 0 316 Serial Peripheral Interface SPI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Low Power Modes By not resetting the SPRF OVRF and MODF flags the user can still service these interrupts after the SPI has been disabled The user can disable the SPI by writing O to the SPE bit The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set 20 11 Low Power Modes 20 11 1 Wait Mode 20 11 2 Stop Mode The WAIT and STOP instructions put the MCU in low power consumption standby modes The SPI module remains active after the
393. width trytte ns Note 8 Input capture period triTL 7 Icyc Notes Vas 0 Vdc timing shown with respect to 20 Vpp and 70 Vss unless otherwise noted 2 See Clock Generation Module Characteristics for more information 3 No more than 1096 duty cycle deviation from 5096 4 Some modules may require a minimum frequency greater than dc for proper operation See appropriate table for this information 5 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset 6 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized 7 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized 8 The minimum period tj i or trj 7 should not be less than the number of cycles it takes to execute the interrupt service routine plus toyc MC68HC908GR8 Rev 4 0 368 Electrical Specifications For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Electrical Specifications 3 0 V Control Timing 23 8 3 0 V Control Timing Table 23 7 3 0 V Control Timing Characteristic Symbol Min Max Unit Frequency of operation Crystal option fosc 32 100 kHz External clock option de 16 4 MHz Internal operating frequency fop 4 1 MHz Internal clock period 1 fop toye 244 ns
394. www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 16 Input Output Ports I O 16 1 Contents 162 GNG que e KAKA KAAGAD ao be de be XO d eke e 205 DUM EI AA AA AAP aes 209 leda POMBE 54h eo 213 165 PONG oe hee DAN BANA GANA NN GA KALA dea ANG 216 US PA aa ae EAT HE NGA LAGA GNG AN Pe dba dna PN 220 DO POTE AGA ANA AA MAKA een GA ee 225 16 2 Introduction Twenty one 21 bidirectional input output I O pins form five parallel ports All I O pins are programmable as inputs or outputs All individual bits within port A port C and port D are software configurable with pullup devices if configured as input port bits The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode NOTE Connect any unused I O pins to an appropriate logic level either Vpp or Vss Although the I O ports do not require termination for proper operation termination reduces excess current consumption and the possibility of electrostatic damage MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Input Output Ports I O 205 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output Ports l O Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 PTA3 PTA2 PTA1 PTAO Port A
395. y set the overrun OR noise flag NF parity error PE or reception in progress flag RPF bits 18 5 2 4 Idle Characters NOTE An idle character contains all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in SCC1 The preamble is a synchronizing idle character that begins every transmission If the TE bit is cleared during a transmission the PE2 TxD pin becomes idle after completion of the transmission in progress Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted When queueing an idle character return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 239 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI 18 5 2 5 Inversion of Transmitted Output The transmit inversion bit TXINV in SCI control register 1 SCC1 reverses the polarity of transmitted data All transmitted values including idle break start and stop bits are inverted when TXINV i
396. y two as the CGMOUT source even if the PLL is not locked LOCK 0 Therefore software should make sure the PLL is locked before setting the BCS bit 7 8 Special Modes The WAIT instruction puts the MCU in low power consumption standby modes 7 8 1 Wait Mode The WAIT instruction does not affect the CGMC Before entering wait mode software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register PCTL to save power Less power sensitive applications can disengage the PLL without turning it off so that the PLL clock is immediately available at WAIT exit This would be the case also when the PLL is to wake the MCU from wait MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 8 2 Stop Mode mode such as when the PLL is first enabled and waiting for LOCK or LOCK is lost If the OSCSTOPENB bit in the CONFIG register is cleared default then the STOP instruction disables the CGMC oscillator and phase locked loop and holds low all CGMC outputs CGMXCLK CGMOUT and CGMINT If the STOP instruction is executed with the VCO clock CGMVCLK divided by two driving CGMOUT the PLL automatically clears the BCS bit in the PLL control register PCTL thereby selecting the crystal clock CGMXCLK divided by two as the source of CGMOU
397. z1868H C908G REM RA Freescale Semiconductor Inc ef p oye MOTOROLA digitaldna intelligence everywhere MC68HC908GR8 MC68HC908GR4 Technical Data M68HC08 Microcontrollers Rev 4 6 2002 WWW MOTOROLA COM SEMICONDUC TORS For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC908GR8 MC68HC908GR4 Technical Data Rev 4 0 Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or

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