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freescale MOTOROLA MC68HC908GR8 MC68HC908GR4 handbook

1. SCI DATA SCI DATA REGISTER REGISTER RECEIVE i z E z E z E S z E TRANSMIT gt cs cs TE cs Ces EEO SHIFT REGISTER Gug Zug oug gug SHIFT REGISTER FETA zo zo czo zo fe TXINV SCTIE R8 TCIE T8 SCRIE HE DMARE TE SCTE Le DMATE RE TC RWU SCRF OR ORIE SBK IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS ENSCI gt WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL SCIBDSRC FROM aa BKF M CONFIG RPF WAKE ILTY CGMKOLK fA ba PRE BA PEN IT12 B i SCALER DIVI Pry SL 0 gt X A SL 1 gt X B d DATA SELECTION CONTROL Figure 18 1 SCI Module Block Diagram Technical Data MC68HC908GR8 Rev 4 0 234 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read iis SCI Control Register 1 Wie LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCC1 f Reset 0 0 0 0 0 0 0 0 Read SCTIE TCIE
2. ACK RESET D gt 2 TO CPU FOR m VECTOR BIL BIH i FETCH INSTRUCTIONS a VDD lt z INTERNAL V 2 PULLUP Kag IRQF m DEVICE Rat n INTERRUPT REQUEST NC HIGH TO MODE VOLTAGE SELECT DETECT LOGIC Figure 12 1 IRQ Module Block Diagram Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 IRQF 0 mase iidne IRQ Status and Control Sip Register INTSCR We ACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 2 IRQ I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA External Interrupt IRQ 169 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interrupt IRQ 12 5 IRQ1 Pin Technical Data A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch A vector fetch software clear or reset clears the IRQ latch If the MODE bit is set the IRQ1 pin is both falling edge sensitive and low level sensitive With MODE set both of the following actions must occur to clear IRQ e Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the latch Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register INTSCR The ACK bit is useful in applications that poll the IRQ1
3. Effect on o v Source CCR 0 58 Flo Operation Description 9o 60 S 0 Form o E 98 o o 2 VIHII NZC gsl l 6 CMP opr IMM Al li 2 CMP opr DIR B1 dd 3 CMP opr EXT C1 hhll 4 CMP opr X IX2 D1 jeeff 4 CMP opr X Compare A with M A M t It11 1 IX1 E1 f 3 CMP X IX F1 2 CMP opr SP SP1 9EE1 ff 4 CMP opr SP SP2 9ED1 eeff 5 COM opr M c M FF M DIR 33 dd 4 COMA A lt A FF M INH 43 1 COMX X X FF M la INH 53 1 COM oprX Complement One s Complement M M SFF M 0 O OR xi 63 f 4 COM X M lt M SFF M IX 73 3 COM opr SP M lt M FF M SP1 9E63 ff 5 CPHX opr LY wi 3 IMM 65 jiiii 1 3 CPHX opr Compare H X with M H X M M 1 ti j t ot d DIR 75 Idd 4 CPX opr IMM A3 fii 2 CPX opr DIR B3 dd 3 CPX opr EXT C3 hhll 4 CPX X IX2 D3 jee ff 4 CPX oprX Compare X with M X M t It11 1 IX1 E3 f 3 CPX opr X IX F3 2 CPX opr SP SP1 9EE3 ff 4 CPX opr SP SP2 9ED3 Jee ff 5 DAA Decimal Adjust A Ajo U 1 INH 72 2 A A 1 or M M 1 or X X 1 5 DBNZ opr rel PC lt PC 3 rel result 0 DIR 3B ddrr 3 DBNZA rel PC lt PC 2 rel result 0 INH 4B rr 3 DBNZX rel Decrement and Branch if Not Zero PC c PC 2 rel result 0 INH 5B ir 5 DBNZ opr X rel PC lt PC 3 rel result 0 IX1 6B frr 4 DBNZ X rel PC lt
4. Priority Interrupt Source a Fan SWI instruction IRQ pin H PLL I2 TIM1 channel 0 I3 TIM1 channel 1 l4 TIM1 overflow I5 TIM2 channel 0 l6 Reserved I7 TIM2 overflow I8 SPI receiver full I9 SPI transmitter empty 110 SCI receive error 114 SCI receive 112 SCI transmit 113 Keyboard 114 ADC conversion complete 115 Lowest Timebase module 116 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA System Integration Module SIM 287 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM 19 6 1 4 Interrupt Status Register 1 Address SFE04 Bit 7 6 5 4 3 2 1 Bit 0 Read l6 I5 l4 I3 l2 i 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 12 Interrupt Status Register 1 INT1 16 11 Interrupt Flags 1 6 These flags indicate the presence of interrupt requests from the sources shown in Table 19 3 1 Interrupt request present 0 No interrupt request present Bit O and Bit 1 Always read 0 19 6 1 5 Interrupt Status Register 2 Address SFE05 Bit 7 6 5 4 3 2 1 Bit 0 Read 114 113 112 111 110 19 18 I7 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 13 Interrupt Status Register 2 INT2 114 17 Interrupt Flags 14 7 These flags indicate the presence of interr
5. Effecton 5 Source e CCR a S flo Operation Description Co o S 9 Form 99 8 glo o 2 VH IINZC gsl l 6 TST opr DIR 3D dd 3 TSTA INH 4D 1 INH 5D 1 TST opr x Test for Negative or Zero A 00 or x 00 or M 00 0 i Bp lge le TST X IX 7D 2 TST opr SP SP1 9E6D ff 4 TSX Transfer SP to H X H X SP 1 INH 95 2 TXA Transfer X to A A X i INH 9F 1 TXS Transfer H X to SP SP e H X 1 7 INH 94 2 A Accumulatorn Any bit C Carry borrow bitopr Operand one or two bytes CCRCondition code registerPC Program counter ddDirect address of operandPCH Program counter high byte dd rrDirect address of operand and relative offset of branch instructionPCL Program counter low byte DDbDirect to direct addressing modeREL Relative addressing mode DIRDirect addressing moderel Relative program counter offset byte DIX Direct to indexed with post increment addressing moderr Relative program counter offset byte ee ffHigh and low bytes of offset in indexed 16 bit offset addressingSP 1 Stack pointer 8 bit offset addressing mode EXTExtended addressing modeSP2 Stack pointer 16 bit offset addressing mode ff Offset byte in indexed 8 bit offset addressingSP Stack pointer H Half carry bitU Undefined H Index register high byteV Overflow bit hh IIHigh and low bytes of operand address in extended addressingX Index register low byte Interrupt maskZ Z
6. a k Seating Plane Dim Min Max Notes Dim Min Max A 36 45 37 21 H 1 65 2 16 1 All dimensions in mm B 13 72 14 28 2 Positional tolerance of leads D shall be within 0 25 mm at J 0 20 T C 3 94 5 08 maximum material condition in relation to seating plane and to K 2 92 343 D 0 36 0 56 each other l L 15 24 BSC F 1 02 1 52 3 Dimension tis to centre of leads when formed parallel M 0 15 4 Dimension B does not include mould protrusion G 2 54 BSC N 0 51 1 02 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Mechanical Specifications 389 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 24 5 28 Pin SOIC Case 751F 14PL E B P IGBlo25 M B M LE MAA 4 de 77 Seating Plane Dim Min Max Notes Dim Min Max A 17 80 18 05 J 0 229 0 317 B 7 40 7 60 1 Dimensions A and B are datums and T is a datum surface K 0 127 0 292 C 2 35 2 65 2 Dimensioning and tolerancing pe
7. Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 3 LVI Status Register LVISR LVIOUT LVI Output Bit This read only flag becomes set when the Vpp voltage falls below the VTnipr trip voltage See Table 14 1 Reset clears the LVIOUT bit Table 14 1 LVIOUT Bit Indication Vpp LVIOUT Vpp gt VTRIPR 0 Vpp lt VTRIPF 1 VIRIPF Vpp lt VTRIPR Previous value MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Low Voltage Inhibit LVI 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Voltage Inhibit LVI 14 6 LVI Interrupts The LVI module does not generate interrupt requests 14 7 Low Power Modes The STOP and WAIT instructions put the MCU in low power consumption standby modes 14 7 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the L VI module can generate a reset and bring the MCU out of wait mode 14 7 2 Stop Mode If enabled in stop mode LVISTOP set the LVI module remains active in stop mode If enabled to generate resets the L VI module can generate a reset and bring the MCU out of stop mode Technical Data MC68HC908GR8 Rev 4 0 188 Low Voltage Inhibit LVI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
8. Control Bits Character Format M PEN and Start Data Parity Stop Character PTY Bits Bits Bits Length 0 OX 1 8 None 1 10 bits 1 OX 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 18 9 2 SCI Control Register 2 SCI control register 2 Enables the following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests e Enables the transmitter e Enables the receiver Enables SCI wakeup e Transmits SCI break characters MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Communications Interface SCI 255 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI Address 0014 Bit 7 6 5 4 3 2 1 Bit 0 Read SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 18 10 SCI Control Register 2 SCC2 SCTIE SCI Transmit Interrupt Enable Bit This read write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests Reset clears the SCTIE bit 1 SCTE enabled to generate CPU interrupt 0 2 SCTE not en
9. DN 9r 1 UOOUOOCUO oo o MILLIMETERS INCHES MIN MAX MIN MAX A 7 000 BSC 0 276 BSC At 3 500 BSC 0 138 BSC B 7 000 BSC 0 276 BSC 3 500 BSC 0 138 BSC 1 400 1 600 0 055 0 063 0 300 0 450 0 012 0 018 1 350 1 450 0 053 0 057 0 300 0 400 0 012 0 016 0 800 BSC 0 031 BSC 0 050 0 150 0 002 0 006 0 090 0 200 0 004 0 008 0 500 0 700 0 020 0 028 12 REF 12 REF 0 090 0 160 0 004 0 006 0 400 BSC 0 016 BSC r 5 1 5 0 150 0 250 0 006 0 010 9 000 BSC 0 354 BSC 4 500 BSC 0 177 BSC V 9 000 BSC 0 354 BSC vi 4 500 BSC 0 177 BSC W 0 200 REF 0 008 REF DETAIL AD X 1 000 REF 0 039 REF Base Metal DIM lo 0 20 0 008 M AC T U Z Gs Section AE AE A o D O d z Z Ac T 9 n m 9 O z JL Gauge Plane 0 25 0 010 Technical Data MC68HC908GR8 Rev 4 0 388 Mechanical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mechanical Specifications 28 Pin PDIP Case 710 24 4 28 Pin PDIP Case 710 F J D Kap a
10. LOBYTE EQU 6 If not SBSW do RTI BRCLR SBSW SBSR RETURN See if wait mode or stop mode was exited by break TST LOBYTE SP If RETURNLO is not zero BNE DOLO then just decrement low byte Technical Data MC68HC908GR8 Rev 4 0 294 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Integration Module SIM DEC HIBYTE SP Else deal with high byte too DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI 19 8 2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared Clear the SIM reset status register by reading it A power on reset sets the POR bit and clears all other bits in the register Address SFE01 Bit 7 6 5 4 3 2 1 Bit 0 Read POR PIN COP ILOP ILAD MODRST LVI 0 Write Reset 1 0 0 0 0 0 0 0 Unimplemented Figure 19 21 SIM Reset Status Register SRSR POR Power On Reset Bit 1 Last reset caused by POR circuit 0 Read of SRSR PIN External Reset Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode R
11. 354 22 11 TIM Channel 0 Status and Control Register TSCO 355 22 12 TIM Channel 1 Status and Control Register TSC1 355 22 13 CHXMAX Laltahoy cueuacecunsukAuRu RR Eur n Rn Eun 359 22 14 TIM Channel O Register High TCHOH 360 22 15 TIM Channel O Register Low TCHOL 360 22 16 TIM Channel 1 Register High TCH1H 360 22 17 TIM Channel 1 Register Low TCH1iL 360 23 1 Typical High Side Driver Characteristics Port PTA3 PTAO Vpp 4 5 Vdc LLsluuss 370 23 2 Typical High Side Driver Characteristics Port PTA3 PTAD Vpn 2 7 VOC oc na naa KAG AKA n naan 370 23 3 Typical High Side Driver Characteristics Port PTCH PTOO Vpp 4 5 YAO ci naaa kA 371 23 4 Typical High Side Driver Characteristics Port PTCT FTOD Vpp 2 7 VO e auesesctosce n Re 371 23 5 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 5 5 Vdc 372 23 6 Typical High Side Driver Characteristics Ports PTB5 PTBO PTD6 PTDO and PTE1 PTEO Vpp 2 7 Vdc 372 23 7 Typical Low Side Driver Characteristics Poit PTAS PTAO Vpp 5 5 Vdo oc cecece ede esse RR 373 23 8 Typical Low Side Driver Characteristics Pot PTAS PTAO Vpn 27 VOC das ees naaa ver ERAS 373 23 9 Typical Low Side Driver Characteristics Port PTC1 PTCO Vpp 4 5 VdB ci saka esr kr teda 374 23 10 Typical Low Side Driver Characte
12. IMM A7 i 2 AIX opr Add Immediate Value Signed to H X H X H X 16 M IMM AF ii 2 AND opr IMM A4 ii 2 AND opr DIR B4 dd 3 AND opr EXT C4 hhi 4 AND opr X IX2 D4 leeff 4 AND oprX Logical AND A A 8 M tt pd E4 f 3 AND X IX F4 2 AND opr SP SP1 9EEA ff 4 AND opr SP SP2 9ED4 lee ff 5 ASL opr DIR 38 ldd 4 ASLA INH 48 1 ASLX Arithmetic Shift Left n INH 58 1 ASL opr X Same as LSL Ch tai aa KA KA KA Ina 68 f 4 ASL X b7 bO IX 78 3 ASL opr SP SP1 9E68 ff 5 ASR opr DIR 37 dd 4 ASRA INH 47 1 ASRX prey INH 57 1 ASR opr X Arithmetic Shift Right C i t i X1 67 lit 4 ASR opr X b7 bo IX 77 3 ASR opr SP SP1 9E67 ff 5 BCC rel Branch if Carry Bit Clear PC PC 2 rel C 20 REL 24 jrr 3 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Central Processing Unit CPU For More Information On This Product Go to www freescale com 147 Central Processing Unit CPU Freescale Semiconductor Inc Table 10 1 Instruction Set Summary Continued Effect on o vo Source CCR 0 58 Flo Operation Description 9o o S a Form oO a o o H I N Z o9 2 2 S IF O O O DIR b0 11 dd 4 DIR b1 13 dd 4 DIR b2 15 dd 4 se DIR b3 17 dd 4 BCLR n opr Clear Bit n in M Mn 0
13. z FFFF COPCTL Write Writing clears COP counter any value Reset Unaffected by reset 1 Non volatile FLASH register Unimplemented R Reserved U Unaffected Figure 2 2 Control Status and Data Registers Sheet 8 of 8 Technical Data MC68HC908GR8 Rev 4 0 46 Memory Map MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map Input Output 1 0 Section Table 2 1 Vector Addresses Vector Priority Vector Address Vector Lowest IF16 SFFDC Timebase Vector High SFFDD Timebase Vector Low IF15 SFFDE ADC Conversion Complete Vector High SFFDF ADC Conversion Complete Vector Low IF14 SFFEO Keyboard Vector High SFFE1 Keyboard Vector Low IF13 FFE2 SCI Transmit Vector High SFFE3 SCI Transmit Vector Low E12 SFFE4 SCI Receive Vector High SFFE5 SCI Receive Vector Low F1 FFE6 SCI Error Vector High FFE7 SCI Error Vector Low IF10 SFFE8 SPI Transmit Vector High SFFE9 SPI Transmit Vector Low IF9 FFEA SPI Receive Vector High FFEB SPI Receive Vector Low IF8 FFEC TIM2 Overflow Vector High FFED TIM2 Overflow Vector Low IF7 FFEE Reserved FFEF Reserved IFG FFFO TIM2 Channel 0 Vector High SFFF1 TIM2 Channel 0 Vector Low IF5 FFF2 TIM1 Overflow Vec
14. 296 System Integration Module SIM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC908GR8 Section 20 Serial Peripheral Interface SPI 20 1 Contents 20 2 na TG Li qoi Fe Hh eee NUR ene e oe RO I oO 297 20 9 EI 0o e knee kets ce he he S 298 20 4 Pin Name Conventions and I O Register Addresses 298 20 5 Functional Description oua ka xAR RE RE EE drach 299 20 6 Transmission Formats a KA ada dsc sed Er ce we 303 20 7 Queuing Transmission Data a 309 20 8 Eror LOUER s cud dod EROR e dO OR Capi p eos 310 20 9 1000300 010004 12 0222 2 07171 177 1501001 2 eke ees 314 20 10 Resetting the SPI nn 2 2264 ce NAKA RR RR mms 316 20 11 Low Power Modes 4 42014 cieeeeeteecdeerescieieoes 317 20 12 SPI During Break Interrupts 002200 eee 318 20 13 VO GHNA iacere T cT 318 20 14 I O Registers nunnan anana 322 20 2 Introduction This section describes the serial peripheral interface SPI module which allows full duplex synchronous serial communications with peripheral devices MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 297 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI 20 3 Features Features of the SPI module include e Full duplex operation e Master and slave
15. Ipp mA wo eo 4 fpus MHz Figure 23 14 Typical Wait Mode Ipp with all Modules Disabled 7 40 C to 125 C Technical Data MC68HC908GR8 Rev 4 0 376 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications Typical Supply Currents lt a o 1 15 A jnre de 1 10 1 05 5 5 V E 3 6 V 1 0 1 2 3 4 5 6 7 8 9 fbus MHz Figure 23 15 Typical Stop Mode lpp with all Modules Disabled 40 C to 125 C MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Electrical Specifications 377 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 23 12 ADC Characteristics Characteristic Symbol Min Max Unit Comments 27 55 Vppap Should be tied i to the same potential V V Supply voltage VDDAD DD Vpp V 8s Vp via separate min max traces Input voltages VADIN 0 VDDAD V VADIN lt VREFH Resolution Bap 8 8 Bits Absolute accuracy VREFL 0 V VppAD VREFH Aap t1 LSB Includes quantization 5V t 1095 taic 1 f tested ADC internal clock ADIC 0 5 048 Zz only at 1 MHz VREFH VDDAD Conversion range Rap VeeeL VnEFH V VRE
16. Operand Single data byte Data None Returned Opcode 19 Command Sequence ECHO MC68HC908GR8 Rev 4 0 200 Monitor ROM MON MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON Functional Description A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64K byte memory map Table 15 8 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Data Returns incremented stack pointer value SP 1 in high byte low Returned byte order Opcode 0C Command Sequence FROM HOST SP SP J READSP READSP HIGH LOW ECHO RETURN Table 15 9 RUN Run User Program Command Description Executes PULH and RTI instructions Operand None Data NG ag Returned Opcode 28 Command Sequence FROM HOST RUN RUN ECHO MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Monitor ROM MON 201 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON 15 5 Security Technical Data NOTE The MCU executes the SWI and PSHH instructions when it enters monitor mode The RUN command tells the MCU to execute the PULH and RTI instructions Before sending the RUN command the host can modify the stacked CPU registers to pre
17. 0 197 READ Read Memory Command 199 WRITE Write Memory Command 199 IREAD Indexed Read Command aaa 200 IWRITE Indexed Write Command 200 READSP Read Stack Pointer Command 201 RUN Run User Program Command LLus 201 Port Control Register Bits Summary 208 Port PD PODES cs PAK kx HR weep KG uc e 211 Fart B Pin PINONG eed Ra Ra NAGA BAWAL DAA Dha 215 Port C PIN FUNCIONS iuuenem eR dmm deos 218 Port D Pin Funcions eae se KA der eK REPRE qa UR ewe 223 Fort E Pin FOOCROUS Lou 0 ces NBA K KAN Ed NGA ads Rue 227 Pin Name Conventions cece eee eee 233 Start DIVIDEND 1233 44 4 dob c eee OR EEEREN aea 244 Technical Data MOTOROLA List of Tables 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables 18 3 18 4 18 5 18 6 18 7 18 8 19 1 19 2 19 3 19 4 20 1 20 2 20 3 20 4 21 7 22 1 ded 22 3 23 1 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23 9 25 1 25 2 25 3 Technical Data Dala BE HG M LS ia kA UE EROR d oor a AG 244 Stop Bit ey MEM 245 Character Format Selection 2 2 0055 255 SCI Baud Rate Prescaling i ng sad ka RR Rer RR 266 SCI Baud Hate Selection a kr hr NG 266 SCI Baud Rate Selection Examples 268 Signal Name Conventions sssaaa RR n onde 273 PIN Bit Set PMN
18. 50 mA port A port B Maximum total loj for all port pins lour sawa a 100 mA Output low voltage ILoad 1 6 MA all I O pine VoL u E T V ILoad 10 MA all I O pins VoL a 15 V ILoad 15 MA pins PTCO PTC1 only VoL 1 0 V Maximum combined lo for port C port E lout xm 5 mA port PTDO PTD3 Maximum combined lo for port PTD4 PTD6 loi EC CE 50 mA port A port B Maximum total lo for all port pins lott a m 100 mA Input high voltage All ports IRQs RESET Vin 0 7 x Vpp Vpp V OSC1 0 8 x Vpp Input low voltage V V E All ports IRQs RESET OSC1 IL ss Na porq v Vpp Supply current Run IDD 15 20 mA Wait 4 8 mA Stop 85 C 3 5 uA Stop gt 85 C 5 10 uA Stop with TBM enabled PP 20 35 uA Stop with LVI and TBM enabled m 300 500 uA I O ports Hi Z leakage current liL 10 uA Input current lin 1 uA Technical Data MC68HC908GR8 Rev 4 0 364 Electrical Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Specifications 5 0 V DC Electrical Characteristics Table 23 4 5 0V DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Pullup resistors as input only Ports PTAS KBDS PTAO KBDO PTC1 PTCO Rey 20 45 65 kQ PTD6 T2CHO PTDO SS Capacitance Cout 12 Ports as input or output Cin m 8 Br Monitor mode entry voltage Vist Vpp 2 5 8 V
19. A module in the M68HC08 Family that supports asynchronous communication serial peripheral interface module SPI A module in the M68HC08 Family that supports synchronous communication set To change a bit from logic O to logic 1 opposite of clear shift register A chain of circuits that can retain the logic levels logic 1 or logic O written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain signed A binary number notation that accommodates both positive and negative numbers The most significant bit is used to indicate whether the number is positive or negative normally logic O for positive and logic 1 for negative The other seven bits indicate the magnitude of the number software Instructions and data that control the operation of a microcontroller software interrupt SWI An instruction that causes an interrupt and its associated vector fetch SPI See serial peripheral interface module SPI stack A portion of RAM reserved for storage of CPU register contents and subroutine return addresses stack pointer SP A 16 bit register in the CPU08 containing the address of the next available storage location on the stack start bit A bit that signals the beginning of an asynchronous serial transmission status bit A register bit that indicates the condition of a device stop bit A bit that signals the end of an asynchronous
20. BREAK ADDRESS REGISTER LOW IAB15 IABO CONTROL BREAK IAB7 IABO Figure 6 1 Break Module Block Diagram Technical Data MC68HC908GR8 Rev 4 0 92 Break Module BRK MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Break Module BRK Functional Description Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 1 0 0 BW 0 SIM Break Status Register FE00 SBSR Write R R R R R R NOTE R Reset 0 0 0 1 0 0 0 0 bis BCFE R R R R R R R SIM Break Flag Control SEEDS Register SBFCR We Reset 0 ea Bit 15 14 13 12 11 10 9 Bit 8 Break Address Register Pl I SFE09 High BRKH Write Reset 0 0 0 0 0 0 0 0 bs Bit 7 6 5 4 3 2 1 Bit 0 Break Address Register _ l l FEOA Low BRKL Write Reset 0 0 0 0 0 0 0 0 Read BERE mana 0 0 0 0 0 0 Break Status and Control SFEOB Register BRKSCR MI Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears BW Unimplemented R Reserved Figure 6 2 I O Register Summary 6 4 1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state 6 4 2 CPU During Break Interrupts The CPU starts a break interrupt by Loading the instruction register with the SWI instruction e Loading the program counter with FFFC and
21. DIR b4 19 ldd 4 DIR bb 1B dd 4 DIR b6 1D dd 4 DIR b7 1F dd 4 BCS rel Branch if Carry Bit Set Same as BLO PC PC 2 rel C 2 1 SS REL 25 jrr 3 BEQ rel Branch if Equal PC e PC 2 rel Z 1 I REL 27 rr BGE opr Med Opera or Equal TO pc PC 2 rel N V 0 REL 90 Ir 3 BGT opr Cnn E Than Signed pc PC 2 rel Z N V 0 REL 92 m l3 BHCC rel Branch if Half Carry Bit Clear PC PC 2 rel H 20 i REL 28 jrr 3 BHCS rel Branch if Half Carry Bit Set PC PC 2 rel H 1 Eee REL 29 jrr 3 BHI rel Branch if Higher PC e PC 2 rel C 2 0 REL 22 m 3 BHS rel udi as BEC or Same PC PC 2 rel C 0 lt 2 TREES 24 r 13 BIH rel Branch if IRQ Pin High PC PC 2 rel IRQ 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC PC 2 rel IRQ 0 REL 2E frr 3 BIT opr IMM A5 lii 2 BIT opr DIR B5 dd 3 BIT opr EXT C5 hhll 4 BIT opr X Jha IX2 DS jeeff 4 BIT oprX Bit Test A amp M 7x E5 f 3 BIT X IX F5 2 BIT opr SP SP1 9EE5 ff 4 BIT opr SP SP2 9ED5 ee ff 5 BLE opr eod Ope ander or Equal To PG e PC 2 rel Z NO V 1 REL 93 r 3 BLO rel Branch if Lower Same as BCS PC PC 2 rel C 2 1 Shae Eza REL 25 rr 3 BLS rel Branch if Lower or Same PC lt PC 2 rel C 2 1 Ee REL 23 jrr 3 BLT opr Branch if Less Than Signed Operands PC c PC 2 rel N O V 1 RE
22. For More Information On This Product Timer Interface Module TIM Go to www freescale com MOTOROLA Freescale Semiconductor Inc Timer Interface Module TIM O Registers CHxMAX Channel x Maximum Duty Cycle Bit When the TOVXx bit is at logic 1 setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As CHxMAX Latency shows the CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW lug PERIOD Y Y Y PTEx TCHx A 1 i A OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE CHxMAX Figure 22 13 CHxMAX Latency 22 10 6 TIM Channel Registers These read write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function The state of the TIM channel registers after reset is unknown In input capture mode MSxB MSxA 0 0 reading the high byte of the TIM channel x registers TCHxH inhibits input captures until the low byte TCHxL is read In output compare mode MSxB MSxA z 0 0 writing to the high byte of the TIM channel x registers TCHxH inhibits output compares until the low byte TCHxL is written MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM
23. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Resets 4 3 4 SIM Reset Status Register This read only register contains flags to show reset sources All flag bits are automatically cleared following a read of the register Reset service can read the SIM reset status register to clear the register after power on reset and to determine the source of any subsequent reset The register is initialized on powerup as shown with the POR bit set and all other bits cleared During a POR or any other internal reset the RST pin is pulled low After the pin is released it will be sampled 32 XCLK cycles later If the pin is not above a V at that time then the PIN bit in the SRSR may be set in addition to whatever other bits are set NOTE Only a read of the SIM reset status register clears all reset flags After multiple resets from different sources without reading the register multiple flags remain set Address SFE01 Bit 7 6 5 4 3 2 1 Bit 0 Read POR PIN COP ILOP ILAD 0 LVI 0 Write POR 1 0 0 0 0 0 0 0 Unimplemented Figure 4 3 SIM Reset Status Register SRSR POR Power On Reset Flag 1 Power on reset since last read of SRSR 0 Read of SRSR since last power on reset PIN External Reset Flag 1 External reset via RST pin since last read of SRSR 0 POR or read of SRSR since last external reset COP
24. NOTE References to TCLK and external TIM clock input are only valid if the MCU has an external TCLK pin If the MCU has no external TCLK pin the TIM module must use the internal bus clock prescaler selections Figure 22 1 shows the structure of the TIM The central component of the TIM is the 16 bit TIM counter that can operate as a free running counter or a modulo up counter The TIM counter provides the timing reference for the input capture and output compare functions The TIM counter modulo registers TMODH TMODL control the modulo value of the TIM counter Software can read the TIM counter value at any time without affecting the counting sequence The TIM channels per timer are programmable independently as input capture or output compare channels If a channel is configured as input capture then an internal pullup device may be enabled for that channel See Port D Input Pullup Enable Register MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Timer Interface Module TIM 337 For More Information On This Product Go to www freescale com INTERNAL TCLK ace PRESCALER TSTOP INTERNAL BUS lt Freescale Semiconductor Inc Timer Interface Module TIM TRST 16 BIT COUNTER 16 BIT COMPARATOR TMODH TMODL CHANNEL 0 16 BIT COMPARATOR TCHOH TCHOL 16 BIT LATCH CHANNEL 1 16 BIT COMPARATOR TCH1H TCH1L 16 BIT LATCH NOTE PRESCALER SEL
25. Nmax use P 0 If N gt Nmax choose P using this table Current N Value P Oe NSN ix 0 Nmax SN SNimay X2 1 NmaxX2 NsNqaax X4 2 Naay 4 NSN S d 3 Then recalculate N Rxf N round d P facuk X 6 Calculate and verify the adequacy of the VCO and bus frequencies fyc and fpys P fvcuk 2 X N B xfgci f5us fvcik 4 7 Select the VCO s power of two range multiplier E according to Technical Data MOTOROLA Clock Generator Module CGMC 107 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC this table Frequency Range E 0 lt fycik lt 9 830 400 9 830 400 lt fyc x lt 19 660 800 1 19 660 800 lt fyc x lt 39 321 600 2 NOTE Do not program E to a value of 3 8 Select a VCO linear range multiplier L where foy 38 4 kHz f KG round EU 2 X from 9 Calculate and verify the adequacy of the VCO programmed center of range frequency fyps The center of range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL E fyrs Ex 2 Iinom For proper operation E E INOM X VRS VGLKI MO 10 Verify the choice of P R N E and L by comparing fyc to fyns and fyci pgs For proper operation fyc must be within the application s tolerance of fyc pgs and fyps must be as close as possible to fyc NOTE
26. Routing should be done with great care to minimize signal cross talk and noise See CGM Component Specifications for capacitor and resistor values SIMOSCEN OSCSTOPENB FROM CONFIG 1 A Do CGMXCLK j M OSC1 OSC2 CGMXFC Vssa VppA AAN t T Voo RB 5 T CBYP RS T 0 01 uF GR 0 1 uF 0 033 UE I iI e e xi C1 Te C2 ES Note Filter network in box can be replaced with a 0 47 uF capacitor but will degrade stability Figure 7 2 CGMC External Connections MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 5 I O Signals The following paragraphs describe the CGMC I O signals 7 5 1 Crystal Amplifier Input Pin OSC1 The OSC1 pin is an input to the crystal oscillator amplifier 7 5 2 Crystal Amplifier Output Pin OSC2 The OSC2 pin is the output of the crystal oscillator inverting amplifier 7 5 3 External Filter Capacitor Pin CGMXFC NOTE The CGMXFC pin is required by the loop filter to filter out phase corrections An external filter network is connected to this pin See Figure 7 2 To prevent noise problems the filter network should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of ot
27. Technical Data MC68HC908GR8 15 1 Contents 15 2 Introduction 15 3 Features 15 2 15 3 15 4 15 5 Section 15 Monitor ROM MON BUTS co oie dod doe ACE OR AA 189 ES I ETLTTItT TO OTT AA T TT Io 189 Functional Description 74 irr re Sa d Rr Rare RN 190 ON td ee bp ied eee NA T T T TT S 202 This section describes the monitor ROM MON and the monitor mode entry methods The monitor ROM allows complete testing of the MCU through a single wire interface with a host computer Monitor mode entry can be achieved without use of the higher test voltage VrsT as long as vector addresses FFFE and FFFF are blank thus reducing the hardware requirements for in circuit programming Features of the monitor ROM include MC68HC908GR8 Rev 4 0 Normal user mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark space non return to zero NRZ communication with host computer Execution of code in RAM or FLASH Technical Data MOTOROLA Monitor ROM MON 189 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Monitor ROM MON FLASH memory security feature e FLASH memory programming interface Enhanced PLL phase locked loop option to allow use of external 32 768 kHz crystal to generate internal frequency of 2 4576 MHz 310 byte monitor ROM code size FE20 to FF55 e Monitor mode entry w
28. VPR1 and VPRO E 2 4 8 1 Do not program E to a value of 3 MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Clock Generator Module CGMC 117 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generator Module CGMC 7 6 2 PLL Bandwidth Control Register The PLL bandwidth control register PBWC Selects automatic or manual software controlled bandwidth control mode e Indicates when the PLL is locked e In automatic bandwidth control mode indicates when the PLL is in acquisition or tracking mode n manual operation forces the PLL into acquisition or tracking mode Address 0037 Bit 7 6 5 4 3 2 1 Bit 0 Read LOCK xm 0 0 0 0 AUTO ACQ R Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 7 5 PLL Bandwidth Control Register PBWC AUTO Automatic Bandwidth Control Bit This read write bit selects automatic or manual bandwidth control When initializing the PLL for manual operation AUTO 0 clear the ACQ bit before turning on the PLL Reset clears the AUTO bit 1 Automatic bandwidth control 0 Manual bandwidth control LOCK Lock Indicator Bit When the AUTO bit is set LOCK is a read only bit that becomes set when the VCO clock CGMVCLK is locked running at the programmed frequency When the AUTO bit is clear LOCK reads as logic O and has no m
29. MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 MC68HC908GR8 D For More Information On This Product Go to www freescale com
30. PTDI ATDO PTD3 ATD11 Veg 20 5 Functional Description Figure 20 1 summarizes the SPI I O registers and Figure 20 2 shows the structure of the SPI module Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read DMAS cO i So a A SPRIE SPMSTR POL PHA PWOM PE PTIE 0010 SPI Control Register Write SPCR Reset 0 0 1 0 1 0 0 0 Read SPRF OVRF MODF SPTE R ERRIE MODFEN PR1 PRO 0011 SPI Status and Control Write Register SPSCR Reset 0 0 0 0 1 0 0 0 Read R7 R6 R5 R4 R3 R2 R1 RO SPI Data Register 0012 SPDR Write T7 T6 T5 T4 T3 T2 T1 TO Reset Unaffected by reset Unimplemented Figure 20 1 SPI I O Register Summary MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 299 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI INTERNAL BUS CGMOUT 2 FROM SIM CLOCK DIVIDER TRANSMIT DATA REGISTER SHIFT REGISTER 5 4 3 2 MISO MOSI SPSCK RESERVED ua TRANSMITTER CPU INTERRUPT REQUEST SPI P RESERVED CONTROL m RECEIVER ERROR CPU INTERRUPT REQUEST Technical Data Figure 20 2 SPI Module Block Diagram The SPI module allows full duplex synchronous serial communication between the MCU and periphe
31. Receive data register full 0 Receive data register not full ERRIE Error Interrupt Enable Bit This read write bit enables the MODF and OVRF bits to generate CPU interrupt requests Reset clears the ERRIE bit 1 MODF and OVRF can generate CPU interrupt requests 0 MODF and OVRF cannot generate CPU interrupt requests OVRF Overflow Bit This clearable read only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register In an overflow condition the byte already in the receive data register is unaffected and the byte that shifted in last is lost Clear the OVREF bit by reading the SPI status and control register with OVRF set and then reading the receive data register Reset clears the OVRF bit 1 Overflow 0 No overflow MC68HC908GR8 Rev 4 0 Technical Data MOTOROLA Serial Peripheral Interface SPI 325 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface SPI Technical Data MODF Mode Fault Bit This clearable read only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set In a master SPI the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set Clear the MODF bit by reading the SPI status and control register SPSCR with MODF set and then writing to the SPI control register SPCR Reset cl
32. Return of all enabled key