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Integrated Device Technology Inc IDT 79RV3081 79RV3081E

1. 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit t1 BusReq Ack BusError Set up to SysCik rising 6 5 ns RdCEn CohReq tla A D Set up to SysCik falling 7 6 ns t2 BusReq Ack BusError Hold from SysClk rising 4 4 ns RdCEn CohReq t2a AID Hold from SysClk falling 2 2 ns t3 A D Addr Diag ALE Wr Tri state from SysCik rising 10 10 ns Burst WrNear Rd DataEn t4 A D Addr Diag ALE Wr Driven from SysCk falling 10 10 ns Burst WrNear Rd DataEn t5 BusGnt Asserted from SysClk rising 8 7 ns t6 BusGnt Negated from SysClk falling 8 7 ns t7 Wr Rd Burst WrNear A D Valid from SysCIk rising 5 5 ns 18 ALE Asserted from SysClk rising 4 4 ns t9 ALE Negated from SysCik falling 4 4 ns t10 AID Hold from ALE negated 2 2 ns t11 DataEn Asserted from SysClk falling 15 15 ns t12 DataEn Asserted from A D tri state 0 0 ns t14 A D Driven from SysCik rising 9 0 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysCIk falling 7 6 ns t16 Addr 3 2 Valid from SysClk 6 6 ns 117 Diag Valid from SysClk 12 11 ns t18 A D Tri state from SysClk falling 10 10 ns t19 AID SysCIk falling to data valid 13 12 ns 120 ClkIn 2x clock mode Pulse Width HIGH 10 8 ns t21 ClkIn 2x clock mode Pulse Width LOW 10 8 ns t22 ClkIn 2x clock mode C
2. IDT79R3081 IDT 79R3081 79R3081E HEH RISController IDT 79RV3081 79RV3081E THH 4 with FPA Integrated Device Technology Inc FEATURES Large on chip caches with user configurability Instruction set compatible with IDT79R3000A R3041 16kB Instruction Cache 4kB Data Cache R3051 and R3071 RISC CPUs Dynamically configurable to 8kB Instruction Cache lt High level of integration minimizes system cost 8kB Data Cache R3000A Compatible CPU Parity protection over data and tag fields Low cost 84 pin packaging Superset pin and software compatible with R3051 R3071 Multiplexed bus interface with support for low cost low R3010A Compatible Floating Point Accelerator Optional R3000A compatible MMU Large Instruction Cache Large Data Cache speed memory systems with a high speed CPU Read Write Buffers e On chip 4 deep write buffer eliminates memory write stalls e 43VUPS at 50MHz e On chip 4 deep read buffer supports burst or simple block 13MFlops reads lt Flexible bus interface allows simple low cost designs On chip DMA arbiter Hardware based Cache Coherency Support Programmable power reduction mode Optional 1x or 2x clock input 20 through 50MHz operation e y version operates at 3 3V Bus Interface can operate at half processor frequency e 50MHz at 1x clock input and 1 2 bus frequency only R3081 BLOCK DIAGRAM BrCond 3 2 0
3. 20MHz 25MHz Symbol Parameter Test Conditions Min Max Min Max Units Von Output HIGH Voltage Vcc Min loH 4mA 2 4 2 4 V VoL Output LOW Voltage Vcc Min IOL 4mA 0 4 0 4 V VIH Input HIGH Voltage 2 0 2 0 V VIL Input LOW Voltage 0 8 0 8 V VIHS Input HIGH Voltage 2 3 2 8 2 8 V VILS Input LOW Voltage 1 2 0 4 0 4 V CIN Input Capacitance 4 12 12 pF Cour Output Capacitance 12 12 pF lec Operating Current Vcc 5 0V TA 25 C 550 650 mA In Input HIGH Leakage VIH VCC 100 100 uA liL Input LOW Leakage Vit GND 100 100 uA loz Output Tri state Leakage VoH 2 4V VoL 0 5V 100 100 100 100 uA NOTES 2889 tbl 09 1 Vit Min 3 0V for pulse width less than 15ns Vu should not fall below 0 5V for larger periods 2 Vins and Vils apply to ClkIn and Reset 3 ViH should not be held above Vcc 0 5V 4 Guaranteed by design 5 Case Temperatures are instant on AC ELECTRICAL CHARACTERISTICS R3081 MILITARY TEMPERATURE RANGE 2 Tc 55 C to 125 C Voc 5 0V 10 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit tl BusReq Ack BusError Set up to SysClk rising 6 5 ns RdCEn CohReq tla A D Set up to SysClk falling 7 6 ns t2 BusReq Ack BusError Hold from SysClk rising 4 4 ns RdCEn CohReq t2a AID Hold from SysCik falling 2 2 ns 13 A D Addr Di
4. ml Master Pipeline Control ClkIn Clock Generator Unit Clock Doubler System Control Floating Point Coprocessor Integer Coprocessor CPO CPU Core Exception Control General Registers Register Unit Registers 32 x 32 16 x 64 Memory Management ALU Exponent Unit Registers site Add Unit is Translation Mult Div Unit A I Int 5 0 Lookaside Buffer TT Address Adder Divide Unit 64 entries e f Multioy Unit PC Control _____MUNMipliy Unit Virtual Address Exception Control FP Interrupt Physical Address Bus Data Bus Configurable Configurable Instruction Data 36 Cache Cache 16kB 8kB 4kB 8kB Data Bus R i R3051 Superset Bus Interface Unit 4 deep 4 deep DMA BIU Coherenc y Read Write Buffer Buffer Arbiter Control Logic Address DMA Rd Wr SysClk Invalidate Data Ctrl Ctrl Control pope dew 01 The IDT logo is a registered trademark and RISController R3041 R3051 R3052 R3071 R3081 R3720 R4400 R4600 IDT kit and IDT sim are trademarks of Integrated Device Technology Inc MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1995 1995 Integrated Device Technology Inc 5 5 ESCE IDT79R3081 RISController INTRODUCTION The IDT R3051 family is a series of high performance 32 bit microprocessors featuring a high level of integration and targeted to high performance
5. MILITARY AND COMMERCIAL TEMPERATURE RANGES Tc 0 C to 85 C VCC 3 3V 5 33MHz 40MHz Symbol Parameter Test Conditions Min Max Min Max Units Von Output HIGH Voltage Vcc Min loH 4mA 2 4 2 4 V VoL Output LOW Voltage Vcc Min IOL 4mA 0 4 0 4 V VIH Input HIGH Voltage 2 0 2 0 V VIL Input LOW Voltage 0 8 0 8 V VIHS Input HIGH Voltage 2 3 2 8 28 vV VILS Input LOW Voltage 1 2 0 4 0 4 V CIN Input Capacitance 4 5 10 10 pF Cour Output Capacitance 45 10 10 pF lec Operating Current Vcc 3 3V TA 25 C 525 600 mA In Input HIGH Leakage VIH VCC 100 100 HA liL Input LOW Leakage Vit GND 100 100 uA loz Output Tri state Leakage VOH 2 4V VoL 0 5V 100 100 100 100 uA NOTES 2889 tbl 09 1 Vi Min 3 0V for pulse width less than 15ns Vu should not fall below 0 5V for larger periods 2 ViHs and ViLs apply to Cikin and Reset 3 ViH should not be held above Vcc 0 5V 4 Guaranteed by design 5 ALE is 12pF for SysClk values C and Cour for all speeds AC ELECTRICAL CHARACTERISTICS RV3081 COMMERCIAL TEMPERATURE RANGE 2 Tc 0 C to 85 C VCC 3 3V 5 33MHz 40MHz Symbol Signals Description Min Max Min Max Unit tl B
6. 3 3 ns 19 ALE Negated from SysCIk falling 3 3 ns t10 AID Hold from ALE negated 1 5 15 ns t11 DataEn Asserted from SysClk falling 13 12 ns t12 DataEn Asserted from A D tri state 0 0 ns t14 AID Driven from SysClk rising 9 0 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysClk falling 5 4 ns 2889 tbl 11 5 5 18 IDT79R3081 RISController AC ELECTRICAL CHARACTERISTICS R3081 cont COMERCIAL TEMPERATURE RANGE 33 40MHz Tc 0 C to 85 C Voc 5 0V 45 MILITARY AND COMMERCIAL TEMPERATURE RANGES 33MHz 40MHz Symbol Signals Description Min Max Min Max Unit t16 Addr 3 2 Valid from SysCIk 5 4 5 ns t17 Diag Valid from SysCIk 10 9 ns 118 A D Tri state from SysClk falling 9 8 ns t19 AID SysClk falling to data valid 11 10 ns t20 ClkIn 2x clock mode Pulse Width HIGH 6 5 5 6 ns t21 ClkIn 2x clock mode Pulse Width LOW 6 5 5 6 ns t22 ClkIn 2x clock mode Clock Period 15 250 12 5 250 ns 123 Reset Pulse Width from Vcc valid 200 200 us 124 Reset Minimum Pulse Width 32 32 tsys t25 Reset Set up to SysClk falling 4 3 ns 126 Int Mode set up to Reset rising 8 7 ns 127 Int Mode hold from Reset rising 0 0 ns 128 Sint SBrCond Set up to SysClk falling 4 3 ns 129 Sint SBr
7. consult the R3081 Family Hardware User s Guide for a complete description of this processor DEVICE OVERVIEW As partofthe R3051 family the R3081 extends the offering of a wide range of functionality in a compatible interface The R3051 family allows the system designer to implement a single base system andutilize interface compatible processors of various complexity to achieve the price performance goals of the particular end system Differences among the various family members pertain to the on chip resources of the processor Currentfamily members include lt TheR3052E which incorporates an 8kB instruction cache a 2kB data cache and full function memory management unit MMU including 64 entry fully associative Translation Lookaside Buffer TLB The R3052 which also incorporates an 8kB instruction cache and 2kB data cache but does not include the TLB and instead uses a simpler virtual to physical address mapping lt The R3051E which incorporates 4kB of instruction cache and 2kB of data cache along with the full function MMU TLB of the R3000A 5 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES lt The R3051 which incorporates 4kB of instruction cache and 2kB of data cache but omits the TLB and instead uses a simpler virtual to physical address mapping lt TheR3081E which incorporates a 16kB instruction cache a 4kB data cache and full function memory management unit MMU including 64 entry fully ass
8. Continued PIN NAME VO DESCRIPTION Int 5 3 Processor Interrupt During normal operation these signals are logically the same as the Int 5 0 Sint 2 0 signals of the R3000 During processor reset these signals perform mode initialization of the CPU but in a different simpler fashion than the interrupt signals of the R3000 There are two types of interrupt inputs the SInt inputs are internally synchronized by the processor and may be driven by an asynchronous external agent The direct interrupt inputs are not internally synchronized and thus must be externally synchronized to the CPU The direct interrupt inputs have one cycle lower latency than the synchronized interrupts Note that the interrupt used by the on chip FPA will not be monitored externally ClkIn Master Clock Input This input clock can be provided at the execution frequency of the CPU 1x clock mode or at twice that frequency 2x clock mode as selected at reset Reset Master Processor Reset This signal initializes the CPU Mode selection is performed during the last cycle of Reset Rsvd 4 1 I O Reserved These four signal pins are reserved for testing and for future revisions ofthis device Users must not connect these pins Note that Rsvd 0 of the R3051 is now used for the CohReq input pin 2889 tbl 04
9. Pins must not be connected NOTE MILITARY AND COMMERCIAL TEMPERATURE RANGES 1DT79R3081 RISController DN St DO DN EJO Zog SSS AJ Leen Leg pr ef OOCks ao STE is 0098 9999 SE g s 35502888 ZZ gt gt OCCOA LO IE gt ELE nan gt gt gt gt DANSE OOTI I OOTI Soot oo TORON Oo olc e E Op T DDD OO Oo OO 00 00 00 00 00 00 00 Do N N IN N N E y N LO N N 3 co o o Ce Ce LO a gt ce 22 st A oO Ka m o lu gt gt rap y S Sen y LO oc Or ke Co Co CH Co N D LO LO Oo N g LO o de N LO LO N LO N 3 m CO N LO dk N N LO YOR MMOH AMTOONDAROKF ANY HNORNROADOE AAAA MMMM st si st st NY III UI U UUUUU LU OO oO 0 mn gt gt gt gt gt own NN gt OOOO DORTZOO 88 TANTO H erte Uc e EE E eas vd d 2905 drw 06 SSA 29 0 puoy g baysng UZOPH y y J01135Ng 19S9y Jupsng MIOSAS SSA JON ugerra IM PH 31V b y PAVODVIG 1 Be1g SSA 99A Z IPPY E IPPYV Je2NIM 181Ng SSA o JON 26 5 5 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES 144 ClkIn SysClk tsys 2889 drw 12 Figure 8 a R3081 Clocking 1x clock input mode full frequency bus 144 4 t43 ClkIn
10. Vins and Vils apply to ClkIn and Reset 3 ViH should not be held above Vcc 0 5V 4 Guaranteed by design 5 ALE is 12pF for SysClk values C and C for all speeds AC ELECTRICAL CHARACTERISTICS RV3081 COMMERCIAL TEMPERATURE RANGE 2 _ Tc 0 C to 85 C Vcc 3 3V 5 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit tl BusReq Ack BusError Set up to SysCik rising 6 5 ns RdCEn CohReq tla A D Set up to SysClk falling 7 6 ns t2 BusReq Ack BusError Hold from SysCIk rising 4 4 ns RdCEn CohReq t2a AID Hold from SysCik falling 2 2 ns t3 A D Addr Diag ALE Wr Tri state from SysClk rising 10 10 ns Burst WrNear Rd DataEn t4 A D Addr Diag ALE Wr Driven from SysClk falling 10 10 ns Burst WrNear Rd DataEn t5 BusGnt Asserted from SysClk rising 8 7 ns 16 BusGnt Negated from SysClk falling 8 7 ns t7 Wr Rd Burst WrNear A D Valid from SysClk rising 5 5 ns 18 ALE Asserted from SysClk rising 4 4 ns t9 ALE Negated from SysCIk falling 4 4 ns t10 A D Hold from ALE negated 3 2 2 ns t11 DataEn Asserted from SysClk falling 15 15 ns t12 DataEn Asserted from A D tri state 0 0 ns t14 A D Driven from SysCIk rising 9 0 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysClk falling 7 6 ns t16 Addr 3 2 Valid from SysClk 6 6 ns t17 Diag Valid from SysCIk 12 11 ns 5 5 12 IDT79R3081 RIS
11. WrNear 2889 drw 24 Figure 16 Request and Relinquish of R3081 Bus to External Master 5 5 32 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES SysClk BusReq a N D a BusGnt A D 31 0 Addr 3 2 Diag 1 0 ALE LULU TATA TA TATA _ Burst WrNear 2889 drw 25 Figure 17 R3081 Regaining Bus Mastership SysCik Sint n t28 t29 2889 drw 26 Figure 18 Synchronized Interrupt Input Timing SysCik Int n t30 t31 2889 drw 27 Figure 19 Direct Interrupt Input Timing IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES SysCik SBrCond n t28 t29 2889 drw 28 Figure 20 Synchronized Branch Condition Input Timing SysCik BrCond n t30 t31 2889 drw 29 Figure 21 Direct Branch Condition Input Timing SysCIk Suma DOI 4 Bia CohReq BusGnt lt t3 A D 31 0 Addr 3 2 Diag 1 0 wi E TEA ALE EEE a Figure 22 Coherent DMA Request 2889 drw 30 5 5 34 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES SysClk T41 Wr SS A A D Addr e e Al Internal valet ie a a Address 2889 drw 31 SysCIk Ack IvdReq Internal Ivd Internal Invalidate Address 2988 drw 32 Figure 24 Cache Word Invalidation 2889 drw 33 Figure 25 End of Coherent Write 5 5 35 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES Mie Sg ca zn Addr 3 2 LA EEE
12. but cost sensitive processing applications The R3051 family is designed to bring the high performance inherent in the MIPS RISC architecture into low cost simplified power sensitive applications Thus functional units have been integrated onto the CPU core in order to reduce the total system cost rather than to increase the inherent performance of the integer engine Nevertheless the R3051 family is able to offer 43VUPS performance at 50MHz without requiring external SRAM or caches The R3081 extends the capabilities of the R3051 family by integrating additional resources into the same pin out The R3081 thus extends the range of applications addressed by the R3051 family and allows designers to implement a single base system and software set capable of accepting a wide variety of CPUs according to the price performance goals of the end system In addition to the embedded applications served by the R3051 family the R3081 allows low cost entry level computer systems to be constructed These systems will offer many times the performance of traditional PC systems yet cost approximately the same The R3081 is able to run any standard R3000A operation system including ACE UNIX Thus the R3081 can be used to build a low cost ARC compliant system further widening the range of performance solutions of the ACE Initiative An overview of this device and quantitative electrical parameters and mechanical data is found in this data sheet
13. loH 4mA 3 5 35 35 35 35 V VoL Output LOW Voltage Vcc Min loL 4mA 0 4 04 04 04 04 V VIH Input HIGH Voltage 3 2 0 20 20 20 20 V VIL Input LOW Voltage 08 08 08 08 08 v Vids Input HIGH Voltage 30 30 30 30 30 V Vis Input LOW Voltage 1 2 04 04 04 04 04 V Cin Input Capacitance 10 10 101 10 10 pF Cour Output Capacitance 4 10 10 101 10 10 pF Icc Operating Current Vcc 5V TA 25 C 475 525 625 700 825 mA In Input HIGH Leakage VIH VCC 100 100 100 100 100 uA liL Input LOW Leakage Vit GND 100 100 100 100 100 uA loz Output Tri state Leakage VoH 2 4V VoL 0 5V 100 100 100 100 100 100 100 100 100 100 uA NOTES 2889 tbl 09 1 Vit Min 3 0V for pulse width less than 15ns ViL should not fall below 2 Vins and ViLs apply to ClkIn and Reset 3 ViH should not be held above Vcc 0 5V 4 Guaranteed by design 5 5 0 5V for larger periods 16 IDT79R3081 RISController AC ELECTRICAL CHARACTERISTICS R3081 COMMERCIAL TEMPERATURE RANGE 2 20 25MHz Tc 0 C to 85 C Vcc 5 0V 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES
14. tap SysCIk t35 tsys 2 2889 drw 13 Figure 8 b R3081Clocking 1x clock input mode half frequency bus ClkIn SysClk 2889 drw 14 Figure 8 c R3081 Clocking 2x clock input mode half frequency bus t22 t21 ClkIn too SysClk 2889 drw 15 tsys Figure 8 d R3081 Clocking 2x clock input mode full frequency bus 5 5 27 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES CC 7 Vcc ClkIn FA Reset 2889 drw 16 Figure 9 Power On Reset Sequence ClkIn En _ 124 Reset 2889 drw 17 Figure 10 Warm Reset Sequence SysCik Reset t25 Lac Int n t26 7 t27 2889 drw 18 Figure 11 Mode Selection and Negation of Reset 5 5 28 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES SysClk IR IR Ge d g a il EM t14 e t14 Add A D 31 0 WW BE i Data Input Addr 3 2 Word Address Si DataEn i cileni Ack 117 Le Cached Miss Address 3 Miss Address 2 Start Turn Ack Sample End Read Bus Ack Ack RdCen Data Read 2889 drw 19 o 9 D D Q Q So E 1 5 Figure 12 Single Datum Read in R3081 5 5 29 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES Rd Id des yl uk S u CH Ada SC Dai ni A D 31 0 BE 0 ll er Se at q wwa DE SC X X u _ zl TTT ET
15. 081 E 20 25 33 40 50 79RV3081 E 20 25 33 79RV3081 E 20 25 33 40 79R3081 E 20 25 FDB FDM 79R3081 79R3081E 79RV3081 79RV3081E MJ Package PF Package MJ Package FD Package Only 5 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial Temperature Range Compliant to MIL STD 883 Class B Military Temperature Range Only 84 Pin MQUAD 84 lead Cavity down Flatpack with Integral Thermal Slug 84 lead PLCC 100 lead TQFP 20 0MHz 25 0MHz 33 33MHz 40 0MHz 50 0MHz 5V Only No TLB Vcc 5V With TLB Vcc 5V No TLB Vcc 3 3V With TLB Vcc 3 3V 2889 drw 37 38
16. ABSOLUTE MAXIMUM RATINGS 2 AC TEST CONDITIONS R3081 Symbol Rating Commercial Military Unit Symbol Parameter Min Max Unit VTERM Terminal Voltage 0 5to 7 0 0 5 to 7 0 V with Respect VIH Input HIGH Voltage 3 0 V to GND Vu Input LOW Voltage 0 V Tc Operating Case 0 to 85 55 to 125 C Temperature VIHS Input HIGH Voltage 3 5 V TBIAS Case Temperature 55 to 125 65 to 135 C VILS Input LOW Voltage 0 V Under Bias 2889 tbl 06 Tsta Storage 55 to 125 65t0 155 C AC TEST CONDITIONS RV3081 Temperature Symbol Parameter Min Max Unit VIN Input Voltage 0 5 to 7 0 0 5 to 7 0 V BEE SES VIH Input HIGH Voltage 3 0 V 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS VIL Input LOW Voltage 0 V may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions VIHS Input HIGH Voltage 3 0 J V above those indicated inthe operational sections ofthis specification is not Vus Input LOW Voltage CZ 0 y implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 89916106 2 Vin minimum 3 0V for pulse width less than 15ns Vin should not exceed Vcc 0 5V OUTPUT LOADING FOR AC TESTING 3 Notmore than one output should be shorted at atime Duration of the short should not exceed 30 seconds 4mA VREF RECOMMENDED OPERATING es To Device TEMPERATURE AND SUPPLY VOL
17. Cond Hold from SysClk falling 2 2 ns 130 Int BrCond Set up to SysCIk falling 4 3 ns 131 Tnt BrCond Hold from SysClk falling 2 2 ns tsys SysClk full frequency mode Pulse Width 2422 2422 2422 2422 ns 132 SysClk full frequency mode Clock HIGH Time 122 1 12241 122 1 12241 ns 133 SysCik full frequency mode Clock LOW Time 22 1 12241 122 1 12241 ns tsys 2 SysClk half frequency model Pulse Width 4 122 4 122 4 122 4 122 ns t34 SysCik half frequency mode Clock HIGH Time 2 t22 1 212241 222 1 22241 ns 185 SysCik half frequency mode Clock LOW Time 24221 22241 222 1 22241 ns 136 ALE Set up to SysClk falling 7 6 ns 137 ALE Hold from SysCIk falling 1 1 ns t38 A D Set up to ALE falling 8 8 ns t39 A D Hold from ALE falling 1 1 ns t40 Wr Set up to SysClk rising 8 7 ns 141 Wr Hold from SysClk rising 3 3 ns 142 ClkIn 1x clock mode Pulse Width HIGH S 13 116 ns 143 ClkIn 1x clock mode Pulse Width LOW 6 13 11 6 ns t44 ClkIn 1x clock mode Clock Period 30 50 25 50 ns tderate All outputs Timing deration for loading over CLp 8 4 1 1 ns 25pF NOTES 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2889 tbl 11 The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 2 3 Guaranteed by design 4 This parameter is used to der
18. Controller AC ELECTRICAL CHARACTERISTICS RV3081 cont COMMERCIAL TEMPERATURE RANGE 2 Tc 0 C to 85 C VCC 3 3V 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit t18 A D Tri state from SysClk falling 10 10 ns t19 AID SysClk falling to data valid 13 12 ns 120 ClkIn 2x clock mode Pulse Width HIGH 10 8 ns t21 ClkIn 2x clock mode Pulse Width LOW 10 8 ns t22 ClkIn 2x clock mode Clock Period 25 250 20 250 ns t23 Reset Pulse Width from Vcc valid 200 200 us 124 Reset Minimum Pulse Width 32 32 tsys 125 Reset Set up to SysClk falling 6 5 ns 126 Int Mode set up to Reset rising 10 9 ns 127 Int Mode hold from Reset rising 0 0 ns 128 Slnt SBrCond Set up to SysClk falling 6 5 ns 129 Sint SBrCond Hold from SysClk falling 3 3 ns 130 Int BrCond Set up to SysClk falling 6 5 ns 131 Int BrCond Hold from SysCIk falling 3 3 ns tsys SysCIk full frequency mode Pulse Width 2422 2422 2422 2422 ns 132 SysClk full frequency mode Clock High Time 122 2 12242 122 2 12242 ns 133 SysCIk full frequency mode Clock LOW Time 5 122 2 122 2 122 2 122 2 ns tsys 2 SysClk half frequency mode Pulse Width gt 4 t22 4 122 4 122 4 122 4 122 ns t34 SysCik half frequenc
19. O gt Diag 1 0 LL ES i EEE BE gt i E a JAAN LL es MAA WrNear 2889 drw 34 Figure 26 End of Coherent DMA Request 5 5 36 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES 84 LEAD PLCC MQUAD SQUARE A A 45 x 04 a C T GES TT TT TT SEATING PLANE 2874 drw 27 NOTES NOUSWNTE All dimensions are in inches unless otherwise noted BSC Basic lead Spacing between Centers D amp E do not include mold flash or protutions Formed leads shall be planar with respect to one another and within 004 inches at the seating plane ND amp NE represent the number of leads in the D amp E directions respectively D1 amp E1 should be measured from the bottom of the package MQUAD is pin amp form compatible with PLCC DWG J84 1 MJ84 1 of Leads 84 84 Symbol Min Max Min Max A 165 180 165 180 AI 095 115 094 114 B 026 032 026 032 b1 013 021 013 021 C 020 040 020 040 C1 008 012 008 012 D 1 185 1 195 1 185 1 195 D1 1 150 1 156 1 140 1 150 D2 E2 1 090 1 130 1 090 1 130 D3 E3 1 000 REF 1 000 REF E 1 185 1 195 1 185 1 195 E1 1 150 1 156 1 140 1 150 e 050 BSC 050 BSC ND NE 21 21 5 5 37 IDT79R3081 RISController ORDERING INFORMATION KAKAK XX A A IDT Speed Package Process Temp Range Device Type VALID COMBINATIONS IDT 79R3
20. TAGE Grade Temperature Case GND Vcc CLD Military 55 C to 125 C OV 5 0 10 L AMA Commercial 0 C to 85 C OV 5 0 5 See Commercial 0 C to 85 C OV 3 3 5 Signal Cip 2889 tbl 07 SysClk 50 pf All Others 2889 tbl 08 5 5 11 IDT79R3081 RISController DC ELECTRICAL CHARACTERISTICS RV3081 COMMERCIAL TEMPERATURE RANGE 2 MILITARY AND COMMERCIAL TEMPERATURE RANGES Tc 0 C to 85 C VCC 3 3V 5 20MHz 25MHz Symbol Parameter Test Conditions Min Max Min Max Units VOH Output HIGH Voltage Vcc Min loH 4mA 2 4 2 4 V VOL Output LOW Voltage Vcc Min loL 4mA 0 4 0 4 V VIH Input HIGH Voltage 2 0 2 0 V VIL Input LOW Voltage 0 8 0 8 V VIHS Input HIGH Voltage 2 3 2 8 28 V VILS Input LOW Voltage 1 2 0 4 0 4 V CIN Input Capacitance 4 10 10 pF Cour Output Capacitance 45 10 10 pF lec Operating Current Vcc 3 3V TA 25 C 375 425 mA In Input HIGH Leakage VIH VCC 100 100 uA liL Input LOW Leakage Vit GND 100 100 uA loz Output Tri state Leakage VoH 2 4V VoL 0 5V 100 100 100 100 uA NOTES 2889 tbl 09 1 Vu Min 3 0V for pulse width less than 15ns Vu should not fall below 0 5V for larger periods 2
21. action Condition 11 11 11 53 53 53 Codes A B Result A B Result Exponent Add Unit Control Unit SR Round and Clocks 53 53 56 A B Result Divide Unit 53 53 56 A B Result Multiply Unit 2889 drw 05 Figure 5 FPA Functional Block Diagram 5 5 1DT79R3081 RISController simple handshake signals to process CPU read and write requests In addition to the read and write interface the R3051 family incorporates a DMA arbiter to allow an external master to control the external bus The R3081 also supports hardware based cache coherency during DMA writes The R3081 can invalidate a specified line of data cache orin fact can perform burst invalidations during burst DMA writes The R3081 incorporates a 4 deep write buffer to decouple the speed of the execution engine from the speed of the memory system The write buffers capture and FIFO processor address and data information in store operations and present it to the bus interface as write transactions at the rate the memory system can accommodate The R3081 read interface performs both single datum reads and quad word reads Single reads work with a simple handshake and quad word reads can either utilize the simple handshake in lower performance simple systems or utilize atightertiming mode when the memory system can burst data at the processor clock rate Thus the system designer can choose to utilize page or nibble mode DRAMs and possi
22. ag ALE Wr Tri state from SysClk rising 10 10 ns Burst WrNear Rd DataEn t4 A D Addr Diag ALE Wr Driven from SysClk falling 10 10 ns Burst WrNear Rd DataEn t5 BusGnt Asserted from SysClk rising 8 7 ns t6 BusGnt Negated from SysClk falling 8 7 ns t7 Wr Rd Burst WrNear A D Valid from SysClk rising 5 5 ns 18 ALE Asserted from SysClk rising 4 5 4 5 ns t9 ALE Negated from SysClk falling 4 A ns t10 AID Hold from ALE negated 3 1 5 1 5 ns t11 DataEn Asserted from SysClk falling 15 15 ns t12 DataEn Asserted from A D tri state 3 0 0 ns t14 A D Driven from SysCIk rising 0 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysCIk falling 7 6 ns t16 Addr 3 2 Valid from SysCIk 6 6 ns t17 Diag Valid from SysClk 12 11 ns 5 5 22 1DT79R3081 RISController AC ELECTRICAL CHARACTERISTICS R3081 cont MILITARY TEMPERATURE RANGE 2 Tc 55 C to 125 C Voc 5 0V 10 MILITARY AND COMMERCIAL TEMPERATURE RANGES 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit t18 A D Tri state from SysClk falling 10 10 ns t19 A D SysCIk falling to data valid 13 12 ns t20 ClkIn 2x clock mode Pulse Width HIGH 10 8 ns t21 ClkIn 2x clock mode Pulse Width LOW 10 8 ns t22 ClkIn 2x clo
23. ansactions to an address within the same 512 word page as the prior write transaction This signal is useful in memory systems which employ page mode or static column DRAMs and allows near writes to be retired quickly Acknowledge An input which indicates to the device that the memory system has sufficiently processed the bus transaction and that the CPU may either terminate the write cycle or process the read data from this read transfer During Coherent DMA this input indicates that the current write transfer is completed and that the internal invalidation address counter should be incremented RdCEn Read Buffer Clock Enable An input which indicates to the device that the memory system has placed valid data on the A D bus and that the processor may move the data into the on chip Read Buffer SysClk System Reference Clock An output from the CPU which reflects the timing of the internal processor Sys clock This clock is used to control state transitions in the read buffer write buffer Memory controller and bus interface unit This clock will either be at the same frequency as the CPU execution rate clock or at one half that frequency as selected during reset BusReq DMA Arbiter Bus Request An input to the device which requests that the CPU tri state its bus interface signals so that they may be driven by an external master BusGnt DMA Arbiter Bus Grant An output from the CPU used to acknowledge that a Bu
24. ate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition NO O0 In 1x clock mode t22 is replaced by t44 2 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 3ns for 40 and 50MHz When using the Reduced Frequency feature the minimum allowed internal CPU speed is 0 5 MHz 5 5 19 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS R3081 COMMERCIAL TEMPERATURE RANGE 2 somHz Tc 0 C to 85 C Voc 5 0V 5 50MHz Symbol Signals Description Min Max Unit t1 BusReq Ack BusError Set up to SysCik rising 5 ns RdCEn CohReq tla A D Set up to SysClk falling 6 ns t2 BusReg Ack BusError Hold from SysClk rising 4 ns RdCEn CohReq t2a A D Hold from SysCik falling 2 ns t3 A D Addr Diag ALE Wr Tri state from SysClk rising 10 ns Burst WrNear Rd DataEn t4 A D Addr Diag ALE Wr Driven from SysCk falling 10 ns Burst WrNear Rd DataEn 15 BusGnt Asserted from SysClk rising 7 ns 16 BusGnt Negated from SysClk falling 7 ns t7 Wr Rd Burst WrNear A D Valid from SysCIk ri
25. bly use interleaving if desired in high performance systems or use simpler techniques to reduce complexity In order to accommodate slower quad word reads the R3081 incorporates a 4 deep read buffer FIFO so that the external interface can queue up data within the processor before releasing itto perform a burst fill of the internal caches The R3081 is R3051 supersetcompatible inits bus interface Specifically the R3081 has additional support to simplify the design of very high frequency systems This support includes the ability to run the bus interface at one half the processor execution rate as well as the ability to slow the transitions between reads and writes to provide extra buffer disable time for the memory interface However it is still possible to design a system which with no modification to the PC Board or software can accept either an R3041 R3051 R3052 R3071 or R3081 SYSTEM USAGE The IDT R3051 family has been specifically designed to allow a wide variety of memory systems Low cost systems can use slow speed memories and simple controllers while other designers may choose to incorporate higher frequencies faster memories and techniques such as DMA to achieve maximum performance The R3081 includes specific support for high perfromance systems including signals necessary to implement external secondary caches and the ability to perform hardware based cache coherency in multi master systems Figure 6 shows a t
26. chieves hitratesin excess of 98 in most applications and substantially contributes to the performance inherent in the R3081 The cache is implemented as a direct mapped cache and is capable of caching instructions from anywhere within the 4GB physical address space The cache is implemented using physical addresses rather than virtual addresses and thus does not require flushing on context switch The instruction cache is parity protected over the instruction word and tag fields Parity is generated by the read buffer during cache refill during cache references the parity is checked and in the case of a parity error a cache miss is processed Data Cache The R3081 incorporates an on chip data cache of 4kB organized as a line size of 4 bytes one word The R3081 allows the system to reconfigure the on chip cache from the default 16kB I Cache 4kB D Cache to 8kB of Instruction and 8kB of Data caches The relatively large data cache achieves hit rates in excess of 95 in most applications and contributes substantially to MILITARY AND COMMERCIAL TEMPERATURE RANGES the performance inherent in the R3081 As with the instruction cache the data cache is implemented as a direct mapped physical address cache The cache is capable of mapping any word within the 4GB physical address space The data cache is implemented as a write through cache to insure that main memory is always consistent with the internal cache In order to minimize p
27. ck mode Clock Period 25 250 20 250 ns t23 Reset Pulse Width from Vcc valid 200 200 us 124 Reset Minimum Pulse Width 32 32 tsys 125 Reset Set up to SysClk falling 6 5 ns 126 Int Mode set up to Reset rising 10 9 ns t27 Int Mode hold from Reset rising 0 0 ns 128 Sint SBrCond Set up to SysClk falling 6 5 ns t29 Sint SBrCond Hold from SysCik falling 3 5 3 ns 130 Int BrCond Set up to SysClk falling 6 5 ns t31 Int BrCond Hold from SysCIk falling 3 5 3 ns tsys SysClk full frequency mode Pulse Width 2422 2422 2422 2422 ns 132 SysClk full frequency mode Clock High Time 122 2 12242 122 2 12242 ns 133 SysCIk full frequency mode Clock LOW Time 122 2 122 2 22 2 12242 ns tsys 2 SysClk half frequency mode Pulse Width 4 122 4 122 4 122 4 122 ns 134 SysCIk half frequency mode Clock HIGH Time 2 122 2 22242 2122 2 212242 ns 135 SysCIk half frequency mode Clock LOW Time 222 2 22242 2122 2 212242 ns 136 ALE Set up to SysCik falling 9 8 ns 137 ALE Hold from SysClk falling 2 2 ns 138 AID Set up to ALE falling 10 9 ns 139 A D Hold from ALE falling 2 2 ns 140 Wr Set up to SysCik rising 10 9 ns 141 Wr Hold from SysClk rising 3 3 ns 142 CikIn 1x clock mode Pulse Width HIGH 20 16 ns 143 CikIn 1x clock mode Pulse Width LOW 20 16 ns 144 Cikin 1x clock mode Clock Period 8 50 50 40 50 ns tderate All outputs Timing derati
28. concurrently with each other as well as concurrently with integer operations lt Largeon chip caches The R3051 family contains caches which are substantially larger than those on the majority of today s microprocessors These large caches minimize the number of bus transactions required and allow the R3051 family to achieve actual sustained performance very close to its peak execution rate The R3081 doubles the cache available on the R3052 making it a suitable engine for IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES Cikin IDT R3081 RISController Address Data Control R3051 Local Bus DRAM IO Controller III Controller PROM 1 0 1 0 DRAM DRAM IDT73720 Bus Exchanger 2889 drw 06 Figure 6 R3081 RISChipset Based System System System System Architecture Development Integration Evaluation Phase and Verfification Software DBG Debugger PIXIE Profiler MIPS Compiler Suite Stand Alone Libraries Floating Point Library Cross Development Tools Adobe PostScript PDL MicroSoft Truelmage PDL Logic Analysis Cache 3051 PeerlessPage Printer OS Diagnostics SPP X Server IDT sim Benchmarks IDT kit Evaluation Board In Circuit Emulation Laser Printer System Hardware Remote Debug X Terminal System Real Time OS Hardware Models General CAD Tools Evaluation Board La
29. d institute a fixed address mapping for the various segments of the virtual address space These devices still support distinct kernel and user mode operation but do not require page management software leading to a simpler software model The memory mapping used by these devices is shown in Figure 4 Note that the reserved spaces are for compatiblity with future family members which may map on chip resources to these addresses References to these addresses in the R3081 will be translated in the same fashion as the rest of their respective segments with no traps or exceptions signalled When using the base versions of the architecture the system designer can implement a distinction between the user tasks and the kernel tasks without having to implement page management software This distinction can be implemented by decoding the output physical address In systems which do not need memory protection and wish to have the kernel and user tasks operate out of the same memory space high order address lines can be ignored by the address decoder and thus all references will be seen in the lower gigabyte of the physical address space Floating Point Co Processor The R3081 also integrates an R3010A compatible floating point accelerator on chip The FPA is a high performance co processor co processor 1 to the CPU providing separate add multiply and divide functional units for single and double precision floating point arithmetic The float
30. e the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition In 1x clock mode t22 is replaced by t44 2 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 3ns for 40MHz and 50MHz When using the Reduced Frequency feature the minimum allowed internal CPU speed is 0 5 MHz NO O0 AC ELECTRICAL CHARACTERISTICS R3081 COMMERCIAL TEMPERATURE RANGE 1 2 33 40MHz Tc 0 C to 85 C Vcc 5 0V 45 33MHz 40MHz Symbol Signals Description Min Max Min Max Unit t1 BusReq Ack BusError Set up to SysCik rising 4 3 ns RdCEn CohReq tla A D Set up to SysClk falling 5 4 5 ns t2 BusReq Ack BusError Hold from SysCIk rising 3 3 ns RdCEn CohReq t2a A D Hold from SysClk falling 1 1 ns 13 AID Addr Diag ALE Wr Tri state from SysClk rising 10 10 ns Burst WrNear Rd DataEn H A D Addr Diag ALE Wr Driven from SysClk falling 10 10 ns Burst WrNear Rd DataEn t5 BusGnt Asserted from SysClk rising 6 5 ns t6 BusGnt Negated from SysCik falling 6 5 ns t7 Wr Rd Burst WrNear A D Valid from SysCIk rising 4 3 5 ns 18 ALE Asserted from SysClk rising
31. eference timing diagrams contained in the R3081 Family Hardware User s Manual 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition In 1x clock mode t22 is replaced by t44 2 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 3ns for 40MHz and 50MHz When using the Reduced Frequency feature the minimum allowed internal CPU speed is 0 5 MHz For the 50MHz version 1x Clock Mode and half frequency bus mode only ONO 5 5 20 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS R3081 cont COMERCIAL TEMPERATURE RANGE 2 somHz Tc 0 C to 85 C Voc 5 0V 45 50MHz Symbol Signals Description Min Max Unit tsys 2 SysCIk half frequency mode Pulse Width 5 2 144 2 144 ns 134 SysClk half frequency mode Clock HIGH Time 144 1 14441 ns 135 SysClk half frequency mode Clock LOW Time 144 1 14441 ns 136 ALE Set up to SysCIk falling 8 ns 137 ALE Hold from SysClk falling 2 ns 138 A D Set up to ALE falling 9 ns t39 A D Hold from ALE falling 2 ns 140 Wr Set up to SysClk rising 9 ns 141 Wr Hold from SysClk ris
32. erations the R3081 monitors the A D bus at the start of a DMA write to capture the write target address for potential data cache invalidates Addr 3 2 Low Address 3 2 A 2 bit bus which indicates which word is currently expected by the processor Specifically this two bit bus presents either the address bits for the single word to be transferred writes or single datum reads or functions as a two bit counter starting at 00 for burst read operations During cache coherency operations the R3081 monitors the Addr bus at the start of a DMA write to capture the write target address for potential data cache invalidates Diag 1 Diagnostic Pin 1 This output indicates whether the current bus read transaction is due to an on chip cache miss and also presents part of the miss address The value output on this pin is time multiplexed Cached During the phase in which the A D bus presents address information this pin is an active HIGH output which indicates whether the current read is a result of a cache miss Miss Address 3 During the remainder of the read operation this output presents address bit 3 ofthe address the processorwas attempting to reference when the cache miss occurred Regardless of whether a cache miss is being processed this pin reports the transfer address during this time On write cycles this output signals whether the data being written as retained in the on chip data cache The value of this pin is ti
33. ess internal resistance from one end of the package to the other reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the PCB for a given temperature Even nominal amounts of airflow will dramatically reduce the junction temperature of the die resulting in cooler operation The MQUAD package is available at all frequencies andis pin and form compatible with the PLCC used for the R3051 Thus designers can inter change R3081s and R3051s ina particular design without changing their PC Board The R3081 is guaranteed in a case temperature range of 0 C to 85 C The type of package speed power of the device and airflow conditions affect the equivalent ambient temperature conditions which will meet this specification The equivalent allowable ambient temperature Ta can be calculated using the thermal resistance from case to ambient Oca of the given package The following equation relates ambient and case temperatures Ta Tc P ca where P is the maximum power consumption at hot temperature calculated by using the maximum Icc specification for the device Typical values for ca at various airflows are shown in Table 1 Note that the R3081 allows the operational frequency to be turned down during idle periods to reduce power consumption This operation is described in the R3081 Hardware User s Guide Reducing the operation frequency dramatically reduces p
34. fici il DataEn a ban I nn Burst ven OA AA AA ye fp FIRE Li ii Ack 117 Cached Miss Address 3 X Miss Address 2 Start Turn Ack Sample RdCEn Sample RdCEn Sample RdCEn Sample New Read Bus RdCen Data Data Data Data Transaction 2889 drw 20 O O D D Q Q Sa 2 a 1 5 Figure 13 R3081 Burst Read 5 5 30 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES SysClk Rd ewe Addr 3 2 N D Q 2 a o E ALE DataEn a Burst a geg RdCEn uf Ack RdCEn Sample RdCEn Sample RdCEn Sample Data Data Data Se Figure 14 a Start of Throttled Quad Read Rd mu p Done e Adar 3 2 cc NA NAN ALE A SEE Gates AM A NANA DE y RdCEn J DE ie ti Ach t2 Ack RdCEn Sample RdCEn Sample New Data Data Transaction 2889 drw 22 Figure 14 b End of Throttled Quad Read 5 5 31 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES t19 t14 DA Y Addr Data A D 31 0 BE Out ti 6 ti 0 Word Add Addr 3 2 E SE i A gt 4 a a T t Cached Reserved e Diag 1 t17 Reserved Reserved Diag 0 t15 D KT YO Ack ti Start Data Ack Negate New Write Out GES Ack Wr Transfer 2889 drw 23 Figure 15 R3081 Write Cycle SysClk poe t2 BusReq N DS D BusGnt t3 A D 31 0 Addr 3 2 Diag 1 0 Rd W i lia ALE MEN E ES
35. hip caches mitigate the performance impact of using aslower system bus clock Slow bus turn around The R3081 allows the system designer to space processor operations so that more time 5 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES is allowed for transitions between memory and the processor on the multiplexed address data bus Configurable cache The R3081 allows the system designer to use software to select either a 16kB Instruction Cache 4kB Data Cache organization or an 8kB Instruction 8kB Data Cache organization Cache Coherent Interface The R3081 has an optional hardware based cache coherency interface intended to support multi master systems such as those utilizing DMA between memory and I O Optional 1x or 2x clock input The R3081 can be driven with an R3051 compatible 2x clock input or a lower frequency 1x clock input THERMAL CONSIDERATIONS The R3081 utilizes special packaging techniques to improve the thermal properties of high speed processors Thus the R3081 is packaged using cavity down packaging with an embedded thermal slug to improve thermal transfer to the suurrounding air The R3081 utilizes the 84 pin MQUAD package the MJ package which is an all aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing The MQUAD package allows for an efficient thermal transfer between the die and the case due to the heat spreading effect of the aluminum The aluminum offers l
36. hold time to ALE The system designer should be careful when designing the ALE net to minimize total loading and to minimize skew between ALE and the A D bus which will ensure adequate address access latch time IDT s field and factory applications groups can provide the system designer with assistance for these and other design issues IDT79R3081 RISController PIN DESCRIPTION MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN NAME 1 0 DESCRIPTION A D 31 0 1 0 Address Data A 32 bit time multiplexed bus which indicates the desired address for a bus transaction inone phase and which is used to transmit data between the CPU and external memory resources during the rest of the transfer Bus transactions on this bus are logically separated into two phases during the first phase information about the transfer is presented to the memory system to be captured using the ALE output This information consists of Address 31 4 The high order address for the transfer is presented on A D 31 4 BE 3 0 These strobes indicate which bytes of the 32 bit bus will be involved in the transfer and are presented on A D 3 0 During write cycles the bus contains the data to be stored and is driven from the internal write buffer On read cycles the bus receives the data from the external resource in either a single data transaction or in a burst of four words and places it into the on chip read buffer During cache coherency op
37. ing 3 ns t42 ClkIn 1x clock mode Pulse Width HIGH S 1666 ns 143 ClkIn 1x clock mode Pulse Width LOW 1666 ns 144 ClkIn 1x clock mode Clock Period 8 40 50 ns tderate All outputs Timing deration for loading over Civ 4 1 ns 25pF NOTES 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2 The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition 5 In 1x clock mode t22 is replaced by t44 2 6 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 3ns for 40MHz and 50MHz 7 When using the Reduced Frequency feature the minimum allowed internal CPU speed is 0 5 MHz 8 For the 50MHz version 1x Clock Mode and half frequencybus mode only 5 5 21 IDT79R3081 RISController DC ELECTRICAL CHARACTERISTICS R3081 MILITARY TEMPERATURE RANGE Tc 55 C to 125 C VCC 5 0V 10 MILITARY AND COMMERCIAL TEMPERATURE RANGES
38. ing point accelerator features low latency operations and autonomous functional units which allow differing types of floating point operations to function concurrently with integer operations The R3010A appears to the software programmer as a simple extension of the integer execution unit with 16 dedicated 64 bit floating pointregisters software references these as 32 32 bit registers when performing loads or stores Figure 5 illustrates the functional block diagram of the on chip FPA Clock Generator Unit The R3081 is driven from a single input clock which can be either atthe processor rated speed or at twice that speed On chip the clock generator unit is responsible for managing the interaction of the CPU core caches and bus interface The R3081 includes an on chip clock doubler to provide higher frequency signals to the internal execution core if 1x clock mode is selected the clock doubler will internally convert it to IDT79R3081 RISController a double frequency clock The 2x clock mode is provided for compatiblity withthe R3051 The clock generator unitreplaces the external delay line required in R3000A based applications Instruction Cache The R3081 implements a 16kB Instruction Cache The system may choose to repartition the on chip caches so that the instruction cache is reduced to 8kB but the data cache is increased to 8kB The instruction cache is organized with a line size of 16bytes four entries This large cache a
39. lock Period 25 250 20 250 ns 123 Reset Pulse Width from Vcc valid 200 200 us 124 Reset Minimum Pulse Width 32 32 tsys 125 Reset Set up to SysCik falling 6 5 ns 126 Int Mode set up to Reset rising 10 9 ns 127 Int Mode hold from Reset rising 0 0 ns 128 Sint SBrCond Set up to SysClk falling 6 5 ns 129 Sint SBrCond Hold from SysClk falling 3 3 ns 130 Int BrCond Set up to SysClk falling 6 5 ns 131 Tnt BrCond Hold from SysClk falling 3 3 ns tsys SysClk full frequency mode Pulse Width 5 2422 2422 2422 2422 ns 132 SysCIk full frequency mode Clock HIGH Time 122 2 12242 122 2 12242 ns NOTES 2889 tbl 10 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2 The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition 5 In 1x clock mode t22 is replaced by t44 2 6 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 3ns for 40MHz and 50MHz 7 When using the Reduced Frequency feature the minimum allowed internal CPU speed is 0 5 MHz 17 IDT79R3081 RISCo
40. me multiplexed during writes Cached During the address phase of write transactions this signal is an active high output which indicates that the store data was retained in the on chip data cache Reserved The value of this pin during the data phase of writes is reserved Diag 0 Diagnostic Pin 0 This output distinguishes cache misses due to instruction references from those due to data references and presents the remaining bit of the miss address The value output on this pin is also time multiplexed VD If the Cached Pin indicates a cache miss then a high on this pin at this time indicates an instruction reference and a low indicates a data reference lfthe read is not due to a cache miss but rather an uncached reference then this pin is undefined during this phase Miss Address 2 During the remainder of the read operation this output presents address bit 2 of the address the processor was attempting to reference when the cache miss occurred Regardless of whether a cache miss is being processed this pin reports the transfer address during this time During write cycles the value of this pin during both the address and data phases is reserved 2889 tbl 02 5 5 9 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Continued PIN NAME VO DESCRIPTION ALE 1 0 Address Latch Enable Used to indicate that the A D bus contains valid addres
41. n Min Max Min Max Unit t18 A D Tri state from SysClk falling 9 8 ns t19 A D SysClk falling to data valid 11 10 ns t20 ClkIn 2x clock mode Pulse Width HIGH 6 5 5 6 ns t21 ClkIn 2x clock mode Pulse Width LOW 6 5 5 6 ns t22 ClkIn 2x clock mode Clock Period 15 250 12 5 250 ns 123 Reset Pulse Width from Vcc valid 200 200 us 124 Reset Minimum Pulse Width 32 32 tsys 125 Reset Set up to SysClk falling 4 3 ns 126 Int Mode set up to Reset rising 8 7 ns 127 Int Mode hold from Reset rising 0 0 ns 128 Slnt SBrCond Set up to SysClk falling 4 3 ns 129 Sint SBrCond Hold from SysClk falling 2 2 ns 130 Int BrCond Set up to SysClk falling 4 3 ns 131 Int BrCond Hold from SysCIk falling 2 2 ns tsys SysClk full frequency mode Pulse Width 2422 2422 2422 2422 ns 132 SysCIk full frequency mode Clock High Time 122 1 12241 122 1 12241 ns 133 SysClk full frequency mode Clock LOW Time 5 122 1 122 1 122 1 12241 ns tsys 2 SysCik half frequency mode Pulse Width 4 t22 4 122 4 122 4 122 4 122 ns t34 SysCik half frequency mode Clock HIGH Time 2 122 1 22241 222 1 22241 ns 185 SysCK half frequency mode Clock LOW Time 2 t22 1 2 19241 222 1 2 t2241 ns 136 ALESet up to SysCIk falling 7 6 ns 137 ALEHold from SysClk falling 1 1 ns 138 A DSet up to ALE falling 8 8 ns 139 A DHold from ALE falling 1 1 ns 140 WrSet up t
42. ne VIRTUAL PHYSICAL Oxffffffff Kernel Mapped kseg2 Any 0xc0000000 Kernel Uncached kseg1 0xa0000000 Monee 3548MB Kernel Cached kseg0 0x80000000 User Mapped Cacheable Any kuseg Memory 512 MB 0x00000000 2889 drw 03 Figure 3 Virtual to Physical Mapping of Extended Architecture Versions VIRTUAL PHYSICAL Ox 1MB Kernel Rsvd Kernel Cached Kernel Cacheable 1024 MB kseg2 Tasks 0xc0000000 Kernel Uncached kseg1 0xa0000000 A ch ernel User Ge SE Cacheable 2048 MB 0x80000000 Tasks 1MB User Rsvd User i Cached Inaccessible 512 MB kuseg Kernel Boot 0x00000000 and I O 512 MB 2889 drw 04 Figure 4 Virtual to Physical Mapping of Base Architecture Versions 5 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES The extended architecture versions of the R3051 family the R3051E R3052E and R3081 E allow the system designer to implement kernel software which dynamically manages user task utilization of system resources and also allows the Kernel to protect certain resources from user tasks These capabilities are important in general computing applications such as ARC computers and are also important in a variety of embedded applications from process control where protection may be important to X Window display systems where virtual memory management can be used The MMU can also be used to simplify system debug R3051 family base versions the R3051 R3052 and R3081 remove the TLB an
43. ntroller MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS R3081 cont COMMERCIAL TEMPERATURE RANGE 20 25MHz Tc 0 C to 85 C Vcc 5 0V 5 20MHz 25MHz Symbol Signals Description Min Max Min Max Unit 133 SysCik full frequency mode Clock LOW Time 122 2 122 2 122 2 122 2 ns tsys 2 SysCIk half frequency mode Pulse Width 5 4 122 4 122 4 122 4 122 ns 134 SysClk half frequency mode Clock HIGH Time 222 2 2 t22 2 2422 222242 ns 135 SysCIk half frequency mode Clock LOW Time 2122 2 2 22 2 222 2 2 t2242 ns 136 ALE Set up to SysCik falling 9 8 ns 137 ALE Hold from SysCIk falling 2 2 ns 138 A D Set up to ALE falling 10 9 ns t39 A D Hold from ALE falling 2 2 ns 140 Wr Set up to SysClk rising 10 9 ns 141 Wr Hold from SysClk rising 3 3 ns 142 Cikin 1x clock mode Pulse Width HIGH S 20 16 ns 143 Cikin 1x clock mode Pulse Width LOW 6 20 16 ns 144 ClkIn 1x clock mode Clock Period 8 50 50 40 50 ns tderate All outputs Timing deration for loading 1 1 ns over CLp 8 4 25pF NOTES 2889 tbl 11 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2 The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 3 Guaranteed by design 4 This parameter is used to derat
44. o SysClk rising 8 7 ns 141 WrHold from SysCIk rising 3 3 ns 142 Cikin 1x clock mode Pulse Width HIGH 6 13 11 6 ns 143 ClkIn 1x clock mode Pulse Width LOW 13 11 6 ns 144 ClkIn 1x clock mode Clock Period 8 30 50 25 50 ns tderate All outputs Timing deration for loading 1 1 ns over Col 4 25pF NOTES 2889 tbl 11 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 2 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition a In 1x clock mode t22 is replaced by t44 2 6 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 5 5 15 IDT79R3081 RISController DC ELECTRICAL CHARACTERISTICS R3081 COMMERCIAL TEMPERATURE RANGE Tc 0 C to 85 C Vcc 5 0V 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES 20MHz 25MHz 33 33MHz 40MHz 50MHZ Symbol Parameter Test Conditions Min Mas Min Max Min Max Min Max Min Max Units Von Output HIGH Voltage Vcc Min
45. oO 3 gt gt 7 Z d 2 d d gt gt Z d d d d d gt gt eee 8 x R 2 JeonJMASs ng E PPY z 4ppy 20A SSA 1 6e1g beypni 0 6e1g 31 Py Oo 3 a M 9 S ugejeq 3 gt 2 20A So E a SSA 3 MIOSAS Juosng Iso Jougsng yoy u3opy baysng Q UOII amp V o puonug BI SZ Seck SZ SS SSES SS BB OS SS SE IS SS 5 5 5 r e e e Ve SBrCond SBrCond 24 5 5 Reserved Pins must not be connected NOTE MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS IDT79R3081 RISController T O in a IN N St ES I T tia E DAD MO E E NT 4 00 10 000 Sr SR ODI a GG YOGA gt gt IT i d d d d gt gt s d d d z gt gt T Y on JEONIMWISIDg eMppy z ppy 29A SSA 1 6e1g beaypa 0 6eig ER Py IM DS e geg a o 99 3 SSA HOSA qugsng 19594 10153 SNE EE USO PH beysng Ra a Y 0 puoog N x 8 8 5cecelgpesgseeeepee ao 8 8 SEKR SES r GC GC GC 8 SBrCond SBrCond 25 5 5 Reserved
46. ociative Translation Lookaside Buffer TLB The cache on the R3081E is user configurable to an 8kB Instruction Cache and 8kB Data Cache The R3081 which incorporates a 16kB instruction cache a 4kB data cache but uses the simpler memory mapping of the R3051 52 and thus omits the TLB The cache on the R3081 is user configurable to an 8kB Instruction Cache and 8kB Data Cache Figure 1 shows a block level representation of the functional units within the R3081E The R3081E could be viewed as the embodiment of a discrete solution built around the R3000A and R3010A However by integrating this functionality on a single chip dramatic cost and power reductions are achieved CPU Core The CPU core is a full 32 bit RISC integer execution engine capable of sustaining close to single cycle execution The CPU core contains a five stage pipeline and 32 orthogonal 32 bit registers The R3081 uses the same basic integer execution core as the entire R3051 family which is the R3000A implementation ofthe MIPS instruction set Thus the R3081 family is binary compatible with the R3051 R3052 R3000A R3001 and R3500 CPUs In addition the R4000 represents an upwardly software compatible migration path to still higher levels of performance The execution engine in the R3081 uses a five stage pipeline to achieve near single cycle instruction execution rates A new instruction can be initiated in each clock cycle the execution engine actually processe
47. on for loading 1 1 ns over CLp 8 4 25pF NOTES 2889 tbl 11 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2 The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified Noa test condition that is the deration factor is applied for each 25pF over the specified test load condition In 1x clock mode t22 is replaced by t44 2 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns Case Temperatures are instant on 5 5 23 atti det IA EN pe MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS IDT79R3081 RISController ZE E E ses E 0 ees 8 gg ao a oo 2 go oo oo oo gg OO
48. ous cache sizes and the hardware floating point can be accurately modeled using Cache 3051 Since the R3041 R3051 R3052 R3071 and R3081 are all pin and software compatible the system designer has maximum freedom in trading between performance and cost A system can be designed and later the appropriate CPU inserted into the board depending on the desired system performance SELECTABLE FEATURES The R3081 allows the system designer to configure certain aspects of operation Some of these options are established when the device is reset while others are enabled via the Config registers BigEndian vs LittleEndian Byte Ordering The part can be configured to operate with either byte ordering ACE ARC systems typically use Little Endian byte ordering However various embedded applications written originally for a Big Endian processor such as the MC680x0 are easier to port to a Big Endian system Data Cache Refill of one or four words The memory system must be capable of performing four word refills of instruction cache misses The R3081 allows the system designer to enable D Cache refill of one or four words dynamically Thus specialized algorithms can choose one refill size while the rest of the system can operate with the other Half frequency bus mode The processor can be configured such that the external bus interface is at one half the frequency of the processor core This simplifies system design however the large on c
49. ower consumption IDT79R3081 RISController OCA Airflow ft min 0 200 400 600 800 1000 MJ Package 22 14 12 11 9 8 PLCC Package 29 26 21 18 16 15 2889 tbl 01 Table 1 Thermal Resistance ca at Various Airflows estimated final values tbd NOTES ON SYSTEM DESIGN The R3081 has been designed to simplify the task of high speed system design Thus set up and hold time requirements have been kept to a minimum allowing a wide variety of system interface strategies To minimize these AC parameters the R3081 employs feedback from its SysClk output to the internal bus interface unit This allows the R3081 to reference input signals to the reference clock seen by the external system The SysCIk output is designed to provide relatively large AC drive to MILITARY AND COMMERCIAL TEMPERATURE RANGES minimize skew due to slow rise or fall times A typical part will have less than 2ns rise or fall 10 to 90 signal times when driving the test load Therefore the system designer should use care when designing for direct SysClk use Total loading due to devices connected on the signal net and the routing of the net itself should be minimized to ensure the SysClk output has a smooth and rapid transition Long rise and or fall times may cause a degradation in the speed capability of an individual device Similarly the R3081 employs feedback on its ALE output to ensure adequate address
50. rocessor stalls due to data write operations the bus interface unit incorporates a 4 deep write buffer which captures address and data at the processor execution rate allowing it to be retired to main memory at a much slower rate without impacting system performance Further support has been provided to allow hardware based data cache coherency in a multi master environment such as one utilizing DMA from I O to memory The data cache is parity protected over the data and tag fields Parity is generated by the read buffer during cache refill during cache references the parity is checked and inthe case of a parity error a cache miss is processed Bus Interface Unit The R3081 uses its large internal caches to provide the majority of the bandwidth requirements of the execution engine and thus can utilize a simple bus interface connected to slower memory devices Alternately a high performance low cost secondary cache can be implemented allowing the processor to increase performance in systems where bus bandwidth is a performance limitation As part of the R3051 family the R3081 bus interface utilizes a 32 bit address and data bus multiplexed onto a single set of pins The bus interface unit also provides an ALE Address Latch Enable output signal to de multiplex the A D bus and ei lt Data Bus e 83 Instructions Operands Register Unit 16 X 64 Exponent Part Fr
51. s five instructions concurrently in various pipeline stages Figure 2 shows the concurrency achieved in the R3081 execution pipeline System Control Co Processor The R3081 family also integrates on chip the System Control Co processor CPO CPO manages both the exception handling capability of the R3081 as well as the virtual to physical address mapping As with the R3051 and R3052 the R3081 offers two versions of memory management and virtual to physical address mapping the extended architecture versions the R3051E R3052E and R3081E incorporate the same MMU as the R3000A These versions contain a fully associative 64 entry TLB which maps 4kB virtual pages into the physical address space The virtual to physical mapping thus includes kernel segments which are hard mapped to physical addresses and kernel and user segments which are mapped page by page by the TLB into anywhere in the 4GB physical address space In this TLB 8 pages can be locked by the kernel to insure deterministic response in real time applications Figure 3 illustrates the virtual to physical mapping found in the R3081E IDT79R3081 RISController 1 IF RD ALU MEM WB al IF RD ALU MEM WB al IF RD ALU MEM WB l 4 IF RD ALU MEM WB 5 IF RD ALU MEM WB Current CPU Cycle 2889 drw 02 Figure 2 R3081 5 Stage Pipeli
52. s information for the bus transaction This signal is used by external logic to capture the address for the transfer typically using transparent latches During cache coherency operations the R3081 monitors ALE at the start of a DMA write to capture the write target address for potential data cache invalidates Read An output which indicates that the current bus transaction is a read 1 0 Write An output which indicates that the current bus transaction is a write During coherent DMA this input indicates that the current transfer is a write DataEn External Data Enable This signal indicates that the A D bus is no longer being driven by the processor during read cycles and thus the external memory system may enable the drivers ofthe memory system onto this bus without having a bus conflict occur During write cycles or when no bus transaction is occurring this signal is negated thus disabling the external memory drivers Burst WrNear Burst Transfer Write Near On read transactions the Burst signal indicates that the current bus read is requesting a block of four contiguous words from memory This signal is asserted only in read cycles due to cache misses it is asserted for all l Cache miss read cycles and for D Cache miss read cycles if quad word refill is currently selected On write transactions the WrNear output tells the external memory system that the bus interface unit is performing back to back write tr
53. sReq has been detected and that the bus is relinquished to the external master IvdReg Invalidate Request An input provided by an external DMA controller to request that the CPU invalidate the Data Cache line corresponding to the current DMA write target address This signal is the same pin as Diag 0 CohReq Coherent DMA Request An input used by the external DMA controller to indicate that the requested DMA operations could involve hardware cache coherency This signal is the Rsvd 0 of the R3051 SBrCond 3 2 BrCond 0 Branch Condition Port These external signals are internally connected to the CPU signals CpCond 3 0 These signals can be used by the branch on co processor condition instructions as input ports There are two types of Branch Condition inputs the SBrCond inputs have special internal logic to synchronize the inputs and thus may be driven by asynchronous agents The direct Branch Condition inputs must be driven synchronously Note that BrCond 1 is used by the internal FPA and thus is not available on an external pin BusError Bus Error Input to the bus interface unit to terminate a bus transaction due to an external bus error This signal is only sampled during read and write operations If the bus transaction is a read operation then the CPU will take a bus error exception 2889 tbl 03 5 5 10 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION
54. ser Printer System Support Chips 2889 drw 07 Figure 7 R3051 Family Development Toolchain 5 5 6 1DT79R3081 RISController many general purpose computing applications such as ARC compliant systems Autonomous multiply and divide operations The R3051 family features an on chip integer multiplier divide unit which is separate from the other ALU This allows the CPU to perform multiply or divide operations in parallel with other integer operations using a single multiply or divide instruction rather than step operations Integrated write buffer The R3081 features a four deep write buffer which captures store target addresses and data at the processor execution rate and retires it to main memory at the slower main memory access rate Use of on chip write buffers eliminates the need for the processor to stall when performing store operations Burstread support The R3051 family enables the system designer to utilize page mode or nibble mode RAMs when performing read operations to minimize the main memory read penalty and increase the effective cache hit rates These techniques combine to allow the processor to achieve over 43 VUPS integer performance 13MFlops of Linpack performance and 70 000 dhrystones without the use of external caches or zero wait state memory devices The performance differences between the various family members depends on the application software and the design of the memory system The impact of the vari
55. ses of project development These tools allow timely parallel development of hardware and software for R3051 family applications and include tools such as e Optimizing compilers from MIPS the acknowledged leader in optimizing compiler technology e Cross development tools available in a variety of development environments e The IDT Evaluation Board which includes RAM EPROM I O and the IDT PROM Monitor lt IDT sim which implements a full prom monitor diagnostics remote debug support peek poke etc e IDT kit which implements a run time support package for R3051 family systems PERFORMANCE OVERVIEW The R3081 achieves a very high level of performance This performance is based on lt An efficient execution engine The CPU performs ALU operations and store operations in a single cycle and has an effective load time of 1 3 cycles and branch execution rate of 1 5 cycles based on the ability of the compilers to avoid software interlocks Thus the execution engine achieves over 35 VUPS performance when operating out of cache lt Afullfeatured floating point accelerator co processor The R3081 incorporates an R3010A compatible floating pointaccelerator on chip with independent ALUs for floating point add multiply and divide The floating point unit is fully hardware interlocked and features overlapped operation and precise exceptions The FPA allows floating point adds multiplies and divides to occur
56. sing 5 ns 18 ALE Asserted from SysClk rising 4 ns 19 ALE Negated from SysClk falling 4 ns t10 AID Hold from ALE negated 1 5 ns t11 DataEn Asserted from SysClk falling 15 ns t12 DataEn Asserted from A D tri state 0 ns t14 AID Driven from SysCik rising 9 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysClk falling 6 ns t16 Addr 3 2 Valid from SysCik 6 ns t17 Diag Valid from SysCIk 11 ns t18 A D Tri state from SysClk falling 10 ns t19 A D SysCIk falling to data valid 12 ns t20 ClkIn 2x clock mode Pulse Width HIGH N A 8 ns 121 Cikin 2x clock mode Pulse Width LOW N A 8 ns 122 ClkIn 2x clock mode Clock Period N A 7 8 ns 123 Reset Pulse Width from Vcc valid 200 us 124 Reset Minimum Pulse Width 32 tsys 125 Reset Set up to SysClk falling 5 ns 126 Int Mode set up to Reset rising 9 ns 127 Int Mode hold from Reset rising 0 ns 128 Sint SBrCond Set up to SysClk falling 5 ns 129 Sint SBrCond Hold from SysClk falling 3 ns 130 Int BrCond Set up to SysClk falling 5 ns 131 Tnt BrCond Hold from SysClk falling 3 ns tsys SysCik full frequency mode Pulse Width N A 8 N A 8 ns 132 SysCIk full frequency mode Clock HIGH Time N A 8 N A 8 ns 133 SysClk full frequency mode Clock LOW Time N A 8 N A 8 ns NOTES 2889 tbl 1 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time 2 The AC values listed here r
57. usReq Ack BusError Set up to SysClk rising 4 3 ns RdCEn CohReq3 tla A D Set up to SysClk falling 5 4 5 ns t2 BusReq Ack BusError Hold from SysClk rising 3 3 ns RdCEn CohReq t2a AID Hold from SysCik falling 1 1 ns 13 A D Addr Diag ALE Wr Tri state from SysClk rising 10 10 ns Burst WrNear Rd DataEn t4 A D Addr Diag ALE Wr Driven from SysClk falling 10 10 ns Burst WrNear Rd DataEn 15 BusGnt Asserted from SysClk rising 6 5 ns t6 BusGnt Negated from SysClk falling 6 5 ns t7 Wr Rd Burst WrNear A D Valid from SysCIk rising 4 3 5 ns 18 ALE Asserted from SysClk rising 3 3 ns t9 ALE Negated from SysClk falling 3 3 ns t10 AID Hold from ALE negated 3 1 5 1 5 ns t11 DataEn Asserted from SysClk falling 13 12 ns t12 DataEn Asserted from A D tri state 0 0 ns t14 A D Driven from SysCIk rising 0 0 ns t15 Wr Rd DataEn Burst WrNear Negated from SysCIk falling 5 4 ns t16 Addr 3 2 Valid from SysCIk 5 4 5 ns t17 Diag Valid from SysClk 10 9 ns 5 5 14 IDT79R3081 RISController AC ELECTRICAL CHARACTERISTICS RV3081 cont COMMERCIAL TEMPERATURE RANGE 2 Tc 0 C to 85 C VCC 3 3V 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES 33MHz 40MHz Symbol Signals Descriptio
58. y mode Clock HIGH Time 222 2 212242 2122 2 2 122 2 ns 185 SysCik half frequency mode Clock LOW Time 5 222 2 212242 2 t02 2 242242 ns 136 ALESet up to SysClk falling 9 8 ns 137 ALEHold from SysClk falling 2 2 ns 138 A DSet up to ALE falling 10 9 ns 139 A DHold from ALE falling 2 2 ns 140 WrSet up to SysClk rising 10 9 ns 141 WrHold from SysCIk rising 3 3 ns t42 Cikin 1x clock mode Pulse Width HIGH 20 16 ns t43 Cikin 1x clock mode Pulse Width LOW 8 20 16 ns 144 ClkIn 1x clock mode Clock Period 8 50 50 40 50 ns tderate All outputs Timing deration for loading 1 1 ns over Cip 4 25pF NOTES 2889 tbl 11 1 All timings referenced to 1 5V All timings measured with respect to a 2 5ns rise and fall time The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User s Manual 2 3 Guaranteed by design 4 This parameter is used to derate the AC timings according to the loading of the system This parameter provides a deration for loads over the specified test condition that is the deration factor is applied for each 25pF over the specified test load condition on In 1x clock mode t22 is replaced by t44 2 In 1x clock mode the design guarantees that the input clock rise and fall times can be as long as 5ns 5 5 13 IDT79R3081 RISController DC ELECTRICAL CHARACTERISTICS RV3081 COMMERCIAL TEMPERATURE RANGE 2
59. ypical system implementation Transparent latches are used to de multiplex the R3081 address and data busses from the A D bus The data paths between the memory system elements and the A D bus is managed by simple octal devices A small set of simple PALs is used to control the various data path elements and to control the handshake between the memory devices and the CPU Depending onthe costvs performance tradeoffs appropriate 5 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES to a given application the system design engineer could include true burst support from the DRAM to provide for high performance cache miss processing or utilize a simpler lower performance memory system to reduce cost and simplify the design Similarly the system designer could choose to implement techniques such as external secondary cache or DMA to further improve system performance DEVELOPMENT SUPPORT The IDT R3051 family is supported by a rich set of development tools ranging from system simulation tools through PROM monitor and debug support applications software and utility libraries logic analysis tools sub system modules and shrink wrap operating systems The R3081 which is pin and software compatible with the R3051 can directly utilize these existing tools to reduce time to market Figure 7 is an overview of the system development process typically used when developing R3051 family applications The R3051 family is supported in all pha

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