hynix HMS77C1000A/HMS77C1001A 8-BIT SINGLE-CHIP MICROCONTROLLERS User Manual (Ver. 2.0)
Contents
1. represents mean 36 and mean 30 respectively where is standard deviation Normal Operation Ipp VpD Ta 25 C fxin 20MHz loL VoL Vpp 3V loL mA 18 0 VoL 04 08 12 16 2 0 V Oct 2001 Ver 2 0 loH VoH Vpp 5V mA 20 16 12 8 4 Vpp VoH 0 5 10 15 20 V Typical RC Oscillator Fosc Frequency vs VDD Cext 0pF Ta 25 C Typical RC Oscillator Fosc Frequency vs VDD MHz 2 00 Cext 100pF B 3 3K Ta 25 C 1 75 1 50 1 25 R 5K 1 00 0 75 ae 0 50 Ha R 100K Vpp Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A lou VoH Vpp 3V loH mA 8 6 4 2 0 Vpp VoH 0 5 1 0 15 V Typical RC Oscillator Fosc Frequency vs Vpp MHz Gext 20pF 4 5 Taz25T 40 R 3 3K 3 5 R 5K 3 0 25 29 R 15K 1 5 1 0 0 5 R 100K 0 Vpp 25 3 35 4 45 5 55 6 V Typical RC Oscillator Fosc Frequency vs VDD MHz 0 8 Cext 300pF 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 E ZA Nbp 25 3 35 4 45 5 55 6 15 HMS77C1000A HMS77C1001A 16 Average Cext Rext Fosc 5V 25 C 3 3K 6 5MHz 5K 5 4MHz OpF 15K 2 3MHz 100K 400KHz 3 3K 4 3M2. amp e Control Control Unit E Signals e e jip ALU Status ALU FIGURE 8 1 HMS700 CPU BLOCK DIAGRAM Oct 2001 Ver 2 0 Data Bus Data Memory Bus 17 HMS77C1000A HMS77C1001A 9 MEMORY The HMS77C100XA has separate memory maps for pro gram memory and data memory Program memory can only be read not written to It can be up to 1K words of program memory Data memory can be read and written to 32 bytes including special function registers 9 1 Program Memory The program memory is organized as 0 5K 12 bit wide words HMS77C1000A and 1K 12 bit wide words HMS77C1001A The program memory words are addressed sequentially by a program counter Increment ing at location 1IFFH HMS77C1000A or 3FFH HMS77C1001A will cause a wrap around to 000g Figure 9 1 and Figure 9 2 show a map of program memo ry After reset CPU begins execution from reset vector which is stored in address 1FFH HMS77C1000A 3FFH HMS77C1001A Stack Level 1 PC lt 9 0 gt Stack Level 1 Stack Level 2 0004 On chip OFFH Program 100H Memory Page 0 gt o 1FFH 8 2004 28 oo o On chip 2 2FFH Program 3004 Memory Page 1 Ag 3FFH Reset Vector PC lt 8 0 gt Stack Level 2 000H a E On chip o 8 OFFH Program 28 100 Memory go 2 1FFH Reset Vector FIGURE 9 2 HMS77C1001A PROGRAM MEMORY MAP AND STACK 9 2 Data Memory Th
3. 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero R W R R R W ro to roza ooo DC Digit carry borrow bit C Carry borrow bit ADDRESS 03H RESET VALUE 0001 1XXX R Readable bit bitO W Writable bit R W R W for addition and subtraction addition 1 A carry from the 4th low order bit of the result occurred 0 A carry from the 4th low order bit of the result did not occur subtraction 1 A borrow from the 4th low order bit of the result did not occur 0 A borrow from the 4th low order bit of the result occurred for additon subtraction and rotation addition 1 A carry occurred 0 A carry did not occur subtraction 1 A borrow did not occur 0 A borrow occurred rotation Load bit with LSB or MSB respectively FIGURE 9 8 STATUS REGISTER Oct 2001 Ver 2 0 21 HMS77C1000A HMS77C1001A 9 3 6 FSR Register The FSR register is an 8 bit register The lower 5 bits are used to store indirect address for data memory The upper 3 bits are unimplemented and read as 0 Figure 9 9 shows how the FSR register can be used in indirect ad dressing mode In reset state the FSR register is initialized with IXXX XXXXp Instruction Word 11 54 0 8 et Direct Addressing mode Data Memory Address 4 feel ile 3 0 Address 04H RESET Value 1XXX XXXXp Indirect Addressi
4. 9 3 5 STATUS Register This register contains the arithmetic status of the ALU the HMS77C1000A HMS77C1001A RESET status and the page select bit for program memo ries larger than 512 words The STATUS register can be the destination for any in struction as with any other register If the STATUS regis ter is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable There fore the result of an instruction with the STATUS register as destination may be different than intended It is recommended that only instructions that do not affect status of CPU be used on STATUS register Care should be exercised when writing to the STATUS register as the ALU status bits are updated upon completion of the write operation possibly leaving the STATUS register with a re sult that is different than intended In reset state the STA TUS register is initialized with 00011 XXXp bit7 PAO Program memory page select bits 0 page O 000h 1FFh HMS77C1000A 1001A 1 page 1 200h 3FFh HMS77C1001A TO Time overflow bit 1 After power up watchdog clear instruction or entering power down mode 0 2 A watchdog timer time overflow occurred PD Power down bit 1 After power up or by the watchdog clear instruction 0 By execution of power down mode Z Zero bit
5. FIGURE 9 10 OPTION REGISTER Oct 2001 Ver 2 0 23 HMS77C1000A HMS77C1001A 10 1 0 PORTS The HMS77C100XA has a 4 bit I O port RA and a 8 bit VO port RB All pin have data RA RB and direction TRISA TRISB registers which can assign these ports as output or input A 0 in the port direction registers configure the corre sponding port pin as output Conversely write 1 to the corresponding bit to specify it as input pin Hi Z state For example to use the even numbered bit of RB as output ports and the odd numbered bits as input ports write 55 to TRISB register during initial setting as shown in Figure 10 1 All the port direction registers in the HMS77C100XA have 1 written to them by reset function This causes all port as input Write 55H to port RB direction register 7 6 5 4 3 2 1 0 TRISB 0 1 0 1 0 1 0 1 Y N Jour in four in PORT RB Purjin four FIGURE 10 1 EXAMPLE OF PORT I O ASSIGNMENT 10 1 Port RA RA is a 4 bit I O register Each I O pin can independently used as an input or an output through the port direction reg ister TRISA A 0 in the TRISA register configure the corresponding port pin as output Conversely write 1 to the corresponding bit to specify it as input pin Bits 7 4 are unimplemented and read as 0 s RA Data Register ADDRESS 05H 3 2 4 RESET VALUE Undefined RA RAS RA2 RA RAO RA Direction Re
6. HMS77C1000A HMS77C1001A 4 PACKAGE DIAGRAM 18 PDIP unit inch MAX MIN Bag KE es e E DS jes e EA pai EB O TYP 0 300 HUE DEAN 0 925 0 895 0 270 0 245 in E3 0 022 EN a a y 9908 0 15 E 020 MAX 0 180 0 140 0 120 0 015 0 065 TYP 0 10 0 045 18 SOP HHH HH O DIN ojo Oo o T O0 NA xx ojo ojo H l H H H mA l H v wo 0 014 nje 0 040 TYP 0 050 JE oo 4 Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A 20 SSOP unit inch a MAX MIN O N 10 je jo o NIN aa ojo ojo oos oo Oct 2001 Ver 2 0 5 HMS77C1000A HMS77C1001A 5 PIN FUNCTION Vpp Supply voltage Vss Circuit ground RESET Reset the MCU Xin Input to the inverting oscillator amplifier and input to the internal main clock operating circuit Xour Output from the inverting oscillator amplifier RA pins can be used as outputs or inputs according to 0 or 1 written the their Port Direction Register TRISA RB0 RB7 RB is a 8 bit CMOS bidirectional I O port
7. RB pins can be used as outputs or inputs according to O or 1 written the their Port Direction Register TRISB ECO ECO is an external clock input to TimerO It should be tied to Vss or Vpp if not in use to reduce current con RA0 RA3 RA is an 4 bit CMOS bidirectional I O port sumption DIP SOP SSOP Input PIN NAME Pin No Pin No In Out Levels Function VDD 14 15 16 P Supply voltage Vss 5 5 6 P Circuit ground Reset signal input programming voltage input This pin is an active low RESET 4 4 I ST reset to the device Voltage on the RESET pin must not exceed Vpp to avoid unintended entering of programming mode XIN 16 18 I ST Oscillator crystal input external clock source input Oscillator crystal output Connects to crystal or resonator in crystal oscilla XOUT 15 17 O tor mode In RC mode Xour pin outputs CLKOUT which has 1 4 the fre quency of Xin and denotes the instruction cycle rate RAO 17 19 10 TTL RA1 18 20 10 TTL 4 bit bi directional I O ports RA2 1 1 O TTL RA3 2 2 O TTL RBO 6 7 O TTL RB1 7 8 10 TTL RB2 8 9 O TTL RBS 9 10 O TTL 8 bit bi directional I O ports RB4 10 11 O TTL RB5 11 12 O TTL RB6 12 13 10 TTL RB7 13 14 O TTL ECO 3 3 ST Clock input to mera Must be tied to Vpp or Vss if not in use to reduce current consumption TABLE 5 1 PINOUT DESCRIPTION Legend input O output I
8. These parameters are for design guidance only and are not tested 2 This parameter is characterized but not tested 3 The test conditions for all Ibp measurements in NOP execution are Xin external square wave all VO pins tristated pulled to Vss ECO Vpp RESET Vpp WDT disabled enabled as specified 4 Does not include current through Rex The current through the resistor can be estimated by the formula IR Vpp 2Rext mA 5 Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to Vpp and Vss as like measurement conditions of supply current 10 Oct 2001 Ver 2 0 7 4 DC Electrical Characteristics 2 Ta 40 C 85 C HMS77C1000A HMS77C1001A Specification Parameter Symbol Test Condition Unit Min Typ Max Input High Voltage VO Ports TTL 0 25Vpp 0 8 RESET ECO ST Vu 0 85Vpp VDD V XiN ST RC only 0 85Vpp Xin ST XT HF LF 0 7Vpp Input Low Voltage VO Ports TTL 0 15Vpp RESET ECO ST Vu Vss 0 15Vpp V Xin ST RC only 0 15Vpp XiN ST XT HF LF 0 3Vpp cnn us m Input Leakage Current Vin Vpp or Vss Xin ST IL XT HF LF 3 0 0 5 3 0 uA Other Pins 1 0 0 2 1 0 Output High Voltage 1 0 Ports VoH loH 5 0mA Vpp 4 5V Vpp 0 9 VDD V XOUT lon 0 5mA Vpp 4 5V RC osc Output Low Voltage 1 0 Ports VoL lot 8 0mA Vpp 4 5V Vss 0 8 V XOUT lo 0 6mA Vpp 4 5V RC osc 1 Data in Ty
9. other reset Most other registers are reset to a reset state on Power On Reset POR PFDR RESET or WDT reset A RESET or WDT wake up from SLEEP also results in a device reset and not a continuation of operation before SLEEP The TO and PD bits STATUS lt 4 3 gt are set or cleared depending on the different reset conditions These bits may be used to determine the nature of the reset HMS77C1000A HMS77C1001A Table 14 2 lists a full description of reset states of all reg isters Figure 14 1 shows a simplified block diagram of the on chip reset circuit Condition PCL STATUS one Addr 024 Addr 03H Power On Reset 1111 1111 0001 1xxx RESET PFD SET reset or a sl reset normal operation RESET wake up or PFD reset from SLEEP 1111 1111 0001 Ouuu WDT reset normal 5 operation 1111 1111 0000 uuuu WDT vvake up from psa anos SLEEP TABLE 14 1 RESET CONDITIONS FOR SPECIAL REGISTERS 1 TO and PD bits retain their last value until one of the other reset conditions occur NS paa 2 The CLRWDT instruction will set the TO and PD bits Legend x unknown u unchanged Register Address PReset Reset WDT Reset VV NJA XXXX XXXX uuuu uuuu uuuu uuuu TRIS N A 1111 1111 1111 1111 1111 1111 OPTION N A 0011 1111 0011 1111 0011 1111 INDF 00H XXXX XXXX uuuu uuuu uuuu uuuu TMRO 01H XXXX XXXX uuuu uuuu uuuu uuuu
10. 4 3MHz 5K 3 5MHz 20pF 15K 1 4MHz 100K 240KHz 3 3K 1 8MHz 5K 1 5MHz TOOK 15K 610KHz 100K 100KHz 3 3K 780KHz 5K 630KHz 300pF 15K 260KHz 100K 42 5KHz TABLE 13 3 RC OSCILLATION FREQUENCIES 32 NUMIX The Electrical Specifications sections show R frequency variation from part to part due to normal process variation Also see the Electrical Specifications sections for variation of os cillator frequency due to VDD for given Rext Cext values as well as frequency variation due to operating temperature for given R C and VDD values The oscillator frequency divided by 4 is available on the Xour pin and can be used for test purposes or to synchro nize other logic VDD XIN Internal 1 1 gt Clock N Cext FIGURE 13 3 RC OSCILLATION MODE Oct 2001 Ver 2 0 14 RESET HMS77C100XA devices may be reset in one of the follow ing ways Power On Reset POR Power Fail detect reset PFDR RESET normal operation RESET wake up reset from SLEEP WDT reset normal operation WDT wake up reset from SLEEP Each one of these reset conditions causes the program counter to branch to reset vector address HMS77C1000A is 1FFy and HMS77C1001A is 3FFy Table 14 1 shows these reset conditions for the PCL and STATUS registers Some registers are not affected in any reset condition Their status is unknown on POR and unchanged in any
11. OSC ripple counter 8 clear 8 to 1 MUX PS2 PSO A S O ns a PSA To TMRO 0 1 MUX PSA WDTE Y SLEEP clearing WDT WDT Time Out FIGURE 15 1 WATCHDOG TIMER BLOCK DIAGRAM A i i Power On RESET and Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Reset WDT Reset OPTION N A LOWOPT PFDEN TOCS TOSE PSA PS2 PS1 PSO 0011 1111 0011 1111 TABLE 15 1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Oct 2001 Ver 2 0 37 HMS77C1000A HMS77C1001A 16 Power Down Mode SLEEP For applications where power consumption is a critical factor device provides power down mode with Watchdog operation Executing of SLEEP Instruction is entrance to SLEEP mode In the SLEEP mode oscillator is turn off and system clock is disable and all functions is stop but all registers and RAM data is held The wake up sources from SLEEP mode are external RESET pin reset and watchdog time overflow reset 16 1 SLEEP The Power Down mode is entered by executing a SLEEP instruction If enabled the Watchdog Timer will be cleared but keeps running the TO bit STATUS lt 4 gt is set the PD bit STATUS lt 3 gt is cleared and the oscillator driver is turned off The I O ports maintain the status they had be fore the SLEEP instruction was executed driving high driving low or hi impedance It should be noted that a RESET generated by a WDT time out does not drive the RESET pin lo
12. PCL 02H 1111 1111 1111 1111 Tb ILI STATUS 03H 0001 1xxx 1003 quuu 0003 quuu FSR 04H 1xxx xxxx luuu uuuu luuu uuuu PORTA 05H XXXX uuuu uuuu PORTB 06H XXXX XXXX uuuu uuuu uuuu uuuu General Purpose Register Files 07 1FH XXXX XXXX uuuu uuuu uuuu uuuu TABLE 14 2 RESET CONDITIONS FOR ALL REGISTERS 1 See Table 14 1 for reset value for specific conditions Legend unimplemented read as 0 x unknown u unchanged q see the tables in Section 17 for possible values Oct 2001 Ver 2 0 33 HMS77C1000A HMS77C1001A Power On RESET Power Fail Detect 6 Noise Filter RESET Vpp pin VVDT Time Overflow Internal RESET Q Internal RESET clear Timer 8 bit asyn ripple counter FIGURE 14 1 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT 14 1 Power On Reset POR The HMS77C100XA family incorporates on chip Power On Reset POR circuitry which provides an internal chip reset for most power up situations To use this feature the user merely ties the RESET Vpp pin to VDD A simplified block diagram of the on chip Power On Reset circuit is shown in Figure 14 1 The Power On Reset circuit and the Internal Reset Timer circuit are closely related On power up the reset latch is set and the IRT is reset The IRT timer begins counting once it detects RESET to be high After the time out peri od which is typically 7 ms
13. Vpp 5V Period No prescaler TwoT DD 5 3 18 30 ms Internal Reset Timer Period TiRT Vpp 5V 9 18 30 mS ECO High or Low Pulse Width TecoH _ No Prescaler Tcv 4 X TXIN 10 nS TEcoL With Prescaler 0 5Tcy 20 ECO Period N Prescaler Value No Prescaler TgcoP 1 2 4 256 20 nS With Prescaler Toy 40 N 1 These parameters are characterized but not tested 2 Datain Typ column is at 25 C unless otherwise stated These parameters are for design guidance only and are not tested TxiNH TxiNL TxiN XIN TxinR TXINF M TRESET gt RESET 0 15Vpp ECO Oct 2001 Ver 2 0 13 HMS77C1000A HMS77C1001A 7 7 Typical Characteristics These graphs and tables are for design guidance only and are not tested or guaranteed In some graphs or tables the data presented are out side specified operating range e g outside specified Vpp range This is for information only and devices are guaranteed to operate properly only within the specified range Operating Area fxiN MHz 24 20 16 12 loL VoL Vpp 5V loL mA 40 Ta 25 C 32 24 16 0 VoL 04 08 12 16 20 VY 14 The data is a statistical summary of data collected on units from different lots over a period of time Typical repre sents the mean of the distribution while max or min
14. az as as ar az as as i This example shows a write Port pin Written here i ye to RB followed by a read Instruction FO PRA A PA X OT irom RE fetched i MEC output RB read RB port J no operation no operation RB7 RBO Port pin read here a FIGURE 10 5 SUCCESSIVE I O OPERATION Oct 2001 Ver 2 0 25 HMS77C1000A HMS77C1001A 11 TIMERO MODULE AND TMRO REGISTER The Timer0 module has the following features Edge select for external clock 8 bit timer counter register TMRO Figure 11 1 is a simplified block diagram of the Timer0 8 bit software programmable prescaler module while Figure 11 2 shows the electrical structure of Internal or external clock select the Timer0 input Tcv Fosc 4 E gt 0 ECO pin TOSE Tocs Data bus 1 8 MUX Sync with Internal TMRO reg Clocks 2cycle delay PSA _ 8 bit Prescaler Car Watchdog Timer 8 1 8 to 1 MUX PS2 PSO PSA WDT Enable bit 4 0 1 MUX PSA Y WDT Time Out FIGURE 11 1 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER pi D m ECO N ka Schmitt Trigger Input Buffer V Note 1 ESD protection circuits FIGURE 11 2 ELECTRICAL STRUCTURE OF ECO PIN 26 Oct 2001 Ver 2 0 11 1 Timer Mode If the OPTION register bitS TOCS
15. into the configuration word XT Crystal Resonator HF High Speed Crystal Resonator LF Low Speed and Low Power Crystal RC External Resistor Capacitor 13 1 XT HF or LF Mode In XT LF or HF modes a crystal or ceramic resonator is connected to the Xjn and Xour pins to establish oscillation Figure 13 1 The HMS77C100XA oscillator design re quires the use of a parallel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufactur ers specifications Bits O and 1 of the configuration register FOSC1 FOSC2 are used to configure the different exter nal resonator crystal oscillator modes These bits allow the selection of the appropriate gain setting for the internal driver to match the desired operating frequency When in XT LF or HF modes the device can have an external clock source drive the Xiy pin Figure 13 2 In this case the Xour pin should be left open C10 SLEEP To internal logic Note 1 See Capacitor Selection tables for recommended values of C1 and C2 2 RF varies with the crystal chosen approx value 9 Ma FIGURE 13 1 CRYSTAL OR CERAMIC RESONATOR HF XT OR LF OSC CONFIGURATION Clock from ext system D gt XIN HMS77C100XA OPEN _ Xour FIGURE 13 2 EXTERNAL CLOCK INPUT OPERATION HF XT OR LF OSC CONFIGURATION Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A Osc Resonato
16. is cleared the timer mode is selected and is operated with internal system clock Tcy The Timer0 module will increment every instruc tion cycle without prescaler If TMRO register is written the increment is inhibited for the following two cycles The user can work around this by writing an adjusted value to the TMRO register Figure 11 3 and Figure 11 4 show the timing diagram of Timer No Prescaler PSA 0 Timer will increment every instruction cycle Q4 HMS77C1000A HMS77C1001A With Prescaler PSA 1 Timer will increment with prescaler division ratio PS2 PSO 1 2 1 256 Counter Mode 11 2 Counter Mode If the OPTION register bitS TOCS is set the counter mode is selected and operates with event clock input In this mode Timer will increment either on every rising or falling edge of pin ECO The incrementing edge is deter mined by the source edge select bit TOSE OPTION lt 4 gt Clearing the TOSE bit selects the rising edge a1 a2 a3 a4 a1 Q2 Q3 a4 a1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 a8 a4 a1 02 Q3 G4 PC biik PC 1 PC PCH PC 2 PC 3 PC 4 PC 5 PC 6 un W TMRO TMRO W E TMRO W TMRO W TMRO W TMRO W Instruction a Write TMRO Read TMRO Read m ro Read TMROS Read Ino S Read TMRO Executed executed reads NTO reads NTO reads NTO reads NTO 1 reads N
17. or SLEEP a WDT reset or wake up reset generates a device RESET The TO bit STATUS lt 4 gt will be cleared upon a Watch dog Timer reset The WDT can be permanently disabled by programming the configuration bit WDTE as a 0 Figure 12 2 Refer to the HMS77C100XA Programming Specifications to deter mine how to access the configuration word 15 1 WDT Period The WDT has a nominal time out period of 14 ms with no prescaler If a longer time out period is desired a pres HMS77C1000A HMS77C1001A caler with a division ratio of up to 1 256 can be assigned to the WDT under software control by writing to the OP TION register Thus time out a period of a nominal 3 5 seconds can be realized These periods vary with tempera ture Vpp and part to part process variations see DC specs Under worst case conditions Vpp Min Temperature Max max WDT prescaler it may take several seconds before a WDT time out occurs 15 2 WDT Programming Considerations The CLRWDT instruction clears the WDT and the postscaler if assigned to the WDT and prevents it from timing out and generating a device RESET The SLEEP instruction resets the WDT and the postscaler if assigned to the WDT This gives the maximum SLEEP time before a WDT wake up reset From TMRO Clock Source Watchdog Timer tf SLEEP ri clearing WDT on chip 8 bit asynchronous MUX RC
18. 2518 H M S77C 10004 f py f 8 BIT SINGLE CHIP MICROCONTROLLERS HMS77C1000A HMS77C1001A User s Manual Ver 2 0 Version 1 1 Published by MCU Application Team 2001 Hynix Semiconductor All right reserved Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual HMS77C1000A HMS77C1001A Contents of Table OVERVIEW nn AD a eed 1 Port RB vent sit Sh e AA 24 NA 4 I O Interfacing aa eee eee ee 24 Features oid conten tri Ends 1 VO Successive Operations 24 BLOCK DIAGRAM 2 TIMERO MODULE AND TMRO REGISTER 26 PIN ASSIGNMENT Ke UN KE kaaa AA kab 3 Timer Mode oo ooooooocoooooo ooo 27 PACKAGE DIAGRAM 4 Counter Mode anaana 27 Fee Se ge ANN Using Timer0 with an External Clock 28 PIN FUNCTION een Kn 6 PIrescaler to intet tatus 28 PORT STRUCTURES 7 CONFIGURATION AREA 30 ELECTRICAL CHARACTERISTICS 9 OSCILLATOR CIRCUITS 31 Absolute Maximum Ratings 9 X
19. Biti Bito Reset WDT Reset TRIS N A I O control registers TRISA TRISB 1111 1111 1111 1111 OPTION N A Contains control bits to configure Timer0 Timer0 WDT dori ia doma prescaler and PFD INDF 004 Uses contents of FSR to address data memory nota ian kr E zit chos physical register TMRO 01H 8 bit real time clock counter XXXX XXXX uuuu uuuu PCL 02u Low order 8bits of PC 1111 1111 1111 1111 STATUS 03H PAO TO PD Z DC C 0001 1xxx 000q quuu FSR 04H Indirect data memory address pointer lxxx xxxx luuu uuuu RA 05H 2 RA3 RA2 RA1 RAO xxxx uuuu RB 06H RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO xxxx xxxx uuuu uuuu TABLE 9 1 SPECIAL FUNCTION REGISTER SUMMARY Legend Shaded boxes unimplemented or unused unimplemented read as 0 x unknown u unchanged q see the tables in Section 17 for possible values 9 3 1 INDF Register The INDF register is not physically implemented register used for indirect addressing mode If the INDF register DirectAddressing Nase adresa Ts 4 opcode 0 4 FSR 0 are accessed CPU goes to indirect addressing mode Then CPU accesses the Data memory which address is the con N V N p v tents of FSR HA b location location If the INDF register are accessed in indirect addressing select 00H select modell e FSR 00H 00H will be loaded into data bus This time note the arithmetic status bits of STATUS reg ister may be affected The FSR lt 4 0 gt bits are used to select data memor
20. Hz 5K 3 5MHz 20pF 15K 1 4MHz 100K 240KHz 3 3K 1 8MHz 5K 1 5MHz 100pF 15K 610KHz 100K 100KHz 3 3K 780KHz 5K 630KHz 300pF 15K 260KHz 100K 42 5KHz Table 7 1 RC Oscillator Frequencies Oct 2001 Ver 2 0 hynix 8 ARCHITECTURE 8 1 CPU Architecture The HMS700 core is a RISC based CPU and uses a modi fied Harvard architecture This architecture uses two sepa rate memories with separate address buses one for the program memory and the other for the data memory This architecture adapts 33 single word instructions that are 12 bit wide instruction and has an internal 2 stage pipeline fetch and execute which results in execution of one in struction per single cycle 200ns 20MHz except for pro gram branches HMS77C1000A HMS77C1001A The HMS77C100XA can address 1K x 12 Bits program memory and 25 Bytes data memory And it can directly or indirectly address data memory The HMS700 core has three special function registers PC STATUS and FSR in data memory map and has ATU Address Translation Unit to provide address for data memory and has an 8 bit general purpose ALU and work ing register W as an accumulator The W register consists of 8 bit register and it can not be an addressed register Instruction PC with 2 level Stack Program Memory Address TI STATUS FSR Indirect Address Address Translation ce Unit m Immediate Data Instruction Decode g
21. LEEP mode is designed to reduce power consump tion To minimize current drawn during SLEEP mode the user should turn off output drivers that are sourcing or sinking current if it is practical It should be set properly that current flow through port doesn t exist First conseider the setting to input mode Be sure that there is no current flow after considering its relationship with external circuit In input mode the pin impedance viewing HMS77C1000A HMS77C1001A from external MCU is very high that the current doesn t flow But input voltage level should be Vss or Vpp Be careful that if unspecified voltage i e if uncertain voltage level not Vssor Vpp is applied to input pin there can be little current max 1mA at around 2V flow Note In the SLEEP operation the power dissipation asso ciated with the oscillator and the internal hardware is lowered however the power dissipation associat ed with the pin interface depending on the external circuitry and program is not directly determined by the hardware operation of the SLEEP feature This point should be little current flows when the input level is stable at the power voltage level Vpp Vss however when the input level becomes higher than the power voltage level by approximately 0 3V a current begins to flow Therefore if cutting off the output transistor at an I O port puts the pin signal into the high impedance state a current flow across the ports input tran
22. O input output P power Not used TTL TTL input ST Schmitt Trigger input Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A 6 PORT STRUCTURES RESET Internal RESET lt Ki Vss Xin Xout XT HF LF Mode EN XT HF LF T Vo To Internal Clock 4 4 Xout Amplifier varies with A the oscillation mode a Xin RC Mode Internal Capacitance appx 6pF T To Internal Clock 4 Ki Fe Xin Oct 2001 Ver 2 0 7 HMS77C1000A HMS77C1001A e RA0 3 RB0 7 VDD Data Reg Direction Reg Data Bus Vss Data Bus 4 S Read ECO Timer Counter Clock Input 4 Ki ECO 8 Oct 2001 Ver 2 0 NUNIX 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings Supply voltage oooconcnnconnonononrnnonenonconenonon nos 0 to 47 5 V Storage Temperature ul eee 65 to 125 C Voltage on RESET with respect to Vss 0 3 to 13 5V Voltage on any pin with respect to Vss 0 3to Vpp 0 3 Maximum current out of Vss pin 150 mA Maximum current into V pp pin 100 mA Maximum output current sunk by lo per I O Pin 25 mA Maximum output current sourced by Ion per I O Pin 7 2 Recommended Operating Conditions HMS77C1000A HMS77C1001A Maximum current EloL aaa an an aaa nanen ance eee eee ve eee eee 120 mA Maximum current Elop oocccooccnoonnnonancnin
23. T HF or LF Mode 31 Recommended Operating Conditions 9 RC Oscillation Mode 31 DC Characteristics 1 10 RESET ooo ccc cc LLL LL La LLL 33 DC Electrical Characteristics 2 11 a aun BOR BA AC Electrical Characteristics 1 12 iiid 4 ER S ee ee GAAN 3 AC Electrical Characteristics 2 13 iS EET tsai pest Typical Characteristics 14 WATCHDOG TIMER WDT 37 ARCHITECTURE 17 WDT Period ia aaa 37 CPU Architecture 17 WDT Programming Considerations 37 MEMORY 18 Power Down Mode SLEEP 38 Program Memory aa aa aa aaa a 18 SLEEP ana deseaba ket 38 Data Memoria bn AP 18 e sg Special Function Registers 19 E pitan m TIME OUT SEQUENCE AND POWER DOWN 1 0 PORTS ir these neces 24 STATUS BITS TO PD 41 Pott RA iaa durim Sete ie 24 POWER FAIL DETECTION PROCESSOR 42 Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A HMS77C1000A 1 HMS77C1001A CMOS SINGLE CHIP 8 BIT MICROCONTROLLER 1 OVERVIEW 1 1 Description The HMS77C1000A and HMS77C1001A are an advanced CMOS 8 bit microcontroller with 0 5K 1K words 12 bit of EPROM The Hynix Semiconductor HMS77C1000A and HMS77C1001A are a powerful microcontroller which provides a high flexibility and cost effective solution to many small applications The HMS77C1000A and HMS77C1001A provide the following standar
24. T senses a high on the RE SET Vpp pin and when the RESET Vpp pin and VDD actually reach their full value is too long In this situation Oct 2001 Ver 2 0 when the internal reset timer times out VDD has not reached the VDD min value and the chip is therefore not guaranteed to function correctly For such situations we recommend that external R circuits be used to achieve longer POR delay times Figure 14 5 Note When the device starts normal operation exits the reset condition device operating parameters volt age frequency temperature etc must be meet to ensure operation If these conditions are not met the device must be held in reset until the operating conditions are met 35 HMS77C1000A HMS77C1001A The POR circuit does not produce an internal reset when Vpp declines lt e O lt go iw R1 t RESET External Power On Reset circuit is required only if VDD power up is too slow The diode D helps discharge the capacitor quickly when VDD powers down R lt 40 kQ is recommended to make sure that voltage drop across R does not violate the device electrical specifi cation R1 100W to 1 kW will limit any current flowing into RESET from external capacitor C in the event of RESET pin breakdown due to Electrostatic Discharge ESD or Electrical Overstress EOS FIGURE 14 5 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW VDD POWER UP 36 hynix 14 2 Inte
25. TO 2 TMRO TO a TO 1 X TO 2 NTO A GG X ier Ei Timer i Clock E E increment inhibited Li FIGURE 11 3 TIMERO TIMING INTERNAL CLOCK NO PRESCALE HG a1 Q2 a3 a4 a1 a2 03 a4 a1 a2 Q3 Q4 Q1 Q2 3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 02 03 Q4 a1 02 a3 Q4 Program I I I I I I I PC 1 X PC y PC 1 Y PC 2 I PC 3 PC 4 I PC 5 PC 6 EN W TMRO TMRO W TMRO W TMRO W TMRO W i TMRO W etc 1 1 1 1 1 1 1 1 Higa l Write EN WAS Read WOS Read TuRo Read Nikon Read TMRO xecuto executed reads NTO reads NTO reads NTO reads NT0 1 reads NT0 2 TMRO To TO 1 NTO J into i I La 1 I pi t increment inhabited Timer0 Clock FIGURE 11 4 TIMERO TIMING Oct 2001 Ver 2 0 INTERNAL CLOCK PRESCALER 1 2 27 HMS77C1000A HMS77C1001A E unix a i r a F Power On RESET and Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Reset WDT Reset TMRO 01H 8 bit real time clock counter XXXX XXXX uuuu uuuu OPTION N A LOWOPT PFDEN TOCS TOSE PSA PS2 PS1 PSO 0011 1111 0011 1111 TABLE 11 1 REGISTERS ASSOCIATED WITH TIMERO Legend x unknown u unchanged 11 3 Using Timer0 with an External Clock When an external clock input is used for Timer0 it mus
26. d features 0 5K 1K words of EPROM 25 bytes of RAM 8 bit timer counter power on reset on chip os cillator and clock circuitry In addition the HMS77C1000A and HMS77C1001A supports power saving modes to reduce power consumption Device name ROM Size RAM Size Package HMS77C1000A 0 5K words 12 bit 25 bytes 18 PDIP SOP or 20 SSOP HMS77C1001A 1K words 12 bit 25 bytes 18 PDIP SOP or 20 SSOP 1 2 Features High Performance RISC CPU 12 bit wide instructions and 8 bit wide data path 33 single word instructions 0 5K 1K words on chip program memory 25 bytes on chip data memory Minimum instruction execution time 200ns 20MHz Operating speed DC 20 MHz clock input Seven special function hardware registers Two level hardware stack Peripheral Features Twelve programmable l O lines One 8 bit timer counter with 8 bit programmable prescaler Power On Reset POR Power Fail Detector noise immunity circuit 2 level detect 2 7V 1 8V Oct 2001 Ver 2 0 Internal Reset Timer IRT Watchdog Timer WDT with on chip RC oscilla tor Programmable code protection Power saving SLEEP mode Selectable oscillator options Configuration word RC Low cost RC oscillator 200KHz 4MHz XT Standard crystal resonator 455KHz 4MHz HF High speed crystal resonator 4 20MHz LF Power saving low frequency crystal resonator 32 200KHz CMOS Technology Low power high spe
27. e data memory consists of 25 bytes of RAM and seven special function registers The data memory locations are FIGURE 9 1 HMS77C1000A PROGRAM MEMORY MAP 18 AND STACK addressed directly or indirectly by using FSR Figure 9 3 shows a map of data memory The special func tion registers are mapped into the data memory File Address gt 00H 00H INDF Special Function 01H TMRO n Registers 02 PCL y 7 07H 03H STATUS DATA MEMORY 05H RA OFH 10H 06H RB DATA MEMORY SRAM 1FH FIGURE 9 3 HMS77C100XA DATA MEMORY MAP Oct 2001 Ver 2 0 9 3 Special Function Registers This devices has seven special function register that are the INDF register the Program Counter PC the STATUS register File Select Register FSR 8 bit Timer TMRO and I O data register RA RB The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of HMS77C1000A HMS77C1001A the device Table 9 1 TMRO RA and RB are not in the G700 CPU They are lo cated in each peripheral function blocks All special func tion register are placed on data memory map The INDF register is not a physical register and this register is used for indirect addressing mode i 3 i i r Power On RESET and Name Address Bit7 Bit6 Bits Bit4 Bit3 Bit2
28. ed CMOS EPROM technol ogy Fully static design Wide operating range 2 5V to 5 5V RC XT LF 4 5V to 5 5V HF HMS77C1000A HMS77C1001A 2 BLOCK DIAGRAM RESET Xin Xout Vpp Vss Power Supply Power Fail Detector System controller OPTION STATUS 8 bit Timer Counter Clock Generator Timing Control Configuration Word WDT TMRO Prescaler Watch dog Timer ry Memory ms WDT time out STACK 1 Data STACK 2 Program Memory Instruction Decoder RAO RA1 RA2 RA3 dh ECO RBO RB1 RB2 RB3 RB4 RB5 RB6 RB7 Oct 2001 Ver 2 0 3 PIN ASSIGNMENT Oct 2001 Ver 2 0 RA2 RA3 ECO RESET Vpp Vss RBO RB1 RB2 RB3 RA2 RA3 ECO RESET Vpp Vss Vss RBO RB1 RB2 RB3 18 PDIP or SOP 1 xe 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 20 SSOP 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 RA1 RAO Xin Xout VDD RB7 RB6 RB5 RB4 RA1 RAO Xin Xout Vpp Vpp RB7 RB6 RB5 RB4 HMS77C1000A HMS77C1001A
29. gister ADDRESS N A RESET VALUE OFH FIGURE 10 2 RA PORT REGISTERS 24 hynix 10 2 Port RB RB is an 8 bit I O register Each I O pin can independently used as an input or an output through the port direction reg ister TRISB A 0 in the TRISB register configure the corresponding port pin as output Conversely write 1 to the corresponding bit to specify it as input pin ADDRESS 06H RB Data Register RESET VALUE Undefined 7 6 5 4 3 2 1 0 RB Direction Register ADDRESS N A RESET VALUE FFH TRISB DILLI FIGURE 10 3 RB PORT REGISTERS Note A read of the ports reads the pins not the output data latches That is if an output driver on a pin is enabled and driven high but the external system is holding it low a read of the port will indicate that the pin is low 10 3 I O Interfacing The equivalent circuit for an I O port pin is shown in Fig ure 10 4 All ports may be used for both input and output operation For input operations these ports are non latching Any in put must be present until read by an input instruction The outputs are latched and remain unchanged until the output latch is rewritten To use a port pin as output the corre sponding direction control bit in TRISA TRISB must be cleared 0 For use as an input the corresponding TRIS bit must be set Any I O pin can be programmed individu ally as input or output 10 4 I O Succe
30. instruction all subrou tine calls or computed jumps are limited to the first 256 locations of any program memory page 512 words long jump instrunciton PC PCL TI Instruction VVord 20 hynix Subroutine call instruction Instruction Word Reset to 0 FIGURE 9 5 LOADING OF BRANCH INSTRUCTION HMS77C1000A jump instruction 9 8 0 PC PCL IP Instruction Word PAO subroutine call Instruction 9 8 7 0 PC PCL Instruction Word Reset to 0 FIGURE 9 6 LOADING OF BRANCH INSTRUCTION HMS77C1001A 9 3 4 Stack Operation The HMS77C100XA have a 2 level hardware stack The stack register consists of two 9 bit save regis ters HMS77C1000A 10 bit save regis ters HMS77C1001A A physical transfer of register contents from the program counter to the stack or vice ver sa and within the stack occurs on call and return instruc tions If more than two sequential call instructions are executed only the most recent two return address are stored If more than two sequential return instructions are executed the stack will be filled with the address previous ly stored in level 2 The stack cannot be read or written by Oct 2001 Ver 2 0 program HMS77C1001A HMS77C1000A 9 8 0 Ps Ne subroutine call return STACK LEVEL1 subroutine call return STACK LEVEL2 FIGURE 9 7 OPERATION OF 2 LEVEL STACK
31. ng mode FIGURE 9 9 FSR REGISTER AND DIRECT INDIRECT ADDRESSING MODE 9 3 7 OPTION Register The OPTION register consists of 8 bit write only register and can not addressed This register is able to control the status of PFD TMRO WDT prescaler and TMRO 22 To modify the OPTION register the content of W register are transferred to the OPTION register by executing the OPTION instruction In reset state the OPTION register is initialized with 001111118 Oct 2001 Ver 2 0 IX HMS77C1000A HMS77C1001A ADDRESS N A VV VV VV VV VV VV VV VV RESET VALUE 0011 1111 5 4 3 2 1 bit7 6 bitO n Value at POR reset LOWOPT Power fail detection level select bit PS2 PSO Prescaler rate select bits 1 Lowered detection level 1 8V 9 5V 0 Normal detection level 2 7V 9 5V Bit Value Timer O rate WDT rate PFDEN Power fail detection enable bit 000 1 2 1 1 1 Enable power fail detection 001 1 4 1 2 0 Disable power fail detection 010 1 8 1 4 TOCS Timer 0 clock source select bit 1 Transition on ECO pin 011 1 16 1 8 0 Internal instruction cycle clock 100 1 32 1 16 TOSE Timer 0 source edge select bit 101 1 64 1 32 1 Increment on high to low transition on ECO 110 1 128 1 64 0 Increment on low to high transition on 111 1 256 1 128 ECO PSA Prescaler assignment bit 1 Prescaler assigned to the WDT 0 Prescaler assigned to the Timer 0
32. nnnnnnnnos 80 mA Note Stresses above those listed under Absolute Maxi mum Ratings may cause permanent damage to the device This is a stress rating only and functional op eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specifications Parameter Symbol Condition Unit Min Max TT vi fxin 20MHz 4 5 5 5 y upply Voltage DD txin 4MHz 2 5 5 5 RC Mode 0 2 4 XT Mode 0 455 4 MHz Operating Frequency FXIN HF Mode 4 20 LF Mode 32 200 KHz Operating Temperature ToPR 40 85 C Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A 7 3 DC Characteristics 1 Ta 40 C 85 C LIA Specification Parameter Symbol Test Condition Unit Min Typ Max Supply Voltage XT RC LF Vop 2 5 5 5 V HF 4 5 5 5 eee ONT qus ZEE VDD rise rate Sypp 0 05 V mS ea Retention VDR 15 z V Power Fail Detection Normal Level Vpep 2 7 V Low Level F 1 8 z Supply Current XT RC4 p t Xin 4MHz Vpp 5V 1 8 3 3 mA HF PP Xin 20MHz Vpp 5V i 9 0 20 mA LF Xin 32KHz Vpp 3V WDT Disabled 17 40 uA Vpp 3V WDT Enabled 4 14 Power Down Current IPD UA Vpp 3V WDT Disabled 0 4 5 1 Data in Typ column is at 25 C unless otherwise stated
33. or frequen 31 HMS77C1000A HMS77C1001A cy is a function of the supply voltage the resistor R and capacitor C values and the operating temperature In addition the oscillator frequency will vary from unit to unit due to normal manufacturing process variations Fur thermore the difference in lead frame capacitance between package types also affects the oscillation frequency espe cially for low C values The external R and C component tolerances contribute to oscillator frequency variation as well The user also needs to take into account variation due to tolerance of external R and C components used Figure 13 3 shows how the R is connected to the HMS77C100XA For Rext values below 2 2 kQ the oscil lator operation may become unstable or stop completely For very high Rext values e g 1 MQ the oscillator be comes sensitive to noise humidity and leakage Thus we recommend keeping Rext between 3 kQ and 100 kQ Ta ble 13 3 shows recommended value of Rext and Cext Although the oscillator will operate with no external ca pacitor Cext 0 pF it is recommend using values above 20 pF for noise and stability reasons With no or small ex ternal capacitance the oscillation frequency can vary dra matically due to changes in external capacitances such as PCB trace capacitance or package lead frame capacitance Cext Rext Average Fxin 5V 25 C 3 3K 6 5MHz pas 5K 5 4MHz p 15K 2 3MHz 100K 400KHz 3 3K
34. oscillation stabilization time it will reset the reset latch and thus end the on chip reset signal VDD RESET INTERNAL POR IRT TIMER OUT INTERNAL RESET FIGURE 14 2 TIME OUT SEQUENCE ON POWER UP RESET NOT TIED TO Vpp 34 Oct 2001 Ver 2 0 hynix HMS77C1000A HMS77C1001A VDD RESET INTERNAL POR IRT TIMER OUT INTERNAL RESET FIGURE 14 3 TIME OUT SEQUENCE ON POWER UP RESET TIOED TO Vpp FAST Vpp RISE TIME INTERNAL RESET Vpp RESET TIRT INTERMALPOR IRT TIMER OUT When Vpp rise slowly the T rT time out expires long before Vpp has reached its final value In this example the chip will reset properly if V 2 Vppmin FIGURE 14 4 TIME OUT SEQUENCE ON POWER UP RESET TIOED TO Vpp SLOW Vpp RISE TIME A power up example where RESET is not tied to VDD is shown in Figure 14 2 VDD is allowed to rise and stabilize before bringing RESET high The chip will actually come out of reset TIRT after RESET goes high and POR PFDR is released In Figure 14 3 the on chip Power On Reset feature is be ing used RESET and VDD are tied together The VDD is stable before the internal reset timer times out and there is no problem in getting a proper reset However Figure 14 4 depicts a problem situation where VDD rises too slowly The time between when the IR
35. p column is at 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2 This parameter are characterized but not tested Oct 2001 Ver 2 0 11 HMS77C1000A HMS77C1001A 7 5 AC Electrical Characteristics 1 Ta 40 C 85 C Specification Parameter Symbol Test Condition Unit Min Typ Max XT osc mode DC 4 0 MHz External Clock Input Fxin HF osc mode DC 20 MHz Frequency LF osc mode DC 200 KHz RC osc mode DC 4 0 MHz li E 5 E XT osc mode 0 1 4 0 MHz scillator Frequenc XIN q y HF osc mode 4 0 20 MHz LF osc mode 5 0 200 KHz XT osc mode 250 nS External Clock Input Period TXIN HF osc mode 50 nS LF osc mode 5 uS RC osc mode 250 nS b t XT osc mode 250 10 000 nS scillator Period XIN HF osc mode 50 8 250 nS LF osc mode 5 200 uS XT osc mode 85 nS i in 1 Clockin XIN Pin TxinL HF osc mode 20 i nS Low to High Time Tx nH LF osc mode 2 uS XT osc mode 25 nS i in 1 Clock in XIN Pin TXINR HF osc mode i 25 nS Rise or Fall Time TXINF LF osc mode 50 ns 1 This parameter is characterized but not tested 12 Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A 7 6 AC Electrical Characteristics 2 Ta 40 C 85 C Specification Parameter Symbol Test Condition Unit Min Typ Max RESET Pulse Width Low TRESET Vpp 5V 100 nS Watchdog Timer Time Out
36. r When as On a RESET the prescaler contains all 0 s Oct 2001 Ver 2 0 29 HMS77C1000A HMS77C1001A 12 CONFIGURATION AREA The device configuration area can be programmed or left unprogrammed to select device configurations such as os cillator type security bit or watchdog timer enable bit bit11 4 3 bito AAAH IDO AAAH 1 AAAH 2 AAAH 3 FFFy Configuration Word FIGURE 12 1 DEVICE CONFIGURATION AREA Four memory locations AAAH AAA 3 H are desig nated as customer ID recording locations where the user can store check sum or other customer identification num bers These area are not accessible during normal execu tion but are readable and writable during program verify mode It is recommended that only the 4 least significant bits of ID recording locations are used bit11 bit 3 CP Code protection bit 1 Code protection disabled 0 Code protection enabled 1 WDT enabled 0 WDT disabled 11 RC oscillator 10 HF oscillator 01 XT oscillator 00 LF oscillator Unimplemented read as 0 bit 2 WDTE Watchdog timer enable bit bit 1 0 FOSC1 FOSCO Oscillator selection bits 3 2 1 bito P Address FFFy FIGURE 12 2 CONFIGURATION WORD FOR HMS77C100XA 30 Oct 2001 Ver 2 0 Mun IX 13 OSCILLATOR CIRCUITS HMS77C100XA supports four user selectable oscillator modes The oscillator modes are selected by programming the appropriate values
37. r Cap Range Cap Range Type Freq C1 C2 XT 455 kHz 22 100 pF 22 100 pF 2 0 MHz 15 68 pF 15 68 pF 4 0 MHz 15 68 pF 15 68 pF HF 4 0 MHz 15 68 pF 15 68 pF 8 0 MHz 10 68 pF 10 68 pF 16 0 MHz 10 22 pF 10 22 pF TABLE 13 1 CAPACITOR SELECTION FOR CERAMIC RESONATORS Note These values are for design guidance only Since each resonator has its own characteristics the user should consult the resonator manufacturer for ap propriate values of external components Osc Crystal Cap Range Cap Range Type Freq C1 C2 LF 32 kHz 15 pF 15pF 100 kHz 15 30 pF 30 47 pF 200 kHZ 15 30 pF 15 82 pF XT 100 kHz 15 30 pF 200 300 pF 200 kHz 15 30 pF 100 200 pF 455 kHz 15 30 pF 15 100 pF 1 MHz 15 30 pF 15 30 pF 2 MHz 15 30 pF 15 30 pF 4 MHz 15 47 pF 15 47 pF HF 4 MHz 15 30 pF 15 30 pF 8 MHz 15 30 pF 15 30 pF 20 MHz 15 30 pF 15 30 pF TABLE 13 2 CAPACITOR SELECTION FOR CRYSTAL 1 For VDD gt 4 5V C1 C2 30 pF is recommended Note These values are for design guidance only Since each crystal has its own characteristics the user should consult the crystal manufacturer for appropri ate values of external components If you change from this device to another device please verify oscillator characteristics in your application 13 2 RC Oscillation Mode The external RC oscillator mode provides a cost effective approach for applications that do not require a precise op erating frequency In this mode the RC oscillat
38. rescaler Output NN I Ls WW f misses sampling A ANOA AUN 4 A 4 A 3 pose me External Clock Prescaler r E Output After Sampling i Increment TMRO Q4 TMRO TO X TO 1 J TO 2 Note 1 Delay from clock input change to TMRO increment is 3TxiN to 7Txin Duration of Q Txin Therefore the error in measuring the interval between two edges on TMRO input 4Txin max 2 External clock if no prescaler selected prescaler output otherwise 3 The arrows indicate the points in time where sampling occurs FIGURE 11 5 TIMERO TIMING WITH EXTERNAL CLOCK 11 4 Prescaler The prescaler may be used by either the Timer0 module or the Watchdog Timer but not both Thus a prescaler as signment for the Timer0 module means that there is no prescaler for the WDT and vice versa The prescaler assignment is controlled in software by the 28 control bit PSA OPTION lt 3 gt Clearing the PSA bit will assign the prescaler to Timer0 The prescaler is neither readable nor writable The PSA and PS2 PSO bits OPTION lt 3 0 gt determine prescaler assignment and prescale ratio When the prescal er is assigned to the Timer0 module prescale values of 1 2 Oct 2001 Ver 2 0 hynix HMS77C1000A HMS77C1001A 1 4 1 256 are selectable signed to WDT a CLRWDT instruction will clear the When assigned to the Timer0 module all instructions writ presealer along with the WD ing to the TMRO register will clear the prescale
39. rnal Reset Timer IRT The Internal Reset Timer IRT provides a fixed 7 ms nom inal time out on reset The IRT operates on an internal RC oscillator The processor is kept in RESET as long as the IRT is active The IRT delay allows VDD to rise above VDD min and for the oscillator to stabilize Oscillator circuits based on crystals or ceramic resonators require a certain time after power up to establish a stable oscillation The on chip IRT keeps the device in a RESET condition for approximately 7 ms after the voltage on the RESET Vpp pin has reached a logic high Vp level and POR released Thus external RC networks connected to the RESET input are not required in most cases allowing for savings in cost sensitive and or space restricted appli cations The Device Reset time delay will vary from chip to chip due to Vpp temperature and process variation The IRT will also be triggered upon a Watchdog Timer time out This is particularly important for applications us ing the WDT to wake the HMS77C100XA from SLEEP mode automatically Oct 2001 Ver 2 0 15 WATCHDOG TIMER WDT The Watchdog Timer WDT is a free running on chip RC oscillator which does not require any external components This RC oscillator is separate from the RC oscillator of the Xin pin That means that the WDT will run even if the clock on the Xin and Xour pins have been stopped for ex ample by execution of a SLEEP instruction During nor mal operation
40. s been caused by a power up condition a RESET or Watchdog Timer WDT reset or a RESET or WDT wake up reset TO PD RESET was caused by 1 1 Power up POR u u RESET or PFD reset normal operation i RESET Wake up or PFD reset from SLEEP 0 1 WDT reset normal operation 0 O WDT wake up reset from SLEEP TABLE 17 1 TO PD STATUS AFTER RESET 1 The TO and PD bits maintain their status u until a reset occurs A low pulse on the RESET input does not change the TO and PD status bits These STATUS bits are only affected by events listed in Oct 2001 Ver 2 0 Table 17 2 Event TO PD Remarks Power up 1 1 WDT Time out 0 u Noeffecton PD SLEEP instruction 1 0 CLRWDT instruction 1 1 TABLE 17 2 EVENTS AFFECTING TO PD STATUS BITS Note A WDT time out will occur regardless of the status of the TO bit A SLEEP instruction will be executed regardless of the status of the PD bit Table 14 1 lists the reset conditions for the special function registers while Table 14 2 lists the reset conditions for all the registers 41 HMS77C1000A HMS77C1001A la YN Ix 18 POWER FAIL DETECTION PROCESSOR HMS77C100XA has an on chip power fail detection cir If Vpp falls below a level for longer 100ns the power fail cuitry to immunize against power noise detection processor may reset MCU and preserve the de vice from the malfunction due to Power Noise Regis
41. sistor requiring it to fix the level by pull up or other means If it is not appropriate to set as an input mode then set to output mode considering there is no current flow Setting to High or Low is decided considering its relationship with external circuit For example if there is external pull up re sistor then it is set to output mode i e to high and if there is external pull down register it is set to low INPUT PIN Vi internal pull up Vpp VDD AF O N Weak pull up current flows O VDD INPUT PIN 4 OPEN A vi EM Very weak current flows X i 0 GND When port is configure as an input input level should be closed to OV or 5V to avoid power consumption FIGURE 16 3 APPLICATION EXAMPLE OF UNUSED INPUT PORT Oct 2001 Ver 2 0 39 HMS77C1000A HMS77C1001A OUTPUT PIN 4 ON OPEN _OFF 10 VDD LON X Ed O In the left case much current flows from port to GND OUTPUT PIN In the left case Tr base current flows from port to GND To avoid power consumption there should be low output to the port FIGURE 16 4 APPLICATION EXAMPLE OF UNUSED OUTPUT PORT 40 Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A 17 TIME OUT SEQUENCE AND POWER DOWN STATUS BITS TO PD The TO and PD bits in the STATUS register can be tested to determine if a RESET condition ha
42. ssive Operations The actual write to an I O port happens at the end of an in struction cycle whereas for reading the data must be valid at the beginning of the instruction cycle Figure 10 5 Therefore care must be exercised if a write followed by a read operation is carried out on the same I O port The sequence of instructions should allow the pin voltage to stabilize load dependent before the next instruction which causes that file to be read into the CPU is executed Oct 2001 Ver 2 0 HMS77C1000A HMS77C1001A V Data Reg Es Data Bus gt ZN Direction Reg Data Bus ZN V Data Bus q lt vss Read FIGURE 10 4 EQUIVALENT CIRCUIT FOR A SINGLE l O PIN a Y A 3 a 3 Power On RESET and Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Reset WDT Reset TRIS N A I O control registers TRISA TRISB 1111 1111 1111 1111 RA 05H RA3 RA2 RA1 RAO XXXX uuuu RB 06H RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO XXXX XXXX uuuu uuuu TABLE 10 1 SUMMARY OF PORT REGISTERS Legend Shaded boxes unimplemented or unused Otherwise the previous state of that pin may be read into the CPU rather than the new state unimplemented read as 0 x unknown u unchanged When in doubt it is better to separate these instructions with a NOP or another instruction not accessing this I O port 91 02 03 04 Q1 02 03 04 01
43. t meet certain requirements The external clock requirement is due to internal phase clock Tosc synchronization Al so there is a delay in the actual incrementing of Timer0 af ter synchronization 11 3 1 External Clock Synchronization The synchronization of ECO input with the internal phase clocks is accomplished by sampling ECO clock or the pres caler output on the Q2 and Q4 falling of the internal phase clocks After the synchronization counter increments on the next instruction cycle Q4 There is a small delay from the time the external clock edge occurs to the time the Timer0 mod ule is actually incrementing Figure 11 5 shows the syn chronization and the increment of the counter mode ECO clock specification No Prescaler PSA 0 High or low time min gt 2T xin 20ns With Prescaler PSA 1 High or low time min 2 4T xin 40ns But there is a noise filter on the ECO pin the minimum low or high time 10ns should be required 11 3 2 TimerO Increment Delay Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actual ly incrementing Figure 11 5 shows the delay from the ex ternal clock edge to the timer incrementing Q1 Q2 as Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or m 2 Ww Small Pulse _ P
44. ter 6 5 4 3 2 1 bit7 bito bit 7 LOVVOPT Povver fail detection level select bit 1 Lowered detection level typ 1 8V 5V 0 Normal detection level typ 2 7V 5V bit 6 PFDEN Power fail detection enable bit 1 Enable power fail detection 0 Disable power fail detection FIGURE 18 1 POWER FAIL DETECTION PROCESSOR The bit6 PFDEN of OPTION register activates the PFD Circuit and bit7 LOWopt lowers the detection level of the Power Noise The normal detection level is typically 2 7V and the lowered detection level is typically 1 8V Fig ure 18 2 shows a Power Fail Detection Situations where the detection level is selected by LOWOPT Bit Note The PFD circuit is not implemented on the in circuit emulator user can not experiment with it There fore after final development user program this function may be experimented on OTP PFDEN 1 po M9 LOWOPT 0 PFDR Internal L RESET e TNvpp2 100nS rv ul CNRC RU REA CA Vpn 1 8V TIRT PFDEN 1 LOWOPT 1 PEDR Internal OT RESET V te a da AYY Vpn 2 7 or 1 8V TiRT Vpp lt VpR PFDR PFDEN 1 Internal LOWOPT 0 1 GEL POR E When Vpp falls below approximately 1 5V level Power On Reset may occur FIGURE 18 2 POWER FAIL DETECTION SITUATIONS 42 Oct 2001 Ver 2 0
45. w For lowest current consumption while powered down the ECO input should be at Vpp or Vss and the RESET pin must be at a logic high level Internal System Clock Oscillator ewer D o a2 Instruction J Fetch SLEEP Execute SLEEP RESET TU Internal _ RESET 22 HH Foton RESET vector 2 FIGURE 16 1 TIMING DIAGRAM OF WAKE UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET Oscillator 2 Xin pin i 22 Fech RESET vector 2 Internal System Clock H Instruction I Fetch SLEEP y Execute SLEEP WDT Overflow l 4 Internal o TRT RESET FIGURE 16 2 TIMING DIAGRAM OF WAKE UP FROM SLEEP MODE DUE TO WATCHDOG TIME OVERFLOW RESET 38 Oct 2001 Ver 2 0 hynix 16 2 Wake up From SLEEP The device can wake up from SLEEP through one of the following events 1 An external reset input on RESET pin 2 A Watchdog Timer time out reset if WDT was en abled 3 PFD reset Both of these events cause a device reset The TO and PD bits can be used to determine the cause of device reset The TO bit is cleared if a WDT time out occurred and caused wake up The PD bit which is set on power up is cleared when SLEEP is invoked The WDT is cleared when the device wakes from sleep re gardless of the wake up source 16 3 Minimizing Current Consumption The S
46. y ad Data OFH dresses 00y to 1Fp Memory 10H HMS77C1000A and HMS77C1001A do not use banking FSR lt 7 5 gt are unimplemented and read as 1 s 1FH Oct 2001 Ver 2 0 FIGURE 9 4 DIRECT INDIRECT ADDRESSING 19 HMS77C1000A HMS77C1001A 9 3 2 TMRO Register The TMRO register is a data register for 8 bit timer counter In reset state the TMRO register is initialized with 00g 9 3 3 Program Counter PC The program counter contains the 10 bit address of the in struction to be executed 9 bit address for HMS77C1000A The lower 8 bits of the program counter are contained in the PCL register which can be provided by the instruction word for a call instruction or any instruction where the PCL is the destination while the ninth bit of the program counter comes from the page address bit PAO of the STA TUS register HMS77C1001A only This is necessary to cause program branches across pro gram memory page boundaries Prior to the execution of a branch operation the user must initialize the PAO bit of STATUS register The eighth bit of the program counter can come from the instruction word by execution of goto instruction or can be cleared by execution of call or any instruction where the PCL is the destination In reset state the program counter is initialized with 1FFy HMS77C1000A or 3FFy HMS77C1001A Note Because PC lt 8 gt is cleared in the subroutine call in struction or any Modify PCL
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