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ST ST72774/ST72754/ST72734 Data Sheet

1. These pins connect a parallel resonant crystal or assume software programmable alternate an external source to the on chip oscillator functions as shown in the pin description Table 1 ST727x4 Pin Description Pin No 3 Description Remarks 8 ono 39 1 PCO HSYNCDIV Port CO or HSYNCDIV output HSYNCO divided by 2 40 2 PC1 AV Port C1 or Active Video input 41 3 2 Port 2 10 bit PWM BRM output 3 42 4 PC3 PWM4 Port 10 bit PWM BRM output 4 43 5 PC4 PWM5 Port C4 10 bit PWM BRM output5 analog controls 44 6 PC5 PWM6 Port C5 or 10 bit PWM BRM output 6 after external filtering 1 7 PC6 PWM7 Port C6 10 bit PWM BRM output 7 2 8 PC7 PWM8 Port C7 or 10 bit PWM BRM output 8 3 9 PB7 AIN3 PWM2 Port 7 or ADC analog input 3 or 10 bit PWM BRM output 2 4 10 PB6 AIN2 PWM1 lO Port B6 or ADC analog input 2 or 10 bit PWM BRM output 1 5 11 PB5 AIN1 Port B5 or ADC analog input 1 6 12 PB4 AINO Port B4 or ADC analog input 0 8 13 Vpp S Supply 4 0V 5 5V 9 14 USBVCC S USB power supply output 3 3V 10 10 15 USBDM lO USB bidirectional data Must be tied to ground aes for devices without 11 16 USBDP USB bidirectional data USB peripheral 12 17 Vss S Ground 0V 13 18 HSYNCI SYNC horizontal synchro
2. 121 4 108 BIT A D CONVERTER eee 123 4 10 l troducllor um tere te e RE A A a RR CR 123 4 10 2 Features cessio RAE AES 123 4 10 3Functional Description 1 4 123 4 10 41 Power Mode 124 4 0 5Interr pts u a a a 124 4 10 6Register Description 125 SsINSTRUGTION A 126 51 ST7 ADDRESSING MODES 126 ky 3 144 ST72774 ST727754 ST72734 D To A 127 51 2 Immediate hake hae dacs Ede eas esas 127 5123 Ditect d Re Glas RUE ERE 127 5 1 4 Indexed No Offset Short 0 127 5 1 5 Indirect Shott bong sce yk ee sapu oy RES 127 5 1 6 Indirect Indexed Short Long 128 5 1 7 Relative mode Direct Indirect 128 5 2 INSTRUCTION GROUPS 1 129 6 ELECTRICAL CHARACTERISTICS 132 6 1 POWER
3. 2 0 80 4 6 5 Programming Considerations 85 4 7 SINGLE MASTER BUS INTERFACE I2C 87 4 7 1 Introduction A A d e d EO Modal 87 4 7 2 Main Features o nostrates dog GANG oad ded steer etre garda ar aed 87 4 7 3 General Description 87 4 7 4 Functional Description Master Mode 89 4 7 5 Register Description 91 48 DDCINTEREAGE DDC or ipso suce rinda tarea 95 Introduction aka Vea Cao etc 95 4 8 2 DDC Interface Features 95 4 8 9 Signal Description a dee RES D x ou Yale 97 4 94 I2G BUS Protocol rola e greet E Rp abies 98 4 8 5 DDG Starndatd u ico sia uwa Rex CAII Wie Gow dia idea 99 4 8 6 Register Description 110 4 9 PWM BRM GENERATOR 116 4 9 1 Introduction eb Ec esteso tcr aa LU ONE 116 4 9 2 Main Features epe uten a DE a 116 4 9 3 Functional Description 116 4 9 4 Register Description
4. ewe fe fe fe m3 Name mm s al ea n Co m a Ps __ ww o o P o OE7 OE0 122 144 4 10 8 BIT A D CONVERTER ADC 4 10 1 Introduction The on chip Analog to Digital Converter ADC peripheral is a 8 bit successive approximation converter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 4 10 2 Main Features m 8 bit conversion m Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag T On off bit to reduce consumption he block diagram is shown in Figure 76 Figure 76 ADC Block Diagram ST72774 ST727754 ST72734 4 10 3 Functional Description 4 10 3 1 Analog Power Supply VppA and VssA are the high and low level reference voltage pins In some devices refer to device pin out description they are internally connected to the Vpp and Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily load
5. Moire 4 4 5 1 Blanking output signal To use the video blanking signal The Video Blanking function uses VSYNCO Program the polarity HFBACK VFBACK as input signals and BLKINV bit in POLR register BLANKOUT output as Video Blanking Output This OE Enable the BLANKOUT output output pin is a 5V open drain output and can be BLKEN bit in ENR register AND wired with any external video blanking signal Note HFBACK VFBACK VSYNCO signals must have positive polarity Figure 42 Video Blanking Stage Simplified Schematic To Edge detector LATR To Edge detector LATR BLANKOUT 60 144 4 SYNC PROCESSOR SYNC Cont d 4 4 6 Input Processing 4 4 6 1 Detecting Signal Presence The Sync Processor provides two ways of checking input signal presence by directly polling the LATR Latch Register or using the Timer interrupts Polling check Use the Latch Register LATR to detect the presence of HSYNCI VSYNCI CSYNCI HFBACK and VFBACK signals These latched bits are set when the falling edge of the corresponding signal is detected They are cleared by software Interrupts check Due to the fact that VSYNCI is connected to Timer Input Capture 1 and HSYNCI or CSYNCI is connected to Timer Input Capture 2 the Timer interrupts can be used to detect the presence of input signals Refer to the 16 bit Timer chapter for the description of the Timer registers To use the interrupt method
6. valid event the the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin When the value of the counter is equal to the value of the contents of the register the OLVL1 bit is output on the pin See Figure 35 Note The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Out put Compare interrupt The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one compare 1 Note IEDG1 1 OC1R 2EDOh OLVL1 0 OLVL2 1 49 144 ST72774 ST727754 ST72734 16 BIT TIMER Cont d 4 3 3 7 Pulse Width Modulation Mode Pulse Width Modulation mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the complete Output Compare 1 function plus the OC2R register Procedure To use pulse width modulation mode select the following in the CR1 register Using the OLVL1 bit select the level to be ap plied to the OCMP1 pin after a successful com parison with OC1R register Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin after a successful com parison with OC2R register And select the following in the CR2 register Set
7. 17271 0 0 1574 ST72774 ST72754 ST72734 8 BIT USB MCU FOR MONITORS WITH UP TO 60K OTP 1K ADC TIMER SYNC TMU PWM BRM H W DDC amp 12 User ROM OTP EPROM up to 60 Kbytes Data RAM up to 1 Kbytes 256 bytes stack 8 MHz Internal Clock Frequency in fast mode 4 MHz in normal mode Run and Wait CPU modes System protection against illegal address jumps and illegal opcode execution Sync Processor for Mode Recognition power management and composite video blanking clamping and free running frequency generation Corrector mode Analyzer mode USB Universal Serial Bus for monitor function Three endpoints Integrated 3 3V voltage regulator Transceiver Suspend and Resume operations Timing Measurement Unit TMU for autoposition and autosize Fast 12C Single Master Interface DDC Bus Interface with DDC1 2B protocol implemented in hardware Programmable DDC Cl modes Enhanced DDC EDDC address decoding 31 I O lines Device Summary Features ST72 1 E 774 J S 9 ST72 T 754 J S 9 ST72774 J S 7 ST72754 J S 7 ST72 T E 734J6 Program Memory Bytes on RAM stack Bytes 256 PSDIP42 TQFP44 10x 10 2 lines programmable as interrupt inputs 16 bit timer with 2 input captures and 2 output compare functions 8 bit Analog to Digital Converter with 4 channels on port B 8 10 bit PWM BRM Digital to Analog outputs Master Reset and Low
8. Since the stack is 256 bytes deep the most significant byte is forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruction RSP the Stack Pointer contains its reset value the SP7 to SPO bits are set which is the stack higher address Figure 6 Stack Manipulation Example T72774 ST727754 ST 72734 The least significant byte of the Stack Pointer called S can be directly accessed by a LD instruction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit without indicating the stack overflow The previously stored information is then overwritten and therefore lost The stack also wraps in case of an underflow The stack is used to save the return address during a subroutine call and the CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instructions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 6 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an interrupt five locations in the stack area CALL Subroutine Interrupt event Stack Higher Address 01FFh Stack Lower Address
9. fast mode see note Clock System section RUM CLMPEN Pull Up Resistor if existing VFBACK VR02071C 56 144 4 SYNC PROCESSOR SYNC Conta 4 4 3 Input Signals The Sync Processor has the following inputs TTL level VSYNCI1 Vertical Sync input1 HSYNCI1 Horizontal Sync input or Composite sync VSYNCI2 Vertical Sync input2 HSYNCI2 Horizontal Sync input2 or Composite sync Note The above input pairs can be used for DSUB or BNC connectors To select these inputs use the HVSEL bit in the POLR register CSYNCI Sync on Green external extractor Note If the CSYNCI is needed for another I O func tion the composite sync signal can be connected to HSYNCI using the SCIO bit in the MCR register HFBACK Horizontal Flyback input VFBACK Vertical Flyback input 4 4 4 Input Signal Waveforms The input signals must contain only synchroniza tion pulses In case of serration pulses on CSYN CI HSYNCI the pulse width should be less than 8us The VSYNCI signal is internally connected to Timer Input Capture 1 ICAP1 The HSYNCI or CSYNCI signal prescaled by 256 is internally connected to Timer Input Cap ture 2 ICAP2 Typical timing range See Figure 38 and 39 If the timer clock is 2 MHz external oscillator fre quency 24 MHz PV accuracy 1 Timer clock 500ns PH 256 accuracy 1 Timer clock 500ns PV Vertical pulse PH
10. Select Input Capture1 edge detection IEDG1 bit in the Timer CR1 register Select Input Capture 2 edge detection must be falling edge IEDG2 bit 0 in the Timer CR2 register Enable Timer Input Capture interrupts ICIE bit in the Timer CR1 register Select the Hsync and Vsync input signals HVSEL bit in the POLR register Enable the prescaler for HSYNCI or CSYNCI signal PSCD bit in the CCR register Select the normal mode LCV1 LCVO bits in the CCR register Perform any of the following Check for VSYNCI presence by monitoring inter rupt requests from Timer ICAP1 When VSYNCI is detected then either detect the VSYNCI polar ity or check for HSYNCI presence Check for HSYNCI presence by monitoring inter rupt requests from Timer ICAP2 On detecting HSYNCI either detect its polarity or check if the composite sync on HSYNCI pin is detected or check for CSYNCI presence ky T72774 ST727754 ST 72734 Check for CSYNCI presence by monitoring inter rupt requests from Timer ICAP2 4 4 6 2 Measuring Sync Period To measure the sync period the Sync processor block uses the Timer Input Capture interrupts ICAP1 connected to VSYNCI signal ICAP2 connected to HSYNCI CSYNCI signal with a 256 prescaler Calculating the difference between two subsequent Input Captures 16 bit value gives the period for 256xPH horizontal period and PV vertical period The period accuracy is
11. POTS m To OOS EO Z Z S O lt 5585 gt m LL gt HSYNCDIV AV PC1 PWM3 2 PWM4 PWM5 PC4 PWM6 5 PWM7 PWM8 PWM2 AIN3 PB7 PWM1 AIN2 PB6 AIN1 PB4 Vpp USBVCC USBDM USBDP Vss HSYNCI VSYNCI VSYNCO PDO HSYNCO PD1 1 2 3 4 5 6 T 8 NC Not connected CLAMPOUT PD6 O PA2 VSYNCI2 4 OSCIN OSCOUT BLANKOUT SDAI PB2 SCLI 1 SDAD SCLD PBO L E OCMP1 TEST RESET PA1 PA2 VSYNCI2 PA3 4 5 OSCIN OSCOUT PA7 BLANKOUT PB3 SDAI PB2 SCLI PB1 SDAD PB0 SCLD PD6 CLAMPOUT PD5 HFBACK PD4 ITB PD3 ITA VFBACK PD2 CSYNCI ky 7 144 ST72774 ST727754 ST72734 PIN DESCRIPTION Cont d RESET Bidirectional This active low signal forces the initialization of the MCU This event is the top priority non maskable interrupt This pin is switched low when the Watchdog has triggered or Vpp is low It can be used to reset external peripherals OSCIN OSCOUT Input Output Oscillator TEST Vpp Input EPROM programming voltage This pin must be held low during normal operating modes Vpp Power supply voltage 4 0V 5 5V Vss Digital Ground Alternate Functions several pins of the I O ports
12. Highest TRAP Sofware NA n FFFCMFFFDh USB Suspend Interrupt USBISTR ESUSP FFFAh FFFBh DDCSR1 poo _ 006891 00 1 2 00 1 2 Interrupt DDCDCR FFF6h FFF7h FFF7h Port D bit 4 External Interrupt ITB MISCR ELM FFF5h Port D bit 3 External Interrupt ITA ITALAT FFF2h FFF3h Input Capture 1 Input Capture2 ICF2 FFF0h FFF1h 1 TIMSR OCF1 2 FFEEh FFEFh Timer L Sa UE NES FFECh FFEDh Peripheral Inter I2CSR1 SB Lowest U nterrupt USBISTR FFE6h FFE7h Priority Many flags can cause an interrupt see peripheral interrupt status register description 24 144 3 4 POWER SAVING MODES 3 4 1 WAIT Mode This mode is a low power consumption mode The WFI instruction places the MCU in WAIT mode The internal clock remains active but all CPU processing is stopped however all other peripherals are still running Note In WAIT mode DMA accesses DDC USB are possible During WAIT mode the bit in the condition code register is cleared to enable all interrupts which causes the MCU to exit WAIT mode causes the corresponding interrupt vector to be fetched the interrupt routine to be executed and normal processing to resume A reset causes the program counter to fetch the reset vector and processing starts as for
13. The status of the EXEDG bit determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter The counter is synchronised with the falling edge of the internal CPU clock At least four falling edges of the CPU clock must occur between two consecutive active edges of the external clock thus the external clock frequency must be less than a quarter of the CPU clock frequency 43 144 ST72774 ST727754 ST72734 16 BIT TIMER Cont d Figure 28 Counter Timing Diagram internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 29 Counter Timing Diagram internal clock divided by 4 ceuaoc INTERNAL CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 30 Counter Timing Diagram internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF 4 44 144 16 TIMER 4 3 3 3 In this section the index i 1 2 The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free running counter after a transition detected by the ICAPipin see figure 5 MS Byte ICiR ICiHR LS Byte ICiLR Rregister is a read only register The active transition is software programmable through the IEDGibit of the
14. oo foss oss foso os Number of Pins 44 140 144 4 8 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics 8 1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options if any The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file in S19 format generated by the development tool All Figure 82 Sales Type Coding Rules Family Version Code ST72774 ST727754 ST 72734 unused bytes must be set to 9Dh opcode for NOP The selected mask options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points Subfamily with x subset index Number of pins ROM size Package Temperature Range ROM Code three letters 0 25 Plastic 9 60K J 42pins No letter ROM 1 Standard 0 to 70 C D Ceramic DIP 7248K S 44pins ____________ 6 O Table 35 Development Tools Development Tool Real time Emulator ST727x4 EMU2B 220V P Supply EU EPROM Programmer Board ST727x4 EPB xx ower Supply 110V Power Supply US Gana Programmer ST72E774 G
15. 39 Port A1 36 40 RESET Reset pin Active low 38 42 PAO OCMP1 Port AO TIMER output compare 1 4 9 144 ST72774 ST727754 ST72734 1 3 MEMORY MAP Figure 3 Memory Map HW Registers 0060 Short Addressing see Table 2 RAM zero page 512 Bytes 256 Bytes Stack 16 bit Addressing RAM 1 Kbyte RAM Short Addressing Reserved RAM zero page 256 Bytes Stack 16 bit Addressing RAM 48 K 8 Kbytes 16 bit Addressing 32 Kbytes Interrupt amp Reset Vectors 512 Bytes see Table 3 any opcode fetch in those areas is considered as illegal and generates a reset this block only contains addresses of interrupts and reset routines no opcode is run from this block ky 10 144 ST72774 81727754 8172734 MEMORY MAP Cont d Table 2 Hardware Register Memory Map Address 0000h 0001h 0002h 0003h R W R W 0004h R W 0006h R W 0008h 0009h 000Ch DDC1 2B DDCDCR DDC1 2B Control Register R W 000Dh DDCAHR DDC1 2B Address Pointer High Register R W R W 000Eh TMUCSR TMU control status register FCh 000Fh T TMUT1CR TMU T1 counter register FFh Read only 00010h TMUT2CR TMU 2 counter register FFh Read only x 000Ah ADC Read only 000Bh R W MU TIMCR2 Timer Control Register 2 R W TIMCR1 Timer Control Register 1 R W TIMSR Timer Status Register Read only TIMIC1HR Timer Input Capture 1 High Register Read only
16. Bit 6 DTOG TX Data Toggle for transmission transfers It contains the required value of the toggle bit O DATAO 1 1 for the next transmitted data packet This bit is set by hardware at the reception of a SETUP PID DTOG TX toggles only when the transmitter has received the ACK signal from the USB host DTOG TX and also DTOG RX see EPnRB are normally updated by hardware at the receipt of a relevant PID They can be also written by software 4 T72774 ST727754 ST 72734 Bits 5 4 STAT_TX 1 0 Status bits for transmission transfers These bits contain the information about the endpoint status which are listed below STAT Meaning DISABLED transmission transfers cannot be execut ed STALL the endpoint is 1 stalled and all transmission requests result ina STALL handshake NAK the endpoint is naked 1 all transmission quests result hand shake VALID this endpoint is ena 1 1 n bled for transmission These bits are written by software Hardware sets the STAT TX bits to NAK when a correct transfer has occurred CTR 1 related to a IN or SETUP transaction addressed to this endpoint this allows the software to prepare the next set of data to be transmitted Bits 3 0 TBC 3 0 Transmit byte count for Endpoint n Before transmission after filling the transmit buffer software must write in the TBC field the transmit packet size expressed in bytes
17. EVF Event flag This bit is set by hardware as soon as an event occurs It is cleared by software reading SR2 register in case of error event or as described in Figure 67 It is also cleared by hardware when the interface is disabled PE 0 0 No event 1 One of the following events has occurred BTF 1 Byte received or transmitted ADSL 1 Address matched in Slave mode while ACK 1 AF 1 No acknowledge received after byte transmission if ACK 1 STOPF 1 Stop condition detected in Slave mode BERR 1 Bus error misplaced Start or Stop condition detected Bit 6 Reserved Forced to 0 by hardware Bit 5 TRA Transmitter Receiver When is set TRA 1 if a data byte has been transmitted It is cleared automatically when BTF is cleared It is also cleared by hardware after detection of Stop condition STOPF 1 or when the interface is disabled PE 0 0 Data byte received if BTF 1 1 Data byte transmitted 4 T72774 ST727754 ST 72734 Bit 4 BUSY Bus busy This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition It indicates a communication in progress on the bus This information is still updated when the interface is disabled PE 0 0 No communication on the bus 1 Communication ongoing on the bus Bit 3 BTF Byte transfer finished This bit is set by hardware as soon as a byte is correctly received or transmitted with interru
18. Figure 52 STOP CONDITION VR02119B 87 144 ST72774 ST727754 ST72734 SINGLE MASTER BUS INTERFACE Cont d Acknowledge may be enabled and disabled by software The speed of the 12 interface may be selected between Standard 0 100 2 and Fast 2 100 400 2 SDA SCL Line Control Transmitter mode the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register Receiver mode the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register Figure 53 12C Interface Block Diagram DATA CONTROL CLOCK CONTROL CLOCK CONTROL REGISTER CCR CONTROL REGISTER CR STATUS REGISTER 1 SR1 STATUS REGISTER 2 SR2 88 144 SCL frequency Fg is controlled by programmable clock divider which depends on the 2 bus mode When the 2 cell is enabled the SDA and SCL ports must be configured as floating open drain output or floating input In this case the value of the external pull up resistance used depends on the application When the 2 cell is disabled the SDA and SCL ports revert to being standard I O port pins DATA REGISTER DR DATA SHIFT REGISTER CONTROL LOGIC INTERRUPT SINGLE MASTER BUS INTERFACE Cont d 4 7 4 Functional Description Master Mode Refer to the CR SR1 and SR2 registers in Section 4 7 5 for the bit
19. TIMIC1LR Timer Input Capture 1 Low Register Read only TIMOC1HR Timer Output Compare 1 High Register R W TIMOCA1LR Timer Output Compare 1 Low Register R W TIMCHR Timer Counter High Register Read only TIMCLR Timer Counter Low Register R W TIMACHR Timer Alternate Counter High Register Read only TIMACLR Timer Alternate Counter Low Register R W TIMIC2HR Timer Input Capture 2 High Register Read only TIMIC2LR Timer Input Capture 2 Low Register Read only TIMOC2HR Timer Output Compare 2 High Register R W TIMOC2LR Timer Output Compare 2 Low Register R W Reserved Area 5 bytes 11 144 ST72774 ST727754 ST72734 P Reset XXh USBPIDR USB PID Register Read only USBDMAR USB DMA address Register XXh R W USBIDR USB Interrupt DMA Register XXh R W USBISTR USB Interrupt Status Register 00h R W USBIMR USB Interrupt Mask Register 00h R W USBCTLR USB Control Register 0110 USBDADDR USB Device Address Register 00h R W USBEPORA USB Endpoint 0 Register A 0000 xxxx ray USBEPORB USB Endpoint 0 Register B 80h R W USBEP1RA USB Endpoint 1 Register A 0000 xxxx USBEP1RB USB Endpoint 1 Register B es R W USBEP2RA USB Endpoint 2 Register A 0000 R W USBEP2RB USB Endpoint2 Register B 0000 R W 10 BIT PWM PWM output enable register Reserved Area 1 byte SYNCCFGR SYNC Configuration Register SYNCMCR SYNC Multiplexer Register SYNCCCR SYNC Counter Register SYNCPOLR SYNC Polarity Register SYNCLATR SYNC Latch Regis
20. The measurement starts in setting HACQ by software When this bit is cleared by hardware the HGENR register returns the result The algorithm is shown in Figure 45 HLow 255 HGENR 1 4 us Note HLow maximum value 641 even if real value is greater 4 maximum it is possible to measure the low level of with the same technique FBSEL bit in the MCR register Figure 45 Horizontal Low Level Measurement Disable H correction Mode 2FHINH 0 Disable H internal generation HVGEN 0 Necessary if Signals HSYNCO Positive polarity are HVSYNCO Select HVBACK or H VSYNCO FBSEL 0 or 1 HACQ 1 Start measurement gt Yes HGENR Result END VR02118A 65 144 ST72774 ST727754 ST72734 SYNC PROCESSOR SYNC Cont d 4 4 8 2 Vertical Output Measurement The function of vertical pulse measurement is to Capture the number of HSYNCO pulses during a Low level of VSYNCO Capture the number of HFBACK pulses during a Low level of VFBACK maximum accuracy Start the measurement by setting VACQ in the CFGR When the measurement is completed this bit is cleared by hardware The VGENR and CFGR registers return the result The algorithm is shown in Figure 46 HLine 2048 V1 bits Hline maximum value 2048 even if real value is greater Viibits VGENR 8 MSB and Q 2 Q 1 Q 0 3 LSB Refer to Figure 44 Note In case of pre post equalization pulses set the 2F
21. VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT Bit 7 CSYN Detection of pulses on CSYNCI Set on falling edge of CSYNCI Cleared by software by writing zero Bit 6 HSYN Detection of pulses on HSYNCI Set on falling edge of HSYNCI1 or HSYNCI2 Cleared by software by writing zero Bit 5 VSYN Detection of pulses on VSYNCI Set on falling edge of VSYNCI1 or VSYNCI2 Cleared by software by writing zero Bit 4 HFLY Detection of pulses on HFBACK Set on falling edge of HFBACK input Cleared by software by writing zero Bit 3 VFLY Detection of pulses on VFBACK Set on falling edge of VFBACK input Cleared by software by writing zero Bit 2 UPLAT Detection of the maximum value of 5 bit up down counter Set when the 5 bit up down counter reaches its maximum value 1Fh or Threshold Cleared by software by writing zero 4 T72774 ST727754 ST 72734 Bit 1 DWNLAT Detection of minimum value of 5 bit up down counter Set when the 5 bit up down counter reaches its minimum value 00 or Threshold Cleared by software by writing zero Note DWNLAT and UPLAT may be used for HSYNCI po larity detection and Composite Sync detection as follows UPLAT DWNLAT HSYNCI Characteristics 0 o 1 0 _ Bit 0 2FHLAT equalization pulses latch This bit may be used to detect pre postequalization pulses or a too high horizontal frequency Set by hardware when Pre Post equalization pulses ar
22. reset value 1 The content of the free running counter has matched the content of the OC1R register To clear this bit first read the SR register then read or write the low byte of the OC1R OC1LR register Bit 5 TOF Timer Overflow 0 No timer overflow reset value 1 The free running counter rolled over from FFFFh to 0000h To clear this bit first read the SR register then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 Input Capture Flag 2 0 No input capture reset value 1 An input capture has occurred To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR regis ter Bit 3 OCF2 Output Compare Flag 2 0 No match reset value 1 The content of the free running counter has matched the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR register ky T72774 ST727754 ST 72734 Bit 2 0 Unused INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the input capture 1 event 7 0 MSB LSB INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the input
23. single Master Mode End of byte transmission flag Transmitter Receiver flag Clock generation 4 7 3 General Description In addition to receiving and transmitting data this interface converts it from serial to parallel format and vice versa using either an interrupt or polled handshake The interrupts are enabled or disabled by software The interface is connected to the 2 bus by data pin SDAI and by a clock pin SCLI It can be connected both with a standard I C bus and Fast 12 bus This selection is made by software Figure 52 2 BUS Protocol START CONDITION 4 172774 1727754 172734 Mode Selection The interface can operate in the two following modes Master transmitter receiver By default it is idle The interface automatically switches from idle to master after it generates a START condition and from master to idle after it generates a STOP condition Communication Flow The interface initiates a data transfer and generates the clock signal A serial data transfer always begins with a start condition and ends with a stop condition Both start and stop conditions are generated by software Data and addresses are transferred as 8 bit bytes MSB first The first byte following the start condition is the address byte A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to
24. 2 2 MAIN FEATURES ERREUR TUER AERE ex RU Datos u E Re REC HL Ea 15 2 9 GPU REGISTERS ii RS DENM ua 15 3 CLOCKS RESET INTERRUPTS amp LOW POWER MODES 18 GLOCK SYSTEM oobis xe ED nie ced ee axe sre ese de 18 3 1 1 General Description us essi d E REGE XI RE TA Kaa eatin 18 3 1 2 Crystal Resonator un e Rt RO S RIS RU EORR DEOR RC g 19 3 1 3 External Glock eias d dre RUE e s miei ear pd eun qe 19 2 2 iore eni iue been ER EE ERE AR a etude SB ded ultus git 20 3 2 1 LVD and Watchdog Reset 20 3 2 2 External Reset 2 2 24 essel eedem Ee RR ee exce e hd 20 3 2 3 Illegal Address Detection 20 3 2 4 Illegal Opcode Detection 20 3 3 INTERRUPTS ended Ee etg eda ARTE Rd 22 3 4 POWER SAVING MODES 25 SAM WAIT MOIE as ecu Ru Eee Rr RU 25 3 4 2 HALT MOJE Et VERUS AIRE AFER bodes 25 3 5 MISCELLANEOUS REGISTER 26 4 ON CHIP PERIPHERALS 2 22 ede ace caine eee 27 4d WO SSL ites pu au k uya Nate Als 27 4 1 1 Introduction em 27 4 1
25. 64 N x 64 increment 118 144 q 172774 1727754 172734 PWM BRM GENERATOR Figure 73 Simplified Filtered Voltage Output Schematic with BRM added VDD PWMOUT 0v VDD OUTPUT VOLTAGE OV BRM EXTENDED PULSE Figure 74 Graphical Representation of 4 Bit BRM Added Pulse Positions BRM VALUE PWM Pulse Number 0 15 0001 bit0 1 wx 6g _ get gg E Examples 0110 0001 bitO 1 119 144 ST72774 ST727754 ST72734 PWM BRM GENERATOR Cont d 4 9 3 2 PWM BRM OUTPUTS The PWM BRM outputs are assigned to dedicated pins If necessary these pins can be used in push pull or open drain modes under software control In these pins the PWM BRM outputs are connected to a serial resistor which must be taken into account to calculate the RC filter Figure 75 Precision for PWM BRM Tuning for VOUTEFF After filtering M 1 E 4 60 61 62 63 164 STEPS OF Vp h PWM UNE E e 4 Bit 2 XR m BRM 1 1 457 0 P 16 sub steps of VDD each or 1024 PME 2 40 50 63 E HHHH Aden m sub steps of 200 each 120 144 yy PWM BRM GENERATOR 4 9 4 Register Description 4 9 4 1 PWM BRM REGISTERS On channel basis the 10 bits are separated into two data registers A 6 bit PWM reg
26. At system reset the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests 1 Initialize the DMAR IDR and IMR registers choice of enabled interrupts address of DMA buffers Refer the paragraph titled initializing the DMA Buffers 2 Initialize the EPORA and EPORB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration Refer to the para graph titled Endpoint Initialization 3 When addresses are received through this channel update the content of the DADDR 4 If needed write the endpoint numbers in the EA fields in the EP1RB and EP2RB register 4 6 5 2 Initializing DMA buffers The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes They can be placed anywhere in the memory space typically in RAM to enable the reception of messages The 10 most significant bits of the start of this memory area are specified by bits DA15 DA6 in registers and IDR the remaining bits are 0 The memory map is shown in Figure 51 Each buffer is filled starting from the bottom last 3 address bits 000 up 4 6 5 3 Endpoint Initialization To be ready to receive Set STAT RX to VALID 11b in EPORB to enable reception To be ready to transmit 1 Write the data in the DMA transmit buffer 2 In register EPnRA specify the number of bytes to be transmitted in the TBC field 172774 1727754 172734 3 En
27. Bit 7 Reserved Forced by hardware to 0 Bits 6 0 These bits are mask bits for all interrupt condition bits included in the ISTR Whenever one of the IMR bits is set if the corresponding ISTR bit is set and the bit in the CC register is cleared an interrupt request is generated For an explanation of each bit please refer to the corresponding bit description in ISTR CONTROL REGISTER CTLR Read Write Reset Value 0000 0110 06h 7 0 0 RESUME PDWN SUSP FRES Bits 7 4 Reserved Forced by hardware to 0 Bit 3 RESUME Resume This bit is set by software to wake up the Host when the ST7 is in suspend mode 0 Resume signal not forced 1 Resume signal forced on the USB bus 82 144 Software should clear this bit after the appropriate delay Bit 2 PDWN Power down This bit is set by software to turn off the 3 3V on chip voltage regulator that supplies the external pull up resistor and the transceiver 0 Voltage regulator on 1 Voltage regulator off Note After turning on the voltage regulator software should allow at least 3 us for stabilisation of the power supply before using the USB interface Bit 1 SUSP Suspend mode This bit is set by software to enter Suspend mode 0 Suspend mode inactive 1 Suspend mode active When the hardware detects USB activity it resets this bit it can also be reset by software Bit 0 FRES Force reset This bit is set by software to forc
28. CONSIDERATIONS 1 2 133 6 2 AC DC ELECTRICAL CHARACTERISTICS 134 GENERAL INFORMATION 139 7 1 PACKAGE MECHANICAL 139 8 ORDERING INFORMATION 141 8 1 TRANSFER OF CUSTOMER 141 4 144 4 172774 1727754 172734 Revision follow up Changes applied since version 4 0 Version 4 0 Version 4 1 Version 4 2 Version 4 3 Version 4 3 March 2001 Page 1 Addition of 727774 32KOTP Addition of 60 K 48K ROM for 5772754 Deletion of table device summary replaced with cross reference to table 36 on page 147 page 13 addition of section 1 4 external connections July 2001 Initial format reapplied text and related figures in the same page Table Device summary reinserted in cover page and updated Update of table 36 ordering information p143 July 2001 Cover addition of feature about system protection added table for device summary addition of stack values page 9 figure 3 replaced 1KByte with 512 Bytes notes about opcode fetch and HALT mode page 10 table CR replaced by WDGCR TIM replaced with Timer and WDG replaced with Watchdog page 115 EDF register addition of from RAM EDE few changes page
29. Description 4 9 3 1 PWM BRM The 10 bits of the 10 bit PWM BRM are distributed as 6 PWM bits and 4 BRM bits The generator consists of a 12 bit counter common for all channels a comparator and the PWM BRM generation logic Figure 69 PWM Generation PWM Generation The counter increments continuously clocked at internal CPU clock Whenever the 6 least significant bits of the counter defined as the PWM counter overflow the output level for all active channels is set The state of the PWM counter is continuously compared to the PWM binary weight for each channel as defined in the relevant PWM register and when a match occurs the output level for that channel is reset This Pulse Width modulated signal must be filtered using an external RC network placed as close as possible to the associated pin This provides an analog voltage proportional to the average charge passed to the external capacitor Thus for a higher mark space ratio High time much greater than Low time the average output voltage is higher The external components of the RC network should be selected for the filtering level required for control of the system variable Each output may individually have its polarity inverted by software and can also be used as a logical output COUNTER OVERFLOW COMPARE VALUE 000 63 Je S S s s s e s e n n OVERFLOW OVERFLOW PWM OUTPUT 1 t Tceu X 64 116 144 4 PWM BRM Outpu
30. Function 2 enable CH 2 0 000 ADCCSR With pull up Push pull Analog input ADC without pull up CH 2 0 001 ADCCSR Analog input ADC without pull up CH 2 0 010 ADCCSR With pull up Push pull 10 bit output 1 PWM OE0 1 PWMOE Analog input without pull up CH 2 0 011 ADCCSR 10 bit output 2 PWM OE1 1 PWMOE ithout pull up Open drain Without pull up Open drain With pull up Push pull Reset state 4 31 144 ST72774 ST727754 ST72734 PORTS Cont d Figure 19 PB0 to PB3 Alternate enable Alternate 1 N BUFFER DATA BUS Alternate enable CMOS Schmitt Trigger Alternate input Figure 20 PB4 to PB7 P BUFFER Analog enable ADC DATA BUS Common Analog Rail O O Analog DDR SEL switch lt 3 N BUFFER Vss lt a CMOS Schmitt Trigger 32 144 4 ST72774 ST727754 ST72734 PORTS Conta 4 1 5 Port C The alternate functions are the PWM outputs for The available port pins of port may be used PC2 7 HSYNCDIV HSYNCO divided by 2 for general purpose PCO and the TMU input for PC1 Table 10 Port C Description With pull up Push pull HSYNCDIV push pull ge With pull up Push pull AV active video input TMU With pull up Push pull 10 bit output 3 PWM 1 PWMOE With pull up Push pull 10 bit output 4 PWM POE 4 1 4 With pull up Push pull 10 bit output 5 P
31. ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled 0 The SCL line is not held low while 1 0 No acknowledge failure 1 Acknowledge failure Bit 3 STOPF Stop detection This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge if 1 An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while STOPF 1 0 No Stop condition detected 1 Stop condition detected Bit 2 Reserved Forced to 0 by hardware 112 144 Bit 1 BERR Bus error This bit is set by hardware when the interface detects a misplaced Start or Stop condition An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while 1 0 No misplaced Start or Stop condition 1 Misplaced Start or Stop condition Bit EDDCF Enhanced address detected This bit is set by hardware when the Enhanced DDC address 60h 61h is detected on the bus while EDDCEN 1 It is cleared by hardware when a Start or a Stop condition STOPF 1 is detected or when the interface is disabled 0 0 No Enhanced DDC address detected on bus 1 Enhanced DDC address detected on bus 4 DDC INTERFACE Cont d DDC DATA REGISTER DR Read Write R
32. No error detected 1 Timeout CRC bit stuffing or nonstandard framing error detected Bit 3 IOVR nterrupt overrun This bit is set when hardware tries to set ERR ESUSP or SOF before they have been cleared by software 0 No overrun detected 1 Overrun detected Bit 2 ESUSP End suspend This bit is set by hardware when during suspend mode activity is detected that wakes the USB interface up from suspend mode This interrupt is serviced by a specific vector 0 No End Suspend detected 1 End Suspend detected Bit 1 RESET USB reset This bit is set by hardware when the USB reset sequence is detected on the bus 0 No USB reset signal detected 1 USB reset signal detected Note The DADDR EPORA EPORB EP1RA EP1RB 2 and EP2RB registers are reset by a USB reset 81 144 ST72774 ST727754 ST72734 USB INTERFACE Cont d Bit 0 SOF Start of frame This bit is set by hardware when a low speed SOF indication keep alive strobe is seen on the USB bus 0 No SOF signal detected 1 SOF signal detected Note To avoid spurious clearing of some bits it is recom mended to clear them using a load instruction where all bits which must not be altered are set and all bits to be cleared are reset Avoid read modify write instructions like AND XOR INTERRUPT MASK REGISTER IMR Read Write Reset Value 0000 0000 00h 7 0 DOV CTR ERR IOVR ESU RES SOF RM M M M SPM ETM M
33. PD5 VDD P BUFFER e D m lt lt N BUFFER gt Vss alternate input a CMOS Schmitt Trigger CSYNCI Input HFBACK Input VFBACK Input TTL Schmitt Trigger Figure 24 PDO to PD1 Alternate enable Alternate P BUFFER DATA BUS Alternate enable Alternate enable Vss Alternate input CMOS Schmitt Trigger 36 144 q 172774 1727754 172734 PORTS Cont d Figure 25 PD6 Alternate enable Alternate VDD P BUFFER DATA BUS Alternate enable Alternate enable Vss Alternate input CMOS Schmitt Trigger VSYNCI2 input TTL Schmitt Trigger 4 37 144 ST72774 ST727754 ST72734 PORTS Cont d 4 1 7 Register Description Data Registers PxDR Read Write Reset Value 0000 0000 00h Data Direction Registers PxDDR Read Write Reset Value 0000 0000 00h as inputs 7 0 7 0 l ETT MSB LSB Table 12 I O Ports Register Map Address Register z Name PADR u 25 E o mo ue E o ws SSCS w wm wa c ws 1s o pn ws us w rover wa s 38 144 4 2 WATCHDOG WDG 4 2 1 Introduction Watchdog timer is used to detect the occurrence of a software fault usually generated by external interference or by unforeseen logical conditions which causes the application program to abandon its nor
34. bit the OCMP1 pin is then dedicated to the output compare 1 function Set the PWM bit Select the timer clock CC1 CC0 see Table 15 Clock Control Bits Load the OC2R register with the value corresponding to the period of the signal Load the register with the value corresponding to the length of the pulse if OLVL1 0 and OLVL2 1 If OLVL1 1 OLVL2 0 the length of the pulse is the difference between the OC2R and OC1R registers Figure 36 Pulse Width Modulation Mode Timing 34E2 COUNTER OCMP1 compare2 The register value required for a specific timing application can be calculated using the following formula 1 5 Value Where t Desired output compare period seconds Internal clock frequency see Miscella neous register CC1 CCO Timer clock prescaler The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 36 Pulse Width Modulation cycle OCMP1 OLVL1 OCMP1 OLVL2 Counter is reset to FFFCh Note After a write instruction to the OC HR register the output compare function is inhibited until the OC LR register is also written The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited The Input Capture interrupts are available When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode
35. capture 1 event 7 0 MSB LSB OUTPUT COMPARE 1 OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 mimi LOW REGISTER HIGH REGISTER OUTPUT COMPARE 1 OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of 53 144 ST72774 ST727754 ST72734 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 E 7 OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 EX LE COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 COUNTER LOW REGISTER CLR Read Write Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 54 144 7 0 miss ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the
36. configured as an analog input at any time The user must avoid any situation in which more than one I O pin is selected as an analog input simultaneously to avoid device malfunction When the analog function is selected for an I O pin the pull up of the respective pin of Port B is disconnected and the digital input is off Table 9 Port B Description ithout pull up Open drain KUN With pull up Push pull SCLD input with CMOS schmitt trigger or open drain output n SDAD input with CMOS schmitt trigger Without pull up open drain output input with CMOS schmitt trigger or open drain output SDAI input with CMOS schmitt trigger or open drain output Analog input ADC without pull up T72774 ST727754 ST 72734 All unused lines should be tied to an appropriate logic level either Vpp or Vss Since the ADC is on the same chip as the microprocessor the user should not switch heavily loaded signals during conversion if high precision is required Such switching will affect the supply voltages used as analog references the accuracy of the conversion depends on the quality of the power supplies Vpp and Vss The user must take special care to ensure that a well regulated reference voltage is present on the Vpp and Vss pins power supply variations must be less than 5V ms This implies in particular that a suitable decoupling capacitor is used at the Vpp pin Alternate
37. functions To enable the IC interface write the CR register TWICE with PE 1 as the first write only activates the interface only PE is set Bit 4 EDDCEN Enhanced DDC address detection enabled This bit is set and cleared by software It is also cleared by hardware when the interface is disabled 0 The 60h 61h Enhanced DDC address is acknowledged 0 Enhanced DDC address detection disabled 1 Enhanced DDC address detection enabled 110 144 Bit 3 Reserved Forced to 0 by hardware Bit 2 ACK Acknowledge enable This bit is set and cleared by software It is also cleared by hardware when the interface is disabled PE 0 0 No acknowledge returned 1 Acknowledge returned after an address byte or a data byte is received Bit STOP Release 2 bus This bit is set and cleared by software or when the interface is disabled 0 Slave Mode 0 Nothing 1 Release the SCL and SDA lines after the cur rent byte transfer BTF 1 The STOP bit has to be cleared by software Bit 0 nterrupt enable This bit is set and cleared by software and cleared by hardware when the interface is disabled PE 0 0 Interrupts disabled 1 Interrupts enabled Refer to Figure 68 for the relationship between the events and the interrupt SCL is held low when the BTF or ADSL is detect ed 4 DDC INTERFACE Cont d DDC STATUS REGISTER 1 SR1 Read Only Reset Value 0000 0000 00h 7 0 Bit 7
38. in the range 0 8 83 144 ST72774 ST727754 ST72734 USB INTERFACE Cont d ENDPOINT n REGISTER B EPnRB Read Write Reset Value 0000 xxxx 0xh 7 0 DTOG STAT STAT CTRL 2 1 These registers and 2 used for controlling data reception on Endpoints 1 and 2 They are also reset by the USB bus reset Note Endpoint 2 and the EP2RB register are not availa ble on some devices see device feature list and register map Bit 7 CTRL Control This bit should be 0 Note If this bit is 1 the Endpoint is a control endpoint Endpoint 0 is always a control Endpoint but it is possible to have more than one control Endpoint Bit 6 DTOG_RX Data toggle for reception transfers It contains the expected value of the toggle bit 0 1 DATA1 for the next data packet This bit is cleared by hardware in the first stage Setup Stage of a control transfer SETUP transactions start always with DATAO PID The receiver toggles only if it receives a correct data packet and the packet s data PID matches the receiver sequence bit Bit 5 4 STAT_RX 1 0 Status bits for reception transfers These bits contain the information about the endpoint status which are listed in the following table 84 144 m srat meaning DISABLED reception transfers cannot be executed the endpoint is stalled
39. instruction using X indexed ad dressing mode to an instruction using indirect X in dexed addressing mode PIY 91 Replace an instruction using X in direct indexed addressing mode by a Y one 129 144 ST72774 ST727754 ST72734 INSTRUCTION GROUPS Cont d Add with Carry E No gem APS 1 BO TUBRCORMAISA UA Bit Set bset Byte 3 BTJT Jump if bit is true btjt Byte 3 Jmp1 CALL Call subroutine BRES E 1 EM C ic Ee C D D P L R Arithmetic Compare tst Reg M reg IRET Interrupt routine return Pop A X PC EA B C C C D IN P Absolute Jump jp TBL w D D N C L P P E C A T CALLR Call subroutine relative il Jump relative always JRIH Jump if ext interrupt 1 MEE JRIL Jump if ext interrupt 0 Y U gt DL JR BTJF Jump if bit is false 0 btjf Byte 3 Jmp1 1 E pl ET ERN C A ___ e E E E mE MEN NEM Demio forse 130 144 M 172774 1727754 172734 INSTRUCTION GROUPS Cont d memo O TAT TTS ITI mes ewemwew pem ___ 0111101 XOR Exclusive OR A AXORM A M N Z 131 144 4 ST72774 ST727754 ST72734 6 ELECTRICAL CHARACTERISTICS The ST72
40. is the only active one When Counter When Counter OC2R compare1 compare2 Note OC1R 2ED0h OC2R 34E2 OLVL1 0 OLVL2 1 50 144 4 4 3 4 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the alternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 ICIE OCIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 Input Capture Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set 4 T72774 ST727754 ST 72734 Bit 4 FOLV2 Forced Output Compare 2 This bit is not cleared by software only by a chip reset 0 No effect 1 Forces the OLVL2 bit to be copied to the OCMP2 pin Bit 3 FOLV1 Forced Output Compare 1 This bit is not cleared by software only by a chip reset 0 No effect 1 Forces OLVL1 to be copied to the 1 pin Bit 2 OLVL2 Output Level 2 This bit i
41. pulse depends on the contents of the OC1R regis ter Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the 1 pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R reg ister the period depends on the value of OC2R register 52 144 Bit 3 2 CC1 CCO Clock Control The value of the timer clock depends on these bits Table 15 Clock Control Bits CC1 CCO Timer Clock External Clock where 1 1 1 available Bit 1 IEDG2 Input Edge 2 This bit determines which type of level transition the ICAP2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK will trigger the free running counter 0 A falling edge triggers the free running coun ter 1 A rising edge triggers the free running coun ter 4 16 BIT TIMER Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 pepe Bit 7 ICF1 Input Capture Flag 1 0 No input capture reset value 1 An input capture has occurred To clear this bit first read the SR register then read or write the low byte of the IC1LR regis ter Bit 6 OCF1 Output Compare Flag 1 0 No match
42. w Wap 56 4 4 2 Main Features ue sott vac ment a axe Sea ata PO pP 56 4 43 Inp ut Sigrials pele Paci a pare te Mo ee xS 57 4 4 4 Input Signal Waveforms 0 1 57 AA S Output Signals chee pida 57 4 4 6 Input Processing 61 AAT O tp t Processing 1 3 seda Oe ae ua et 64 4 4 8 Analyzer Mode sc gece Ede 65 4 4 9 Corrector Mode 67 4 4 10Register 68 4 5 TIMING MEASUREMENT UNIT TMU 75 AS A Introduction ga ass ene ee a ice hio 75 4 5 2 Mait T Gatil 6S Ea be prey us Lame vibra 75 4 5 3 Functional Description 75 4 5 4 Register Description 77 4 6 USB INTERFACE USB 79 4 621 INtrOGuction 2 ine ert Fade Y AA 79 4 6 2 Main Feat es ru Eat SUE dr dac E TUS rap 79 4 6 3 Functional Description 21 4 2 0 79 4 6 4 Register Description
43. when the interface is disabled PE 0 92 144 Following a byte transmission this bit is set after reception of the acknowledge clock pulse In case an address byte 1 sent this bit is set only after the EV2 event See Figure 54 BTF is cleared by reading SR1 register followed by writ ing the next byte in DR register Following a byte reception this bit is set after transmission of the acknowledge clock pulse if ACK 1 BTF is cleared by reading SR1 register followed by reading the byte from DR register The SCL line is held low while BTF 1 0 Byte transfer not done 1 Byte transfer succeeded Bit 2 Reserved Forced to 0 by hardware Bit 1 M IDL Master ldle This bit is set by hardware as soon as the interface is in Master mode writing START 1 It is cleared by hardware after generating a Stop condition on the bus It is also cleared when the interface is disabled PE 0 0 Idle mode 1 Master mode Bit 0 SB Start bit generated This bit is set by hardware as soon as the Start condition 15 generated following write START 1 An interrupt is generated if ITE 1 It is cleared by software reading SR1 register followed by writing the address byte in DR register It is also cleared by hardware when the interface is disabled 0 0 Start condition 1 Start condition generated q SINGLE MASTER BUS INTERFACE Cont d STATUS REGISTER 2 SR2 Read Only Reset Value 0000 0000
44. 00h 7 0 Bit 7 5 Reserved Forced to 0 by hardware Bit 4 AF Acknowledge failure This bit is set by hardware when no acknowledge is returned An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while AF 1 0 No acknowledge failure 1 Acknowledge failure Bit 3 0 Reserved Forced to 0 by hardware CLOCK CONTROL REGISTER CCR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 FM SM Fast Standard mode This bit is set and cleared by software It is not cleared when the interface is disabled PE 0 4 172774 1727754 172734 0 Standard 2 mode 1 Fast ZC mode Bit 6 0 CC6 CC0 7 bit clock divider These bits select the speed of the bus Fscu depending on the 2 mode They not cleared when the interface is disabled PE 0 Standard mode FM SM 0 lt 100kHz FscL Fopy 2x CC6 CC0 2 Fast mode FM SM 1 gt 100kHz FscL Fopy 3x CC6 CC0 2 Note The programmed assumes no load on SCL and SDA lines DATA REGISTER DR Read Write Reset Value 0000 0000 00h 7 0 or os os fos oe or oo Bit 7 0 D7 DO 8 bit Data Register These bits contains the byte to be received or transmitted on the bus Transmitter mode Byte transmission start auto matically when the software writes in th
45. 0100h 17 144 5772774 6 727754 5 72734 3 CLOCKS INTERRUPTS amp LOW POWER MODES 3 1 CLOCK SYSTEM 3 1 1 General Description The MCU accepts either a crystal or an external clock signal to drive the internal oscillator The internal clock CPU CLK running at fcpy is derived from the external oscillator frequency fosc which is divided by 3 Depending on the external quartz or clock frequency a division factor of 2 is optionally added to generate the 12 MHz clock for the Sync Processor clamp function as Figure 7 Clock divider chain FAST 1 for 24MHZ oscillator 18 144 shown in Figure 7 and a second divider by 2 for the 6MHz USB clock The CPU clock is used also as clock for the ST727x4 peripherals Note In the Sync processor an additional divider by two is added in fast mode same external timing for this peripheral fcpu 4 or 8 MHz CPU and peripherals 12 MHz Sync processor Clampout signal 6 MHz USB 12 MHz or 24MHz TMU FAST 0 for 12 MHz oscillator 4 CLOCK SYSTEM 3 1 2 Crystal Resonator The internal oscillator is designed to operate with an AT cut parallel resonant quartz crystal resonator in the frequency range specified for fosc The circuit shown in Figure 8 is recommended when using crystal and Table4 Recommended Crystal Values on page 19 lists the recommended capacitance and feedback resistance v
46. 135 Note 1 replaced note 2 added SUSpend mode limitation Whole document all mentions of HALT mode either deleted or rewritten October 2001 p140 chapter 8 section 8 1 code for unused bytes FFh replaced with 9Dh opcode for NOP page 141 update of table 36 Ordering information page 142 list of available devices updated page 114 DDC DCR register bit 5 1 text or read from RAM deleted November 2001 page 10 one adddress corrected in the figure 3 map 0400h page 14 addition of mandatory 1K resistor text and figure 5 144 ST72774 ST727754 ST72734 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST72774 ST72754 and ST72734 are HCMOS microcontroller units MCU from the ST727x4 family with dedicated peripherals for Monitor applications They are based around an industry standard 8 bit core and offer an enhanced instruction set The processor runs with an external clock at 12 or 24 MHz with a 5V supply Due to the fully static design of this device operation down to DC is possible Under software control the ST727x4 can be placed in WAIT mode thus reducing power consumption The HALT mode is no longer available The enhanced instruction set and addressing modes afford real programming potential Illegal opcodes are patched and lead to a reset Figure 1 ST727x4 Block Diagram In addition to standard 8 bit data management the ST7 features true bit manipulation 8x8 unsigned multiplication an
47. 1727754 8172734 Table 13 Watchdog Timing 8 MHz CR Register WDG timeout period initial value ms Max FFh 393 216 Min COh 6 144 Notes Following a reset the watchdog is disabled Once activated it cannot be disabled except by a reset The T6 bit can be used to generate a software reset the WDGA bit is set and the T6 bit is cleared 4 2 4 Interrupts None 4 2 5 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 WDGA T6 T5 T4 T8 T2 TO Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh becomes cleared Table 14 Watchdog Timer Register Map and Reset Values Address Register 7 1 Hex Label WDGCR WDGA T6 T5 T4 T3 T2 T1 TO Reset Value 0 1 1 1 1 1 1 1 40 144 4 4 3 16 4 3 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input signals input capture or generation of up to two output waveforms output compare and PWM Pulse lengt
48. 2 Common Functional Description 28 4 1 3 eR e t RE web eet de dore 29 4 4 uk EE a ee ee HE 31 4 1 5 Pott ES OA eed ee tei dey Ged de Ve e eee eet 33 4 1 6 Port D ini ne fh ds BG NEW ee 35 4 1 7 Register Description 1 38 4 2 WATCHDOG TIMER WDG 39 42 1 Introduction A oS Ree Sa ed 39 42 2 Main Features oe se he aa 39 4 2 3 Functional Description 1 4 39 4 2 4 cst Pals bh ote enti ROT etd 40 4 2 5 Register Description 40 4 3 16 BIT TIMER TIM deg eh ee tee asqa EP 41 4 31 Introduction cnl cin REI ae rca EY Issue Ee is 41 4 3 2 Mam Features issu Dag pk ppc ig 41 4 3 3 Functional Description 2 lt 2 2 41 4 3 4 Register 51 4 4 SYNC PROCESSOR SYNC 2 2 22 2 0 14 56 2 144 437 T72774 ST727754 ST 72734 4 41 Introductio gt saqin a aaa De DOR S hunu bh aves aca Rea ta ne
49. 34 SYNC PROCESSOR SYNC 4 4 7 Output Processing Configure the following bits 4 4 7 1 Generating Free Running Frequencies CP zn The free running frequencies function is used to HACQ 0 Drive the monitor when bad sync signals VACQ 0 Stabilize the OSD screen when the monitor is PH Horizontal period HGENR 1 4 us locked s Pulse width 2 us gt HGENR min 8 Perform fast alignment for maintenance purpos 4 es Polarity Positive Note When free running mode is active the analyzer HGENR range 8 255 and corrector modes must be disabled Vertical Period VCORDIS 1 VEXT 0 in CFGR and PV Vertical period PH V11bits us registers for vertical output measurement 2FHINH 0 in CFGR register for horizontal low level measurment VACQ 0 in CFGR register for ana V11bits is a concatenation of VGENR and the Q 2 Q 1 Q 0 bits of the CFGR register Refer to Figure 44 Pulse width 4 gt min value 8us lyzer mode N The Sync processor can generate any of the Polarity Positive following output sync signals HSYNCO VSYNCO VGENR CFGR range 5 7FF CLAMPOUT BLANKOUT To select the generation mode Program the horizontal period using the HGENR register Program the vertical period using the VGENR 8 bits and CFGR 3 bits registers 2047 scan lines per frame Refer to Figure 44 Table 17 Typical values for gen
50. 44 ST72774 ST727754 ST72734 USB DC Electrical Characteristics Symbol Inputs Levels YU UNU Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold VOH Output Levels Static Output Low Static Output High USBVCC voltage level USBV Vpo 5V Notes RL is the load connected on the USB drivers All the voltages are measured from the local ground potential USBGND Figure 78 USB Data signal Rise and fall time Differential Datas Lines Crossover VCRE da Points Note1 Measured from 10 to 90 of the data signal 138 144 4 172774 1727754 172734 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 79 42 Pin Shrink Plastic Dual In Line Package 600 mil Width mm inches repeh 0 009 0 010 0 015 zu ojo alo pm p LEAD DETAIL eA ___ 1524 Fe js ec po EN Sx a ojo efej alo N 60 e o M afore ramo pep 0 035 El CDIP42SW L 4 139 144 5772774 5 727754 5 72734 Figure 81 44 Thin Quad Flat Package 0 10mm D E 004 seating plane F _ UL IDENTIFICATION L1 fra pe oss oj pe
51. 7x4 device contains circuitry to protect the inputs against damage due to high static voltage or electric field Nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages lt 15 recommended for proper operation that Vin and Vout be constrained to the range Vss lt Vin OF Vout lt Table 33 Absolute Maximum Ratings Symbol Vpp Recommended Supply Voltage To enhance reliability of operation it is recommended to connect unused inputs to an appropriate logic voltage level such as Vgg or Vpp All the voltages in the following table are referenced to Vss Value 0 3 to 6 0 Input Voltage Vss 0 3 to Vpp 0 3 Analog Input Voltage A D Converter Output Voltage Vss 0 3 to Vpp 0 3 Vss 0 3 to Vpp 0 3 Output Current Accumulated injected current of all I O pins Vpp Operating Temperature Range Storage Temperature Range 65 to 150 ESD susceptibility 132 144 2000 4 6 1 POWER CONSIDERATIONS The average chip junction temperature Ty in degrees Celsius may be calculated using the following equation Ty Pp x 0J4 1 Where is the Ambient Temperature in C 0 is the Package Junction to Ambient Thermal Resistance in C W Pp is the sum of and is the product of lpp ang expressed in Watts This is the
52. B of ALR is always 0 DDC v2 P amp D mode CF 1 0 bits 10b 128 byte Data Structure gt 256 bytes Reserved 256 bytes 2 AHR 7 1 0000h DDC2B Transition Mode This mode avoids the display switching to DDC2B mode if spurious noise is detected SCL while the host is in DDC1 mode When the DDC1 2B interface is in DDC1 mode and detects a falling edge on SCL it enters the transition state see Figure 61 If a valid 122 sequence START followed by a valid Device Address for CFO 0 see Table 25 is not Figure 61 Transition Mode Waveforms Addr Pointer AHR 7 1 15 9 87 ALR Notes LSB of AHR is ignored and taken as 1 MSB of ALR is always 0 received within either 128 Vsync pulses or a period of approximately 2 seconds then the interface will revert to DDC1 mode at the EDID start address If the interface decodes a valid DDC2B Device Address it will lock into DDC2B mode subsequently disregard VSYNCI When in transition mode the Vsync pulse counter or the 2 sec timeout counter is reset by any activity on the SCL line DDC1 mode gt 4 Transition mode SCL o Kw ALR 6 X h SDA 4 101 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d DDC2B Mode DDC1 2B Interface enters DDC2B mode either from the transition state or from the initial state if software sets the HWPE bit while P amp D only or FPDI 2 mod
53. CK must be positive 76 144 q TIMING MEASUREMENT UNIT Cont d 4 5 4 Register Description CONTROL STATUS REGISTER TMUCSR Bit 7 2 Read only Bit 1 0 Read Write Reset Value 1111 1100 FCh Bit 7 5 T2 10 8 MSB of T2 Counter Most Significant Bits of the T2 counter value see T2 Counter register description Bit 4 2 T1 10 8 5 1 Counter Most Significant Bits of the T1 counter value see T1 Counter register description Bit 1 H_V Horizontal or Vertical Measurement This bit is set and cleared by software to select the type of measurement It cannot be modified while the START bit 1 measurement in progress 0 Vertical measurement 1 Horizontal measurement Bit 0 START Start measurement This bit is set by software and cleared by hardware when the measurements are completed It can not be cleared by software 0 Measurement done 1 Start measurement 4 172774 1727754 172734 T1 COUNTER REGISTER TMUT1CR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the low part of the counter value 7 0 sp When 1 measurement is finished rising edge on AV input the 11 bit counter value is transferred to this register and to the T1 10 8 bits in the CSR register T1 is H1 value if the H_V bit 1 T1 is V1 value if the H_V bit 0 T2 COUNTER REGISTER TMUT2CR Read Only Reset Value 1111 1111 FFh This is an 8 bit register t
54. Chip Internal Power represents the Power Dissipation on Input and Output Pins User Determined For most applications lt and may be neglected may be significant if the device is configured to drive Darlington bases or sink LED Loads Table 34 Thermal Characteristics 172774 1727754 172734 An approximate relationship between Pp and if Po is neglected is given by Pp K Ty 273 C 2 Therefore Pp x TA 273 C 0JA x Pp 3 Where Kis aconstant for the particular part which may be determined from equation 3 by measuring Pp at equilibrium for a known TA Using this value of K the values of Pp and Ty may be ob tained by solving equations 1 and 2 iteratively for any value of TA Symbol 4 133 144 ST72774 ST727754 ST72734 6 2 AC DC ELECTRICAL CHARACTERISTICS T 0 to 70 C unless otherwise specified GENERAL Conditions Mm RUN amp WAIT mode I O in input mode CPU WAIT mode 5 CPU HALT mode see Note 1 fcpu 8 MHz USB Suspend mode see Note 2 TA 20 Note 1 HALT mode no longer exists Note 2 The USB cell must be put in suspend mode as well as the MCU in HALT mode Since the latter no longer exists for enhanced arcing protection the measurement of the USB suspend consumption parameter is no longer relevant CONTROL TIMING Frequency of Operation external frequency internal frequency fosc 24MHz intern
55. Control Register CR Timing resolution is one count of the free running counter fcPU CC1 CC0 Procedure To use the input capture function select the following in the CR2 register Select the timer clock CC1 CC0 see Table 15 Clock Control Bits Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit And select the following in the CR1 register Set the ICIE bit to generate an interrupt after an input capture 172774 1727754 172734 Select the edge of the active transition the ICAP1 pin with the IEDG1 bit When input capture occurs ICFi bit is set The register contains the value of the free running counter on the active transition on the ICAP pin see Figure 32 A timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request is done by 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register After reading the ICiHR register transfer of input capture data is inhibited until the IC LR register is also read register always contains the free running counter value which corresponds to the most recent input capture 45 144 ST72774 81727754 81T72734 16 BIT TIMER Cont d Figure 31 Input Capture Block Dia
56. HINH bit in the CFGR register 4 4 8 3 Detection of pre equalization pulses This function uses two bits 2FHDET in POLR register continuously updated by hardware 2FHLAT LATR register set by hardware when a higher frequency is detected and reset by soft ware A measurement of the low level of HSYNCO is necessary before reading this information Note Reset the 2FHLAT bit in the LATR register on the third Hsync pulse after the Vsync pulse 66 144 Figure 46 Vertical Output Measurement No Measure H Lines Disable V correction Mode VCORDIS 1 0 Disable H internal generation HVGEN 0 H amp VSYNCO Positive polarity Select H VBACK or H VSYNCO FBSEL 0 or 1 VACQ 1 Start measurement Yes VGENR amp CFGR Result Necessary if Signals are H VSYNCO VR02118B 4 SYNC PROCESSOR SYNC 4 4 9 Corrector Mode In this mode you can perform the following functions Inhibit pre post equalization pulses This removes all pre post equalization pulses on the HSYNCO signal The inhibition starts on the falling edge of HSYNCO and lasts for HGENR 1 4 2 us The decrease of 2us one minimum pulse width avoids the removal of the next pulse of HSYNCO Procedure 1 HSYNCO and VSYNCO polarities must be positive 2 Measure the low level of HSYNCO 3 Set the 2FHINH bit in the CFGR register Extend VSYNCO pulse width by several scan lines This function can be also u
57. Horizontal pulse 4 T72774 ST727754 ST 72734 4 4 5 Output Signals The Sync Processor has the following outputs HSYNCO Horizontal Sync Output Enable SYNOP bit in ENR register Programmable polarity 0 1 bits in MCR register In case of composite sync signal the signal can be blanked by software during the vertical period HINH bit in ENR register In case of separate sync no blanking is generated VSYNCO Vertical Sync Output Enable SYNOP bit in ENR register Programmable polarity VOP bit in the MCR register In case of composite sync the delay of the extracted Vsync signal is minimum 500ns HSYNCO pulse width maximum 8750ns max threshold in ex traction mode 57 144 ST72774 81727754 8T72734 SYNC PROCESSOR SYNC Cont d Figure 38 Typical Horizontal Sync Input Timing 5ys lt Typical Hor Total time lt 66 66us 200kHz 15kHz Or lt Maximum Sync pulse width 7us Note Minimum HPeriod 500ns S W interrupt servicing time VR01961 1 Timer Clock Figure 39 Vertical Sync Input Timing 5ms lt Typical Ver Total time lt 25ms 200Hz 40Hz gt Syne pulse width 0 0384ms 0 600ms Note Minimum VPeriod 500ns S W interrupt servicing time VRO1961A 1 Timer Clock 58 144 q SYNC PROCESSOR SYNC Cont d ClampOut and Moire Signal Clamp Output signal The clamping pulse generator can control the puls
58. Horizontal sync analyzer must both be disabled HVGEN HACQ 0 0 Disable 1 Enable Bit 3 VEXT VSYNCO pulse width extension in case of post equalization pulses The sync generator and the Horizontal and Vertical sync analyzer must be disabled HVGEN 0 0 VACQ 0 VCORDIS 0 Vertical extension must be enabled VGENR gt 0 0 Disable 1 Enable Bits 2 0 Q 2 Q 0 These are the read write LSB of the VGENR 11 bit counter Refer to Figure 44 4 SYNC PROCESSOR SYNC Cont d MUX CONTROL REGISTER MCR Read Write Reset Value 0010 0000 20h 7 0 sesso Bit 7 6 BP1 BPO Back Porch Pulse control Back Porch pulse width ofo No Back Porch Moire output selected ___ Bak Poons ons KAEA 333ns Back Porch 10 ns 666ns Back Porch 10 ns Bit 5 FBSEL VSYNCO HSYNCO analysis 0 amp VFBACK 1 HSYNCO amp VSYNCO Bit 4 SCIO HSYNCI CSYNCI selection 0 HSYNCI 1 CSYNCI Bit 3 2 HS1 HSO Horizontal Signal selection These bits allow inversion of the HSYNCI CSYNCI 4 172774 1727754 172734 HSO HSYNCI Selection Mode n CLAMPOUT after HSYNCO rising edge HSYNCO lt HSYNCI CSYNCI CLAMPOUT after HSYNCO rising edge HSYNCO lt HSYNCI CSYNCI CLAMPOUT after HSYNCO falling edge HSYNOO lt HSYNCI CSYNCI 1 CLAMPOUT after HSYNCO falling edge HSYNOO HSYNCI CSYNCI Note In cas
59. M ST72774S7T1 48K ROM ST72754S9T1 60K ROM ST72754S7T1 48K ROM Device CSDIP42 ST72E774J9D0 60K EPROM ST72E754J9D0 60K EPROM ST72E734J6D0 32K EPROM Software Development STMicroelectronics Customer External laboratory Special Marking No Yes For marking one line is possible with maximum 16 characters for SDIP42 10 characters for TQFP44 Authorized characters are letters digits and spaces only Mask Options None We have checked the ROM code verification file returned to us by STMicroelectronics It conforms exactly with the ROM code file orginally supplied We therefore authorize STMicroelectronics to proceed with device manufacture Signature Dato dates wks 4 143 144 Information furnished is believed to accurate reliable However STMicroelectronics assumes responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or sy
60. P D42 DIL42 ST72E774 GP Q44 44 stands for the power supply code assigned by ST Microelectronics EU 220V US 110V 141 144 ST72774 ST727754 ST72734 Table 36 Ordering Information Sales Type ROM EPROM bytes TMU USB Package ST72X774 1 ST72E774J9D0 60K EPROM CSDIP42 ST72T774J9B1 60K OTP ST72774J9B1 xxx 60K ROM PSDIP42 ST72774J7B1 xxx 48K ROM 1K Yes Yes ST72774S7T1 xxx 48K ROM ST72T774S9T1 60K OTP TQFP44 ST72774S9T1 xxx 60K ROM ST72X754 1 ST72E754J9D0 60K EPROM CSDIP42 ST72T754J9B1 60K OTP ST72754J9B1 xxx 60K ROM PSDIP42 ST72754J7B1 xxx 48K ROM 1K Yes No ST72T754S9T1 60K OTP ST72754S9T1 60K ROM TQFP44 ST72754S7T1 xxx 48K ROM ST72X734 2 ST72E734J6D0 32K EPROM CSDIP42 ST72T734J6B1 xxx 32K OTP 512 No No ST72734J6B1 xxx 32K ROM 1 8 bit 2 LSB A D converter 2 8 bit 4 LSB A D converter 142 144 4 T72774 ST727754 ST 72734 STMicroelectronics OPTION LIST ST727x4 MICROCONTROLLER FAMILY GUSIOMER hiss Address mala ERREUR Ex Contact dad due Phone No Zaa hi ahua hu ss The ROM code name assigned by ST STMicroelectronics reference Device SDIP42 ST72774J9B1 60K ROM ST72774J7B1 48K ROM ST72754J9B1 60K ROM ST72754J7B1 48K ROM ST72734J6B1 32K ROM Device 44 ST72774S9T1 60K RO
61. PE 1 the corresponding I O pins select ed by hardware as alternate functions Note To enable the 2 interface write the CR register TWICE with PE 1 as the first write only activates the interface only PE is set Bit 4 Reserved Forced to 0 by hardware Bit 3 START Generation of a Start condition This bit is set and cleared by software It is also cleared by hardware when the interface is disabled PE 0 or when the Start condition is sent with interrupt generation if ITE 1 In master mode 0 No start generation 1 Repeated start generation In idle mode 0 No start generation 1 Start generation when the bus is free 4 T72774 ST727754 ST 72734 Bit 2 ACK Acknowledge enable This bit is set and cleared by software It is also cleared by hardware when the interface is disabled PE 0 0 No acknowledge returned 1 Acknowledge returned after a data byte is re ceived Bit 1 STOP Generation of a Stop condition This bit is set and cleared by software It is also cleared by hardware when the interface is disabled PE 0 or when the Stop condition is sent In Master mode only 0 No stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent Bit 0 nterrupt enable This bit is set and cleared by software and cleared by hardware when the interface is disabled PE 0 0 Interrupts disabled 1 Interrupts enabled Refer to Figu
62. R Read Only Reset Value 0000 0000 00h or os os os os oe m oo Bit 7 0 D 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh Note Reading this register reset the COCO flag Address Register Hex Name ADCDR Reset Value ADCCSR rad Reset Value 4 125 144 ST72774 ST727754 ST72734 5 INSTRUCTION SET 5 1 ST7 ADDRESSING MODES so most of the addressing modes may be subdivided in two sub modes called long and The ST7 Core features 17 different addressing modes which can be classified 7 groups Long addressing mode is more powerful be Addressing Mode Example cause it can use the full 64 Kbyte address space however it uses more bytes and more CPU cy cles 2 isless powerful COUR it can generally only access page zero OOFFh range but the instruction size is more A 55 X compact and faster All memory to memory in structions use short addressing modes only CLR CPL NEG BSET BRES BTJT BTJF Bit operation peat bye ss INC DEC RLC RRC SLL SRL SRA SWAP 2 ST7 Assembler optimizes the use of long and The ST7 Instruction set is designed to minimize short addressing modes the number of bytes required per instruction To do Table 31 ST7 Addressing Mode Overview Pointer Pointer Syntax Destination Address Size Length Source Bytes mem j j j j
63. TA FROM 2 DEVICE Slave Address A1h 98 144 4 DDC INTERFACE 4 8 5 DDC Standard The DDC standard is divided in several data transfer protocols DDC1 DDC2B DDC CI For DDC1 2B refer to the VESA DDC Standard v3 0 specification For DDC CI refer to the DDC Commands Interface v1 0 DDC1 is a uni directional transmission of EDID v1 128 bytes from display to host clocked by VSYNCI DDC2B is a uni directional channel from display to host The host computer uses base level 2 commands to read the EDID data from the dis play which is always in slave mode Specific types of display contain EDID at fixed I C device addresses within the device refer to Table 25 DDC CI is a bi directional channel between the host computer and the display The DDC CI of fers a display control interface based on 2 bus It includes the DDC2Bi and DDC2AB standards Note The DDC2AB standard is no longer handled by the interface 4 8 5 1 DDC1 2B Interface 4 8 5 1 1 Functionnal description Refer to the DCR AHR registers in Section 4 8 6 for the bit definitions The DDC1 2B Interface acts as interface between a DDC bus and the microcontroller memory In addition to receiving and transmitting serial data this interface directly transfers parallel data to and from memory using a DMA engine only halting CPU activity for two clock cycles during each byte transfer The interface
64. TERRUPT DMA REGISTER IDR Read Write Reset Value xxxx 0000 x0h 7 0 EPO CNT2 CNT1 CNTO Figure 51 DMA buffers Bits 7 6 DA 7 6 DMA adaress bits 7 6 The software must write the start address of the DMA memory area whose most significant bits are given by DA15 DA6 The remaining 6 address bits are set by hardware See Figure 51 Bits 5 4 EP 1 0 Enapoint number read only These bits identify the endpoint which required attention 00 Endpoint 0 01 Endpoint 1 10 Endpoint 2 When a CTR interrupt occurs see register ISTR the software should read the EP bits to identify the endpoint which has sent or received a packet Bits 3 0 CNT 3 0 Byte count read only This field shows how many data bytes have been received during the last data reception Note Not valid for data transmission Endpoint 2 TX Endpoint 2 RX 010111 Endpoint 1 RX 010000 001111 Endpoint 0 TX 001000 000111 Endpoint 0 RX DA15 6 000000 000000 Endpoint 1 TX 011000 80 144 4 USB Cont d PID REGISTER PIDR Read only Reset Value xx00 0000 x0h Bits 7 6 TP3 TP2 Token PID bits 3 amp 2 USB token PIDs are encoded in four bits TP3 TP2 correspond to the variable token bits 3 2 Note PID bits 1 amp 0 have a fixed value of 01 When a CTR interrupt occurs see register ISTR the software should read the TP3 and TP2 bits to retrieve the PID name of the to
65. VGENR gt 0 Reset the VCORDIS bit in the POLR register Set the bit in the CFGR register 8 Set the 2FHEN bit in the ENR register Notes 1 When corrector mode is active the free running frequencies generator and analyzer mode must be disabled 0 in ENR register HACQ 0 VACQ 0 in the CFGR register If VGENR 0 all VSYNCO correction functions are disabled except the 2FHEN bit which must be cleared if VGENR 0 or VCORDIS 1 67 144 ST72774 ST727754 ST72734 SYNC PROCESSOR SYNC Cont d 4 4 10 Register Description CONFIGURATION REGISTER CFGR Read Write Reset Value 0000 0000 00h 7 0 HACQ VACQ MES VEXT Bit 7 HACQ Horizontal Sync Analyzer Mode Set software reset hardware when the measurement is done The sync generator must be disabled HVGEN 0 0 Measurement is done the result can be read in HGENR 1 Start measuring HSYNCO HFBACK low lev el Bit 6 VACQ Vertical Sync Analyzer Mode Set by software reset by hardware when the measurement is done The sync generator must be disabled HVGEN 0 0 Measurement is done and the result can be read in VGENR 68 144 1 Start measuring the number of scan lines dur ing VSYNCO VFBACK low level Bit 5 Reserved Must be cleared Bit 4 2FHINH Inhibition of Pre Post equalization pulses This function removes equalization pulses on HSYNCO signal The sync generator and the
66. Voltage Detector LVD reset Programmable Watchdog for system reliability Fully static operation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction m True bit manipulation m Complete development support on PC DOS Windows Real Time Emulator EPROM Programming Board and Gang Programmer Full software package assembler linker C compiler source level debugger 48K 32K 512 256 us 08 USB 08 08 Peripherals ADC 3 16 bit timer 122 DDC TMU Sync PWM LVD Watchdog DDC Sync 16 bit timer PWM Watchdog Operating Supply 4 0V to 5 5V supply operating range Oscillator Frequency 12 or 24 MHz Operating Temperature 0 to 70 C Package PSDIP42 CSDIP42 or PSDIP42 or TQFP44 CSDIP42 some devices only refer to Device Summary 2 Contact Sales office availability 3 8 bit 2 LSB A D converter 4 8 bit 4 LSB A October 2003 1 144 Table of Contents 1 GENERAL DESCRIPTION euer Eb a paj Ue 6 11 INTRODUCTION Sa cn ee A EEEE 6 1 2 PIN DESGRIPTION Sy thes Sept ais eR UR uba 7 1 3 MEMORY ku a dae nite RR P OR E ARR 10 1 4 EXTERNAL 6 0 14 2 CENTRAL PROCESSING UNIT 15 Z INTRODUCTION trt eite rhe ee pee dee dee t De AR Td Re e 15
67. WM PWMOE 4 5 1 5 With pull up Push pull 10 bit output 6 PWM PWMOE 1 With pull up Push pull 10 bit output 7 PWM PWMOE OE7 1 PC7 With pull up Push pull 10 bit output 8 PWM PWMOE Reset State 4 33 144 ST72774 ST727754 ST72734 PORTS Cont d Figure 21 PC0 PC2 to PC7 DATA BUS Figure 22 PC1 lt DATA BUS DR SEL 34 144 DR n Alternate enable EE PULL UP Alternate Vpp output P BUFFER N BUFFER D Vss Gi CMOS Schmitt Trigger P BUFFER Vpp CMOS Schmitt Trigger q PORTS 4 1 6 Port D The Port D I O pins are normally used for the input and output of video synchronization signals of the Sync Processor but are set to Input with pull up upon reset The I O mode can be set individually for each port bit to Input with pull up T72774 ST727754 ST 72734 Port D bit 6 is switched to the alternate CLAMPOUT by resetting the CLMPEN bit of the ENR Register inside SYNC block If the SYNC function is selected Port D bit 5 and 3 MUST be set as input to enable the HFBACK or VFBACK timing inputs and output push pull through the Port D DDR The configuration to support the Sync Processor requires that the SYNOP bit7 and CLMPEN bit6 of the ENR Enable Register of SYNC is reset SYNOP enables port D bits 0 1 and CLMPEN enables Port D bit 6 to the sync outputs Port D
68. a normal reset Table 5 gives a list of the different sections affected by the low power modes For detailed information on a particular device please refer to the corresponding part 3 4 2 HALT Mode The HALT mode is the MCU lowest power consumption mode Meanwhile the HALT mode also stops the oscillator stage completely which is the most critical condition in CRT monitors For this reason the HALT mode has been disabled and its associated HALT instruction is now considered as illegal and will generate a reset 4 T72774 ST727754 ST 72734 Figure 14 WAIT Flow Chart WFI INSTRUCTION OSCILLATOR ON PERIPH CLOCK ON CPU CLOCK OFF CLEARED OSCILLATOR PERIPH CLOCK CPU CLOCK IF 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note Before servicing an interrupt the CC register is pushed on the stack The I Bit is set during the inter rupt routine and cleared when the CC register is popped 25 144 ST72774 ST727754 ST72734 3 5 MISCELLANEOUS REGISTER MISCELLANEOUS REGISTER MISCP Address 0009h Read Write Reset Value 0001 0000 10h 7 0 VSYNC FLY S HSYNC SEL DIVEN FAST ITBLAT ITALAT ITBITE ITAITE Bit 7 VSYNCSEL DDC1 VSYNC Selection This bit is set and cleared by software It is used to choose the VSYNC signal in DDC1 mode 0 VSYNCI selected 1 VSYNCI2 selected Note VSYNCI 2 is only available for the DDC cell not for
69. able the endpoint by setting the STAT_TX bits to VALID 11b in EPnRA Note Once transmission and or reception are enabled registers EPnRA and or respectively must not be modified by software as the hardware can change their value on the fly When the operation is completed they can be accessed again to enable a new operation 4 6 5 4 Interrupt Handling Start of Frame SOF The interrupt service routine must monitor the SOF events and measure the interval between each SOF event If 3ms pass without a SOF event the software should set the USB interface to suspend mode USB Reset RESET When this event occurs the DADDR register is reset and communication is disabled in all endpoint registers the USB interface will not respond to any packet Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset To do this you set the STAT bits in the EPORB register to VALID End Suspend ESUSP The CPU is alerted by activity on the USB which causes an ESUSP interrupt Correct Transfer CTR 1 When this event occurs the hardware automat ically sets the STAT TX or STAT RX to NAK Note Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register independently of the endpoint number addressed by the transfer which generated the CTR interrupt Note If the event triggering the CTR interrupt is a SETUP transaction both STAT TX STAT set t
70. ace generates in sequence ky T72774 ST727754 ST 72734 Acknowledge pulse if if the ACK bit is set EVF and bits are set by hardware with an in terrupt if the ITE bit is set Then the interface waits for a read of the SR1 register followed by a read of the DR register holding the SCL line low see Figure 54 Transfer sequencing EV3 To close the communication before reading the last byte from the DR register set the STOP bit to generate the Stop condition The interface goes automatically back to idle mode M IDL bit cleared Note In order to generate the non acknowledge pulse af ter the last received data byte the ACK bit must be cleared just before reading the second last data byte Master Transmitter Following the address transmission and after SR1 register has been read the master sends bytes from the DR register to the SDA line via the internal shift register The master waits for a read of the SR1 register followed by a write in the DR register holding the SCL line low see Figure 54 Transfer sequencing EVA When the acknowledge bit is received the interface sets EVF and bits with an interrupt if the ITE bit is set To close the communication after writing the last byte to the DR register set the STOP bit to generate the Stop condition The interface goes automatically back to idle mode M IDL bit cleared Error Case AF Detection of a non acknowledge bi
71. al frequency fosc 12MHz Crystal Oscillator Start up Time Power up rise time Note The minimum period tj should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles 134 144 ST72774 ST727754 ST72734 AC DC ELECTRICAL CHARACTERISTICS Cont d STANDARD I O PORT PINS Conditions Output Low Level Voltage Port A 7 2 0 Port B 7 4 Port C 7 0 Port D 6 0 Push Pull Output High Level Voltage Port A 7 2 0 Port B 7 4 Port C 7 0 Port D 6 0 Push Pull Input High Level Voltage Port A 7 0 Vin Port B 7 0 Port C 7 0 Port D 6 0 RESET Input Low Voltage Port A 7 0 Port B 7 0 Port C 7 0 Port D 6 0 RESET I O Ports Hi Z Leakage Current Port A 7 0 Port B 7 0 Port C 7 0 Port D 6 0 RESET Capacitance Ports as Input or Output RESET gt gt Note Note All voltages referred to Vss unless otherwise specified POWER ON OFF Electrical Specifications Symbo Parameter Conditions Typ Power ON OFF Reset Trigger VrTRH Vpp Variation 50mV mS 3 35 s V Vpp rising edge VIRM Vpp minimum 2 ON OFF Reset Vpp Variation 50mV mS Power ON OFF LVD Hysteresis Vpp Variation 50mV mS D Power ON OFF Reset Trigger Vpp Variation 50mV mS 3 1 3 4 3 7 V Vpp falling edge D 135 144 4 ST72774 ST727754 ST72734 AC DC ELECTRICAL CHARACTERISTICS Cont d 8 bit A D C
72. alues The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start up stabilization time Figure 8 Crystal Ceramic Resonator CRYSTAL CLOCK Recommended for oscillator stability 4 172774 1727754 172734 Table 4 Recommended Crystal Values Cj 4 Maximum total capacitance on pins OSCIN and OSCOUT the value includes the external capacitance tied to the pin plus the parasitic capacitance of the board and of the device Rsmax Maximum series parasitic resistance of the quartz allowed Note The tables are relative to the quartz crystal only not ceramic resonator 3 1 3 External Clock An external clock should be applied to the OSCIN input with the OSCOUT pin not connected as shown in Figure 9 The Crystal clock specifications do not apply when using an external clock input The equivalent specification of the external clock source should be used Figure 9 External Clock Source Connections OSCIN OSCOUT L EXTERNAL CLOCK 19 144 ST72774 8T727754 8T72734 3 2 RESET The Reset procedure is used to provide an orderly software start up or to quit low power modes Five conditions generate a reset When a watchdog reset occurs the RESET pin is pulled low permitting the MCU to reset other devices as when Power on off Figure 10 3 2 2 External Reset The external rese
73. am DDC1 2B CONTROL REGISTER DCR ADDRESS LOW REGISTER ALR amp ADDRESS HIGH REGISTER ADDRESS DATA CONTROL LOGIC DATA CONTROL DATA SHIFT REGISTER SCLD DDC1 2B CONTROL LOGIC VSYNCI 1 894 HWDDC VSYNCI2 DDC1 2B for MONITOR IDENTIFICATION INTERRUPT Y Bit in MISCR Register DATA REGISTER DR DATA CONTROL SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER OAR HARDWARE ADDRESS DDC CI Factory CONTROL REGISTER CR CONTROL LOGIC DDC INTERRUPT ky STATUS REGISTER 1 SR1 STATUS REGISTER 2 SR2 DDC CI for MONITOR ADJUSTMENT and CONTROL 96 144 DDC INTERFACE Cont d 4 8 3 Signal Description Serial Data SDA The SDA bidirectional pin is used to transfer data in and out of the device It is an open drain output that may be or wired with other open drain or open collector pins An external pull up resistor must be connected to the SDA line Its value depends on the load of the line and the transfer rate Serial Clock SCL The SCL input pin is used to synchronize all data in and out of the device when in I C bidirectional mode An external pull up resistor must be connected to the SCL line Its value depends on the load of the line and the transfer rate Note When the DDC1 2B and DDC Cl Factory Interfaces are disabled HWPE bit 0 in the DCR register and PE bit 0 in the CR register SDA and SCL pins re vert to standard I O p
74. and all reception requests result in a STALL handshake NAK the endpoint is na ked and all reception re quests result in handshake VALID this endpoint is enabled for reception These bits are written by software Hardware sets the STAT bits to when a correct transfer has occurred CTR 1 related to OUT or SETUP transaction addressed to this endpoint so the software has the time to elaborate the received data before acknowledging a new transaction Bits 3 0 EA 3 0 Endpoint address Software must write in this field the 4 bit address used to identify the transactions directed to this endpoint Usually EP1RB contains 0001 and EP2RB contains 0010 ENDPOINT 0 REGISTER B EPORB Read Write Reset Value 1000 0000 80h 7 0 DTOG STAT STAT RX1 RXO 9 0 x This register is used for controlling data reception on Endpoint 0 It is also reset by the USB bus reset Bit 7 Forced by hardware to 1 Bit 6 4 Refer to the EPnRB register for a description of these bits Bit 3 0 Forced by hardware to 0 4 USB INTERFACE Cont d 4 6 5 Programming Considerations In the following the interaction between the USB interface and the application program is described Apart from system reset action is always initiated by the USB interface driven by one of the USB events associated with the Interrupt Status Register ISTR bits 4 6 5 1 Initializing the Registers
75. arity control in MCR The delay between VSYNCI polarity changes and the VPOL bit typically toggles within 4 msecs The polarity detector includes an integrator to filter possible incoming VSYNCI glitches 5 bit Up Down Counter Check for HSYNCI Polarity This method involves the internal 5 bit up down counter The counter value CV4 CVO bits is updated with the 5 bit counter value at every detected edge on the signal monitored It is incremented when the signal is high otherwise it is decremented Start the detection phase Initialize the 5 bit counter write 00000 in the CCR register CV4 CVO bits Select normal mode on falling edge LCV1 LCVO 0 in the CCR register Software checks the counter value CV4 CVO after an interrupt with the signal internally con nected or ICAP2 or by polling timeout 1501 Positive polarity The counter value 1Fh Negative polarity The counter value 1Fh on the falling edge In case of a composite incoming signal the software just has to check that the VSYNCO period and polarity are stable 62 144 4 4 6 4 Extracting VSYNCO from CSYNCI In case of composite sync the Vertical sync output signal is extracted with the 5 bit up down counter Initially the width of Horizontal Sync component pulse is automatically determined by hardware which defines a threshold for the 5 bit counter with a possible user defined tolerance The circuit then monitors for any inco
76. as shown in the following table The BRM values shown may be combined together to provide a summation of the incremental pulse intervals specified The pulse increment corresponds to the PWM resolution Then 3 0 us long pulse will be output at 8 us intervals except for cycles numbered 2 4 6 10 12 14 where the pulse is broadened to 3 125 us Note If 00h is written to both PWM and registers the generator output will remain at 0 Conversely if both registers hold data 3Fh and OFh respective ly the output will remain at 1 for all intervals 1 to 15 but it will return to zero at interval 0 for an amount of time corresponding to the PWM resolu tion An output be set to continuous 1 level by clearing the PWM and BRM values and setting POL 1 inverted polarity in the PWM register This allows a PWM BRM channel to be used as an additional I O pin if the DAC function is not required Table 28 Bit BRM Added Pulse Intervals Interval 0 not selected For example if BRM 4 Bit Data Incremental Pulse Intervals Data 18h is written to the PWM register 0000 none Data 06h 000001 10b is written to the BRM reg 0001 i 8 ister 0010 i 4 12 with a 8 2 internal clock 125ns resolution 0100 2 6 10 14 1000 1 3 5 7 9 11 13 15 Figure 72 pulse addition PWM gt 0 m 0 1 m m 15 Topu X 64 Topu x 64 Topu x 64 Topu x
77. at the given address an Acknowledge will be generated on the 9th clock pulse Start A0h Ack 00h Ack Device Slave Address Data Address 4 8 4 3 Data Transfer Once the slave address is acknowledged the data transfer can proceed in the direction given by the R W bit sent in the address Data is transferred with the most significant bit MSB first Data bits can be changed only when SCL is low and must be held stable when SCL is high One complete data byte transfer requires 9 clock pulses 8 bits 1 acknowledge bit 4 8 4 4 Acknowledge Bit ACK NACK Every byte put on the SDA line is 8 bit long followed by an acknowledge bit This bit is used to indicate a successful data transfer The bus transmitter either master or slave releases the SDA line during the 9th clock period after sending all 8 bits of data then To generate an Acknowledge ACK of the cur rent byte the receiver pulls the SDA line low To generate No Acknowledge NACK of the current byte the receiver releases the SDA line hence at a high level 4 8 4 5 STOP Condition A STOP condition is defined by a low to high transition of SDA while SCL is stable high It ends the communication between the Interface and the bus master Figure 58 12 Signal Diagram DataN FOh Ack STOP WRITE DATA TO 2 DEVICE Slave Address Start Ath Ack Device Slave Address Data1 00h Data2 BOh Ack DataN FOh STOP READ DA
78. ated to the output compare i function Select the timer clock CC1 CC0 see Table 15 Clock Control Bits And select the following in the CR1 register Select the OLVLibit to applied to the OCMP ipins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When match is found OCFi bit is set takes OLVLi bit value OCMP pin latch is forced low during reset and stays low until valid compares change it to a high level ky T72774 ST727754 ST 72734 A timer interrupt is generated if the OCIE bit is set in the CR2 register and the bit is cleared in the CC register CC Clearing the output compare interrupt request is done by 3 Reading the SR register while the OCFi bit is set 4 An access read or write to the register Note After a processor write cycle to the register the output compare function is inhibited until the register is also written If the OCE bit is not set the pin is a general I O port and the OLVL bit will not appear when match is found but an interrupt could be generated if the OCIE bit is set The value in the 16 bit register and the bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout The register value required for a specific timing application can be calculated using the f
79. b EDID AOh Ath 128b EDID AOh Ath 256b EDID A2h A3h 256b EDID A6h A7h pug v2 P amp D 128b EDID No AOh Ath Reserved 128b EDID 1 256b EDID A2h A3h Reserved q 114 144 ST72774 81727754 8172734 DDC INTERFACE Contd Table 26 DDC Register Map and Reset Values our 5 EDDCEN EXE ACK STOP EN SR VF T ADSL of oo a SR STOPF BERR EDDCF ERN CEN s A ADD2 ADD1 ADDO DR D7 D2 D1 we io RENE SENE pr d 2 CFO WP HWPE pe of AH AHR7 AHR6 5 AHR4 2 1 0 R BTF 0 F 0 0 0 D 4 D3 0 ED E CF1 0 0 Reset Value 50 0 1 51 EN 52 0 54 OAR ADD7 ADD6 ADD5 ADD4 ADD3 Reset Value 0 0 5 D 0 0 0C R F 0 0 R 0 115 144 4 ST72774 ST727754 ST72734 4 9 PWWBRM GENERATOR DAC 4 9 1 Introduction This PWM BRM peripheral includes two types of PWM BRM outputs with differing step resolutions based on the Pulse Width Modulator PWM and Binary Rate Multiplier BRM Generator technique are available It allows the digital to analog conversion DAC when used with external filtering 4 9 2 Main Features m Fixed frequency fopy 64 m Resolution Top m 10 Bit PWM BRM generator with a step of 210 bmV if 5 4 9 3 Functional
80. bit 4 3 are the alternate inputs ITA ITB for the interrupt falling edge detector When a falling edge occurs on these inputs an interrupt will be generated depending on the status of the INTX ITAITE amp ITBITE bits in the MISCR Register Note As these inputs are switched from normal functionality the video synchronization signals may also be monitored directly through the Port D Data Register for such tasks as checking for the presence of video signals or checking the polarity of Horizontal and Vertical synchronization signals when the Sync Inputs are switched directly to the using the multiplexers of the Sync Proces sor Table 11 Port D Description 1 0 Alternate Function VSYNCO SYNOP 0 With pull up Push pull push pull output ENR SYNC With pull Push pull HSYNCO SYNOP 0 ith pull u ush pu R D push pull output ENR SYNC CSYNCI input with TTL Schmitt With pull up Push pull trigger amp pull up ITB input with CMOS Schmitt With pull up Push pull trigger amp pull up HFBACK input with TTL Schmitt With pull up Push pull trigger amp pull up With pull Push pull CLAMPOUT CLMPEN 0 ith pull u ush pu R p push pull output ENR SYNC Reset state ITA input with CMOS Schmitt ef trigger amp pull u With pull up Push pull 33 VFBACK input with T TL Schmitt trigger amp pull up 4 35 144 5772774 5 727754 5 72734 PORTS Conta Figure 23 PD2 to
81. ce to DDC1 mode software must first clear the CFO bit in the DCR Figure 59 DDC1 Waveforms XX PE SCL register while the HWPE bit 0 and then set the HWPE bit to enable the DDC1 2B Interface A proper initialization sequence see Figure 59 must supply nine clock pulses on the VSYNCI pin in order to internally synchronize the device During this initialization sequence the SDA pin is in high impedance On the rising edge of the 10th pulse applied on VSYNCI the device outputs on SDA the most significant MSB bit of the byte located at data address OOh A byte is clocked out by means of 9 clock pulses Vsync 8 clock pulses for the data byte itself and an extra pulse for a Don t Care bit As long as SCL is not held low each byte of the memory array is transmitted serially on SDA The internal address counter is incremented automatically until the last byte is transmitted Then it rolls over to relative location OOh The physical mapping of the data structure depends on the configuration and on the content of the AHR register which can be set by software see Figure 60 00h ani eee 8 9 10 11 Vsync AR Cn O o SDA i7 gt C gt Vsync ee 100 144 4 DDC INTERFACE Cont d Figure 60 Mapping of DDC1 data structure ST72774 ST727754 ST 72734 DDC v2 mode CF 1 0 bits 006 128 byte Data Structure ALR 256 bytes 256 AHR Addr Pointer Note MS
82. cessive approximations cycles and the Cape sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy While the ADC is on these two phases are continuously repeated At the end of each conversion the sample capacitor is kept loaded with the previous measurement load The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement 4 10 3 4 Software Procedure Refer to the control status register CSR and data register DR in Section 4 10 6 for the bit definitions and to Figure 77 for the timings 124 144 ADC Configuration The total duration of the A D conversion is 12 ADC clock periods 1 fApc 4 fcpu The analog input ports must be configured as input no pull up no interrupt Refer to the ports chapter Using these pins as analog inputs does not affect the ability of the port to be read as a logic input In the CSR register Select the CH 3 0 bits to assign the analog channel to be converted ADC Conversion In the CSR register Set the ADON bit to enable the A D converter and to start the first conversion From this time on the ADC performs a continuous conver sion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register and remains valid until the nex
83. corresponds to pin of the associated port This corresponding bit must be set to configure its associated pin as output and must be cleared to configure its associated pin as input Table 7 Pin Functions on page 28 The Data Direction Registers can be read and written The typical I O circuit is shown on Figure 15 Any write to an I O port updates the port data register even if it is configured as input Any read of an I O port returns either the data latched in the port data register pins configured as output or the value of the I O pins pins configured as input Remark when pin does not exist inside an port the returned value is a logic one configured as input At reset all DDR registers are cleared which configures all port s I Os as inputs with or without pull ups see Table 8 to Table 12 Ports Register Map The Data Registers DR are also initialized at reset 4 1 2 1 Input mode When DDR 0 the corresponding is configured in Input mode In this case the output buffer is switched off the state of the I O is readable through the Data Register address but the state comes directly 28 144 from the CMOS Schmitt Trigger output and not from the Data Register output 4 1 2 2 Output mode When DDR 1 the corresponding is configured in Output mode In this case the output buffer is activated according to the Data Register s content A read operatio
84. cur in sequence Acknowledge pulse is generated if the ACK bit is set EVF and ADSL bits are set An interrupt is generated if the ITE bit is set Then the interface waits for a read of the SR1 register holding the SCL line low see Figure 67 Transfer sequencing EV1 Next the DR register must be read to determine from the least significant bit if the slave must enter Receiver or Transmitter mode 107 144 ST72774 ST727754 ST72734 DDC INTERFACE Slave Receiver Following the address reception and after SR1 register has been read the slave receives bytes from the SDA line into the DR register via the internal shift register After each byte the following events occur in sequence Acknowledge pulse is generated if the ACK bit is set EVF and BTF bits are set An interrupt is generated if the ITE bit is set Then the interface waits for a read of the SR1 register followed by a read of the DR register holding the SCL line low see Figure 67 Transfer sequencing EV2 Slave Transmitter Following the address reception and after SR1 register has been read the slave sends bytes from the DR register to the SDA line via the internal shift register The slave waits for a read of the SR1 register followed by a write in the DR register holding the SCL line low see Figure 67 Transfer sequencing EV3 When the acknowledge pulse is received EVF and BTF bits are set An interr
85. d dress follows the opcode q 5 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may ST72774 ST727754 ST72734 be subdivided into 13 main groups as illustrated in the following table gana T T Increment Decrement INC DEC Compare and Tests TNZ Logical operations AND ADD SRL JRT Arithmetic operations ADC Shift and Rotates SLL Unconditional Jump or Call JRA Using a pre byte The instructions are described with one to four bytes In order to extend the number of available opcodes for an 8 bit CPU 256 opcodes three different prebyte opcodes are defined These prebytes modify the meaning of the instruction they precede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC opcode 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address These prebytes enable instruction Y as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y one PIX 92 Replace an instruction using di rect direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode It also changes an
86. d addressing modes The operand is referenced by its memory address which is defined by the unsigned addition of an index register value X or Y with a pointer value located in memory The pointer address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 32 Instructions Supporting Direct Indexed Indirect Indirect Indexed Addressing Modes Instructions ADC ADD SUB SBC Arithmetic Addition subtrac tion operations D P 128 144 ShornsucionsOny Funci n BSET BRES Bit Operations Bit Test and Jump Opera BTJT BTJF tions SLL SRL SRA RLC RRC SWAP Swap Nibbles CALL JP Call or Jump subroutine Shift and Rotate Operations 5 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset follows the opcode Relative Indirect The offset is defined in memory of which the a
87. d indirect addressing modes The device includes an on chip oscillator CPU System protection against illegal address jumps Sync Processor for video timing amp Vfback analysis up to 60K Program Memory up to 1K RAM USB DMA a Timing Measurement Unit I O a timer with 2 input captures and 2 output compares a 4 channel Analog to Digital Converter DDC Fe Single Master Watchdog Reset and eight 10 bit PWM BRM outputs for analog DC control of external functions Up to 60K Bytes ROM OTP EPROM Up to 1K Bytes RAM 1 SSauqqv OSCIN PROCESSOR DAC PWM PA0 OCMP1 1 PA2 VSYNCI2 PA7 BLANKOUT PB6 PB7 AIN2 AIN3 PWM1 PWM2 PB4 PB5 AINO AIN1 PB1 SDAD PB0 SCLD USBVCC USBDP USBDM PDO VSYNCO PD1 HSYNCO PD2 CSYNCI PDS ITA VFBACK PD4 ITB PD5 HFBACK PD6 CLAMPOUT SYNC PCO HSYNCDIV PC1 AV PC2 PC7 PWM3 PWM8 4 6 144 1 2 DESCRIPTION Figure 2 44 and 42 SDIP Package Pinouts 172774 1727754 172734 5 PWM6 4 PWM5 O PWM4 L1 PC2 PWM3 PCO HSYNCDIV OCMP1 PC1 AV 00 4 PWM7 PC6 PWM8 PWM AIN3 PB7 PWM1 AIN2 PB6 AIN1 PB5 AIN0 PB4 NC Vpp USBVCC USBDM USBDP o u 00 00000000 lt Z Zn NN
88. definitions By default the 2 interface operates in idle mode M IDL bit is cleared except when it initiates a transmit or receive sequence To switch from default idle mode to Master mode a Start condition generation is needed Start condition and Transmit Slave address Setting the START bit causes the interface to switch to Master mode M IDL bit set and generates a Start condition Once the Start condition is sent EVF and SB bits set by hardware with an interrupt if the ITE bit is set Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address byte holding the SCL line low see Figure 54 Transfer sequencing EV1 Then the slave address byte is sent to the SDA line via the internal shift register After completion of this transfer and acknowledge from the slave if the ACK bit is set The EVF bit is set by hardware with interrupt generation if the ITE bit is set Then the master waits for a read of the SR1 register followed by a write in the CR register for example set PE bit holding the SCL line low see Figure 54 Transfer sequencing 2 Next the master must enter Receiver Transmitter mode Master Receiver Following the address transmission and after SR1 and CR registers have been accessed the master receives bytes from the SDA line into the DR register via the internal shift register After each byte the interf
89. e 6 Interrupt Mapping on page 24 for vector addresses The interrupt service routine should finish with the IRET instruction which causes the contents of the registers to be recovered from the stack and normal processing to resume Note that the bit is then cleared if and only if the corresponding bit stored in the stack is zero Though many interrupts can be simultaneously pending a priority order is defined see Table 6 Interrupt Mapping on page 24 The RESET pin has the highest priority If the I bit is set only the TRAP interrupt is enabled All interrupts allow the processor to leave the WAIT low power mode Software Interrupt The software interrupt is the executable instruction TRAP The interrupt is recognized when the TRAP instruction is executed regardless of the state of the bit When the interrupt is recognized it is serviced according to the flowchart on Figure 13 22 144 ITA ITB interrupts The ITA PD3 ITB PD4 pins can generate an interrupt when a falling edge occurs on these pins if these interrupts are enabled with the ITAITE ITBITE bits respectively in the miscellaneous register and the bit of the CC register is reset When an enabled interrupt occurs normal processing is suspended at the end of the current instruction execution It is then serviced according to the flowchart on Figure 13 Software in the ITA or ITB service routine must reset the cause of this interrupt by cleari
90. e DR reg ister Receiver mode the first data byte is received au tomatically in the DR register using the least sig nificant bit of the address Then the next data bytes are received one by one after reading the DR register 93 144 1 72774 1727754 172734 2 SINGLE MASTER BUS INTERFACE Cont d Table 24 2 Register EA a Reset Value 0 0 0 0 0 e ao Reset Value 0 0 0 0 0 SR2 AF 5D Reset Value 0 5C CCR FM SM CC6 CC5 CC4 CC3 CC2 CC1 CCO Reset Value 0 0 0 0 0 0 0 0 59 DR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO Reset Value 0 0 0 0 0 0 0 0 4 94 144 4 8 DDC DDC 4 8 1 Introduction DDC Display Data Channel Bus Interface is mainly used by the monitor to identify itself to the video controller by the monitor manufacturer to perform factory alignment and by the user to adjust the monitor s parameters The DDC interface consists of two parts m fully hardware implemented interface supporting DDC1 and DDC2B specification 3 0 compliant It accesses the ST7 on chip memory directly through a built in DMA engine A second interface supporting the slave 2 functions for handling DDC CI mode DDC2Bi factory alignment or Enhanced DDC EDDC by software 4 8 2 DDC Interface Features 4 8 2 1 Hardware DDC1 2B Interface Features m Full hardware su
91. e Jj immediate St Dea eao CA tong feas No Offset Direct Indexed Id 00 FF 1 with Y register ason oa Ser LG ELIGE mE A Tos LO Note 1 Atthe time the instruction is executed the Program Counter PC points to the instruction following 4 126 144 ST7 ADDRESSING MODES Cont d 5 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required information for the CPU to process the operation Inherent Instruction NOP No operation TRAP S W Interrupt Wait For Interrupt Low Power Mode HALT Disabled forces a RESET IRET Interrupt Sub routine Return Reset Carry Flag Reset Stack Pointer Load NOP WF RET Reset Interrupt Mask Z CLR Clear m SLL SRL SRA RLC RRC SWAP Swap Nibbles 5 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte contains the operand value Load C D N Shift and Rotate Operations Bit Compare Logical Operations AND OR XOR ADC ADD SUB SBC Arithmetic Operations 4 172774 1727754 172734 5 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opc
92. e a reset of the USB interface just as if a RESET sequence came from the USB 0 Reset not forced 1 USB interface reset forced The USB is held in RESET state until software clears this bit at which point a USB RESET interrupt will be generated if enabled DEVICE ADDRESS REGISTER DADDR Read Write Reset Value 0000 0000 00h 7 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO Bit 7 Reserved Forced by hardware to 0 Bits 6 0 ADD 6 0 Device address 7 bits Software must write into this register the address sent by the host during enumeration Note This register is also reset when a USB reset is re ceived from the USB bus or forced through bit FRES in the CTLR register ky USB INTERFACE Cont d ENDPOINT n REGISTER A EPnRA Read Write Reset Value 0000 xxxx 0xh 7 0 ST STAT STAT TBC TBC TBC OUT _TX _TX1 3 2 1 0 These registers EPORA EP1RA and EP2RA are used for controlling data transmission They are also reset by the USB bus reset Note Endpoint 2 and the EP2RA register are not availa ble on some devices see device feature list and register map Bit 7 ST OUT Status out This bit is set by software to indicate that a status out packet is expected in this case all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed When ST OUT is reset OUT transactions can have any number of bytes as needed
93. e detected Must be reset by software It is valid when the sync generator and Horizontal analyzer are disabled HVGEN 0 HACQ 0 71 144 ST72774 ST727754 ST72734 SYNC PROCESSOR SYNO Cont d HORIZONTAL SYNC GENERATOR REGISTER HGENR Read Write Reset Value 0000 0000 00h 7 0 EI EE Case HVGEN 1 Generation mode In this mode this register contains the Hsync free running frequency The generated signal is Pulse width 2 us Period PH HGENR 1 4 us Polarity Positive Note The value in HGENR must be in the range 8 255 Case HVGEN 0 Analyzer corrector Mode Sub case HACQ 1 Analyzer Mode By setting HACQ bit by software the Analyzer mode starts When is cleared by hardware HGENR returns the duration of HSYNCO HFBACK low level The analysis should be done before corrector mode Sub case HACQ 0 Corrector Mode In this mode the final HSYNCO signal on the pin can be corrected in order to detect and inhibit pre post equalization pulses 72 144 VERTICAL SYNC GENERATOR REGISTER VGENR Read Write Reset Value 0000 0000 00h 7 0 BE ALLY ES Case HVGEN 1 Generation mode In this mode this register contains the Vsync free running frequency 11 bit value The generated signal is Pulse width 4 PH us horizontal period Period PV PH V11bits us Polarity Positive Note The value in VGENR must be in the range 5 255 The Vsync gene
94. e is selected Once in DDC2B mode the Interface always acts as a slave following the protocol described in Figure 62 The DDC1 2B Interface continuously monitors the SDA and SCL lines for a START condition and will Figure 62 DDC2B protocol example Start 0 00h Device Slave Data Address Address Legend Bold data control signal from host not respond no acknowledge until one is found A STOP condition at the end of a Read command after a NACK forces the stand by state A STOP condition at the end of a Write command triggers the internal DMA write cycle The Interface samples the SDA line on the rising edge of SCL and outputs data on the falling edge of SCL In any case SDA can only change when SCL is low Data1 Device Slave 48 128 256 bytes EDID gt Address ltalics data control signal from display 102 144 4 172774 1727754 172734 Figure 63 DDC1 2B Operation Flowchart Wait for HWPE 1 Tox bit 0 g 5 3 o SDA Hi Z Vsync Counter 0 Start 2 sec Timer 5 E Received valid Y Device Address D S N Relative Address ALR 0 Y Received valid Vsync Counter 1 Device Address O N Y 5 E N Counter 128 Send Acknowledge or Timer expired 2 Respond to Command Y 103 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d EDID Data structure mapping An internal address pointer defines the mem
95. e of composite sync if HSYNCO blanking is enabled 0 in the ENR register H81 must 1 CLAMPOUT after HSYNCO rising edge not al lowed Bit 1 VOP Vertical Polarity control The VOP bit inverts the VSYNCO Sync signal 0 No polarity inversion VSYNCO VSYNCI 1 Inversion enabled VSYNCO lt VSYNCI Note If at each vertical input capture the VPOL bit is cop ied by software on the VOP bit the VSYNCO signal will have a constant positive polarity Note The internally extracted VSYNCO has ALWAYS negative polarity Bit 0 Reserved Must always be cleared 69 144 ST72774 ST727754 ST72734 SYNC PROCESSOR SYNC Cont d COUNTER CONTROL REGISTER CCR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 PSCD Prescaler Enable bit 0 Enable the Prescaler by 256 1 Disable the Prescaler and reset it to 7Fh This also disables the ICAP2 event Bit 6 5 LCV1 LCVO VSYNCO Extraction Control VSYNCO Control Bits Normal mode Counter capture on input falling edge Normal mode Counter capture on input rising edge Extraction mode CSYNCI HSYNCI Positive polarity CV4 0 counter maximum threshold LCVO Extraction mode 1 CSYNCI HSYNCI Negative polarity CV4 0 counter minimum threshold Bit 4 0 CV4 CVO Counter Captured Value These bits contain the counter captured value in different modes In VSYNCO extraction mode they contain the HSYNCI pulse width measurement POLARITY REGISTER POLR B
96. e width and polarity signal and can be configured as pseudo front porch or back porch To use the ClampOut signal Select the Clamping Pulse width 1 bits in MCR register Program the Clamp polarity CLPINV bit in POLR register Select the ClampOut signal as back porch after falling edge of HSYNCO or pseudo front porch after the rising edge of HSYNCO 50 51 bits in MCR register Enable the CLAMPOUT signal CLMPEN bit in ENR register Figure 40 Clamping Pulse CLAMPOUT Delay T72774 ST727754 ST 72734 Moire Signal The Moire output signal is available instead of the clamping signal to reduce the screen Moire effect and improve color transitions The CLAMPOUT pin is alternatively used to output a Moire signal The output signal toggles at each HFBACK rising edge After each VFBACK falling edge the value of the Moire output is the opposite of the previous one independent of the number of HFBACK pulses during the VFBACK low level To use the Moire signal Select the Moire signal Reset the 1 bits in MCR register Enable the output signal CLMPEN bit in ENR register HSYNCO i ml Maximum delay Fixed delay of 10 to 30ns fosc 2 approx 110ns CLAMPOUT Programmable clamping width 0 167ns 333ns 666ns 4 59 144 ST72774 81T727754 8172734 Figure 41 Moire Output instead of Clamping Output VFBACK HFBACK
97. ed as Input lines with pull up or as Push pull Outputs Table 8 Port A Description 1 0 mur 172774 1727754 172734 6 3 defined Input lines without pull or as Output Open lines PA 2 0 be defined as Input lines with pull up or as Push pull Outputs 6 3 can be defined as Input lines without pull up or as Output Open drain lines Alternate Function With pull up push pull With pull up push pull VSYNCSEL 1 With pull up push pull VSYNCI2 MISCR ma werd TN E 1 With pull up push pull BLANKOUT ENR SYNC Reset State 4 29 144 5772774 5 727754 5 72734 PORTS Cont d Figure 17 PAO to 2 PA7 Alternate enable Alternate Vpp output DR latch P BUFFER DATA BUS lt N BUFFER DR SEL 1 1 4 0 CMOS Schmitt Trigger Figure 18 to PA6 Alternate enable Alternate 1 output N BUFFER e 2 e lt lt Alternate enable Vss Alternate input CMOS Schmitt Trigger 30 144 4 PORTS 4 1 4 Port The alternate functions are the I O pins of the on chip DDC SCLD SCDAD for PBO 1 the I O pins of the on chip 12 SCLI amp SCDAI for PB2 3 and 4 bits of port B bit can be used as the Analog source to the Analog to Digital Converter Only one I O line must be
98. ed or badly decoupled power supply lines See electrical characteristics section for more details AIN0 ANALOG TO DIGITAL CONVERTER 4 123 144 ST72774 ST727754 ST72734 4 10 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the result never decreases if the analog input does not and never increases if the analog input does not If the input voltage is greater than or equal to VppA high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage is lower than or equal to VssA low level voltage reference then the conversion result in the DR register is 00 The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the parametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time 4 10 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 77 m Sample capacitor loading duration tj During this phase the Van input voltage to be measured is loaded into the sample capacitor m A D conversion duration During this phase the A D conversion is computed 8 suc
99. entative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instructions Bit 1 Z Zero This bit is set and cleared by hardware This bit indicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and software It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions 4 CPU REGISTERS Contd Stack Pointer SP Read Write Reset Value 01 FFh 15 8 0 0 0 0 0 0 0 1 7 0 TT canon The Stack Pointer is a 16 bit register which is always pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 6
100. erated HSYNC signals HGENR hex value HPerod PuiseWidin Table 18 Typical values for generated VSYNC signals HGENR V11bits H Period V Period V Freq hex value hex value 0 us 95 Rz 8 us Hz 04 6 3 ms 61 Hz 8 us 125 kHz 400 us 1024 122 Hz 32 us As 3s ee 625 40000 64ms 9 4 64 144 T72774 ST727754 ST 72734 SYNC PROCESSOR SYNC Cont d 4 4 8 Analyzer Mode The analyzer block is used for all extra measurements on the sync signals to manage the monitor functions Measure the number of scan lines per frame VFBACK to simplify the OSD ver tical centering Measure the low level of HSYNCO or HFBACK This function can be used for VSYNCO pulse extension or for a fast estimation of the incoming Hsync signal period Detection of the pre post equalization pulses Notes 1 Analyzer mode should be performed before corrector mode 2 When analyzer mode is active the free running frequencies generator and corrector mode must be disabled HVGEN 0 in ENR register 2FHINH 0 in CFGR register for Horizontal low level measurement VEXT 0 VCORDIS 1 CFGR POLR reg isters for Vertical output measurement 3 If H VBACK are selected FBSEL 0 corrector mode must be disabled 4 For all measurements HSYNCO and VSYNCO must be POSITIVE 4 4 8 1 Horizontal Low Level Measurement
101. errupt enabled Bit 0 ITAITE ITA Interrupt Enable This bit is set and cleared by software 0 ITA interrupt disabled 1 ITA interrupt enabled 4 4 PERIPHERALS 4 1 1 0 PORTS 4 1 1 Introduction The ports allow the transfer of data through digital inputs and outputs and for specific pins the input of analog signals or the Input Output of alternate signals for on chip peripherals DDC TIMER Figure 15 Pin Typical Circuit 172774 1727754 172734 Each programmed independently as digital input or digital output Each pin can be an analog input when an analog switch is connected to the Analog to Digital Converter ADC Alternate enable Alternate 1 output Data Bus o lt S O Alternate Input Vpp P BUFFER if required PULLIUP if required Alternate enable Analog Enable do Y Analog Switch if required N BUFFER Alternate Enable Digital Enable Note This is the typical I O pin configuration For cost optimization each port is customized with a specific configuration ky 27 144 ST72774 S1727754 9172734 PORTS Cont d Table 7 Pin Functions 4 1 2 Common Functional Description Each port pin of the I O Ports can be individually configured under software control as either input or output Each bit of a Data Direction Register DDR
102. erview of the USB interface hardware NRZI encoding For general information on the USB refer to the Universal Serial Bus Specifications document available at http www usb org Transceiver pE 3 3V Voltage Regulator ST72774 ST727754 ST72734 Serial Interface Engine The SIE Serial Interface Engine interfaces with the USB via the transceiver The SIE processes tokens handles data transmission reception and handshaking as required by the USB standard It also performs frame formatting including CRC generation and checking Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit receive and how many bytes need to be transmitted DMA When token for a valid Endpoint is recognized by the USB interface the related data transfer takes place using DMA At the end of the transaction an interrupt is generated Interrupts By reading the Interrupt Status register application software can know which USB event has occurred Figure 50 USB block diagram ENDPOINT REGISTERS Address data busses and interrupts INTERRUPT REGISTERS MEMORY 79 144 ST72774 ST727754 ST72734 USB INTERFACE Cont d 4 6 4 Register Description DMA ADDRESS REGISTER DMAR Read Write Reset Value Undefined 7 0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 Bits 7 0 DA 15 8 DMA address bits 15 8 See the description of bits DA7 6 in the next register IDR IN
103. eset Value 0000 0000 00h T72774 ST727754 ST 72734 DDC OWN ADDRESS REGISTER OAR Read Write Reset Value 0000 0000 00h de 0 7 0 Bit 7 0 D7 DO 8 bit Data Register These bits contain the byte to be received or transmitted on the bus Transmitter mode Byte transmission start auto matically when the software writes in the DR reg ister Receiver mode the first data byte is received au tomatically in the DR register using the least sig nificant bit of the address Then the next data bytes are received one by one after reading the DR register 4 Bit 7 1 ADD7 ADD1 Interface address These bits define the I C bus programmable address of the interface They are not cleared when the interface is disabled PE 0 Bit 0 ADD0 This bit is Don t Care the interface acknowledges either 0 or 1 It is not cleared when the interface is disabled PE 0 Note Address 011 is always ignored 113 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d DDC1 2B CONTROL REGISTER DCR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 Reserved Forced by hardware to 0 Bit 5 EDF End of Download interrupt Flag This bit is set by hardware and cleared by software 0 Download not started or not completed yet 1 Download completed Last byte of data struc ture relative address 7Fh or FFh has been stored in RAM Bit 4 EDE End of Download interrupt Enable This bit is set and cleared b
104. f VSYNCO or VFLYBACK For vertical analysis refer to Figure 49 Obtain the minimum number of horizontal sync pulses V1 between the falling edge of the vertical sync signal VSYNCO or VF BACK and the first rising edge of the active video input during 2 consecutive frames Clock Start Stop CONTROL fosc HSYNCO or 1 FROM SYNC PROCESSOR VSYNCO or VFBACK 1 Note 1 Selection between Sync outputs or Flyback inputs is made in MISCR register bit 6 FLY_SYN 4 75 144 ST72774 ST727754 ST72734 TIMING MEASUREMENT UNIT Cont d Obtain the minimum number of horizontal sync output pulses V2 between the last fall ing edge of the active video input AV and the rising edge of the vertical sync signal VSYN CO or VFBACK during two 2 consecutive frames The H_V bit selects horizontal or vertical measurement This selection should be made prior to starting the measurement by setting the START bit This bit is set by software but only cleared by hardware at the end of the measurement When the measurement is finished rising edge of AV horizontal or vertical sync signals the results T1 T2 are transferred into the corresponding registers H1 H2 or V1 V2 Note The values of the H1 H2 or V1 V2 registers are available only at the end of a measurement after the START bit has been cleared 4 5 3 1 Horizontal Measurement When the H_V bit 1 and when the START bit is se
105. ffered At 10 Other Instructions Returns the buffered At t0 Dt Read LSB LSB value at 0 Sequence completed The user must read the MSB first then the LSB value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MSB several times After a complete reading sequence if only the CLR register or ACLR register are read they return the LSB of the count value at the time of the read An overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is set A timer interrupt is generated if TOIE bit of the CRiregister is set and bit of the CC register is cleared If one of these conditions is false the interrupt remains pending to be issued as soon as they are both true T72774 ST727754 ST 72734 Clearing the overflow interrupt request is done by 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Notes The TOF bit is not cleared by accesses to ACLR register This feature allows simultaneous use of the overflow function and reads of the free running counter at random times for example to measure elapsed time without the risk of clearing the TOF bit erroneously The timer is not affected by WAIT mode 4 3 3 2 External Clock The external clock where available is selected if CCO 1 and CC1 1 in CR2 register
106. gister ACLR is the least significant byte LSB These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit overflow flag see note page 43 Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value The timer clock depends on the clock control bits ofthe CR2 register as illustrated in Table 15 Clock Control Bits The value in the counter register repeats every 131 072 262 144 or 524 288 internal processor clock cycles depending on the CCO bits 41 144 5772774 5 727754 5 72734 16 BIT Cont d Figure 27 Block Diagram ST7 INTERNAL BUS CPU CLOCK MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT FREE RUNNING COMPARE COMPARE CAPTURE CAPTURE COUNTER REGISTER REGISTER REGISTER REGISTER 2 COUNTER ALTERNATE REGISTER CC1 CCO ER vee wai OVERFLOW EXTCLK OUTPUT COMPARE EDGE DETECT O ICAP1 CIRCUIT CIRCUITI CIRCUIT EDGE DETECT C ICAP2 i CIRCUIT2 Puro gt o OOCMP1 n im 2 Oocmp2 CIE JOCIE FoLv2 2 IEDG1JOLVL1 locte ocze orm cot cco fence EXEDG CRI CR2 Jv gt V TIMER INTERRUPT 42 144 q 16 16 bit read sequence from either the Counter Register or the Alternate Counter Register Beginning of the sequence Read MSB LSB is bu
107. gister OAR Control register CR The following four registers are used during data transmission reception Data Register DR Control Register CR Status Register 1 SR1 Status Register 2 SR2 The interface decodes an I C or DDC2Bi address stored by software in the OAR register and or the EDDC address 60h 61h as its default hardware address After a reset the interface is disabled 4 172774 1727754 172734 4 8 5 2 2 m General description 2 mode the interface can operate in the following modes Slave transmitter receiver Both start and stop conditions are generated by the master The 12 clock SCL is always received by the interface from a master but the interface is able to stretch the clock line The interface is capable of recognizing both its own programmable address 7 bit and its default hardware address Enhanced DDC address 60h 61h The Enhanced DDC address detection may be enabled or disabled by software It never recognizes the Start byte 01h whatever its own address is m Slave Mode As soon start condition is detected the address is received from the SDA line and sent to the shift register then it is compared with the programmable address of the interface or the Enhanced DDC address if selected by software Address not matched the interface ignores it and waits for another Start condition Address matched the following events oc
108. gram EDGE DETECT EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R 16 BIT 16 BIT FREE RUNNING COUNTER Figure 32 Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note Active edge is rising edge 46 144 Control Register 1 CR1 Status Register SR Control Register 2 CR2 4 16 BIT TIMER Cont d 4 3 3 4 Output Compare In this section the index may be 1 or 2 This function can be used to control an output waveform or indicating when a period of time has elapsed When a match is found between the Output Compare register and the free running counter the output compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the free running counter each timer clock cycle MS Byte OCIHR LS Byte OCILR These registers readable and writable not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter fcPU CC1 CC0 Procedure To use the output compare function select the following in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedic
109. hat contains the low part of the counter value 7 0 pu Spp When a T2 measurement is finished rising edge on the selected sync signal the 11 bit counter value is transferred to this register and to the T2 10 8 bits in the CSR register T2 is H2 value if the V bit 1 T2 is V2 value if the H V bit 0 77 44 ST72774 ST727754 ST72734 TIMING MEASUREMENT UNIT Cont d Table 22 TMU Register Map and Reset Values Address Register Hex Name CSR s bs bs un m Pu START Reset Value is vs EN Reset Value 1 1 1 1 1 1 1 1 8 Reset Value 1 1 1 1 1 1 1 1 4 78 144 4 6 USB USB 4 6 1 Introduction USB Interface implements low speed function interface between the USB and the ST7 microcontroller It is a highly integrated circuit which includes the transceiver 3 3 voltage regulator SIE and DMA No external components are needed apart from the external pull up on USBDM for low speed recognition by the USB host 4 6 2 Main Features USB Specification Version 1 0 Compliant Supports Low Speed USB Protocol m Two or Three Endpoints including default one depending on the device see device feature list and register map m CRC generation checking decoding and bit stuffing USB Suspend Resume operations DMA Data transfers On Chip 3 3V Regulator On Chip USB Transceiver 4 6 3 Functional Description The block diagram in Figure 50 gives an ov
110. high part of the counter value 7 0 E ES ALTERNATE COUNTER LOW REGISTER ACLR Read Write Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 MSB LSB INPUT CAPTURE 2 HIGH REGISTER IC2HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event 7 0 MSB LSB INPUT CAPTURE 2 LOW REGISTER IC2LR Read Only Reset Value Undefined ST72774 ST727754 ST72734 16 BIT TIMER Cont d Table 16 16 Bit Timer Register Map Address Register 7 1 Hex Name CR2 OC1E OC2E OPM PWM CC0 IEDG2 EXEDG m or oor tor e o o 437 55 144 ST72774 ST727754 ST72734 4 4 SYNC PROCESSOR SYNC 4 4 1 Introduction Control the sync output polarities The Sync processor handles all the management Generate free running frequencies tasks of the video synchronization signals and is used with the timer and software to provide information and status on the video standard and timings This block supports multiple video standards such as Separate Sync Composite m Analyzer Mode Generate a video blanking signal Generate a clamping signal or a Moire signal Sync and v
111. hs and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler 4 3 2 Main Features Programmable prescaler fp divided by 2 4 or 8 Overflow status flag and maskable interrupt External clock input must be at least 4 times slower than the CPU clock speed with the choice of active edge m Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt Pulse width modulation mode PWM One pulse mode m 5 alternate functions on I O ports The Block Diagram is shown in Figure 27 Note Some external pins are not available on all devices Refer to the device pin out description 172774 1727754 172734 4 3 3 Functional Description 4 3 3 1 Counter The principal block of the Programmable Timer is a 16 bit free running counter and its associated 16 bit registers Counter Registers Counter High Register CHR is the most sig nificant byte MSB Counter Low Register CLR is the least sig nificant byte LSB Alternate Counter Registers Alternate Counter High Register ACHR is the most significant byte MSB Alternate Counter Low Re
112. ia an external extractor Sync on Measure the number of scan lines per frame to Green The internal clock in the Sync processor is simplify OSD vertical centering 4 MHz Detect HSYNCI reaching too high a frequency Detect pre post equalization pulses 4 4 2 Main Features Measure the low level of HSYNCO or Input Processing Presence of incoming signals edge detection Read the HSYNCI VSYNCI input signal levels Inhibit Pre Post equalization pulses Measure the signal periods Program VSYNCO pulse width extension _ VSYNCO pulse widths during Betectinesyne polarities post equalization pulse detection only Detect the composite sync and extract VSYNCO pre and post equalization pulse detection Corrector Mode Note Some external pins are not available on all devices m Output Processing Refer to the device pinout description Figure 37 Sync Processor Block Diagram ICAP1 TIMER VSYNCH D VSYNCI2 D vsync Control Logic Up Down EN VSYNC Generator 5 Bit Counter 40 200 Hz K N Sync Generator Typical Pulse Width Sync Analyzer 20 256 us Positive polarity fINT Latch Latch Sync Corrector HSYNC Generator see note 00 1F Hardware Block 15 200 kHz match match Duty cycle range BS PSCD HSYNCI1 D HSYNCI2 O HSYNCI CSYNCI Generator Note CLK is
113. ins T72774 ST727754 ST 72734 Transmit only Clock Vsync Vsync2 The Vsync input pins are used to synchronize all data in and out of the device when in Transmit only mode These pins are ONLY used by the DDC1 2B interface when in DDC1 mode 97 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d 4 8 4 BUS Protocol A standard 122 communication is normally based on four parts START condition device slave address transmission data transfer and STOP condition They are described brielfly in the following section and illustrated in Figure 58 for more details refer to the 2 bus specification 4 8 4 1 START condition When the bus is free both SCL and SDA lines at a level a master can initiate communication by sending a START signal This signal is defined as a high to low transition of SDA while SCL is stable high The bus is considered to be busy after a START condition This START condition command for data transfer must precede any 4 8 4 2 Slave Address Transmission The first byte following a START condition is the slave address transmitted by the master This address is 7 bit long followed by an 8th bit Least significant bit LSB which is the data direction bit R W bit 0 indicates a transmission WRITE from the master to the slave A 1 indicates a request for data READ from the slave to the master If a slave device is present on the bus
114. ister corresponding to the binary weight of the PWM pulse A 4 bit BRM register defining the intervals where an incremental pulse is added to the beginning of the original PWM pulse Two BRM channel val ues share the same register Note The number of PWM and BRM channels available depends on the device Refer to the device pin de scription and register map PWN 1 8 REGISTERS Read Write Reset Value 1000 0000 80h 7 0 Ps pas Bit 7 Reserved read as 1 Bit 6 POL Polarity Bit When POL is set output signal polarity is inverse otherwise no change occurs Bits 5 0 P 5 0 PWM Pulse Binary Weight for channel i For example 10 bit Effective with external RC filtering DAC value ST72774 ST727754 ST72734 BRM REGISTERS BRM21 Channels 2 1 BRM43 Channels 4 3 BRM65 Channels 6 5 BRM87 Channels 8 7 Read Write Reset Value 0000 0000 00h 7 0 OOOO Bits 7 4 B 7 4 BRM Bits channel i 1 Bits 3 0 B 3 0 BRM Bits channel i 4 9 4 2 OUTPUT ENABLE REGISTER Read Write Reset Value 1000 0000 80h 7 0 Bit 7 0 OE 7 0 Output Enable Bit When is set PWM output function is enabled 0 PWM output is disabled 1 PWM output is enabled Note From the programmer s point of view the PWM and registers can be regarded as being combined to give one data value TES Ds DE TIER ERST 121 144 5772774 5 727754 5 72734 Table 29 PWM Register
115. its 5 4 Read Only other bits Read Write Reset Value 0000 1000 08h 7 0 o VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV Bit 7 SOG Sync On Green Detector SOG is set by hardware if CSYNCI pulse is not included in the window between HSYNCI rising edge HSYNCI falling edge dt Cleared by software 70 144 Table 19 Sync On Green Window WINDOW DELAY me Bit 6 Reserved forced by hardware to 0 Bit 5 VPOL Vertical Sync polarity read only 0 Positive polarity 1 Negative polarity Note If the Vertical Sync polarity is changing the VPOL bit will be updated after a typical delay of 4 msec Bit 4 2FHDET Detection of Pre Post Equalization pulses read only This bit is continuously updated by hardware It is valid when the sync generator and horizontal analyzer are disabled HVGEN 0 HACQ 0 0 None detected 1 Pre Post Equalization pulses detected Bit 3 HVSEL Alternate Sync Input Select This bit selects between the two sets of Horizontal and Vertical Sync inputs 0 HSYNCI2 VSYNCI2 1 VSYNCI1 Bit 2 VCORDIS Extension Disable Signal Extension with VGENR Register 0 enable 1 disable Bit 1 CLPINV Programmable ClampOut pulse polarity 0 Positive 1 Negative Bit 0 BLKINV Programmable blanking polarity 0 Negative 1 Positive q SYNC PROCESSOR SYNC Con d LATCH REGISTER LATR Read Write Reset Value 0000 0000 00h 7 0 CSYN HSYN
116. ized Both EDID structures v1 and v2 are used FPDI 2 0 1 1 CF0z1 DDC1 is disabled and device addresses A6h A7h are recognized EDID v2 is used Table 25 Valid Device Addresses and EDID structure Device Address 2 bit CF1 bit bit Transfer Type EDID v1 Ath 1010 000x EDID v2 A2h A3h 1010 001x EDID v2 A6h A7h 1010 011x 4 SRB NRW 128 byte EDID structure write read 0 1 f 0 256 byte EDID structure write read sasa 9 256 byte EDID structure write read 99 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d The Write and Read operations allow the EDID data to be downloaded during factory alignment for example Writes to the memory by the DMA engine can be inhibited by means of the WP bit in the DCR register A write of the last data structure byte sets a flag and may be programmed to generate an interrupt request The Data address sub address is either the second byte of write transfers or is pointed to by the internal address counter automatically incremented after each byte transfer Physical address mapping of the data structure within the memory space is performed with a dedicated register accessible by software 4 8 5 1 2 Mode description DDC1 Mode This mode is only enabled when the DDC v2 or P amp D DDC v2 standards are validated It transmits only the EDID v1 data 128 bytes To switch the DDC1 2B Interfa
117. ken received The USB standard defines TP bits as Bit 5 0 Reserved Forced by hardware to 0 INTERRUPT STATUS REGISTER ISTR Read Write Reset Value 0000 0000 00h 7 0 0 DOVR CTR ERR IOVR ESUSP RESET SOF When an interrupt occurs these bits are set by hardware Software must read them to determine the interrupt type and clear them after servicing Note These bits cannot be set by software Bit 7 Reserved Forced by hardware to 0 Bit 6 DOVR DMA over underrun This bit is set by hardware if the ST7 processor can t answer a DMA request in time 0 No over underrun detected 1 Over underrun detected 4 T72774 ST727754 ST 72734 Bit 5 CTR Correct Transfer This bit is set by hardware when a correct transfer operation is performed The type of transfer can be determined by looking at bits TP3 TP2 in register PIDR The Endpoint on which the transfer was made is identified by bits EP1 EPO in register IDR 0 No Correct Transfer detected 1 Correct Transfer detected Note A transfer where the device sent a NAK or STALL handshake is considered not correct the host only sends ACK handshakes A transfer is considered correct if there are no errors in the PID and CRC fields if the DATAO DATA1 PID is sent as expect ed if there were no data overruns bit stuffing or framing errors Bit 4 ERR Error This bit is set by hardware whenever one of the errors listed below has occurred 0
118. king HSYNCO is blanked during VSYNCO pulse 0 Enabled 1 Disabled the extracted Bit 1 HSIN1 read only Returns the HSYNCI1 pin level Bit 0 2 VSIN1 read only Returns the pin level Table 20 Summary of the Main Sync Processor Modes Sync Processor Mode SYNOP HVSEL HVGEN HACQ VACQ DSUB Selected as Inputs HSYNCH VSYNCI1 BNC Selected as Inputs HSYNCI2 VSYNCI2 Don t drive the monitor with any Sync signals Generate Sync Signals to drive the Monitor hardware Use the Sync Processor to drive the monitor hardware by incoming Sync signals Analyse the number of Scan Lines 1 during one vertical frame Analyse the HSYNC delay 1 between two pulses 4 73 144 ST72774 81T727754 8172734 SYNC PROCESSOR SYNC Cont d Table 21 SYNC Register Map and Reset Values ves Tes Reset Value 0 E C EN 0 0 MCR BP1 BPO FBSEL SCIO Reset Value 0 0 40 41 42 3 AER Tete 0 0 0 HS1 0 VOP CCR PSCD LCV0 CV4 V2 CV1 CV0 ERES cd n Reset Value 0 0 0 1 0 0 0 Reset Value 0 0 0 0 0 0 0 0 lz Reset Value 0 0 Reset Value 0 Reset Value 1 1 0 0 0 0 1 4 74 144 172774 1727754 172734 4 5 TIMING MEASUREMENT UNIT TMU 4 5 1 Introduction The timing measurement unit TMU allows the analysis of the current video timing characteristics in order to control displa
119. mal sequence The Watchdog circuit generates reset on expiry of programmed time period unless the program Figure 26 Watchdog Block Diagram ST72774 ST727754 ST72734 refreshes the counter s contents before the T6 bit becomes cleared 4 2 2 Main Features m Programmable timer 64 increments of 49152 CPU cycles m Programmable reset m Reset if watchdog activated when the bit reaches zero WATCHDOG CONTROL REGISTER CR 7 BIT DOWNCOUNTER CLOCK DIVIDER 49152 4 2 3 Functional Description The counter value stored in the CR register bits T6 T0 is decremented every 49 152 machine cycles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T6 TO rolls over from 40h to 3Fh becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns The application program must write in the CR register at regular intervals during normal ky operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and COh see Table 13 Watchdog Timing fCPU 8 MHz WDGA bit is set watchdog enabled The 6 bit is set to prevent generating an imme diate reset The T5 TO bits contain the number of increments which represents the time delay before the watchdog produces a reset 39 144 ST72774 8
120. ming period greater than this previously captured value This is then processed as the VSYNCO signal To use the Vsync extractor the following steps are necessary Detection of a composite sync signal When the UPLAT and DOWNLAT bits in LATR register are set a composite sync signal or a HSYNCI polarity change is detected If these bits are stable during two subsequent ICAP2 interrupt the composite sync signal is stable Defining a threshold Select the normal mode LCV1 LCVO 0 in the CCR register Initialize the counter capture CV4 CVO to 0 This automatically measures the HSYNCI pulse width It defines a threshold in the 4 0 bits used by the 5 bit up down counter It also allows to check the HSYNCI polarity refer to the 5 bit Up Down Counter Check paragraph If a user defined tolerance is to be added then an updated value should be written in the CCR register CV4 CVO bits In a composite sync signal Hsync and Vsync always have the same polarity Starting the hardware extraction mode According to the Composite sync polarity select the extraction mode LCV1 LCVO in CCR register and rewrite the counter if necessary Negative polarity minimum threshold 00h Positive polarity maximum threshold 1Fh Note The extracted VSYNCO signal negative polarity always has ky 172774 1727754 172734 SYNC PROCESSOR SYNC 4 4 6 5 Example of VSYNCO ext
121. n is directly performed from the Data Register output 4 1 2 3 Analog input Each I O can be used as analog input by adding an analog switch driven by the ADC The must be configured in Input before using it as analog input The CMOS Schmitt trigger is OFF and the analog value directly input through an analog switch to the Analog to Digital Converter when the analog channel is selected by the ADC 4 1 2 4 Alternate mode A signal coming from a on chip peripheral can be output on the I O In this case the I O is automatically configured in output mode This must be controlled directly by the peripheral with a signal coming from the peripheral which enables the alternate signal to be output A signal coming from an I O can be input in a on chip peripheral Before using an I O as Alternate Input it must be configured in Input mode DDR 0 So both Alternate Input configuration and Input configuration are the same with or without pull up The signal to be input in the peripheral is taken after the CMOS Schmitt trigger or TTL Schmitt trigger for SYNC The state is readable as in Input mode by addressing the corresponding Data Register q Figure 16 Input Structure for signals TTL trigger HSYNCI Input VSYNCI Input no pull up logic if existing TTL trigger CSYNCI Input HFBACK Input VFBACK Input I O logic if existing 4 1 3 Port A PA7 and PA 2 0 can be defin
122. ng the ITALAT ITBLAT or ITAITE ITBITE bits in the miscellaneous register Peripheral Interrupts Different peripheral interrupt flags are able to cause an interrupt when they are active if both the I bit of the CC register is reset and if the corresponding enable bit is set If either of these conditions is false the interrupt is latched and thus remains pending The interrupt flags are located in the status register The Enable bits are in the control register When an enabled interrupt occurs normal processing is suspended at the end of the current instruction execution It is then serviced according to the flowchart on Figure 13 The general sequence for clearing an interrupt is an access to the status register while the flag is set followed by a read or write of an associated register Note that the clearing sequence resets the internal latch A pending interrupt i e waiting for being enabled will therefore be lost if the clear sequence is executed 4 172774 1727754 172734 INTERRUPTS Conta Figure 13 Interrupt Processing Flowchart FROM RESET FETCH NEXT INSTRUCTION I EXECUTE INSTRUCTION STACK PC X A SET BIT LOAD PC FROM INTERRUPT VECTOR RESTORE PC X A CC FROM STACK THIS CLEARS BIT BY DEFAULT VR01172D 4 23 144 5772774 5 727754 5 72734 INTERRUPTS Conta Table 6 Interrupt Mapping Source AS Register Maskable Priority Bk Deseo a reser mes n
123. nisation input TTL levels 14 19 VSYNCI SYNC vertical synchronisation input Refer to Figure 16 15 20 PDO VSYNCO Port DO or SYNC vertical synchronisation output 16 21 PD1 HSYNCO Port D1 or SYNC horizontal synchronisation output TTL levels with pull up 17 22 PD2 CSYNCI Port D2 or SYNC composite synchronisation input SYNC input 8 144 r 72 ST72774 ST727754 ST 72734 Pin No 3 Pin Name Type Description Remarks ca 18 23 PD3 VFBACK ITA 8 54 2 22 inputorinterrupt tall Table 11 scription 19 24 PDA ITB lO Port D4 or Interrupt falling edge detector input 2 20 25 lO Port D5 or SYNC horizontal flyback input Bed s pull up 21 26 PD6 CLAMPOUT Port D6 or SYNC clamping MOIRE output 22 27 PBO SCLD Port BO or DDC serial clock 24 28 PB1 SDAD Port B1 or DDC serial data 25 29 PB2 SCLI Port B2 or 126 serial clock 26 30 PB3 SDAI Port or 2 serial data 27 31 PA7 BLANKOUT Port A7 or SYNC blanking output 28 32 OSCOUT Oscillator output 29 33 OSCIN Oscillator input 30 34 Port 31 35 Port 5 32 36 4 Port 4 33 37 Port 34 38 PA2 VSYNCI2 Port A2 or SYNC vertical synchronisation input 2 DDC1 only 35
124. o NAK 2 Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer Note When a interrupt occurs the TP3 TP2 bits in the PIDR register and EP1 EP0 bits in the IDR reg ister stay unchanged until the CTR bit in the ISTR register is cleared 3 Clear the CTR bit in the ISTR register 85 144 ST72774 ST727754 ST72734 USB INTERFACE Cont d Table 23 USB Register Map and Reset Values Hex Name Reset Value x x 0 0 Reset Value x x x x x x x IDR DA7 DA6 EP1 Reset Value X x x ISTR SUSP DOVR CTR ERR Reset Value 0 0 0 0 IMR Reset Value CTLR Reset Value DADDR Reset Value Reset Value EP1RA Reset Value EP1RB CTRL DTOG RX STAT RX1 STAT RXO 2 Reset Value 0 0 0 0 x x EP2RA ST OUT DTOG TX STAT TX1 STAT TXO TBC3 TBC2 TBC1 Reset Value 0 0 0 0 x x x EP2RB CTRL DTOG RX STAT RX1 STAT RXO 2 Reset Value 0 0 0 0 x x Reset Value 86 144 4 4 7 SINGLE MASTER BUS 2 4 7 1 Introduction The 12 Bus Interface serves an interface between the microcontroller and the serial I C bus It provides single master functions and controls all 2 bus specific sequencing protocol timing supports fast mode 400kHz 4 7 2 Main Features Parallel bus I2C protocol converter Interrupt generation Standard I C mode Fast I C mode 7 bit Addressing 2
125. ode but only allows 00 FF addressing space Direct long The address is a word thus allowing 64 Kbyte addressing space but requires 2 bytes after the opcode 5 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte after the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode 5 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory pointer The pointer address follows the opcode The indirect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long 127 144 ST72774 ST727754 ST72734 The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode 5 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexe
126. ollowing formula OCR A foru Where At Desired output compare period in seconds fcpu Internal clock frequency 1 Timer clock prescaler The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which be already set Write to the register enables the output compare function and clears the OCFi bit 47 144 ST72774 81T727754 8172734 16 BIT TIMER Cont d Figure 33 Output Compare Block Diagram 16 BIT FREE RUNNING 2 CC1 CCO Pols 16 bit Control Register 2 CR2 Control Register 1 CR1 OUTPUT COMPARE gt CIRCUIT OCIE OLVL2 OLVL1 16 bit 16 bit area Status Register SR Figure 34 Output Compare Timing Diagram Internal Clock Divided by 2 Su Laon T 1 OCMP2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OCFi AND OCMPi PIN OLVLi 1 48 144 4 16 BIT Cont d 4 3 3 5 Forced Compare Mode In this section may represent 1 or 2 The following bits of the CR1 register are used MN FOLV2 FOLV1 OLVL2 OLVL1 When the FOLVi bit is set the OLVLi bit is copied to the OCMP pin The FOLVi bit is not cleared b
127. one timer clock 500ns at 2 MHz so that the tolerance is 500ns for PH and 256 PH PH accuracy 1 95ns Notes 1 In case of composite sync the HSYNCI period measurement can be synchronized on the VSYNCI pulse by setting and resetting the prescaler PSCD bit in the CCR register for this function the ICAP2 detection must be selected as falling edge This avoids errors in the period measurement due to the Vsync pulse 2 The Timer Interrupt request should be masked during a write access to any of the Sync processor control registers Important Note Since the recognition of the video mode relies on the accuracy of the measurements it is highly recommended to implement a counter style algorithm which performs several consecutive measurements before switching between modes The purpose of this algorithm is to filter out any glitches occurring on the video signals 61 144 ST72774 ST727754 ST72734 SYNC PROCESSOR SYNC Cont d 4 4 6 3 Detecting Signal Polarity The Sync Processor provides two ways for checking input signal polarity by polling the latches or using the 5 bit up down counter Polling check HSYNCI polarity detection UPLAT DWNLAT bits in LATR register These bits are directly connected to the 5 bit Up Down counter UPLAT 1 DOWNLAT 0 HSYNCI polarity O UPLAT 0 DOWNLAT 1 HSYNCI polarity gt 0 VSYNCI Polarity Detection VPOL bit VSYNCO polarity in POLR and VOP bit VSYNCO pol
128. onverter Symb Parameter Conditions min unt 2 o X Ea EU fopy 8MHZ 2 2 tioAD Sample capacitor loading time Vpp 5V Raw renato L JE Rang _ memamo a e sue Sample capacior j LC PWM BRM Electrical and Timings Parameter Conditions Wax Unit c ReeWonme _ ___ Res Totens 9s s 5 q 136 144 ST72774 ST727754 ST72734 AC DC ELECTRICAL CHARACTERISTICS Cont d I2C DDC Bus Electrical specifications Hysteresis of Schmitt trigger inputs Fixed input levels 0 2 On Vpp related input levels lom Output fall time from VIH min to VIL max with a bus capacitance from 10 pF to 400 pF 20 0 1 with up to 3 mA sink current at VOL1 Tor ne b with up to 6 mA sink current at VOL2 20 0 1 not applicable Cb capacitance of one bus in pF I2C DDC Bus Timings Parameter Capacitive load for each bus line 1 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2 The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal Cb total capacitance of one bus line in pF 437 137 1
129. ory location being addressed It is made of two 8 bit registers and ALR AHR is initialized by software It defines the 256 byte block within the 64K address space containing the data structure ALR is loaded with the data address sent by the master after a write Device Address It defines the Figure 64 Mapping of DDC2B data structure byte within the data structure currently addressed ALR is reset upon entry into the DDC2B mode One exception to this arrangement is when the CF 1 0 bits 10b In this case the two EDID versions must coexist at non overlapping addresses The LSB of AHR is therefore ignored and automatically set to 1 to address the 128 byte EDID and set to 0 to address its 256 byte counterpart see Figure 64 DDC v2 P amp D FPDI 2 modes CF 1 0 bits 10b Basic EDID v1 Extended EDID v1 if present EDID v2 FFFFh A 128 byte Data A 5 Structure 5 256 byte Data 128 byte Data a ALR 80h gt FFh Structure Structure 00h gt 7Fh e e ee 0000h 0000h 0000h AOh A1h AOh A1h A2h A3h A6h A7h 15 87 0 v2 P amp D mode CF 1 0 bits 10b Basic EDID v1 Extended EDID v1 if present EDID v2 FFFFh FFFFh FFFFh 128 byte Data E Structure 128 byte Data ALR ie FFh A Structure At gt 7Fh Q o 2 Ex Nom Dat ALR N 512 0000h 0000h 0000h AOh A1h AOh A1h A2h A3h 15 987 15 987 0 Addr Poin
130. pport for DDC1 2B communications VESA specification versions 2 and 3 m Hardware detection of DDC2B addresses A0h Ath and optionally A2h A3h P amp D or A6h A7h FPDI 2 Separate mapping of EDID version 1 128 bytes and EDID version 2 256 bytes when both must coexist m Support for error recovery mechanism Detection of misplaced Start and Stop conditions Figure 56 DDC Interface Overview VSYNC 4 4 VSYNCI VSYNC2 4 4 VSYNCI2 4 172774 1727754 172734 2 byte random and sequential read modes m DMA transfer from any memory location and to RAM m Automatic memory address incrementation m End of data downloading flag and interrupt capability 4 8 2 2 DDC CI Factory Interface Features General 2 Features Parallel bus I2C protocol converter Interrupt generation Standard mode Fast IC mode 7 bit Addressing Slave Features 12C bus busy flag Start bit detection flag Detection of misplaced Start or Stop condition Transfer problem detection Address Matched detection Programmable Address detection and or Hardware detection of Enhanced DDC ED DC addresses 60h 61h End of byte transmission flag Transmitter Receiver flag Stop condition Detection 12 SLAVE INTERFACE DDC CI Factory Alignment HARDWARE DDC1 2B INTERFACE 95 144 5772774 5 727754 5 72734 DDC INTERFACE Cont d Figure 57 DDC Interface Block Diagr
131. pt generation if ITE 1 It is cleared by software reading SR1 register followed by a read or write of DR register It is also cleared by hardware when the interface is disabled PE 0 Following a byte transmission this bit is set after reception of the acknowledge clock pulse BTF is cleared by reading SR1 register followed by writing the next byte in DR register Following a byte reception this bit is set after transmission of the acknowledge clock pulse if ACK 1 BTF is cleared by reading SR1 register followed by reading the byte from DR register The SCL line is held low while BTF 1 0 Byte transfer not done 1 Byte transfer succeeded Bit 2 ADSL Address matched Slave mode This bit is set by hardware as soon as the received slave address matched with the OAR register content or the Enhanced DDC address is recognized An interrupt is generated if ITE 1 It is cleared by software reading SR1 register or by hardware when the interface is disabled PE 0 The SCL line is held low while ADSL 1 0 Address mismatched or not received 1 Received address matched Bit 1 0 Reserved Forced to 0 by hardware 111 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d DDC STATUS REGISTER 2 SR2 Read Only Reset Value 0000 0000 00h 7 0 Bit 7 5 Reserved Forced to 0 by hardware Bit 4 AF Acknowledge failure This bit is set by hardware when no acknowledge is returned An interrupt is generated if
132. raction for a negative composite sync with serration pulses Refer to Figure 43 In extraction mode the 5 bit comparator checks the counter value with respect to the threshold When the incoming signal is high the counter is increased otherwise it is decreased When the counter reaches the threshold on its way down VSYNCO is asserted During the vertical blanking the counter value is decreased down to a programmable minimum i e it does not underflow When the vertical period is finished the counter starts counting up and when the maximum is reached VSYNCO is negated The extracted signal may be validated by software since it is input to Timer ICAP1 Serration pulses during vertical blanking can be filtered if the serration pulse widths are less than 8us In the same way positive composite sync signals can be used by properly selecting the edge sensitivity in HSYNCI width measurement mode LCVO bit Figure 43 Extraction from a Composite Signal negative polarity Composite signal Counter value 1 8us Serration pulses Max Pulse width 8 1F Threshold Input 4 Threshold 0 Min VSYNCO generated gt VSYNCO Pulse gt Max Delay 8us or threshold HSYNCO n VR01990 Figure 44 Obtaining the 11 bit Vertical Period V11BITS vw T AT Em c 4 VGENR CCh CFGR 3h V11bits 663h 63 144 5772774 51727754 51727
133. rating a STOP condition Addr Poi XXXXh Aw ADDR 1 ADDR n 1 ADDR n ointer DATA ADDR DATA IN 1 DATAIN2 DATAINn 1 m Read Operations All read operations consist of retrieving the data pointed to by an internal address counter which is initialized by a dummy write and incremented by any read DDC1 2B Interface always waits for an acknowledge during the 9th bit time If the master does not pull the SDA line low during this bit time the DDC1 2B Interface ends the transfer and switches to a stand by state Current address read After generating a START condition the master sends a read device address RW 1 The DDC1 2B Interface ac knowledges this and outputs the data byte point ed to by the internal address pointer which is subsequently incremented The master must NOT acknowledge this byte and must terminate the transfer with a STOP condition ky Random address read The master performs a dummy write to load the data address into the ALR Then the master sends a RESTART condi tion followed by a read Device Address RW 1 Sequential address read This mode is similar to the current and random address reads except that the master DOES acknowledge the data byte for the DDC1 2B Interface to output the next byte in sequence To terminate the read opera tion the master must NOT acknowledge the last data byte and must generate a STOP condition The data outp
134. ration mode works as an 11 bit hor izontal line counter 2047 scan lines per frame max The 3 LSB are in the CFGR register Refer to Figure 44 Case HVGEN 0 Analyzer Corrector Mode Sub case 1 Analyzer Mode Set the VACQ bit to start analyzer mode When VACQ is cleared by hardware VGENR CFGR returns the number of scan lines during the VSYNCO VFBACK low level period Sub case 0 Corrector Mode VSYNCO pulse width is extended by VGENR scan lines If VGENR 0 all VSYNCO corrections are disabled q SYNC PROCESSOR SYNC Cont d ENABLE REGISTER ENR Read Write Reset Value 1100 0011 C3h 7 0 SYNOP BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1 Bit 7 enable 0 Enabled 1 Disabled SYNOP HSYNCO VSYNCO outputs Bit 6 CLMPEN Clamping or Moire output ena ble 0 Clamping or Moire output function of BPO BP1 enabled 1 Clamping or Moire output disabled Bit 5 BLKEN B anking Output 0 Disabled 1 Enabled Bit 4 HVGEN Sync Generation function 0 Analyzer Corrector Mode 1 Generation of HSYNCO and VSYNCO free running frequencies T72774 ST727754 ST 72734 Bit 3 2 VSYNCO Extension VSYNCO is forced high when detecting pre and post equalization pulses It is valid when the sync generator and analyzer are disabled HVGEN 0 HACQ 0 VACQ 0 Refer to the procedure in Section 4 4 9 Corrector Mode 0 Disabled 1 Enabled Bit 2 HINH HSYNCO Blan
135. re 55 for the relationship between the events and the interrupt SCL is held low when the SB or BTF flags or an EV2 event See Figure 54 is detected 91 144 ST72774 ST727754 ST72734 SINGLE MASTER BUS INTERFACE Cont d STATUS REGISTER 1 SR1 Read Only Reset Value 0000 0000 00h 7 0 Bit 7 EVF Event flag This bit is set by hardware as soon as an event occurs It is cleared by software reading SR2 register in case of error event or as described in Figure 54 It is also cleared by hardware when the interface is disabled PE 0 0 No event 1 One of the following events has occurred BTF 1 Byte received or transmitted SB 1 Start condition generated 1 No acknowledge received after byte transmission if 1 Address byte successfully transmitted Bit 6 Reserved Forced to 0 by hardware Bit 5 TRA Transmitter Receiver When BTF is set TRA 1 if a data byte has been transmitted It is cleared automatically when BTF is cleared It is also cleared by hardware when the interface is disabled 0 0 Data byte received if BTF 1 1 Data byte transmitted Bit 4 Reserved Forced to 0 by hardware Bit 3 BTF Byte transfer finished This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE21 I is cleared by software reading SR1 register followed by a read or write of DR register It is also cleared by hardware
136. resentative of the result of the instruction just executed This register can also be handled by the PUSH and POP instructions These bits can be individually tested and or controlled by specific instructions Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruction The H bit is useful in BCD arithmetic subroutines Bit 3 I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt This bit is cleared by software 0 Interrupts are enabled 1 Interrupts are disabled This bit is controlled by the RIM SIM and IRET instructions and is tested by the JRM and JRNM instructions Note Interrupts requested while is set are latched and can be processed when is cleared By default an interrupt routine is not interruptable because the bit is set by hardware when you 16 144 enter it and reset by the IRET instruction at the end of the interrupt routine If the bit is cleared by software in the interrupt routine pending interrupts are serviced regardless of the priority level of the current interrupt routine Bit 2 N Negative This bit is set and cleared by hardware It is repres
137. s registers reset 3 2 4 Opcode Detection instructions corresponding to no valid opcode generate a reset Refer to ST7 Programming Manual 4 20 144 172774 1727754 172734 Cont d Figure 10 Low Voltage Detector Functional Diagramgure 11 LVD Reset Signal Output RESPOF INTERNAL RESET Note See electrical characteristics section for values of VIRM Figure 12 Reset Timing Diagram toxov fcpu Py L E EFFE Y FFFF _ 4096 CPU clock CYCLES N DELAY WATCHDOG RESET Note Refer to Electrical Characteristics for values of tppr toxov ana tRL 21 144 4 ST72774 ST727754 ST72734 3 3 INTERRUPTS The ST727x4 may be interrupted by one of two different methods maskable hardware interrupts as listed in Table 6 and a non maskable software interrupt TRAP The Interrupt processing flowchart is shown in Figure 13 The maskable interrupts must be enabled in order to be serviced However disabled interrupts can be latched and processed when they are enabled When an interrupt has to be serviced the PC X A and CC registers are saved onto the stack and the interrupt mask I bit of the Condition Code Register is set to prevent additional interrupts The Y register is not automatically saved The PC is then loaded with the interrupt vector of the interrupt to service and the interrupt service routine runs refer to Tabl
138. s copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and is set in the CR2 register This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 Input Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the register and the bit is set in the CR2 register 51 144 ST72774 ST727754 ST72734 16 BIT TIMER Cont d CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Enable 0 Output Compare 1 function is enabled but the OCMP1 pin is a general I O 1 Output Compare 1 function is enabled the OCMP pin is dedicated to the Output Com pare 1 capability of the timer Bit 6 OC2E Output Compare 2 Enable 0 Output Compare 2 function is enabled but the OCMP2 pin is a general I O 1 Output Compare 2 function is enabled the OCMP2 pin is dedicated to the Output Com pare 2 capability of the timer Bit 5 OPM One Pulse Mode 0 One Pulse Mode is not active 1 One Pulse Mode is active the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin the active transition is given by the IEDG1 bit The length of the generated
139. s set and an interrupt is generated if the ITE bit is set The SCL line is stretched low m STOPF Detection of a Stop condition after an acknowledge time slot The state machine is reset Then the STOPF flag is set and an interrupt is generated if the ITE bit is set q ST72774 ST727754 ST72734 DDC INTERFACE Cont d Figure 67 Transfer Sequencing Slave receiver S assess Slave transmitter _ ET EV2 EV4 Legend S Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITE 1 EVF 1 ADSL 1 cleared by reading SR1 register EV2 EVF 1 BTF 1 cleared by reading SR1 register followed by reading DR register EV3 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register 4 EVF 1 STOPF 1 cleared by reading SR2 register Figure 68 Event Flags and Interrupt Generation ITE INTERRUPT EVF 109 144 4 ST72774 ST727754 ST72734 DDC INTERFACE Cont d 4 8 6 Register Description DDC CONTROL REGISTER CR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 6 Reserved Forced to 0 by hardware Bit 5 PE Peripheral enable This bit is set and cleared by software 0 Peripheral disabled 1 Slave capability Notes When 0 all the bits of the CR register and the SR register are reset All outputs are re leased while PE 0 When 1 the corresponding pins are se lected by hardware as alternate
140. sed to extend the video blanking signal Procedure 1 HSYNCO and VSYNCO polarities must be positive 2 Set the 2FHINH bit in the CFGR register only if some pre post equalizations pulses are detected 2FHLAT 2FHDET flags 3 The extension will be the number of HSYNCO periods set in the VGENR register 4 Reset the VCORDIS bit in the POLR register Extend VSYNCO width during all post equaliza tion pulses This function extends the VSYNCO pulse width when post equalization pulses are detected 2FHDET bit in the POLR register and 2FHLAT bit in the LATR register 4 T72774 ST727754 ST 72734 Procedure 1 HSYNCO and VSYNCO polarities must be positive 2 Set the 2FHINH bit in the CFGR register to remove pre post equalization pulses 3 Measure the low level of HSYNCO 4 Update HGENR FFh HGENR 1 4 to add tolerance 5 Write VGENR gt 0 6 Reset the VCORDIS bit in the POLR register 7 Set the VEXT bit in the CFGR register Extend VSYNCO pulse width during pre and post equalization pulses for test only This function allows extending the VSYNCO pulse width as long as equalization pulses are detected VSYNCO VSYNCO 2FHDET Procedure and VSYNCO polarities must be positive Set the 2FHINH bit in the CFGR register to remove pre post equalization pulses Measure the low level of HSYNCO Update HGENR FFh HGENR 1 4 Write
141. stems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics All Rights Reserved Purchase of Components by STMicroelectronics conveys a license under the Philips 2 Patent Rights to use these components in an 2 system is granted provided that the system conforms to the 2 Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com
142. supports by hardware Two DDC communication protocols called DDC1 and DDC2B T72774 ST727754 ST 72734 Write operations into RAM Read operations from RAM In DDC1 the interface reads sequential EDID v1 data bytes from the microcontroller memory and transmits them on SDA synchronized with Vsync In DDC2B mode it operates in 2 slave mode The DDC1 2B Interface supports several DDC versions configured using the CF 2 0 bits in the DCR register which can only be changed while the interface is disabled HWPE bit 0 in the DCR register They define which EDID structure version is used and which Device Addresses are recognized Depending on the DDC version one or two device address pairs will be recognized and the corresponding EDID structure will be validated refer to Table 25 DDC v2 CF2 0 CF1 0 CF0 0 DDC1 is ena bled and device addresses AOh A1h are recog nized EDID v1 is used DDC v2 CF2 1 CF1 0 CF0 0 DDC1 is disa bled and device addresses AOh A1h are recog nized EDID v1 is used Plug and Display CF2 0 CF1 0 CF0 1 DDC1 is disabled and device addresses A2h A3h are recognized EDID v2 is used Plug and Display DDC v2 2 0 1 1 CF0 0 DDC1 is enabled and device addresses AOh A1h and A2h A3h are recognized Both EDID structures v1 and v2 are used Plug and Display DDC v2 CF2 1 CF1 1 CF0 0 DDC1 is disabled and device addresses AOh A1h and A2h A3h are recogn
143. t In this case the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set To resume set the START or STOP bit Note The SCL line is not held low 89 144 ST72774 ST727754 ST72734 SINGLE MASTER BUS INTERFACE Cont d Figure 54 Transfer Sequencing Master receiver 2 EVi EV2 7 EV3 Master transmitter Legend S Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITE 1 EV1 EVF 1 SB 1 cleared by reading SR1 register followed by writing DR register EV2 EVF 1 cleared by reading SR1 register followed by writing CR register for example PE 1 EV3 EVF 1 BTF 1 cleared by reading SR1 register followed by reading DR register EV4 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register Figure 55 Event Flags and Interrupt Generation ITE Ad EVF EVF aan also be set by EV2 or an error from the SR2 register 90 144 4 PC SINGLE MASTER BUS INTERFACE Cont d 4 7 5 Register Description I C CONTROL REGISTER CR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 6 Reserved Forced to 0 by hardware Bit 5 PE Peripheral enable This bit is set and cleared by software 0 Peripheral disabled 1 Master capability Note When 0 all the bits of the CR register and the SR register except the Stop bit are reset All outputs are released while PE 0 Note When
144. t by software the measurement starts after the next vertical sync pulse The TMU searches the minimum values of H1 and H2 until the rising edge of the next following vertical sync pulse The START bit is then cleared by hardware Figure 48 Horizontal Measurement The values of the H1 and H2 registers are available only at the end of a measurement in other words when the START bit is at 0 4 5 3 2 Vertical Measurement When the H V bit 0 and when the START bit is set by software the TMU measures the minimum V1 and V2 values during 2 consecutive vertical frames The START bit is then cleared by hardware 4 5 3 3 Special cases If an overflow of the counter occurs during any of the measurements the measured T1 or T2 val ues will be 7FFh If the AV signal is always low no active video the measured T1 or T2 values will also be 7FFh If T1 lt 0 AV already high when the falling edge of the sync signal occurs the measured T1 val ue will be fixed to 1 If T2 lt 0 AV still high when the rising edge of the sync signal occurs a specific T2 value will be re turned Note Refer to Application Note AN1183 for further de tails HSYNCO or Jb EL HFBACK H1 2 measured in oscillator clock periods Note HSYNCO HFBACK must be positive Figure 49 Vertical Measurement VSYNCO or M E A VFBACK 1 V2 measured in horizontal pulses Note VSYNCO or VFBA
145. t conversion has ended A write to the CSR register with ADON set aborts the current conversion resets the COCO bit and starts a new conversion Figure 77 ADC Conversion Timings COCO BIT SET 4 10 4 Low Power Mode Demon WAIT No effect on A D Converter Note The A D converter is disabled by resetting the ADON bit With this feature power consumption is reduced when no conversion is needed and be tween single shot conversions 4 10 5 Interrupts None 4 8 A D CONVERTER ADC 4 10 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 COCO Conversion Complete This bit is set by hardware It is cleared by software reading the result in the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bit 3 0 CH 3 0 Channel Selection These bits are set and cleared by software They select the analog input to convert Note The number of pins AND the channel selection var ies according to the device Refer to the device pinout Table 30 ADC Register Map 172774 1727754 172734 E AINO DATA REGISTER D
146. t is an active low input signal applied to the RESET pin of the MCU As shown in Figure 12 the RESET signal must remain low for 1000ns m LVD m watchdog m external pulse at the RESET pin m ilegal address m ilegal opcode A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point An internal Schmitt trigger at the RESET pin is provided to improve noise immunity 3 2 3 Illegal Address Detection An opcode fetch from an illegal address refer to Figure 3 generates an illegal address reset Program execution at those addresses is forbidden especially to protect page 0 registers against spurious accesses An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active 3 2 1 LVD and Watchdog Reset The Low Voltage Detector LVD generates a reset when Vppis below when Vppis rising or Vip when yppis falling referto Figure 11 This circuitry is active only when Vpp is above VrTnv During LVD Reset the RESET pin is held low thus permitting the MCU to reset other devices Table 5 List of sections affected by RESET and WAIT Refer to 3 6 for Wait Mode eatin FEET WAT Timer Counter sete PESA x Set Interrupt Mask Bit I Bit CC to 0 Interrupt enable x Reset WAIT latch O nn Port data registers reset Other on chip peripheral
147. ter AHR lt 7 1 gt ALR Addr Pointer lt 7 1 gt B ALR 104 144 q DDC INTERFACE Cont d m Write Operation Once the DDC1 2B Interface has acknowledged a write transfer request i e a Device Address with RW 0 it waits for a data address When the latter is received it is acknowledged and loaded into the ALR Then the master may send any number of data bytes that are all acknowledged by the DDC1 2B Interface The data bytes are written in RAM if the WP bit 0 in the DCR register otherwise the RAM location is not modified In any case all write operations are performed in RAM and therefore do not delay DDC transfers although concurrent software execution is halted for 2 cycles Figure 65 Write sequence T72774 ST727754 ST 72734 After each byte is transferred the internal address counter is automatically incremented If the counter is pointing to the top of the structure it rolls over to the bottom since the incrementation is performed only on the 7 or 8 LSB s of the pointer depending on the selected data structure size In other words ALR rolls over from FFh to 00h for Device Addresses A2h A3h A6h A7h Otherwise it rolls over from 7Fh to or from FFh to 80h depending on the MSB of the last data address received Then after that last byte has been effectively written in RAM the EDF flag is set and an interrupt is generated if EDE is set The transfer is terminated by the master gene
148. ter SYNCHGENR SYNC H Sync Generator Register SYNCVGENR SYNC V Sync Generator Register SYNCENR SYNC Processor Enable Register Reserved Area 8 bytes 12 144 4 172774 1727754 172734 Reset DDCCR DDC CI Control Register DDCSR1 DDC CI Status Register 1 Read ee DDCSR2 DDC CI Status Register 2 Read only DDC CI Reserved DDCOAR DDC CI 7 Bits Slave address Register R W Reserved DDCDR DDC CI Data Register R W Reserved Area 2 bytes I2C Data Register Reserved Reserved 2 12C Clock Control Register R W I2CSR2 2 Status Register 2 Read only 12CSR1 2 Status Register 1 Read only 2 12 Control Register R W Table 3 Interrupt Vector Map Vector Address Description Remarks FFEO FFE1h Not used FFE2 FFE3h Not used FFE4 FFE5h Not used FFE6 FFE7h USB interrupt vector Internal Interrupts FFE8 FFE9h Not used FFEA FFEBh 2 interrupt vector FFEC FFEDh Timer Overflow interrupt vector FFEE FFEFh Timer Output Compare interrupt vector FFFO FFF1h Timer Input Capture interrupt vector FFF2 FFF3h ITA falling edge interrupt vector External Interrupts FFF4 FFF5h ITB falling edge interrupt vector FFF6 FFF7h DDC1 2B interrupt vector Internal Interrupt FFF8 FFF9h DDC CI interrupt vector FFFA FFFBh USB End Suspend interrupt vector FFFC FFFDh TRAP software interrupt vector CPU Interrupt FFFE FFFFh RESET vector 4 13 144 ST72774 ST727754 ST72734 1 4 External connections The follo
149. the SYNC processor cell Bit 6 FLY SYN Flyback or Synchro Switch This bit is set and cleared by software It is used to choose the signals the Timing Measurement Unit will analyse 0 horizontal and vertical synchro outputs analysis 1 horizontal and vertical Flyback inputs analysis Bit 5 HSYNCDIVEN HSYNCDIV Enable This bit is set and cleared by software It is used to enable the output of the HSYNCO output on PCO 0 HSYNCDIV disabled 1 HSYNCDIV enabled 26 144 Bit 42 FAST Fast Mode This bit is set and cleared by software It is used to select the external clock frequency If the external clock frequency is 12 MHz this bit must be at O else if the external frequency is 24 MHz this bit must be at 1 Bit Falling Edge Detector Latch This bit is set by hardware when a falling edge occurs on pin ITB PD4 in Port D An interrupt is generated if ITBITE 1and the bit in the CC register 0 It is cleared by software 0 No falling edge detected on ITB 1 Falling edge detected on ITB Bit 2 ITALAT Falling Edge Detector Latch This bit is set by hardware when a falling edge occurs on pin ITA PD3 in Port D An interrupt is generated if ITAITE 1and the bit in the CC register 0 It is cleared by software 0 No falling edge detected on ITA 1 Falling edge detected on ITA Bit 12 ITBITE ITB Interrupt Enable This bit is set and cleared by software 0 ITB interrupt disabled 1 ITB int
150. ts Cont d PWM BRM Outputs The PWM BRM outputs are assigned to dedicated ST72774 ST727754 ST 72734 Table 27 6 Bit PWM Ripple After Filtering V RIPPLE mV The RC filter time must be higher than TCPUx64 ce mV Figure 70 Typical PWM Output Filter 1 28 78 12 8 0 78 OUTPUT OUTPUT VOLTAGE STAGE With RC filter R 1KQ fcpu 8 MHz Vpp 5V PWM Duty Cycle 50 R Rext Figure 71 PWM Simplified Voltage Output After Filtering A PWMOUT OV OV CHARGE DISCHARGE Vop V mV O A e ripple OUTPUT gt VOLTAGE Vourava PWMOUT OV DDS ie ge CHARGE DISCHARGE Vripple mV CHARGE DISCHARGE OUTPUT VOLTAGE gt V OV OUTAVG CHARGE DISCHARGE VR01956 4 117 144 ST72774 ST727754 ST72734 PWM BRM GENERATOR Cont d BRM Generation The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles This has the effect of fine tuning the PWM Duty cycle without modifying the base duty cycle thus with the external filtering providing additional fine voltage steps The incremental pulses with duration of Tcpy are added to the beginning of the original PWM pulse The PWM intervals which are added to are specified in the 4 bit BRM register and are encoded
151. ulator is an 8 bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index Registers X and Y In indexed addressing modes these 8 bit registers are used to create either effective addresses or temporary storage areas for data manipulation The Cross Assembler generates a precede instruction PRE to indicate that the following instruction refers to the Y register The Y register is not affected by the interrupt automatic procedures not pushed to and popped from the stack Program Counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and Program Counter High which is the MSB RESET VALUE XXh 7 0 RESET VALUE XXh 7 0 RESET VALUE XXh 15 8 7 PCL 0 RESET VALUE RESET VECTOR FFFEh FFFFh 7 0 fa 2 VALUE 1 1 1 X 1 X X X 15 817 0 VALUE STACK ADDRESS ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER X Undefined Value ky 15 144 ST72774 ST727754 ST72734 CPU REGISTERS Cont d CONDITION CODE REGISTER CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the interrupt mask and four flags rep
152. upt is generated if the ITE bit is set Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master The interface detects this condition and in this case EVF and STOPF bits are set An interrupt is generated if the ITE bit is set 108 144 Then the interface waits for a read of the SR2 register see Figure 67 Transfer sequencing EVA Error Cases BERR Detection of a Stop or a Start condition during a byte transfer In this case the EVF and the BERR bits are set and an interrupt is gener ated if the ITE bit is set If itis a Stop then the interface discards the data releases the lines and waits for another Start condition If itis a Start then the interface discards the data and waits for the next slave address on the bus AF Detection of a non acknowledge bit In this case the EVF and AF bits are set and an inter rupt is generated if the ITE bit is set Note In both cases SCL line is not held low however SDA line can remain low due to possible 0 bits transmitted last It is then necessary to release both lines by software How to release the SDA SCL lines Set and subsequently clear the STOP bit while BTF is set The SDA SCL lines are released after the transfer of the current byte Other Events m ADSL Detection of a Start condition after an acknowledge time slot The state machine is reset and starts a new process The ADSL bit i
153. ut are from consecutive memory addresses The internal address counter is incre mented automatically after each byte If the counter is pointing to the top of the structure it rolls over to the bottom since the incrementation is performed only on the 7 or 8 LSB s of the counter depending on the selected data structure size 105 144 ST72774 ST727754 ST72734 DDC INTERFACE Cont d Figure 66 Read sequences CURRENT ADDRESS READ Addr ADDR ADDR 1 Pointer DEV ADDR DATA OUT RANDOM ADDRESS READ Adar XXXXh ADDR ADDR 1 Pointer DEV ADDR DATA OUT RESTART SEQUENTIAL ADDRESS READ Addr ADDR ADDR 1 ADDR 1 ADDR DEV ADDR 1 DATA 2 DATA OUT n ME 106 144 DDC INTERFACE Cont d 4 8 5 2 DDC CI Factory Alignment Interface 4 8 5 2 1 Functional Description Refer to the CR SR1 and SR2 registers in Section 4 8 6 for the bit definitions The DDC CI interface works as an interface between the microcontroller and the DDC2Bi EDDC or Factory alignment protocols It receives and transmits data in Slave IC mode using interrupt or polled handshaking The interface is connected to the 12 bus by adata pin SDAD and a clock pin SCLD configured as open drain The DDC CI interface has five internal register locations Two of them are used for initialization of the interface Own Address Re
154. wing figure shows the recommended ex ternal connections for the device The Vpp pin is only used for programming OTP and EPROM devices and must be tied to ground user mode The 10 nF and 0 1 uF decoupling capacitors on the power supply lines are a suggested EMC per formance cost tradeoff Figure 4 Recommended External Connections EXTERNAL RESET CIRCUIT Or configure unused I O ports The external reset network including the manda tory 1K serial resistor is intended to protect the device against parasitic resets especially in noisy environments Unused I Os should be tied high to avoid any un necessary power consumption on floating lines An alternative solution is to program the unused ports as inputs with pull up by software as input with pull up Vpp 14 144 10K C Unused 4 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation 2 2 MAIN FEATURES 63 basic instructions Fast 8 bit by 8 bit multiply 17 main addressing modes Two 8 bit index registers 16 bit stack pointer Low power modes Maskable hardware interrupts Non maskable software interrupt 2 3 CPU REGISTERS The 6 CPU registers shown in Figure 5 are not present in the memory mapping and are accessed by specific instructions Accumulator A Figure 5 CPU Registers T72774 ST727754 ST 72734 The Accum
155. y software only by a chip reset The OLV bit has to be toggled in order to toggle the pin when itis enabled bit 1 The OCFi bit is not set and thus no interrupt request is generated 4 3 3 6 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The one pulse mode uses the Input Capture1 function and the Output Compare1 function Procedure To use one pulse mode select the following in the the CR1 register Using the OLVL1 bit select the level to be ap plied to the 1 pin after the pulse Using the OLVL2 bit select the level to be ap plied to the 1 pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit And select the following in the CR2 register Set the bit the pin is then dedi cated to the Output Compare 1 function Figure 35 One Pulse Mode Timing COUNTER ICAP1 1 4 172774 1727754 172734 Set the bit Select the timer clock CC1 CC0 see Table 15 Clock Control Bits Load the register with the value corresponding to the length of the pulse see the formula in Section 4 3 3 7 One pulse mode cycle Counter is initialized to FFFCh When event occurs on ICAP1 OCMP1 OLVL2 When S CIR OCMP1 OLVL1
156. y position and size consists of measuring the timing between the horizontal or vertical sync output signals and the active video signal input AV 4 5 2 Main Features m Horizontal or vertical timing measurement m Oscillator clock fosc 24 or 12 MHz used for horizontal measurement m Horizontal sync signal HSYNCO or HFBACK and Vertical sync signal VSYNCO or VFBACK used for all measurements m Measurements performed on positive signals only m 11 bit counter m Overflow detection 4 5 3 Functional Description The Timing Measurement Unit is centered around an 11 bit counter Depending on the H V bit of the control register the TMU measures the horizontal or vertical video characteristics Figure 47 TMU Block Diagram ST7 INTERNAL BUS TMUCSR TMUT1CR 1 TMUT2CR T2 COMPARATOR 11 bit COUNTER For horizontal analysis refer to Figure 48 Obtain the minimum number of oscillator clock cycles H1 between the falling edge of the horizontal sync signal HSYNCO or HFBACK and the first rising edge of the active video in put AV for all lines between 2 consecutive vertical sync pulses Obtain the minimum number of oscillator clock cycles H2 between the last falling edge of the active video input AV and the rising edge of the horizontal sync signal HSYNCO or HF BACK for all lines between 2 consecutive vertical sync pulses Note Horizontal measurement is inhibited during the high level o
157. y software 0 Interrupt disabled 1 ADDC1 2B interrupt is generated if EDF bit is set Bits 6 3 2 CF 2 0 Configuration bits These bits are set and cleared by software only when the peripheral is disabled HWPE 0 They define which EDID structure version is used and which Device Addresses are recognized as shown in the following table CF 2 0 Bit Values DDC v2 001 P amp v2 P amp D Yes 128b EDID Yes Bit WP Write Protect This bit is set and cleared by software 0 Enable writes to the RAM 1 Disable DMA write transfers and protect the RAM content CPU writes to the RAM are not affected Bit 0 HWPE Peripheral Enable This bit is set and cleared by software 0 Release the SDA port pin and ignore Vsync and SCL port pins The other bits of the DCR and the content of the AHR are left un changed 1 Enable the DDC Interface and respond to the DDC1 DDC2B protocol ADDRESS POINTER HIGH REGISTER AHR Read Write Reset Value see Register Map 7 0 AHR contains the 8 MSB s of the 16 bit address pointer It therefore defines the location of the 256 byte block containing the data structure within the CPU address space Note AHRO is ignored when CF 1 0 10 P amp D v2 mode to allow non overlapping 128 byte and 256 byte data structures EDID version used DDC1 Mode support Transition Mode support DDC2B Addresses Recognized Yes 128b EDID Yes 256b EDID 9 A2h A3h 128

ST ST72774/ST72754/ST72734 Data Sheet

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