ATMEL AT49BV8192 AT49BV8192T AT49LV8192 AT49LV8192T DATA SHEET
Contents
1. 65 C to 150 C age to the device This is a stress rating only and functional operation of the device at these or any All Input Voltages including NC Pins with Respect to 0 6V to 6 25V All Output Voltages with Respect to Ground 0 6V to Vec 0 6V Voltage on RESET with Respect to 0 6V to 13 5V AEL other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability AIMEL DCand AC Operating Range AT49BV LV8192 12 AT49BV LV8192 15 AT49BV LV8192 20 Operating Com 0 C 70 C 0 C 70 C 0 C 70 C Temperature Case Ind 40 C 85 C 40 C 85 C 40 C 85 C AT49LV8192 3 0V to 3 6V 3 0V to 3 6V 3 0V to 3 6V Vec Power Supply AT49BV8192 2 7V to 3 6V 2 7V to 3 6V 2 7V to 3 6V Operating Modes Mode CE OE WE RESET Vpp Ai Read Vi Vi Vin Vig X Ai Dour Program Erase Vit Vin Vit Vin 5V 10 Ai Din Standby Program 1 E inibi Vin X X Vin x x High Z Program Inhibit X X Vin Vin Vit Program Inhibit X Viu Vin Vit Output Disable X Vin Vie X High Z Reset X X Vit X X High Z Product Identification z 3 BRIS Vis Bs Manufactu2. oE K tOES tOEH ADDRESS 5 a tCH E 1 WE gt WPH WP L tD8 _ 1p H_ DATA CE Controlled tOES tOEH ADDRESS gt lt T X az tCH S CE N Kx Ay N WPH L tWP tDS tDH DATA IN Program Cycle Characteristics Symbol Parameter Min Typ Max Units tgp Word Programming Time 30 us tas Address Set up Time 0 ns Address Hold Time 100 ns tos Data Set up Time 100 ns tou Data Hold Time 0 ns twp Write Pulse Width 200 ns tweu Write Pulse Width High 200 ns tec Erase Cycle Time 10 seconds Program Cycle Waveforms PROGRAM CYCLE OE WE las laH AO A18 Fa Y 2AAA 5555 ADDRESS 5555 tps amic DATA AA 55 AO AL AA Sector or Chip Erase Cycle Waveforms OE 1 K z ES we NNNM WE tas tay AO A18 5555 3 2AAA 5555 5555 2AAA Note 2 ins lEc DATA AA 55 80 AA 55 Note 3 WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 Notes 1 OE must be high only when WE and CE are both low For chip erase the address should be 5555 For sector erase the address depends on what sector is to be erased See note 4 under command definitions For chip erase the data should be 10H and for sector erase the data shoul
3. AC Read Waveforms 2 9 4 ADDRESS ADDRESS VALID lt m ICE m tOE OE DF gt tOH HIGHZ OUTPUT N N OUTPUT TENE VALID p Notes 1 CE may be delayed up to tace tog after the address transition without impact on taco 2 OE may be delayed up to tcc tog after the falling edge of CE without impact on tee or by tace toe after an address change without impact on tacco 3 is specified from OE or CE whichever occurs first C 5 pF 4 This parameter is characterized and is not 100 tested Input Test Waveforms and Measurement Level Output Test Load 2 4V 3 3V AC Lo AC DRIVING lt 1 5V N MEASUREMENT 1 8K DUTPUR LEVELS dy LEVEL PIN tn tr 5 ns 1 3K 100 pF Pin Capacitance f 1 Mhz T 25500 Typ Max Units Conditions Cin 4 6 pF Vin OV Cour 8 12 pF Vout OV Note 1 This parameter is characterized and is not 100 tested AIMEL 1 AIMEL AC Word Load Characteristics Symbol Parameter Min Max Units tas toes Address OE Set up Time 10 ns tay Address Hold Time 100 ns tes Chip Select Set up Time 0 ns tcu Chip Select Hold Time 0 ns twp Write Pulse Width WE or CE 200 ns tos Data Set up Time 100 ns tou Data OE Hold Time 10 ns tweu Write Pulse Width High 200 ns AC Word Load Waveforms WE Controlled
4. A T49BV 8192 4 hy Fa Features Low Voltage Operation 2 7V Read 5V Program Erase Fast Read Access Time 120 ns Internal Erase Program Control Sector Architecture One 8K Words 16K bytes Boot Block with Programming Lockout Two 8K Words 16K bytes Parameter Blocks One 488K Words 976K bytes Main Memory Array Block Fast Sector Erase Time 10 seconds 8 Megabit Word By Word Programming 30 us Word Hardware Data Protection 51 2K X 1 6 DATA Polling For End Of Program Detection Low Power Dissipation 25 mA Active Current CMOS Flash 50 uA CMOS Standby Current Typical 10 000 Write Cycles Memory Description The AT49BV8192 and AT49LV8192 are 3 volt 8 megabit Flash Memories organized AT49BV81 92 as 512K words of 16 bits each Manufactured with Atmel s advanced nonvolatile CMOS technology the devices offer access times to 120 ns with power dissipation of AT49 BV81 92T just 67 mW at 2 7V read When deselected the CMOS standby current is less than 50 AT49LV8192 un continued Pin Configurations AT49LV8192T Pin Name Function A18 Addresses CE Chip Enable OE Output Enable E Write Enable RESET Reset SOIC SOP V Program Erase Power 1 zz Suppl 2 upply 4 Data 4 1 00 1 015 5 Inputs Outputs No Connect f 8 TSOP Top View Type 1 A16 14 2 8 47 P NC GND A13 io 4 45 45 B 1015 A11 q 5 44 H 1 07 A109 6 43
5. B 1014 A9 qd 7 42 Bn o6 8 4 B 1013 NC 10 a 39 E WE g T 38 iac RESET 9 12 37 B vcc VPP vcd 14 19 3 B jog O NC A181 16 15 34 33 E 1o02 1 010 A17 q 17 32 H 1 09 A7 9g 18 31 P 01 A6 19 30 H 1 08 HE A5 20 a 29 b A39 22 27 P GND 0978B A 1 1 97 A2 23 26 CE A1 24 25 AO AIMEL The device contains a user enabled boot block protection feature Two versions of the feature are available the AT49BV LV8192 locates the boot block at lowest order addresses bottom boot the AT49BV LV8192T locates it at highest order addresses top boot To allow for simple in system reprogrammability the AT49BV LV8192 does not require high input voltages for programming Reading data out of the device is similar to reading from an EPROM it has standard CE OE and WE inputs to avoid bus contention Reprogramming the AT49BV LV8192 is performed by first erasing a block of data and then programming on a word by word basis The device is erased by executing the erase command sequence the device internally controls the erase opera tion The memory is divided into three blocks for erase operations There are two 8K word parameter block sec tions and one sector consisting of the boot block and the Block Diagram AT49BV LV8192 main memory array block The AT49BV LV8192 is pro grammed on a word by word basis The device has the capability to protect the data in the boot block this
6. boot code to stay in the device while data in the rest of the device is updated This feature does not have to be acti vated the boot block s usage as a write protected region is optional to the user The address range of the 49BV LV8192 boot block is 00000H to 01FFFH while the address range of the 49BV LV8192T is to 7FFFFH Once the feature is enabled the data in the boot block can no longer be erased or programmed when input levels of 5 5V or less are used Data in the main memory block can still be changed through the regular programming method To activate the lockout feature a series of six program commands to specific addresses with specific data must be performed Please refer to the Command Definitions table BOOT BLOCK LOCKOUT DETECTION A software method is available to determine if programming of the boot block section is locked out When the device is in the soft ware product identification mode see Software Product Identification Entry and Exit sections a read from address location 00002H will show if programming the boot block is locked out If the data on 1 00 is low the boot block can be programmed if the data on I O0 is high the program lock out feature has been enabled and the block cannot be pro grammed The software product identification exit code should be used to return to standard operation BOOT BLOCK PROGRAMMING LOCKOUT OVER RIDE The user can override the boot block programming lockout by
7. data from the device will result in 1 06 toggling between one and zero Once the program cycle has completed will stop tog gling and valid data will be read Examining the toggle bit may begin at any time during a program cycle HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT49BV LV8192 in the following ways a Voc sense if Voc is below 1 8V typical the program function is inhib ited D Voc power on delay once Voc has reached the Voc sense level the device will automatically time out 10 ms typical before programming c Program inhibit hold ing any one of OE low CE high or WE high inhibits pro gram cycles d Noise filter pulses of less than 15 ns typi cal on the WE or CE inputs will not initiate a program cycle INPUT LEVELS While operating with a 2 7V to 3 6V power supply the address inputs and control inputs OE CE and WE may be driven from 0 to 5 5V without adversely affecting the operation of the device The I O lines can only be driven from 0 to Vec 0 6V Command Definition in Hex 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Command Bus Cycle Cycle Cycle Cycle Cycle Cycle Sequence Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr Dout Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5
8. 555 AA 2AAA 55 SAMO 30 Word Program 4 5555 AA 2AAA 55 5555 AO Addr Din Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit 3 5555 AA 2AAA 55 5555 FO Product ID Exit 1 xxxx FO Notes 1 The DATA FORMAT in each bus cycle is as follows 1 015 1 08 Don t Care 1 07 1 00 Hex 2 The 8K word boot sector has the address range 00000H to 01FFFH for the AT49BV LV8192 and 7EO00H to 7FFFFH for the AT49BV LV8192T 3 Either one of the Product ID Exit commands can be used 4 SA sector addresses For the AT49BV LV8192 SA 03XXX for PARAMETER BLOCK 1 SA 05XXX for PARAMETER BLOCK 2 SA 7FXXX for MAIN MEMORY ARRAY For the AT49BV LV8192T SA 7DXXX for PARAMETER BLOCK 1 SA 7BXXX for PARAMETER BLOCK 2 SA 79XXX for MAIN MEMORY ARRAY 5 When the boot block programming lockout feature is not enabled the boot block and the main memory block will erase together form the same sector erase command Once the boot region has been protected only the main memory array sector will erase when its sector erase command is issued Absolute Maximum Ratings Temperature Under 55 C to 125 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage
9. TION MODE 96 Software Product Identifcation Exit LOAD DATA AA TO TO ADDRESS 5555 ANY ADDRESS OR LOAD DATA FO l LOAD DATA 55 EXIT PRODUCT TO IDENTIFICATION ADDRESS 2AAA MODE LOAD DATA FO TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE 9 Notes 1 Data Format 1 015 1 08 Don t Care 1 07 1 00 Hex Address Format A14 A0 Hex 2 A1 A182 V Manufacture Code is read for AO Vj Device Code is read for AO Vi 3 The device does not remain in identification mode if pow ered down 4 The device returns to standard operation mode 5 Manufacturer Code 1FH Device Code AOH 49BV LV8192 A3H 49BV LV8192T 6 Either one of the Product ID Exit commands can be used Boot Block Lockout Enable Algorithm Notes AEL LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second 1 Data Format 1 015 1 08 Don t Care 7 1 00 Hex Address Format A14 AO Hex 2 Boot block lockout feature enabled 11 Ordering Information AIMEL tace Icc mA ns Active Standby Ordering Code Pac
10. V8192T 15TI 48T 40 to 85 C 200 25 0 05 AT49BV8192T 20RC 44R Commercial AT49BV8192T 20TC 48T 0 to 70 C AT49BV8192T 20RI 44R Industrial AT49BV8192T 20TI 48T 40 to 85 C 120 25 0 05 AT49LV8192T 12RC 44R Commercial AT49LV8192T 12TC 48T 0 to 70 C AT49LV8192T 12RI 44R Industrial AT49LV8192T 12TI 48T 40 to 85 C 150 25 0 05 AT49LV8192T 15RC 44R Commercial AT49LV8192T 15TC 48T 0 to 70 C AT49LV8192T 15RI 44R Industrial AT49LV8192T 15TI 48T 40 to 85 C 200 25 0 05 AT49LV8192T 20RC 44R Commercial AT49LV8192T 20TC 48T 0 to 70 C AT49LV8192T 20RI 44R Industrial AT49LV8192T 20TI 48T 40 to 85 C Package Type 44R 44 Lead 0 525 Wide Plastic Gull Wing Small Outline Package SOIC SOP 48T 48 Lead Thin Small Outline Package TSOP AMEL 13
11. d be 30H AIMEL AIMEL Data Polling Characteristics Symbol Parameter Min Typ Max Units tox Data Hold Time 10 ns OE Hold Time 10 ns tor OE to Output Delay ns twn Write Recovery Time 0 ns Notes 1 These parameters are characterized and not 100 tested 2 See tog spec in AC Read Characteristics Data Polling Waveforms tOEH y m OE HIGHZ a 1 07 AO A18 An An An An An Toggle Bit Characteristics Symbol Parameter Min Typ Max Units tou Data Hold Time 10 ns OE Hold Time 10 ns toe OE to Output Delay ns OE High Pulse 150 ns twr Write Recovery Time 0 ns Notes 1 These parameters are characterized and not 100 tested 2 See tog spec in AC Read Characteristics Toggle Bit Waveforms WE tOEH tOEHP aon tOE 7 HIGH i 1 06 E N 0 fIWR C Notes 1 Toggling either OE or CE or both OE and CE will operate toggle bit The togpp specification must be met by the toggling input s 2 Beginning and ending state of l O6 will vary 3 Any address location may be used but the address should not vary Software Product Identification Entry LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICA
12. e to completion When the boot block pro gramming lockout feature is not enabled the boot block and the main memory block will erase together from the same sector erase command Once the boot region has been protected only the main memory array sector will erase when its sector erase command is issued WORD PROGRAMMING Once a memory block is erased it is programmed to a logical O on a word by word basis Programming is accomplished via the internal device command register and is a 4 bus cycle operation The device will automatically generate the required internal program pulses Any commands written to the chip during the embedded programming cycle will be ignored If a hardware reset hap pens during programming the data at the location being programmed will be corrupted Please note that a data 0 cannot be programmed back to a 1 only erase operations can convert 5 to 1 s Programming is completed after the specified tgp cycle time The DATA polling feature may also be used to indicate the end of a program cycle BOOT BLOCK PROGRAMMING LOCKOUT The device has one designated block that has a programming lockout feature This feature prevents programming of data in the designated block once the feature has been enabled The size of the block is 8K words This block referred to as the boot block can contain secure code that is used to bring up the system Enabling the lockout feature will allow the
13. feature is enabled by a command sequence Once the boot block programming lockout feature is enabled the data in the boot block cannot be changed when input levels of 3 6 volts or less are used The typical number of program and erase cycles is in excess of 10 000 cycles The optional 8K word boot block section includes a repro gramming lock out feature to provide data integrity The boot sector is designed to contain user secure code and when the feature is enabled the boot sector is protected from being reprogrammed During a chip erase sector erase or word programming the Vpp pin must be at 5V 10 AT49BV LV8192T DATA INPUTS OUTPUTS 1 00 1 015 CONTROL LOGIC l l INPUT OUTPUT BUFFERS i i PROGRAM DATA d LATCHES p INPUT OUTPUT BUFFERS PROGRAM DATA LATCHES Y GATING Y GATING Y DECODER um 7FFFF ADDRESS MAIN MEMORY BOOT BLOCK 488K WORDS 7E000 X DECODER 75000 PARAMETER PARAMETER BLOCK 2 BLOCK 1 l 8K WORDS 8K WORDS 7c000 PARAMETER PARAMETER 7BFFF BLOCK 1 BLOCK 2 8K WORDS 8K WORDS 7A000 1 MAIN MEMORY 8K WORDS 488K WORDS Device Operation READ The AT49BV LV8192 is accessed like an EPROM When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs The outputs are put in the high impedance state whenever CE o
14. kage Operation Range 120 25 0 05 AT49BV8192 12RC 44R Commercial AT49BV8192 12TC 48T 0 to 70 C AT49BV8192 12RI 44R Industrial AT49BV8192 12TI 48T 40 to 85 C 150 25 0 05 AT49BV8192 15RC 44R Commercial AT49BV8192 15TC 48T 0 to 70 C AT49BV8192 15RI 44R Industrial AT49BV8192 15TI 48T 40 to 85 C 200 25 0 05 AT49BV8192 20RC 44R Commercial AT49BV8192 20TC 48T 0 to 70 C AT49BV8192 20RI 44R Industrial AT49BV8192 20TI 48T 40 to 85 C 120 25 0 05 AT49LV8192 12RC 44R Commercial AT49LV8192 12TC 48T 0 to 70 C AT49LV8192 12RI 44R Industrial AT49LV8192 12TI 48T 40 to 85 C 150 25 0 05 AT49LV8192 15RC 44R Commercial AT49LV8192 15TC 48T 0 to 70 C AT49LV8192 15RI 44R Industrial AT49LV8192 15TI 48T 40 to 85 C 200 25 0 05 AT49LV8192 20RC 44R Commercial AT49LV8192 20TC 48T 0 to 70 C AT49LV8192 20RI 44R Industrial AT49LV8192 20TI 48T 40 to 85 C Package Type 44R 44 Lead 0 525 Wide Plastic Gull Wing Small Outline Package SOIC SOP 48T 48 Lead Thin Small Outline Package TSOP Ordering Information tace Icc mA ns Active Standby Ordering Code Package Operation Range 120 25 0 05 AT49BV8192T 12RC 44R Commercial AT49BV8192T 12TC 48T 0 to 70 C AT49BV8192T 12RI 44R Industrial AT49BV8192T 12TI 48T 40 to 85 C 150 25 0 05 AT49BV8192T 15RC 44R Commercial AT49BV8192T 15TC 48T 0 to 70 C AT49BV8192T 15RI 44R Industrial AT49B
15. r OE is high This dual line control gives designers flexibility in preventing bus conten tion COMMAND SEQUENCES When the device is first pow ered on it will be reset to the read or standby mode depending upon the state of the control line inputs In order to perform other device functions a series of command sequences are entered into the device The command sequences are shown in the Command Definitions table VO8 1 015 are don t care inputs for the command codes The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low respec tively and OE high The address is latched on the falling edge of CE or WE whichever occurs last The data is latched by the first rising edge of CE or WE Standard microprocessor write timings are used The address loca tions used in the command sequences are not affected by entering the command sequences RESET A RESET input pin is provided to ease some sys tem applications When RESET is at a logic high level the device is in its standard operating mode A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state When a high level is reasserted on the RESET pin the device returns to the Read or Standby mode depending upon the state of the control inputs By applying a 12V 0 5V input signal to the RESET pin the boot block array can be repro grammed even if the boot block prog
16. ram lockout feature has been enabled see Boot Block Programming Lockout Override section ERASURE Before a word can be reprogrammed it must be erased The erased state of memory bits is a logical 1 The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands CHIP ERASE The entire device can be erased at one time by using the 6 byte chip erase software code After the chip erase has been initiated the device will internally time the erase operation so that no external clocks are required The maximum time to erease the chip is tec If the boot block lockout has been enabled the Chip Erase will not erase the data in the boot block it will erase the main memory block and the parameter blocks only After the chip erase the device will return to the read or standby mode SECTOR ERASE As an alternative to a full chip erase the device is organized into three sectors that can be indi vidually erased There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array block The Sector Erase command is a six bus cycle operation The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE The sector erase starts after the rising edge of WE of the sixth cycle The erase operation is internally controlled it will automatically tim
17. rer Code A0 Vi Hardware Vit Viu Vin Vin E A18 Vip Vu A0 Device Code AO Vy A18 Vy Manufacturer Code Software Viu AO Vy A18 Vy Device Code Notes 1 X can be V or Vi 2 Refer to AC Programming Waveforms 3 V4 2 12 0V 0 5V 4 Manufacturer Code 1FH Device Code AOH 49BV LV8192 A3H 49BV LV8192T 5 See details under Software Product Identification Entry Exit DC Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin OV to Voc 10 uA lio Output Leakage Current Vio OV to Voc 10 uA Isp Voc Standby Current CMOS CE Voc 0 3V to Voc 50 uA lega Voc Standby Current TTL CE 2 0V to Voc 1 mA leg Voc Active Current f 5 MHz loy O mA 25 mA Vit Input Low Voltage 0 6 V Viu Input High Voltage 2 0 V VoL Output Low Voltage lo 2 1 mA 0 45 V Vou Output High Voltage lou 400 uA 2 4 V Note 1 Inthe erase mode lcc is 50 mA AC Read Characteristics AT49BV LV8192 12 AT49BV LV8192 15 AT49BV LV8192 20 Symbol Parameter Min Max Min Max Min Max Units tacc Address to Output Delay 120 150 200 ns toe CE to Output Delay 120 150 200 ns toc OE to Output Delay 0 50 0 100 0 100 ns toe CE or OE to Output Float 0 30 0 50 0 50 ns ba Output Hold from OE CE 0 0 0 or Address whichever occurred first
18. taking the RESET pin to 12 volts during the entire chip erase sector erase or word programming oper ation When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel It may be accessed by hardware or software operation The hardware operation mode can be used by an external pro grammer to identify the correct programming algorithm for the Atmel product For details see Operating Modes for hardware operation or Software Product Identification The manufacturer and device code is the same for both modes DATA POLLING The AT49BV LV8192 features DATA polling to indicate the end of a program cycle During a pro gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I O7 Once the program cycle has been completed true data is valid on all outputs and the next cycle may begin During a chip or sector erase operation an attempt to read the device will give a 0 on I O7 Once the program or erase cycle has completed true data will be read from the device DATA polling may begin at any time during the program cycle AMEL AIMEL TOGGLE BIT In addition to DATA polling the AT49BV LV8192 provides another method for determining the end of a program or erase cycle During a program or erase operation successive attempts to read
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ATMEL AT49BV8192 AT49BV8192T AT49LV8192 AT49LV8192T DATA SHEET