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MICROCHIP PIC18CXX8 handbook

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1. Name Address Name Address Name Address Name TRISKE F5Fh F3Fh RXM1EIDO LATK F5Eh CANSTATROO F3Eh CANSTATRO2 F1Eh RXM1EID8 PORTK FSDh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F5Ch RXB1D6 F3Ch 1 6 F1Ch RXM1SIDH FSBh RXB1D5 F3Bh TXB1D5 F1Bh RXMOEIDO F5Ah RXB1D4 F3Ah 104 F1Ah RXMOEID8 F59h RXB1D3 F39h TXB1D3 F19h RXMOSIDL F58h RXB1D2 F38h TXB1D2 F18h RXMOSIDH FS7h RXB1D1 F37h TXB1D1 F17h RXF5EIDO TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EID8 RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDO BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EID8 BRGCON2 51 RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH CANCON F4Fh F2Fh FOFh RXF3EIDO CANSTAT F4Eh 1 4 F2Eh CANSTATRO3 FOEh RXF3EID8 7 F4Dh TXBOD7 F2Dh 207 FODh RXF3SIDL RXBODe 9 F4Ch TXBOD6 F2Ch FOCh RXF3SIDH RXBOD5 9 F4Bh 5 F2Bh 205 FOBh RXF2EIDO RXBOD4 F4Ah 4 F2Ah
2. PORTA I RAO ANO 5 RA1 AN1 21 Table Pointer lt 21 gt Data Latch d RA2 AN2 VREF 8 118 Data 4 21 inc dec logic 15 RA4 TOCKI RAB AN4 SS LVDIN Address Latch RA6 20 PCLATU PCLATH 12 PORTB lt lt Address lt 12 gt PCU PCH PCL d RBO INTO Program Counter 4 N 12 N A 4 gt RB1 INT1 Address Latch BSR FsRo Bank0 X RB2 INT2 H RB3 INT3 Program Memory 31 Level Stack FSR1 32 Kbytes FSR2 12 RB7 RB4 Data Latch 1 inc dec PORTC Peod RCO T10SO T13CKI TABLELATCH 7 RC1 T10SI gt x RC2 CCP1 16 8 RC3 SCK SCL ROMLATCH p lt RC4 SDI SDA lt RC5 SDO 4 X RC6 TX CK IR gt RC7 RX DT PORTD 8 Sx RD7 PSP7 RD0PSP0 PRODH PRODL a 8x 8 Multiply iub 8 E Control 3 D y RESICE i WREG RE3 rI ower OSC2 CLKO Tino 8 RES imer RE5 OSC1 CLKI sis UE iming NT scillator 8 E j DIX Generation lt Start up Timer 1 4 RE7 CCP2 Power on ALUS8 gt PORTF c LE atchdo Timer EX RFe ANtIRFO ANS Precision B 8 rown out Reference Reset PORTG gt X RGO CANTX1 RG1 CANTX2 L r RG2 CANRX MCLR VDD Vss RG3 RG4 BOR bi LVD 0 Timer2 Timer3 Ls A
3. ai balosbato jesbs joaoi osbs jo o lezlasha Q1 polosb4 oi l2 bs ado ashr pa RC7 RX DT X gt 5 Bit7 gt Bit 0 gt gt x 5 gt Bit 7 pin a Wordi L gt q Word 2 0 i RC6 TX CK i y T i ERR pin 1 TXREG reg e 6 Write Word1 Write Word 2 TXIF bit 5 tu 6 Interrupt flag 6 x TRMTbit i TXENbit 6 i 6 Note Sync Master mode SPBRG 0 continuous transmission of two 8 bit words FIGURE 16 7 SYNCHRONOUS TRANSMISSION THROUGH TXEN RC7 RX DT pin X bito X biti X bit 6 X bit6 x bit7 RC6 TX CK pin JA f Write to i reg TXIF bit TRMT bit Sn nA TXEN bit DS30475A page 178 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 16 3 2 USART SYNCHRONOUS MASTER Steps to follow when setting up a Synchronous Master RECEPTION Reception Once Synchronous Master mode is selected reception 1 Initialize the SPBRG register for the appropriate is enabled by setting either enable bit SREN RCSTA baud rate Section 16 1 register o
4. TABLE 23 1 OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a 0 RAM location in Access RAM BSR register is ignored a 1 RAM bankis specified by BSR register ACCESS ACCESS 0 RAM access bit symbol BANKED 1 RAM access bit symbol bbb Bit address within an 8 bit file register 0 to 7 BSR Bank Select Register Used to select the current RAM bank Destination select bit d 0 store result in WREG d 1 store result in file register f dest Destination either the WREG register or the specified register file location 8 bit Register file address 0 00 to fa 12 bit Register file address 0x000 to OKFFF This is the source address fa 12 bit Register file address 0x000 to OKFFF This is the destination address k Literal field constant data or label may be either an 8 bit 12 bit or a 20 bit value label Label name mm The mode of the TBLPTR register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions No Change to register such as TBLPTR with Table reads writes Post Increment register such TBLPTR with Table reads and writes Post Decrement register such TBLPTR with Table reads and writes Pre Increment register such as TBLPTR with Table reads and writes n The relative address 2 s complement number for relative b
5. R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 IPR1 PSPIP ADIP RCIP TXIP SSPIP 1 TMR2IP TMR1IP bit 7 bit 0 U 0 R W 1 U 0 U 0 R W 1 R W 1 R W 1 R W 1 IPR2 CMIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 IPR3 IVRP WAKIP ERRIP 2 TXB1IP TXBOIP RXB1IP RXBOIP bit 7 bit 0 IPR1 bit 7 PSPIP Parallel Slave Port Read Write Interrupt Priority bit 1 High priority 0 Low priority bit 6 ADIP A D Converter Interrupt Priority bit 1 High priority 0 Low priority bit 5 RCIP USART Receive Interrupt Priority bit 1 High priority 0 Low priority bit 4 TXIP USART Transmit Interrupt Priority bit 1 High priority 0 Low priority bit3 SSPIP Master Synchronous Serial Port Interrupt Priority bit 1 High priority 0 Low priority bit 2 CCP1IP CCP1 Interrupt Priority bit 1 High priority 0 Low priority bit 1 TMR2IP TMR2 to PR2 Match Interrupt Priority bit 1 High priority 0 Low priority bit O TMR1 Overflow Interrupt Priority bit 1 High priority 0 Low priority DS30475A page 86 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 REGISTER 7 7 IPR2 bit 7 bit 6 bit 5 4 bit 3 bit 2 bit 1 bit O IPR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O IPR REGISTERS CONT D Unimplemen
6. 7 Error BusOff Counter Transmit Shift Receive Shift Protocol CRC Generator CRC Check minie State lt Machine Y Transmit Bit Logic Timing Bit Timing Logic Generator TX RX DS30475A page 184 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 17 2 Control Registers for the CAN Module Note Not all CAN registers are available in the access bank There are many registers associated with the CAN module Descriptions of these registers are grouped into sections These sections are REGISTER 17 1 Control and Status Registers Transmit Buffer Registers Receive Buffer Registers Baud Rate Control Registers Interrupt Status and Control Registers 17 21 CAN CONTROL AND STATUS REGISTERS This section shows the CAN Control and Status registers CANCON CAN CONTROL REGISTER R W 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 REQOP2 REQOP1 REQOPO ABAT WIN2 WIN1 WINO bit 7 bit O bit 7 5 REQOP2 REQOPO Request CAN Operation Mode bits 1xx Request Configuration mode 011 Request Listen Only mode 010 Request Loopback mode 001 Request Disable mode 000 Request Normal mode bit 4 ABAT Abort All Pending Transmissions bit 1 Abort all pending transmissions in all transmit buffers 0 Transmissions proceeding as normal bit 3 1 WIN2 WINO Window A
7. Address Name Address Name Address Name Address Name FFFh TOSU 20 FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2 2 FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2 2 FBDh CCP1CON F9Dh PIE FFCh STKPTR FDCh PREINC2 2 FBCh CCPR2H F9Ch FFBh PCLATU FDBh PLUSW2 2 FBBh CCPR2L F9Bh FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ S FF9h PCL FD9h FSR2L FB9h F99h TRISH FF8h TBLPTRU FD8h STATUS FB8h F98h TRISG FF7h TBLPTRH FD7h TMROH FB7h F97h TRISF FF6h TBLPTRL FD6h TMROL FB6h F96h TRISE FF5h TABLAT FD5h TOCON FB5h CVRCON F95h TRISD FF4h PRODH FD4h FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA INTCON2 FDih WDTCON FB1h T3CON F91h FFOh INTCON3 FDOh RCON FBOh PSPCON F90h LATH FEFh INDFO FCFh TMR1H FAFh SPBRG F8Fh LATG FEEh POSTINCO TMR1L LATF FEDh POSTDECO FCDh T1CON FADh TXREG F8Dh LATE FECh PREINCO FCCh TMR2 TXSTA F8Ch FEBh PLUSWO FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSROH FCAh T2CON FAAh F8Ah LATB FE9h FSROL FC9h SSPBUF FA9h F89h LATA FE8h WREG FC8h SSPADD FA8h F88h PORTJ FE7h INDF1 2 FC7h SSPSTAT FA7h F87h PORTH FE6h POSTINC1 2 F
8. 222 Programming Device Instructions Propagation Segment 219 PSPCON Register PSPMODE n 95 109 PWM CCP Module 2 132 Block Diagram 132 CCPR1H CCPR1L Registers 132 2 132 Example Frequencies Resolutions 133 Output Diagram 132 Perl d E 132 Setup for PWM Operation TMR2 to PR2 Match Q Q Clbk lonia fee t cae e oe ra 132 R RAM See Data Memory RCSTA Register nic eee Receive Buffers uu Receive Buffers Diagram 214 Receive Interrupt ses 225 Receive Message Buffering 213 Receiver Error Passive 226 Receiver Overrun 226 Receiver Warning 226 Register sens a 48 Registers SSPSTAT tanins dtd e ein ane eus 136 T3CON DIAGRAM 123 SOCON Me D EET 123 RESET ends 29 251 Timing Diagram ren tne 325 Resynchronization 2 220 RETEIE 254 444 291 292 RETEW 4s 292 RETURN Za aaa dedi PTUS 293 Revision History sites ns anni 349 act Tenue MUR t 293 Sample Point ssh 219 SCI See USART SU Ier 141 Serial Clock SCK Lec dee f eed be ces 141 Serial Communicati
9. 130 Configuration Bits Configuration Mode sse 210 Configuring the Voltage Reference 243 CPFSEQ CPFSGT CPFSLT CRC Error CVRCON Register 2000 Microchip Technology Inc Advanced Information DS30475A page 353 PIC18CXX8 D Data ii Et bn ds le 48 General Purpose Registers 48 Special Function Registers 48 DAW cocotte ccn mere it veri nisin 280 DC Characteristics 313 314 315 316 317 eaae eu 280 Device Differences 2 349 Device Functionality 2 8 184 Direct Addressing 62 Electrical Characteristics 311 EITala Lane Error Detection Error Interrupt Error Modes se Error Modes and Error Counters Error States Filter Mask Truth Table 2 216 Firmware Instructions esee 261 gels e 223 G General Call Address Sequence 150 General Call Address Support 150 GOTO 282 H Hard Synchronization 2 220 eode a Gh cS std CS Mers nn 89 SSP
10. 2 Wake up from iron Brown out SLEEP or g PWRTEN 0 PWRTEN 1 Oscillator Switch HS with PLL enabled 72 ms 1024Tosc 2 ms 1024Tosc 2 ms 72 ms 1024Tosc 2 ms 1024Tosc 2 ms HS XT LP 72 ms 1024Tosc 1024Tosc 72 ms 1024Tosc 1024Tosc EC 72 ms 72 ms External RC 72 ms 72 ms Note 1 2 ms Nominal time required for the 4X PLL to lock 2 72ms is the nominal power up timer delay REGISTER 3 1 RCON REGISTER BITS AND POSITIONS R W 0 R W 0 U 0 R W 1 R W 1 R W 1 R W 1 R W 1 IPEN LWRT RI TO PD POR BOR bit 7 bit 0 TABLE 3 2 STATUS BITS THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition es RI TO POR BOR STKFUL STKUNF Power on Reset 0000h 00 1 1100 MCLR Reset during normal 0000h 00 uuuu u u u u u operation Software Reset during normal 0000h Ou 0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h Ou u uull u u u 1 1 u 1 operation Stack Underflow Reset during 0000h Ou u uull u u u 1 1 1 u normal operation MCLR Reset during SLEEP 0000h 00 u 10uu u 1 O u u u u WDT Reset 0000h Ou u Oluu u 0 T u u u u WDT Wake up PC 2 uu u OOuu u 0 0 u u u u Brown out Reset 0000h Ou 1 11u0 1 1 1 u 0 u u Interrupt wake up from SLEEP 20 uu u oouu u 0 0 u u u u
11. Legend u unchanged x unknown unimplemented bit read as 0 Note 1 When the wake up is due to an interrupt and the GIEH or GIEL bits are set the PC is loaded with the interrupt vector 0x000008h 0x000018h 2000 Microchip Technology Inc Advanced Information DS30475A page 31 PIC18CXX8 FIGURE 3 3 TIME OUT SEQUENCE POWER UP MCLR TIED TO VDD gt MCLR INTERNAL POR PWRT TIME OUT Tost OST TIME OUT INTERNAL RESET FIGURE 3 4 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO CASE 1 VDD 6 MCLR INTERNAL POR lt TPWRT gt PWRT TIME OUT Tosr OST TIME OUT INTERNAL RESET FIGURE 3 5 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED Vpp CASE 2 VDD _____ gt lt f MCLR INTERNAL POR TPWRT PWRT TIME OUT OST TIME OUT INTERNAL RESET DS30475A page 32 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 FIGURE 3 6 SLOW RISE TIME MCLR TIED TO VDD 5V VoD AV MCLR INTERNAL POR a 9 TDEADTIME Tower PWRT TIME OUT I TOST OST TIME OUT INTERNAL RESET FIGURE 3 7 TIME OUT SEQUENCE ON POR W ENABLED MCLR TIED TO VDD VDD
12. 8 9 LATJ and TRISJ Registers EXAMPLE 8 9 INITIALIZING PORTJ CLRF PORTJ Initialize PORTJ by Note This port is available on PIC18C858 clearing output 2 h data latches PORT is 8 bit wide bi directional port available CLRF Alternate method only on the PIC18C858 devices The corresponding to clear output Data Direction register is TRISJ Setting a TRISJ bit data latches 21 will make the corresponding PORTJ an input MOVLW OxCF Value used to ie put the corresponding output driver in initialize data hi impedance mode Clearing a TRISJ bit 0 will direction make the corresponding PORTJ pin an output i e put MOYWES zDRISJ FRS RIO aS Inputs the contents of the output latch on the selected pin noc RJ7 RJ6 as inputs Read modify write operations on the LATJ register read and write the latched output value for PORTJ PORTJ on the PIC18C858 is an 8 bit port with Schmitt Trigger input buffers Each pin is individually config urable as an input or output FIGURE 8 18 PORTJ BLOCK DIAGRAM RD Data Bus D WR LATJ 5 ve 5 _ D 5 WR PORTJ Data Latch 4 Pin D Q Y WR TRISJ oka TS TRIS Latch RD TRISJ Schmitt V Trigger Q D EN RD PORTJ Note pins have diode protection to VDD and Vss DS30475A page 106 Advanced Information 2000 Microchip Technology Inc
13. BAUD Fosc 40MHz SpprG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value Kbps kgAup ERROR decimal KBauD ERROR decimal ERROR decimal KBaup ERROR decimal 0 3 5 5 E NA z NA 2 1 2 NA 24 2 40 0 07 214 2 40 0 15 162 2 40 40 16 129 9 6 9 62 016 64 9 55 0 54 53 9 53 0 76 40 9 47 136 32 192 18 94 1 36 32 19 10 0 54 26 1953 41 73 19 19 53 4173 15 768 7813 173 7 73 66 409 6 7848 4173 4 7848 173 3 96 89 29 6 99 6 10313 4742 4 9766 173 3 10447 851 2 300 312 50 44 17 1 25781 1406 1 NA 5 312 50 417 0 500 625 2500 0 NA NA HIGH 625 0 515 63 0 39063 0 31250 0 LOW 244 255 2 01 255 1 53 255 1 22 255 Baup FOSC 8 MHz sPBRG 10 MHz 7 15909 MHz SERO 5 0688 MHz RATE value value value value Kbps ERROR decimal kgaup ERROR decimal ERROR decimal KBaup ERROR decimal 0 3 NA NA NA NA 1 2 120 40 16 207 1 20 40 16 129 1 20 40 23 92 1 20 0 65 24 240 016 103 2 40 40 16 64 2 38 0 83 46 2 40 0 32 9 6 9 62 016 25 977 41 73 15 9 32 2 90 11 9 90 343 7 19 2 1923 40 16 12 19 53 173 7 18 64 2 90 5 19 80 313 3 76 8 8333 4851 2 78 13 173 1 111 86 44565 0 79 0 313 0 96 83 33 1319 2 78 13 1862 1 NA NA 300 250 4667 0 156 25 47 92 0 5 5 500
14. Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other BOR RESETS INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 0004 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00 0000 00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Slave transmission TABLE 16 11 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other BOR RESETS INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN FERR
15. Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR RESETS RXBOD7 0 77 0076 0075 RXB0OD74 RXBOD73 RXBOD72 RXB0D71 RXBOD70 xxxx uuuu uuuu RXBOD6 RXBOD67 RXBOD66 RXBOD65 RXBOD64 RXBOD63 RXBOD62 RXBOD61 RXBOD60 xxx uuuu uuuu RXBOD5 0057 RXBOD56 RXBOD55 RXBOD54 RXBOD53 RXBOD52 RXBOD51 RXBOD50 xxxx uuuu uuuu RXBOD4 RXB0D47 RXBOD46 0045 RXBOD44 RXBOD43 RXBOD42 RXB0D41 RXBOD40 xxx uuuu uuuu RXBOD3 RXB0D37 RXBOD36 RXBOD35 RXBOD34 RXBOD33 RXBOD32 RXB0D31 RXBOD30 xx uuuu uuuu RXBOD2 0027 RXBOD26 RXBOD25 RXBOD24 RXBOD23 RXBOD22 0 21 RXBOD20 xxx uuuu uuuu RXBOD1 0017 0016 0015 RXBOD14 RXBOD13 RXBOD12 RXBOD11 RXBOD10 uuuu uuuu RXBODO 0 07 0006 0005 RXBOD04 RXBODO3 RXBODO RXBODOO xxxx xxxx uuuu uuuu RXBODLC RXRTR RESB1 RESBO DLC3 DLC2 DLC1 DLCO Oxxx xxxx Ouuu uuuu RXBOEIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO Lx gusce lourd RXBOEIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 XXXX XXXX uuuu uuuu RXBOSIDL SID2 SID1 SIDO SRR EXID EID17 EID16 uuuu u uu RXBOSIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 uuuu uuuu RXBOCON RXFUL RXM1 RXMO RXRTRRO RXBODBEN JTOFF FILHITO 000 0000 000 0000 CANSTAT OPMODE2 OPMODE1
16. 71 72 SDI MSbIn Bit6 7 LSb In 4 Note Refer to Figure 25 4 for load conditions TABLE 25 14 EXAMPLE SPI SLAVE MODE REQUIREMENTS CKE 1 T Symbol Characteristic Min Max Units Conditions 70 TssL2scH SSJ to or SCKT input TCY TssL2scL 71 TscH SCK input high time Continuous 1 25TCY 30 E ns 71 Slave mode Single Byte 4 Note 1 72 SCK input low time Continuous rase 72 Slave mode Single Byte gt ns Note 1 73A 2 Last clock edge of Byte1 to the 1st clock edge af Byte 3 40 ns 2 74 TscH2diL Hold time of SDI data input to SCK px D 100 ns TscL2diL 77 TssH2doZ SST to SDO ou 75 TdoR SDO data output rise time 25 ns CXX8 45 ns 76 TdoF SDO data output imm 25 ns 78 TscR SCK outp i PIC18CXX8 25 ns Master PIC18LCXX8 45 ns 79 TscF me 25 ns 80 TscH2do 5 ta i PIC18CXX8 50 ns TscL2d d PIC18LCXX8 100 ns 82 TssL2doV DO data output valid after SSL PIC18CXX8 50 ns edge PIC18LCXX8 100 ns 83 TscH2ssH 55 7 after SCK edge 1 5TCY 40 ns TscL2ssH Note 1 Requires the use of parameter 73A 2 Only if parameter s 71A and 72A are used DS30475A page 332 Advanced Information 2000 Microchip Technology Inc PIC18CXX8
17. Interrupt to CPU Vector to Location 0018h Q UU 11 D PEIE GIEL DS30475A page 76 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 7 1 Control Registers 7 1 1 INTCON REGISTERS This section contains the control and status registers REGISTER 7 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O The Registers are readable and writable registers which contain various enable priority and flag bits INTCON REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W x GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF bit 7 bit 0 GIE GIEH Global Interrupt Enable bit When IPEN 0 1 Enables all un masked interrupts 0 Disables all interrupts When IPEN z 1 1 Enables all high priority interrupts 0 Disables all high priority interrupts PEIE GIEL Peripheral Interrupt Enable bit When IPEN 0 1 Enables all un masked peripheral interrupts 0 Disables all peripheral interrupts When IPEN 1 1 Enables all low priority peripheral interrupts 0 Disables all priority peripheral interrupts TMROIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO overflow interrupt 0 Disables the TMRO overflow interrupt INTOIE INTO External Interrupt Enable
18. 1 TppS2ppS 3 TCC ST 2 specifications only 2 TppS 4 Ts 2 specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 Osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss 55 dt Data in 10 TOCKI io port ti MCLR wr WR Uppercase letters and their meanings F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance only AA output access High High BUF Bus free Low Low 8 2 specifications only HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition DS30475A page 320 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 25 3 2 TIMING CONDITIONS The temperature and voltages specified in Table 25 3 apply to all timing specifications unless otherwise noted Figure 25 4 specifies the load conditions for the timing specifications TABLE 25 3 TEMPERATURE AND VOLTAGE SPECIFICATIONS AC AC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt lt 85 C for industrial 40 C lt TA lt 125 C for extended Operating voltage VDD range as described in DC spec Section 25 1 LC parts operate for industrial temperatures only FIGURE 25 4 LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 RL Pin CL P 4
19. RCO Yes Timer1 OSC for Timer1 Timer3 RC1 Yes Timer1 OSC for Timer1 Timer3 RC2 No RC3 Yes SPI 2C Master Clock RC4 Yes 2 Data Out RC5 Yes SPI Data Out RC6 Yes USART Async Xmit Sync Clock RC7 Yes USART Sync Data Out Note O pins have diode protection to VDD and Vss 2000 Microchip Technology Inc Advanced Information DS30475A page 93 PIC18CXX8 TABLE 8 5 PORTC FUNCTIONS Name Bit Buffer Type Function RCO T1OSO T13CKI bito ST Input output port pin or oscillator output or Timer1 Timer3 clock input RC1 T1OSI biti ST Input output port or oscillator input RC2 CCP1 bit2 ST Input output port pin or Capture1 input Compare1 output PWM1 output RC3 SCK SCL bit3 ST Input output port pin or Synchronous Serial clock for SPI I2C RC4 SDI SDA bit4 ST Input output port pin or SPI Data in SPI mode or Data I O IFC mode RC5 SDO bit5 ST Input output port pin or Synchronous Serial Port data output RC6 TX CK bit6 ST Input output port pin Addressable USART Asynchronous Transmit or Addressable USART Synchronous Clock RC7 RX DT bit7 ST Input output port pin Addressable USART Asynchronous Receive or Addressable USART Synchronous Data Legend ST Schmitt Trigger input TABLE 8 6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
20. DS30475A page 296 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 SUBFWB Cont 1 SUBFWB REG Before Instruction REG 3 WREG 2 C 1 After Instruction REG OxFF WREG 2 C 0 2 0 1 is negative Example 2 SUBFWB REG Before Instruction REG 2 WREG 5 1 After Instruction REG 2 WREG 3 C 1 2 0 resultis positive Example 3 SUBFWB REG Before Instruction REG 1 WREG 2 C After Instruction REG 0 WREG 2 C 1 Z 1 resultis zero N 0 SUBLW Subtract WREG from literal Syntax abel SUBLW k Operands 0 lt k lt 255 Operation k WREG gt WREG Status Affected N OV C DC Z Encoding 0000 1000 kkkk kkkk Description WREG is subtracted from the eight bit literal k The result is placed in WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example 1 SUBLW 0x02 Before Instruction WREG 1 C 2 After Instruction WREG 1 C 1 result is positive 2 0 0 2 SUBLW 0x02 Before Instruction WREG 2 C Em After Instruction WREG 0 C 1 result is zero Z 1 0 Example 3 SUBLW 0x02 Before Instruction WREG 3 C 2 After Instruction WREG OxFF 2 5 complement C 0 resultis negative 2 0 1 2000 Microchip Technology Inc Advanced In
21. uuuu uuuu TXBODO TXBODO7 TXBODO6 0005 TXBOD04 TXBODO2 1 TXBODOO xxx xxxx uuuu uuuu TXBODLC DLC3 DLC2 DLC1 DLCO xxxx 0u00 uuuu TXBOEIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO TXBOEIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 uuu TXBOSIDL SID2 SID1 SIDO EXIDEN EID17 EDIG Noos uuu uou TXBOSIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 enda p TXBOCON TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 0000 0000 0000 0000 CANSTAT OPMODE2 OPMODE1 OPMODEO ICODE2 ICODE1 ICODEO XXX uuu uuu TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx uuuu uuuu TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 uuuu uuuu TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 uuuu uuuu TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 1043 1042 TXB1D41 TXB1D40 xxx uuuu uuuu TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxx uuuu TXB1D2 TXB1D27 TXB1D26 1 025 TXB1D24 1023 TXB1D22 TXB1D21 TXB1D20 uuuu uuuu TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxx uuuu uuuu TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 1003 TXB1D02 TXB1D01 TXB1D00 xxx
22. 2000 Microchip Technology Inc Advanced Information DS30475A page 43 PIC18CXX8 4 2 3 PUSH AND POP INSTRUCTIONS Since the Top of Stack TOS is readable and writable the ability to push values onto the stack and pull values off the stack without disturbing normal program execu tion is a desirable option To push the current PC value onto the stack a PUSH instruction can be executed This will increment the stack pointer and load the cur rent PC value onto the stack TOSU TOSH and TOSL can then be modified to place a return address on the stack The PoP instruction discards the current TOS by decre menting the stack pointer The previous value pushed onto the stack then becomes the TOS value 4 2 4 STACK FULL UNDERFLOW RESETS These RESETs are enabled by programming the STVREN configuration bit When the STVREN bit is disabled a full or underflow condition will set the appro priate STKFUL or STKUNF bit but not cause a device RESET When the STVREN bit is enabled a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device RESET The STKFUL or STKUNF bits are only cleared by the user software or a POR 4 3 Fast Register Stack A fast return option is available for interrupts and calls A fast register stack is provided for the STATUS WREG and BSR registers and is only one layer in depth The stack is not readable or writable and is loaded with the current value of the
23. 2 RXBnDmO bit 7 bit 0 RXBnDm7 RXBnDm0 Receive Buffer n Data Field Byte m bits where 0 lt lt 1 and 0 lt lt 7 Each Receive Buffer has an array of registers For example Receive buffer 0 has 8 registers RXBODO to RXBOD7 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2000 Microchip Technology Inc Advanced Information DS30475A page 197 PIC18CXX8 REGISTER 17 20 RXERRCNT RECEIVE ERROR COUNT REGISTER R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 RECO bit 7 bit 0 bit 7 0 REC7 RECO Receive Error Counter bits This register contains the Receive Error value as defined by the CAN specifications When RXERRCNT gt 127 the module will go into an error passive state RXERRCNT does not have the ability to put the module in Bus Off state Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS30475A page 198 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 17 24 MESSAGE ACCEPTANCE FILTERS This subsection describes the Message Acceptance filters REGISTER 17 21 bit 7 0 REGISTER 17 22 bit 7 5 bit 4 bit 3 bit 2 bit 1 0 RE
24. Transmit Message flowchart 212 Transmit Message Priority 211 Transmitter Error Passive 226 Transmitter 226 TRISE Register enden dtr enit 97 TOTESZ para enn uu 303 TXSTA Register BRGH Bit ira nase nin nan 169 U Universal Synchronous Asynchronous Receiver Transmitter See USART Asynchronous Mode Master Transmission Receive Block Diagram Reception 2 Transmit Block Diagram Baud Rate Generator BRG Baud Rate Error Calculating 169 Baud Rate Formula i High Baud Rate Select BRGH Bit 169 Serial Port Enable SPEN Bit m Synchronous Master Mode Reception 0440 Timing Diagram Synchronous Receive 338 Timing Diagram Synchronous Transmission 337 Transmission entrent 178 Synchronous Slave Mode 180 DS30475A page 358 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 W Wake up from SLEEP 251 257 Timing Diagram aaa 258 Watchdog Timer WDT 22 2 2222 142 251 255 Block Diagram 256 Postscaler See Postscaler WDT Programming Considerations 255 RC Oscillator 255 Time out Per
25. NEGF Negate 1 NOP No Operation Syntax labe f a Syntax label Operands 0 lt 1 lt 255 Operands None 0 1 Operation No operation Operation pe Test Status Affected None Status Affected N OV C DC Z Encoding 5600 0000 7126050017 20000 Encoding 0110 110a ffff 1111 Description Location is negated using two s Description No operation complement The result is placed in Words 1 the data memory location If a is 0 the Access Bank will be Cycles selected overriding the BSR value Q Cycle Activity If a is 1 the Bank will be selected Q1 Q2 Q3 Q4 as per the BSR value Decode No No No Words 1 operation operation operation Cycles 1 i xample Q Cycle Activity Q1 Q2 Q3 Q4 None Decode Read Process Write register Data register Example NEGF REG Before Instruction REG N OV C DC Z After Instruction REG N OV C DC Z 0011 1010 0x3A 1100 0110 0xC6 oooo 2000 Microchip Technology Inc Advanced Information DS30475A page 289 PIC18CXX8 POP Pop Top of Return Stack Syntax label Operands None Operation TOS 2 bit bucket Status Affected None Encoding 0000 0000 0000 0110 Description The TOS value is pulled off the return stack and is discarded The TOS value then becomes the previ ou
26. Yes meets criteria Valid Message Received Yes meets criteria essage torn Identifier meets a filter criteria Go to Start The RXRDY bit determines if the receive register is empty and able to accept a new message The RXBODBEN bit determines if RXBO can roll over into RXB1 if it is full Is Is RXRDY 0 RXODBEN 1 gt 5 gt Yes No M aT RXBO Generate Overrun Error No message into Generate Overrun Error RXRDY 0 Set RXBOOVEL Set RXB1OVFL Y Set RXRDY 1 Yes Y Y Move message into RXB1 Set FILHIT 0 Is according to which filter criteria ERRIE 1 Y was met Set RXRDY 1 Y Go to Start Set FILHIT 2 0 according to which filter criteria was met Is Y Yes Is RXIE 1 Generate Interrupt RXIE 1 Yes Y No Set CANSTAT lt 3 0 gt according No to which receive buffer the message was loaded into Y Y 2000 Microchip Technology Inc Advanced Information DS30475A page 215 PIC18CXX8 17 6 Message Acceptance Filters and Masks The Message Acceptance Filters and Masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buff ers Once a valid message has been
27. Read PORTK pins Write PORTK Data Latch XXXx xxxx uuuu uuuu TXERRCNT TEC7 TEC6 5 4 2 0000 0000 0000 0000 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 RECO 0000 0000 0000 0000 COMSTAT RXBOOVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 5000 0000 0000 0000 CIOCON TX1SRC TX1EN ENDRHI CANCAP 1000 1000 BRGCON3 WAKFIL SEG2PH2 SEG2PH1 SEG2PHO 5 000 0 000 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PHO PRSEG2 PRSEG1 PRSEGO 5000 0000 0000 0000 BRGCON1 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 0000 0000 0000 0000 REQOP2 REQOP1 REQOPO ABAT WIN2 WIN1 WINO XXXX XXX uuuu uuu CANSTAT OPMODE2 OPMODE1 OPMODEO ICODE2 ICODE1 ICOEDO XXX XXX uuu uuu Legend x unknown u unchanged unimplemented value depends on condition Note 1 2 Bit 21 of the TBLPTRU allows access to the device configuration bits 3 Other non power up RESETs include external RESET through MCLR and Watchdog Timer Reset 4 These registers are reserved on PIC18C658 Bit 6 of PORTA LATA and TRISA are enabled ECIO and oscillator modes only In all other oscillator modes they are disabled and read 0 2000 Microchip Technology Inc Advanced Information DS30475A page 55 PIC18CXX8
28. Block Diagram ert rrr 122 Postscaler See Postscaler Timer2 PR2 Register u us eh 121 132 Prescaler See Prescaler Timer2 SSP Clock Shift neret 121 122 TMRe Register ses 121 2 to PR2 Match Interrupt 121 122 132 Timer3 5 Senes 123 Oscillator 123 125 Overflow Interrupt 128 125 Special Event Trigger CCP 125 TMR3H R gist r sims sites 123 Timing Diagrams Acknowledge Sequence Timing Baud Rate Generator with Clock Arbitration BRG Reset Due to SDA Collision Bus Collision START Condition Timing 163 Bus Collision During RESTART Condition 165 Bus Collision During RESTART Condition 2 25 eum as n 165 Bus Collision During START Condition SCL 0 164 Bus Collision During a STOP Condition 166 Bus Collision for Transmit and Acknowledge 162 BUS Date Meta ites a 2 Master Mode First Start bit timing 2 Master Mode Reception timing 2 Master Mode Transmission timing 157 Master Mode Transmit Clock Arbitration 161 Repeat Start Condition Slave Synchronization
29. fae Symbol Characteristic Min Max Units Conditions 40 TtOH TOCKI High Pulse Width No Prescaler 0 5Tcy 20 ns With Prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 EET With Prescaler 10 42 TOCKI Period No Prescaler TCY 10 With Prescaler Greater of ns prescale 20 ns or K 40 value 1 2 4 256 45 Synchronous ae ns High Synchronous PIC18CXX8 1 ns Time with prescaler PIC18L 5 ns Asynchronous PIC NA 30 ns NX PIC18 50 ns 46 presc O STCY 5 ns 10 ns PIC18LCXX8 25 ns PIC18CXX8 30 ns PIC18LCXX8 TBD TBD ns 47 chronous Greater of ns N prescale Input 20 ns or TCY 40 value Period N 1 2 4 8 Asynchronous 60 ns Ft1 oscillator input frequency range DC 50 kHz 48 Tcke2tmrl Delay from external T1CKI clock edge to 2Tosc 7Tosc timer increment DS30475A page 326 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 FIGURE 25 10 CAPTURE COMPARE PWM TIMINGS CCP1 AND CCP2 Capture Mode A oe Compare or PWM Mode Note Refer to Figure 25 4 for load conditions TABLE 25 9 CAPTURE COMPARE PWM REQUIREMENTS C D CCP2 Symbol Characteristic ax Units Conditions 5
30. 2 24 NA 3 NA 2 2 9 6 NA z 9 62 023 185 9 60 0 131 192 1923 4016 207 19 23 40 16 129 19 24 4023 9 1920 0 65 768 7692 016 51 7576 1 36 32 7782 132 22 7454 294 16 96 9524 079 41 96 15 016 25 9420 188 18 9748 4154 12 300 30770 4256 12 31250 417 7 298 35 0 57 5 316 800 4560 3 500 _ 500 0 7 500 0 4 44744 1051 3 42240 15 52 2 HIGH 400 0 2500 0 1789 80 0 1267 20 0 LOW 15 63 255 9 77 5 255 6 99 5 255 4 95 255 Baup 5 4 gppgng 3579545MHz sPBRG 1MHz SPBRG 32 768 kHz value value Kbps ERROR decima ERROR decima KBauD ERROR decimal KBauD ERROR decimal 0 3 5 NA P s 5 0 30 114 26 1 2 NA 3 1 20 016 207 1 17 248 6 24 NA A 2 40 0 16 103 2 73 41378 2 9 6 9 62 4016 103 9 62 40 23 92 9 62 40 16 25 8 20 4467 0 192 1923 4046 51 19 04 083 46 19 23 4016 12 NA 768 7692 4016 12 7457 290 11 83 33 8 51 2 NA 96 1000 417 9 9943 4357 8 83 33 13 19 2 NA z 1 300 33333 41141 2 298 30 0 57 2 250 1667 0 NA 500 500 0 1 44744 1051 1 NA NA 3 2 HIGH 1000 0 89489 0 250 x 0 8 20 0 LOW 3 91 255 3 50 255 0 98 255 0 03 255 DS30475A page 170 Advanced Information 2000 Microchip Technology Inc PIC18CXX8 TABLE 16 4 BAUD RATES ASYNCHRONOUS MODE 0
31. Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE DCFSNZ TEMP ZERO NZERO Before Instruction TEMP After Instruction TEMP TEMP 1 If TEMP 0 Address ZERO If TEMP 0 Address NZERO Advanced Information DS30475A page 281 PIC18CXX8 GOTO Unconditional Branch Syntax abel GOTO O