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Alliance Semiconductor AS7C1025B handbook

1. Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time twc 10 12 _ 15 _ 20 ns Chip enable CE to write end tow 8 9 10 12 ns Address setup to write end taw 8 9 10 10 ns Address setup time tas 0 0 0 _ 0 ns Write pulse width twp 7 8 9 12 ns Write recovery time tWR 0 0 0 0 ns Address hold from end of write tan 0 0 0 _ 0 ns Data valid to write end tpw 5 6 _ 8 10 ns Data hold time tDH 0 0 0 0 ns 4 5 Write enable to output in high Z twz 5 _ 6 _ 7 8 ns 4 5 Output active from write end tow 1 1 1 _ 2 ns 4 5 Write waveform 1 WE controlled p twc taw WR Address X X Din Y Data valid XK k twz i Dout 3 26 04 v 1 3 Alliance Semiconductor P 50f9 AS7C1025B Write waveform 2 CE controlled i twe gt taw r tay Address k tas tw gt CE x twp gt WE ze twz tpw gt gt tb Din Data valid Dout AC test conditions Output load see Figure B Input pulse level GND to 3 5 V See Figure A Input rise and fall times 2 ns See Figure A Input and output timing reference levels 1 5 V 5 V 4800 Thevenin equivalent Dout 13 168 Q ee C Dout 1 728 V 9 GND Figure A Input pulse Figure B 5 V Output load Notes 1 During Vcc power up a pull up res
2. enable OE and chip enable CE with write enable WE high The chips drive I O pins with the data word referenced by the input address When either chip enable or output enable is inactive or write enable is active output drivers stay in high impedance mode All chip inputs and outputs are TTL compatible and operation is from a single 5 V supply The AS7C1025B is packaged in common industry standard packages Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on Vcc relative to GND Vi 0 50 7 0 V Voltage on any pin relative to GND Vo 0 50 Vec 0 5 V Power dissipation Pp 1 0 W Storage temperature plastic Tiig 65 150 C Ambient temperature with Vcc applied Thias 55 125 G DC current into outputs low lout 20 mA NOTE Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and func tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Truth table CE WE OE Data Mode H X X High Z Standby Isp Isp1 L H H High Z Output disable Icc L H L Dour Read Icc L L X Din Write Icc Key X don t care L low H high 3 26 04 v 1 3 Alliance Semiconductor P 20f9
3. 04 v 1 3 Alliance Semiconductor P 30f9 Read cycle over the operating range AS7C1025B 10 12 15 20 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 12 _ 15 20 ns Address access time tan 10 _ 12 15 20 ns 3 Chip enable CE access time tack 10 12 15 20 ns 3 Output enable OE access time tor 5 6 7 8 ns Output hold from address change toH 3 3 3 ns 5 CE low to output in low Z teLz 3 3 3 x ns 4 5 CE low to output in high Z tcHz 4 5 6 7 ns 4 5 OE low to output in low Z toLz 0 0 0 0 ns 4 5 OE high to output in high Z tonz 4 5 6 7 ns 4 5 Power up time tpu 0 0 0 _ 0 _ ns 4 5 Power down time tpp 10 12 15 20 ns 4 5 Key to switching waveforms __ Rising input N Falling input m Undefined don t care Read waveform 1 address controlled 9 tre x Address taa tou Dout K Data valid X Read waveform 2 CE and OE controlled 9 x t 5 CE RC1 toe 5E tolz Dour STE ee Data valid sn Nii current yr 50 SB 3 26 04 v 1 3 Alliance Semiconductor P 4of9 AS7C1025B Write cycle over the operating range 10 12 15 20
4. 2 i8 A STC 1025BE NUR March 2004 i AS7C1025B Fs 5V 128K X 8 CMOS SRAM Center power and ground Features e Industrial and commercial temperatures JEDEC standard packages e Organization 131 072 x 8 bits 32 pin 300 mil SOJ e High speed 32 pin 400 mil SOJ 10 12 15 20 ns address access time ESD protection gt 2000 volts 5 6 7 8 ns output enable access time Latch up current gt 200 mA e Low power consumption ACTIVE 605mW max 10 ns e Low power consumption STANDBY 55 mW max CMOS Pin arrangement e 6 T 0 18 u CMOS technology Easy memory expansion with CE OE inputs e Center power and ground e TTL LVTTL compatible three state I O Logic block diagram 32 pin SOJ 300 mil 32 pin SOJ 400 mil Voc gt AO 1 V 320 16 31 A15 GND m G3 30 DI A14 Input buffer ced eee 1 00 6 SN 270 07 Vv VOL Td 267 1106 AO Vcc 8 Q 25 DI GND Al T o 1 07 GND 9 HM 240 Vec X pz 512 x 256 x 8 E 1 02 10 L 230 105 ae ye DE oe apa A5 1 048 576 5 A4 13 2001 All A6 oO io A5 14 19 A10 A7 x 1 1 00 A6 15 18 ag A8 H A7 16 172 as i E wE Column decoder Conto k OE circuit OE oO JNMTHNO Siss ks ksk ka ITLLLLLLL Selection guide 10 12 15 20 Unit Maximum address access t
5. 7C1025B Ordering Codes Package Access time Temperature 10 ns 12 ns 15 ns 20 ns 300 mil SOJ Commercial AS7C1025B 10TJC AS7C1025B 12TJC AS7C1025B 15TJC AS7C1025B 20TJC Industrial AS7C1025B 10TJI AS7C1025B 127JI AS7C1025B 15TJI AS7C1025B 20TJI 400 mil SOJ Commercial AS7C1025B 10JC AS7C1025B 12JC AS7C1025B 15JC AS7C1025B 20JC Industrial AS7C1025B 10JI AS7C1025B 12JI AS7C1025B 15JI AS7C1025B 20JI Note Add suffix N to the above part number for LEAD FREE parts Ex AS7C1025B 10TJCN Part numbering system AS7C 1025B XX X X X Package Temperature range _ sa Device number Access time TJ SOJ 300 mil C commercial 0 C to 70 C pada PREE P J SOJ 400 mil PART I industrial 40 C to 85 C 3 26 04 v 1 3 Alliance Semiconductor P 80f9 AS7C1025B FS Alliance Semiconductor Corporation Copyright Alliance Semiconductor 2575 Augustine Drive All Rights Reserved Santa Clara CA 95054 Part Number AS7C1025B Tel 408 855 4900 Document Version v 1 3 Fax 408 855 4999 www alsc com Copyright 2003 Alliance Semiconductor Corporation All rights reserved Our three point logo our name and Intelliwatt are trademarks or registered trademarks of Alliance All other brand and product names may be the trademarks of their respective companies Alliance reserves the right to make changes to this document and its products at any time w
6. AS7C1025B Recommended operating conditions Parameter Symbol Min Nominal Max Unit Supply voltage Vcc 4 5 5 0 5 5 V Vin 2 2 Vect 0 5 v Input voltage Vir 0 5 0 8 Vv commercial Ta 0 70 C Ambient operating temperature industrial Ta 40 85 SU Vr min 1 0V for pulse width less than 5ns Vig max Vcc 2 0V for pulse width less than 5ns DC operating characteristics over the operating range 10 12 15 20 Parameter Symbol Test conditions Min Max Min Max Min Max Min Max Unit Input leakage current Ipy Vcc Max Vij GND to Voc 1 1 1 1 uA Output leakage Vcc Max CE Vip current ro Vout GND to Vcc i g 1 i pA i Vcc Max Operating pow r le uo 100 9 80 ma supply current CE lt Vir f fmax lour 0 mA Vcc Max Standby power supply ice cc _ 50 _ 45 _ 45 o 40 mA current CE gt Vip f fax Vec Max Isp CE 2 Vec 0 2 V 10 10 10 10 mA VIN lt 0 2 Vor VIN gt Vcc 0 2 V f 0 VoL IoL 8 mA Vec Min o4 04 04 04 v Output voltage Voy lon 4MA Vcc Min 24 24 gal 24 amp Capacitance f 1 MHz T 25 C Vee NOMINAL Parameter Symbol Signals Test conditions Max Unit Input capacitance Cin A CE WE OE Vin 0V 5 pF T O capacitance Cyo T O VIN Vout 0V 7 pF 3 26
7. ime 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 110 100 90 80 mA Maximum CMOS standby current 10 10 10 10 mA 3 26 04 v 1 3 Alliance Semiconductor P 1of9 Copyright Alliance Semiconductor All rights reserved AS7C1025B Functional description The AS7C1025B is a high performance CMOS 1 048 576 bit Static Random Access Memory SRAM devices organized as 131 072 x 8 bits They are designed for memory applications where fast data access low power and simple interfacing are desired Equal address access and cycle times t44 tac twc of 10 12 15 20 ns with output enable access times tog of 5 6 7 8 ns are ideal for high performance applications The chip enable input CE permits easy memory and expansion with multiple bank memory systems When CE is high the device enters standby mode If inputs are still toggling the device will consume Igp power If the bus is static then full standby power is reached Iggj For example the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions A write cycle is accomplished by asserting write enable WE and chip enable CE Data on the input pins 1 00 through 1 07 is written on the rising edge of WE write cycle 1 or CE write cycle 2 To avoid bus contention external devices should drive I O pins only after outputs have been disabled with output enable OE or write enable WE A read cycle is accomplished by asserting output
8. istor to Vcc on CE is required to meet Igg specification 2 This parameter is sampled but not 100 tested 3 For test conditions see AC Test Conditions Figures A and B 4 terz and tcyz are specified with CL 5 pF as in Figure B Transition is measured 500 mV from steady state voltage 5 This parameter is guaranteed but not 100 tested 6 WE is high for read cycle 7 CE and OE are low for read cycle 8 Address is valid prior to or coincident with CE transition low 9 All read cycle timings are referenced from the last valid address to the first transitioning address 10 N A 11 All write cycle timings are referenced from the last valid address to the first transitioning address 12 N A 13 C 30 pF except all high Z and low Z parameters where C 5 pF 3 26 04 v 1 3 Alliance Semiconductor P 6 of 9 AS7C1025B Package dimensions 32 pin SOJ 32 pin SOJ 300 mil 400 mil Symbol Min Max Min Max A 0 128 0 145 0 132 0 146 Al 0 025 0 025 A2 0 095 0 105 0 105 0 115 B b c D E 32 pin SOJ 300 mil 400 mil 0 026 0 032 0 026 0 032 0 016 0 020 0 015 0 020 0 007 0 010 0 007 0 013 0 820 0 830 0 820 0 830 Pin 1 B i ii 0 255 0 275 0 354 0 378 Al lt lt E1 0 295 0 305 0 395 0 405 C ili Seating E2 0 330 0 340 0 435 0 445 plane ca e 0 050 BSC 0 050 BSC 3 26 04 v 1 3 Alliance Semiconductor P 70f9 AS
9. ithout notice Alliance assumes no responsibility for any errors that may appear in this document The data contained herein represents Alliance s best data and or estimates at the time of issuance Alliance reserves the right to change or correct this data at any time without notice If the product described herein is under development significant changes to these specifications are possible The information in this product data sheet is intended to be general descriptive information for potential customers and users and is not intended to operate as or provide any guarantee or warrantee to any user or customer Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein and disclaims any express or implied warranties related to the sale and or use of Alliance products including liability or warranties related to fitness for a particular purpose merchantability or infringement of any intellectual property rights except as express agreed to in Alliance s Terms and Conditions of Sale which are available from Alliance All sales of Alliance products are made exclusively according to Alliance s Terms and Conditions of Sale The purchase of products from Alliance does not convey a license under any patent rights copyrights mask works rights trademarks or any other intellectual property rights of Alliance or third parties Alliance does not authorize its products for use as critical compone
10. nts in life supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user and the inclusion of Alliance products in such life supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use

Alliance Semiconductor AS7C1025B handbook

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