FAIRCHILD RM3182A Data Sheet
Contents
1. 7 500 6 EE 400 z 5 E 4 3 300 a e 3 S 200 I 6 2 Ps LOGIC p 100 o 1 3 2 0 8 0 ie 55 25 125 55 25 125 Temperature C Temperature C Figure 1 Supply Current vs Temperature Figure 2 IREF ILOGIC vs Temperature CL 0 pF RL Open Circuit 2 5 2 0 a a g 1 5 2 Select 0 o N 2 0 5 a 77 Q 3 3 D ive 0 3 0 3 12 5 50 100 150 O 50 100 150 200 250 300 350 400 450 500 Frequency H2 External Capacitor pF Figure 3 AmpA AmpB Output Impedance Typical Figure 4 Slew Rate vs Ca CB Powered by ICminer com Electronic Library Service CopyRight 2003 Powered by ICminer com RM3182A PRODUCT SPECIFICATION Applications Heat Sinking Air Flow and Short Circuit Protection The user application will determine if and how much heat sinking air flow will be required for the RM3182A Consideration must be given to ambient temperature load conditions and output voltage swing In addition power consumption increases with increased operating frequency Use the numbers given in the Thermal Characteristics Table to determine that the maximum allowable junction tempera ture of 175 C is not exceeded Outputs Out A and Out B are short circuit protected by the internal 37 5 back termination resistors During a short circuit of the output to either power supply or ground the device must be able to dissipate the generated heat For example if the o2. is required then Out A and Out B pins are recommended to maintain the output impedance In this configuration driving the full ARINC load of 30nF II 400 the output characteristic takes on the transfer function of a low pass filter due to the internal 37 5Q resistor the line resistance and the capacitance associ ated with the cable This will result in a lower rise fall time of the device Equation 1 1 relates the output voltage at Out A and Out B to the voltage at the power amplifier s output Output A is taken for this example AmpA Z 2 1 1 Out A Z172 Rour Where ROUT 37 5Q and ZL RL II CL The output as a function of frequency is given by equation 1 2 7 Ri 1 2 Aour jo Amp Gog 2Rour l ORD Pin Assignments VREF VLOGIC Rate Select Amp B Syne Clock Data A Data B CA CB Out A Out B VEE Amp A GND Voc 65 4192 Using equation 1 2 a time constant can be determined for the given application which is shown in equation 1 3 1 3 t Rour ll RC So for the maximum loading condition of 30nF II 400Q the resulting time constant is 1 9 us This shows that with a maximum load the output waveform is greatly affected by the low pass filter combinabon of the ROUT II RL resistor and the load capacitance A New Option Amp A Amp B The RM3182A also provides the user the option of connect ing the data line directly to the power output amplifiers thus bypassing the internal 37 5Q resistance of
3. perform can be or b support or sustain life and c whose failure to reasonably expected to cause the failure of the life support perform when properly used in accordance with device or system or to affect its safety or effectiveness instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user www fairchildsemi com 5 20 98 0 0m 001 Stock DS3003182A 1998 Fairchild Semiconductor Corporation Powered by ICminer com Electronic Library Service CopyRight 2003
4. Pee ee Se FAIRCHILD SEMICONDUCTOR m RM3182A www fairchildsemi com ARINC 429 Differential Line Driver Features e Adjustable rise and fall times e Low supply current Capable of driving 30 nF Il 400 e Digitally selectable 12 5 or 100 kbit sec data rate e Adjustable output voltages swing Output overvoltage protected Short circuit protected TTL and CMOS compatible inputs e MIL STD 883B screening available e Available in 16 lead ceramic sidebrazed DIP and 28 Terminal LCC Block Diagram Charge Pumps Data A Clock Syne VREF Data B Cap B Vioaic F Iser B Vioaic Vioaic lser A Rate Select Rate Select Iser B Cap B GND Note Pin numbers are for the DIP package Description The RM3182A is a complete differential line driver IC When Data A Data B or Sync or Clock Signal is low the driver forces the output to a Voltage Null level OV 250 mV Designed to address the ARINC 429 stan dard the RM3182A has output rise and fall times that can be adjusted by the selection of an external capacitor CA or CB and an output voltage range adjustable through an externally applied VREE signal All logic inputs and sync control inputs are TTL CMOS compatible The device is constructed on a monolithic IC using a junction isolated bipolar process Sputtered SiCr resistors in the internal bias circuitry provide for stable bias currents a
5. combination 10 to 90 Rise Fall time Data Rate Rate Select uS Kbits sec Comments Powered by ICminer com The last functional block of the device consists of a voltage follower and a high power output differential amplifier The voltage follower buffers the signals presented at the charge caps and presents the mirrored signal to the differ ence amplifier to drive the ARINC line Two different outputs are available from the differential amplifiers Amp A Amp B and Out A Out B The outputs Amp A and Amp B are the direct outputs of the power amplifier The outputs Out A and Out B include 37 5Q series resistors added to minimize bus reflections by matching the power amplifier s output imped ance to the cable s impedance of 759 Amp A and Amp B may be used to customize the output impedance of the device These outputs can also be used to enhance the device s drive capability For example driving the standard 30 nF II 400 load defined in the ARINC specifications see output drive capability and capacitive loads for more details All outputs are protected from voltage spikes with diodes connected between the output pins and the supply lines Electronic Library Service CopyRight 2003 Powered by ICminer com PRODUCT SPECIFICATION RM3182A Output Drive Capability and Capacitive Loads The Traditional Approach The RM3182A is capable of driving a high capacitive resis tive load If complete ARINC compliance
6. e The basic pin spacing is 100 2 54mm between centerlines Each pin centerline shall be located within 010 25mm of its exact longitudinal position relative to pins 1 and 16 Applies to all four corners leads number 1 8 9 and 16 eA shall be measured at the centerline of the leads 7 Allleads Increase maximum limit by 003 08mm measured at the center of the flat when lead finish applied Fourteen spaces Powered by ICminer com Electronic Library Service CopyRight 2003 PRODUCT SPECIFICATION RM3182A Mechanical Dimensions continued 28 Terminal LCC Notes 1 The index feature for terminal 1 identification optical orientation or handling purposes shall be within the shaded index areas shown on oso 100 1 52 254 planes 1 and 2 Plane 1 terminal 1 identification may be an extension o50 oss 1 27 27 2 24 24 of the length of the metallized terminal which shall not be wider than 022 os se 71 raven E soo tee aioe ae 2 Unless otherwise specified a minimum clearance of 015 inch 0 38mm shall be maintained between all metallized features 11 23 11 68 e g lid castellations terminals thermal pads etc 300 BSC 7 62 BSC 3 Dimension A controls the overall package thickness The maximum 150 BSG 3 81 BSG A dimension is the package height before being solder dipped 050 BSG 1 27 BSC The corner shape square notch radius etc may vary at the 040 REF 1 02 REF manufac
7. his circuit shows the complete configuration for a 100 Kbits sec 10V differential output swing using the terminated output pins l Adjust By Cg or Rate Select I l l VREF i VReF l I I i weigh Veer I I I LOW VREF 65 4188 Figure 5 Switching Waveforms Electronic Library Service CopyRight 2003 PRODUCT SPECIFICATION RM3182A 15V 10 uF l Tantalum 10 pF en Input RM3182A To Bus O ne 10 pF Tantalum 7 15V NC No Connection 65 5891A Figure 6 ARINC 429 Bus Driver Applications 100 kb s Mode Powered by ICminer com Electronic Library Service CopyRight 2003 RM3182A PRODUCT SPECIFICATION Notes Powered by ICminer com Electronic Library Service CopyRight 2003 PRODUCT SPECIFICATION RM3182A Notes Powered by ICminer com Electronic Library Service CopyRight 2003 RM3182A PRODUCT SPECIFICATION Mechanical Dimensions 16 Lead SideBraze Ceramic DIP 014 023 36 58 045 065 1 14 1 65 38 21 84 7 11 7 87 2 NOTE 1 py EET Notes 1 Index area a notch or a pin one identification mark shall be located adjacent to pin one The manufacturer s identification shall not be used as pin one identification mark The minimum limit for dimension b2 may be 023 58mm for leads number 1 8 9 and 16 only Dimension Q shall be measured from the seating plane to the base plan
8. mA ee Negatve Supply Curent Data Rate 010100 Koitsisee 40 49 68 mA Losic VioGIC Supply Curent Data Rate 010100 Keitsisec 180 214 300 vA vi input Logic Level High Dependenton Voge 20 vege v vw maton Pos Von OupuVorago Hoh Win respestie croua 78 s0 fes f v V Vnu Output Votege Nul Both Data Inputs Loge 0 280 0 280 mw e E S A m _ Input Curenttow vnzosv e AT PA ai pt Gapctanes imran ae oF Output Short Circuit Current aoa RST ROSAS and or BouT shorted line to 156 mA line or to GND Iscvcc Vcc Short Circuit Current AouT and or BOUT shorted line to mA line or to GND ISCVEE VEE Short Circuit Current AOUT and or BOUT shorted line to 140 165 mA line or to GND Note 1 Guaranteed by design Powered by ICminer com Electronic Library Service CopyRight 2003 PRODUCT SPECIFICATION RM3182A Typical Power Dissipation Characteristics Vcc 15V VEE 15V VREF 5V TA 25 C CA CB 56pF Positive Negative Pin VLoGic Total Data Rate Rate Supply Supply Supply Power Kbits sec Load Select Current Current Current Dissipatlon 0 100 Open Circuit Logic 1 0 214 uA 160 mW 12 5 14 Full Load 19 6 mA 22 7 mA 200 uA 655 mW Full Load 39 1 mA 38 4 mA 200 uA 1165 mw Note 1 RL 400Q CL 0 03 uF see Block Diagram Typical Performance Characteristics
9. nd a tighter tolerance of output impedance The RM31872A is available in 16 lead ceramic sidebrazed DIP 28 Terminal LCC and can be ordered with MIL STD 883B high reliability screening CL 65 5890A Rev 1 0 0 Powered by ICminer com Electronic Library Service CopyRight 2003 RM3182A PRODUCT SPECIFICATION Functional Description The device contains three main functional blocks The first block is a digital section used to decode the ARINC Clock Synchronization and Data inputs as shown in Block Dia Table 1 I O Truth Table swe cok Dmna Daab OwA out Comments gram This block takes these inputs and channels the data to the charge pump circuits The logical relationship for these pins is presented in Table 1 EE VREF Sa Gem a a a The second functional block is a charge pump circuit that is used to control the output waveform and its timing character istics This is achieved through charging and discharging a capacitor with a known current The capacitor is user select able and is connected between CA or CB pins and ground A rate select pin digital input enables to set the rise and fall Table 2 Rate Select Pin Truth Table time If this pin is tied to ground the device functions in the high rate This mode is recommended if the user does not have an application requiring data rate switching In the table below recommended capacitor values are given for each possible data
10. the device and matching the line more precisely For example using a 1 37 5Q resistor allows better control of the output impedance By applying the load directly to the power amplifiers output pins the resulting waveform is virtually unchanged when driving other loads There may be applications where these pins present a more desirable result For instance if the line that the chip is driving is short then the parasitic compo nents of the line can be neglected and power amplifier can be tied directly to the lines This option can be utilized to achieve a greater noise immunity through bypassing the internal resistors 5 2 D o 02 m O o wu g Sio S08 Ar2 gt gt 2 lt NC Clock Data A NC NC Data B NC CB CA NC NC Amp A NC NC lt wun gM S y zZ S S 67 976 65 4193 Electronic Library Service CopyRight 2003 RM3182A PRODUCT SPECIFICATION Absolute Maximum Ratings Parameter Min Max Units Supply Voltage Vec to ve o o o s S yi i MLoaic Theshold Voltage Soo o o 7 S yi i YREF Voltage s S So o oe S yi i Teemave ooo f e ee v Sorge Tempere Rane o o o e o o Operating ea Ps ts oY iuncion Temperature E CY CEE E Cd Thermal Characteristics Still air soldered into PC board Electrical Characteristics Vcc 15V VEE 15V VREF 5V VLOGIC 5V Rate Select OV RL Open Circuit CL 0 pF and 55 C lt TA lt 125 C oc Postive Suppy Conen Data Rate O7o 100 Keeses 40 57 68
11. turer s option from that shown on the drawing The index 020 REF 51 REF corner shall be clearly unique 5 Dimension B3 minimum and L3 minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed Dimension B3 maximum and L3 maximum define the maximum width and depth of the castellation at any point on its surface Measurement of these dimensions may be made prior to solder dripping 6 Chip carriers shall be constructed of a minimum of two ceramic layers LID PLANE 2 PLANE 1 See Note 1 DETAIL A Index Corner j x 45 x 45 3 pics M4 DETAIL A 11 Powered by ICminer com Electronic Library Service CopyRight 2003 RM3182A PRODUCT SPECIFICATION Ordering Information Part Number Operating Temperature Range RM3182AS 16 Lead Sidebraze Ceramic DIP 55 C to 125 C RM3182AL 28 Terminal Leadless Chip Carrier 55 C to 125 C LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body device or system whose failure to
12. utput is shorted to ground and Vcc 15V the device must dissipate 15V x 0 165A 2 5W An appro priate heat sink is required in this situation Note that the Amp A and Amp B outputs are not short circuit protected Shorting these pins to either power supply or ground will cause failure of the device An added external resistor will protect the circuit by limiting the current Data A Data B Out A or Amp A Adjust By C or Rate Select Out B or Amp B Differential Out A Out B Output or Amp Out A Amp Out B Note Outputs unloaded Power Supply Considerations Three power supplies are required to operate the RM3182A in a typical ARINC 429 bus application 15V for VCC 15V for VEE and 5V for both VREF and VLOGIC The dif ferential output swing of the RM3182A is equal to 2 x VREF Using 5V gives a differential output swing of 10V If a different output voltage swing is required an additional power supply is needed to set VLOGIC Each power supply pin should be decoupled to ground using a high quality 10 wF tantalum capacitor This is especially true when driving a large capacitive or resistive loads The decoupling capacitors should be located as close to the device pins as possible to eliminate the wiring inductance Typical ARINC 429 Application Figure 5 shows typical switching waveform for the RM3182A in any configuration Figure 6 depicts connections for a ARINC 429 high speed bus driver application T
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FAIRCHILD RM3182A Data Sheet