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MAXIM MAX180 Data Sheet

1. gt e HBEN 0164 CLKIN 4 166 mm REFOUT ME E az I D11 D9 DGND D6 D4 H MAX181ACPL O Cto 70 C 40PlasticDIP 1 2 MAX181BCPL O Cto 70 C 40PlasticDIP 90 160 4 064 mm MAX181CCPL O Cto 70 C 40PlasticDIP 1 MAX181ACQH O Cto 70 C 44PLCC 1 2 MAX181 MAX181BCQH O0 Cto 70 C 44PLCC 1 MAX181CCQH O Cto 70 C 44 1 1 H MAX181AEPL 40 C to 85 C 40 Plastic DIP 1 2 I MAX181BEQH 40 C to 85 C 44 PLCC t1 MAX181CEQH 40 Cto 85 C 44 PLCC 1 MAX181AMJL 55 Cto 125C 40CERDIP 1 2 MAX181BMJL 55 Cto 125 C 40 CERDIP 1 MAX181CMJL 55 Cto 125 C 40 CERDIP 1 Contact factory for dice specifications Contact factory for availability and processing to MIL STD 883 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 20 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1991 Maxim Integrated Products Printed USA maxim is a registered trademark of Maxim Integrated Products
2. 0 ns BUSY to Data Out Valid ns CS RD or WR to CLK Setup time for 15 clock ns conversion CS RD or WR to CLK Setup time for 16 clock conversion Note 1 Performance at power supply tolerance limits guaranteed by power supply rejection test Note 2 Vpp 5V Vss 15V FS 5V REFIN 5V Note 3 Typical change over temperature is 1LSB Note 4 FS Tempco AFS AT where AFS is full scale change from Ta 25 C to TMIN or to TMAX Note 5 Guaranteed by design Note 6 REFIN TC AREFIN AT where AREFIN is reference voltage change from Ta 25 C to TMIN or to TMAX Note 7 Load current should remain constant during conversion This current is in addition to the DAC input current Note8 All inputs OV to 5V swing with tr tr 5 10 to 90 of and timed from a voltage level of 1 6V Note 9 tis and t21 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0 8V or 2 4V Note 10 t17 is defined as the time required for the data lines to change 0 5V when the circuit load is as shown in Figure 2 MAX180 MAX181 FUNCTION DIP PLCC DIP PLCC Analog Inputs to the mux OV to 5V unipolar 2 5V to 5 1 6 2 7 1 6 2 7 42 5V bipolar Analog Inputs to the mux OV to 5V unipolar 2 5V to AING AIN7 78 8 9 2 5V bipolar ADCIN 8 9 Analog Input to track and hold 9 1 Pin Description 10 Reference Input 0
3. MA AMAIL SVI Complete 8 Channel 12 Bit Data Acquisition Systems General Description Features The MAX180 MAX181 are complete 12 bit Data Acquisition 12 Bit Resolution 1 2LSB Linearity System DAS which combine 8 6 channel input multi 8 Channel Multiplexed Inputs 180 plexer high bandwidth Track and Hold T H low arift zener reference and flexible microprocessor uP interface Single Ended 1 of 6 Multiplexer MAX181 with high conversion speed and low power consumption Built In Track and Hold The 180 181 can be configured by uP for 100kHz Sampling Rate unipolar or bipolar conversions and single ended or differ ential inputs Both devices sample and digitize at 100kHz DC and Dynamically Tested throughput rate and feature a fast 8 or 16 bit uP interface Internal 25ppm C Voltage Reference The MAX180 has 8 analog input channels while the MAX 181 Each Channel Configurable for Unipolar OV to has 6 The multiplexer output of the MAX180 is fed directly 5V or Bipolar 2 5V to 2 5V Input Range into the Analog to Digital Converter ADC input The Each Channel Configurable for Single Ended or MAX181 brings out both the multiplexer output and ADC input Differential Inputs to separate pins allowing a programmable gain amplifier to Fast 8 16 Bit uP Interface be inserted between the MUX and the ADC 5V and 12V to 15V Supply Operation The systems allow the user to choo
4. 0 3V 17V AGND to 0 3V Vpp 0 3V AIN _ MUXOUT ADCIN REFADJ OFFADJ to REFIN 0 3V VDD 0 3 REFIN to DGND CS WR RD CLK 2 0 0 3V Vss 0 3 Continuous Power Dissipation any package to 70 C derates above 70 C by Operating Temperature Ranges BIP DIFF HBEN to DGND BUSY D0 D11 to DGND 0 3V Vpp 0 3V 0 3V Vpp 0 3V MAX18 C _ to 70 C MAX18 E 40 C to 85 MAX18 MJL 55 C to 125 C Storage Temperature Range 65 C to 160 C Lead Temperature soldering 10sec 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are siress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 45V 35 Vss 12V 5 or 15V 5 REFIN 5V Internal Reference Mode Bipolar Mode Slow Memory Mode see text 1 6MHz external MAX180 MAX181 all grades TA TMIN to TMAX unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN UNITS ACCURACY Note 2 N 18_
5. 12 Bit Data Acquisition Systems r DATA VALID DATA VALID r 18 117 DATA OUT EWDATA 2 HOLD TRACK dl t7 U DATA IN DATA VALID X DATA VALID K 7 H7 DATA QUT i NEW DATA 2 NEW J 07 00 DTT D8 HOLD 16 Figure 7b Input Output Port Mode timing two byte read MODE 1 gt 9 LE LXVW OSLXVW 180 181 Complete 8 12 Bit Data Acquisition Systems DATAIN A DATAVALID K 14 gt tis DATA OUT NEW DATA D11 D0 WR READY OUTPUT 70 3CLK Figure 8a Slow Memory Mode timing parallel read MODE 0 HBEN 0 t3 03 lt t DATAIN XONAVAUDE DATA VALID X i21 t17 4 OLD DATA NEW DATA 3 DATA OUT 07 00 07 00 WR READY OUTPUT HOLD TRACK Figure 8b Slow Memory Mode timing two byte read MODE 0 10 IA AXIA Complete 8 12 Bit Data Acquisition Systems t3 DATAIN DATAVAUDKE O O DATA OUT i OLDDATA NEWDATA 1j ng 011 00 117 WR READY OUTPUT HOLD TRACK Figure ROM Mode timing parallel read MODE 0 HBEN 0 118 F w b 1 14 lig t 13 DATA IN X
6. 18 B C Resolution Integral Nonlinearity Error Differential Nonlinearity Error Unipolar Offset Error Note 3 Unipolar Gain Error Gain Error Tempco Note 4 Channel to Channel Matching DYNAMIC PERFORMANCE Note 2 Signal to Noise SINAD bipolar mode Ta 25 C Total Harmonic Distortion up to the 5th harmonic bipolar mode Ta 25 C Distortion Ratio SFDR Spurious Free Dynamic Range bipolar mode Ta 25 C Full Power Sampling Bandwidth Track and Hold Acquisition Time Note 5 Asynchronous hold mode Conversion Time 15 16 clock cycles 12 Bits LSB Guaranteed monotonic over temperature LSB LSB LSB 2 10 LSB 2 15 LSB ppm C 1 4 LSB 10kHz input signal 100kHz sampling rate 70 dB 10kHz input signal 100kHz sampling rate 80 dB 10kHz input signal 100kHz sampling rate 80 dB In track mode under sampled waveform 6 MHz 1 875 HS Note 5 7 500 8 125 5 ROM Slow Memory and 1 Port Modes 9 375 10 000 M ANALOG INPUT Voltage Range REFIN VoD Unipolar Single Ended Range 0 50 Unipolar Differential Range 0 5 0 Bipolar Single Ended Range to AGND 2 5 2 5 Bipolar Differential Range AIN_ to AIN 2 5 2 5 MAXIMA Complete 8 12 Bit Data Acquisition Systems ELEC
7. 11 11 13 5V Reference Output 12 14 5V Reference Adjust Connect to Vpp if not required Offset Adjust Connect to Vpp if not required MODE 14 16 14 16 Interface Mode Select pin 15 17 15 17 Negative Supply 15V or 12V D11 D8 16 19 18 21 16 19 18 21 Three State Data Outputs MSB D11 DGND 20 22 Digital Ground D7 DO 21 28 24 31 21 28 24 31 Three State Data Outputs LSB DO 29 32 29 32 Clock Input TTL CMOS compatible HBEN 30 33 30 33 High Byte Enable Input 31 35 31 35 READ Input WR 32 36 32 36 WRITE Input MODE 1 or Open READY Output MODE 0 CS 33 37 33 37 CHIP SELECT Input BUSY 34 38 34 38 BUSY Output DIFF 35 39 35 39 Single Ended Mode DIFF 0 Differential Mode DIFE 1 BIP 36 40 36 40 Unipolar Mode 0 Bipolar Mode BIP 1 37 39 41 43 lexer Channel Address Input A2 MSB AO LSB 40 44 Positive Supply 5V Input substrate connected to VDD N C 1 12 1 12 No Connect No internal connection Leave pin open or UT 23 34 23 34 connect to AGND 5 KS 180 181 Complete 8 12 Bit Data Acquisition Systems 1 wal High Z to tov and VoL to b High Z to VoL tov and to VoL Figure 1 Load Circuits for Access Time A D Converter Operation The MAX180 MAX 1
8. LOGIC INPUTS Input Low Voltage VIL MODE 05 V CS RD WR CLK 2 DIFF BIP HBEN 08 Input High Voltage VIH MODE 45 V CS RD WR CLK A2 A0 DIFF BIP HBEN 2 4 MODE 15 35 V Input Floating Voltage VFLT MODE 2 5 V MODE 50 _ 100 Input Current TA TMIN to TMAX x50 100 uA CS RD WR CLK A2 A0 Ta 250 1 DIFF BIP HBEN TA Twin to Tmax 10 Input Capacitance Note 5 15 LOGIC OUTPUTS va Output High Voltage Floating State Leakage Current Floating State Output Capacitance Note 5 011 00 BUSY RDY Isink 1 6mA D11 DO BUSY RDY IsouRcE 360 4 0 D11 DO Vout OV to MAXUM 3 LS LXVW O8 LXVW 180 181 Complete 8 Channel 12 Bit Data Acquisition Systems ELECTRICAL CHARACTERISTICS continued VDD 45V 5 Vgs 12V 5 or 15V 596 REFIN 5V Internal Reference Mode Bipolar Mode Slow Memory Mode see text CLK 1 6MHz external 180 181 all grades Ta TMIN to Tmax unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS UNITS POWER REQUIREMENTS Supply Voltage Note 1 Supply Current EI NN Vss 12V Power Dissipation PD 5V VSS 15V Input near FS Vss 12V Vpp 4 75V to 5 25V PSR Input near FS Vpp 5V Vss 14 25V to 15 75V Input near FS 5
9. used to place the uP into wait state When the conversion is complete BUSY releases the from its wait state The uP can then access the conversion result with a read instruction For 16 bit bus operation HBEN 0 and the 12 bit result is read directly For 8 bit bus operation HBEN 0 during the conversion and the read instruction returns the 8 LSBs second read with HBEN 1 returns the 4 MSBs in the low nibble Note In any mode HBEN 1 disables conversion start ROM Mode Parallel Read MODE 0 ROM mode avoids using uP wait states conversion starts with a read instruction and the 12 data bits from the previous conversion appear at D11 DO The data from the first read in a sequence is often disregarded when ROM mode is used second read accesses the resutts of the first conversion and starts a new conver sion The time between successive reads must be longer than the conversion time of the MAX180 MAX181 Figure 9a 16 bit bus ROM Mode 2 Byte Read MODE 0 As in memory mode only D7 DO are used for a 2 byte read conversion starts with a read instruction when HBEN is low At this point the data outputs contain the 8 LSBs from the previous conversion Two more read op erations are needed to access the conversion result The first with HBEN high accesses the 4 MSBs with 4 leading zeros The second read with HBEN low outputs the 8 LSBs and starts a new conversion Figure 9b 8 bit bus detai
10. 81 use successive approximation and input track and hold T H circuitry to convert an analog signal to a series of 12 bit digital output codes The control logic interfaces easily to uPs requiring only a few passive components for most applications The T H does not require an external capacitor Figure 3 shows the MAX180 typical operating circuit Starting a Conversion Regardless of the mode or interface selected the follow ing sequence occurs once conversion is started 1 data inputs that configure the data acquisition system DAS latch and the interface signals the uP that a conversion has started 2 directs the selected input signal to the T H input 3 Afixedtime delay allows the T H to acquire the signal In all modes except asynchronous hold this delay is 3 clock cycles In asynchronous hold the uP controls this delay 4 The T H switches to hold mode The T H output delivers a stable single ended sample of the input signal to the A D input 5 The successive approximation cycle begins The ADC tests and sets each of the 12 bits in turn from most to least significant Bit decisions occur on the CLKIN falling edges for a total of 12 clock cycles 6 Output data is latched by the output registers and the interface signals the uP that conversion is com plete and data is available 10pF l DGND b to High Z DGND a VoH to High Z Figure 2 Load Circuits for Bus Hel
11. DAAVAID X DATA VALID T R DATA VALID 114 t H4 07 00 D11 D8 D7 D0 DATA OUT C OLDDATA j 3 _ NEW 2 17 li 7 16 117 WR READY OUTPUT HOLD TRACK Figure 9b ROM Mode timing two byte read MODE 0 8 IXVW 08 L XVMW 180 181 Complete 8 12 Bit Data Acquisition Systems 2 111 DATA IN X DATAVAD K X DATA VALID 8 8 H6 7 DATA OUT NEWDATA f D11 DO HOLD TRACK Figure 10a Asynchronous Hold Mode timing parallel read MODE open circuit 7 COCO DATAVALD X 8 b NEWDATA 3 new ava 07 00 D11 D8 Figure 106 Asynchronous Hold Mode timing two byte read MODE open circuit 132 00 MAXIM Complete 8 12 Bit Data Acquisition Systems t2 gt 220ns Conversion takes 15 clocks gt Conversion takes 16 clocks A WR rising edge starts a conversion in Input Output Port Mode Figure 7a 75 Figure 11 CS RD or WR to CLK Setup and Hold Time for Synchronous Operation Digital Interface Input Output Port Mode MODE 1 In this mode data inputs and outputs are usually con nected together Figure 6 and the uP writes the config uration data to the DAS internal register with a write instruction Figure 7 This st
12. O are the 12 bit conversion results D11 is the MSB 14 MAAKI AMI Complete 8 12 Bit Data Acquisition Systems Layout Grounding Bypassing Use printed circuit boards for best system performance wire wrap boards are not recommended board lay out should ensure that digital and analog signal lines are separated as much as possible Do not run analog and digital especially clock lines parallel to one another or digital lines underneath the ADC package Figure 12a shows the recommended system ground con nections A single point analog STAR ground should be established at AGND separate from the logic ground All other analog grounds and DGND should be connected to this STAR ground and no other digital system grounds should be connected here For noise free operation the ground return to the power supply from this STAR ground should be low impedance and as short as possible Figure 12a Hecommended Grounding and Ground Plane The ADC s high speed comparator is sensitive to high frequency noise in the VDD and Vss power supplies These supplies should be bypassed to the analog STAR ground with 0 1uF and 47uF bypass capacitors Minimize capacitor lead length for best supply noise rejection If the 5V power supply is very noisy connect a small 100 resistor to filter the noise Figure 12b Gain and Offset Adjustment Figure 13 plots the nominal unipolar I O transfer function of t
13. TRICAL CHARACTERISTICS continued VDD 5V 5 Vss 12V 5 or 15V 5 REFIN 5V Internal Reference Mode Bipolar Mode Slow Memory Mode see text CLK 1 6MHz external MAX180 MAX181 all grades TA TMIN to TMAX unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS UNITS ANALOG INPUT continued Input Current 180 21 0 ADCIN MAX181 30 1 Mux On Resistance 2 5V IMuxouT 1 25mA 181 2 Mux On Leakage Current AIN_ MUXOUT 25V MAX181 100 nA Mux Off Leakage Current 15V 15V 181 100 nA lout OFF 5V Vour 45V 181 100 Input Capacitance Note 5 CIN ADCIN 25 35 pF MUXOUT 35 45 REFERENCE INPUT Input Range Note 5 4 92 500 5 08 V NE 2 mA D j 25 REFERENCE OUTPUT TA 25 C 498 500 502 V MAX18 C 45 VREF Load Regulation Note 7 lout OMA to SMA TA 25 C 02 10 mV mA REFADJ OFFADJ Input Current VREFADJ VOFFADJ Vpp to REFIN d 1 uA Disable Threshold 4 5 V REFADJ Adjustment Range REFIN REFADJ AGND 60 80 mV OFFADJ Adjustment Range REFIN OFFADJ AGND 15 25 LSB
14. V Vss 11 4V to 12 6V Power Supply Rejection with Internal Reference LSB 1 8 1 2 TIMING CHARACTERISTICS 5V Vss 12V fct K 1 6MHz Internal Reference Mode TA TMIN to Tmax unless otherwise noted Note 8 PARAMETER SYMBOL CONDITIONS Taz425C MAXI8 MAXIB M MIN MIN CS to RD Hold time we fo CS to WR Setup time o8 CStoWRHoldtime u 5 o Jo 0 ns WRlowPuseWidh ts 10 12 ns 100 120 ns o ns 180 200 260 280 ns RD Low Pulse Width 130 150 ns RD High Pulse Width 200 200 ns DATA IN to RD Setup Time 113 80 100 120 ns DATA IN to RD Hold Time 114 0 0 0 ns RD to BUSY Fall Dela 50pF 150 170 200 ns RD to Data out Valid tie CL 100 Note 9 50 100 130 150 ns RD to Data out Three State Notes 9 10 30 50 65 75 ns HBEN to RD or WR Setup Time l8 100 120 ns HBEN to RD or WR Hold Time 0 0 0 ns CS to READY Fall Delay 50pF d 110 130 150 ns 4 LA AXI AMA Complete 8 12 Bit Data Acquisition Systems TIMING CHARACTERISTICS continued 5V Vss 12V feLk 1 6MHz Internal Reference Mode TA Tmin to Tmax unless otherwise noted Note 8 PARAMETER 8 UNITS
15. When the clock and convert signals are synchronized small end point errors offset and full scale are the most that can be generated by clock feedthrough but even these errors are eliminated by ensuring that the start of a conversion RD or WR and CS falling edge does not occur within 100ns of a clock transition Figure 11 Output Data Format The 12 data bits can be output either in full parallel or as two 8 bit bytes Table 2 shows the data bus output format To obtain parallel output for 16 bit uPs HBEN is tied low Note The output data 011 00 is right justified i e DO the LSB is the right most bit in the 16 bit word two byte read makes use of outputs D7 DO Byte selection is controlled by HBEN which multiplexes the data outputs When HBEN is low the lower 8 bits appear at the data outputs When HBEN is high the upper 4 bits appear at DO D3 with the leading 4 bits low in locations D4 D7 Note The 4 MSBs always appear at D11 D8 when the outputs are enabled regardless of the state of HBEN Table 2 Data Bus Output CS amp RD LOW Application Hints initialization After Power Up In some applications power is removed from the ADC during periods of inactivity to conserve power This is increasingly common in battery powered systems To initialize the MAX180 MAX181 at power up execute a read operation with HBEN low ignoring the data out puts Minimizing System Induced Noise The 180 181 are inse
16. arts a conversion as indi cated by the high to low transition of BUSY The mux connects the selected input channel to the T H which acquires the signal during the first 3 clock cycles On the falling edge of the 3rd clock the T H switches to hold mode and the A D conversion starts 15 clock cycles after WR goes high BUSY goes high and the conversion result latches into three state output buffers The can then access the conversion result with a read instruction For 16 bit bus operation HBEN 0 and the 12 bit result is read directly For 8 bit bus operation HBEN z 0 during the conversion and the read instruction returns the 8 LSBs A second read with HBEN 1 returns the 4 MSBs in the low nibble Note In any mode HBEN 1 disables conversion start The DAS internal register is 5 bits wide 3 bits for the analog channel address 1 bit for single ended differential mux operation and 1 bit for unipolar bipolar A D operation Slow Memory Mode MODE 0 The DAS appears to the uP as memory or as a slow peripheral in memory mode The 5 configuration bits can be preset by an external data latch a decoded device address or any external selection logic read instruction initiates conversion as shown Figure 8 In this mode the WR input functions as the RDY output and goes low when CS goes low BUSY goes low after RD goes low indicating the beginning of a signal acquisition cycle and can be
17. d adjust R1 until the output code switches between 0000 0000 and 0000 0000 0001 For full scale apply FS 1LSB 2 49817V to the input and adjust R2 so the output code switches between 0111 1111 1110 and 0111 1111 1111 Figure 15 There may be some interaction between these adjustments f an external reference is used adjust gain by varying the value of the reference instead of R2 OUTPUT CODE FULL SCALE TRANSITION FS 3 2LSB AIN INPUT VOLTAGE LSBs Figure 13 MAX180 MAX 181 Unipolar Transfer Function 16 Dynamic Performance Wide bandwidth analog input and 100kHz throughput make the MAX180 MAX181 ideal for wideband signal processing To support these and other related applica tions fast Fourier transform FFT test techniques guar antee the ADC s dynamic frequency response distortion and noise at the rated throughput Specifically this in volves applying a low distortion sine wave to the ADC input and recording the digital conversion results for a specified time The data is then analyzed using an FFT algorithm that determines its spectral content Conver sion errors are seen as spectral elements outside of the fundamental input frequency ADCs have traditionally been evaluated by specifications such as zero and full scale error and integral INL and differential DNL nonlinearity Such parameters are widely accepted for specifying performance with DC and slowly varying signals but less useful
18. ective resolution effective number of bits the ADC provides from the measured SNR N z SNR 1 76 6 02 Figure 17 shows the effective number of bits as a function of the input frequency for the MAX180 MAX181 Total Harmonic Distortion Total harmonic distortion THD is the ratio of the RMS sum of all the harmonics in the frequency band above DC and below one half the sample rate to the RMS CONFIGURATION IS 40 PIN DIP Figure 15 Offset and Gain Adjustment amplitude of the fundamental frequency This is pressed as THD 20Log 2 V3 2 VN 2 V1 where V1 is the fundamental RMS amplitude and V2 to VN are the amplitudes of the 2nd through Nth harmonics Spurious Free Dynamic Range Spurious free dynamic range is the ratio of the fundamen tal RMS amplitude to the amplitude of the next largest spectral component in the frequency band above DC and below one half the sample rate Usually this peak occurs at some harmonic of the input frequency But if a 5 e 2 al gt lt 12 50 25 00 3750 50 00 s 100kHz FREQUENCY kHz fin 10kHz Figure 16 FFT Piot for the MAX180 MAX181 EL LL EL HL LLULT PLE 10 100 1M INPUT FREQUENCY Hz EFFECTIVE BITS Figure 17 MAX180 MAX 181 Effective Bits vs Input Frequency 17 LSLEXVW OSLXVM 180 181 Complete 8 12 Bit Data Acquisiti
19. he MAX180 MAX181 Code transitions occur halfway between successive integer LSB values Output coding for unipolar operation is natural binary with 1LSB 1 22mV 5 4096 Figure 14 shows the bipolar input transfer function where output coding is twos comple ment Vss SUPPLY Vpp SUPPLY 12 15V GND Vss AGND Yop GND 5V DIGITAL 180 1 CIRCUITRY Star ground R 10Q optional tor filtering a noisy Ypo supply Figure 12b Power Supply Grounding 15 LSEXVHW OS LXVM 180 181 Complete 8 12 Bit Data Acquisition Systems If offset and gain adjustments are not desired connect OFFADJ and REFADJ to Vpp Figure 15 s circuit provides 1 2 50 LSBs of adjustment range for gain and 0 44 18LSBs of adjustment range for offset This is ideal for applications that require gain full scale range or offset adjustment If the adjustment inputs are used bypass to AGND with a 0 1uF capacitor Offset should be adjusted before gain For the OV to 5V input range apply LSB 0 61mV to the analog input and adjust R1 so the digital output code changes between 0000 0000 0000 and 0000 0000 0001 To adjust full scale apply FS 1LSB 4 99817V and adjust R2 until the output code changes between 1111 1111 1110 and 1111 1111 1111 There may be a slight interaction between the adjustments To adjust bipolar 2 5 offset apply LSB 0 61mV to the analog input an
20. in signal process ing applications where the ADC s impact on the system transfer function is the main concern The significance of the various DC parameters does not translate well to the dynamic case so different tests are required 0 F AIN INPUT VOLTAGE LSBs Figure 14 MAX180 MAX181 Bipolar Transfer Function MA AKILA Complete 8 12 Bit Data Acquisition Systems Signal to Noise Ratio and Effective Number of Bits Signal to noise ratio SNR is the ratio between the RMS amplitude of the fundamental frequency to the RMS am plitude of all other ADC spectral components excluding harmonics The output band is limited to frequencies above DC and below one half the ADC sample conver sion rate This band includes both distortion and noise components For this reason the signal to noise and distortion ratio SINAD is a better measure of the ADC s performance The theoretical minimum ADC noise is caused by quan tization error and is a direct result of the ADC s resolution SNR 6 02N 1 76 dB where N is the number of bits of resolution A perfect 12 bit ADC can therefore do no better than 74dB Figure 16 shows the result of sampling a pure 10kHz sinusoid at a 100kHz rate with the MAX180 MAX181 An output FFT plot shows the relative output amplitude at discrete spectral frequencies Figure 16 By transposing the equation that converts resolution to SNH we can determine the eff
21. inquish Time MIXED MULTIPLEXER CONFIGURATION SHOWN REFADJ OFFADJ Voc SE CHO AIN0 REFOUT REFIN S E CH1 2 AIN1 DIFF CH2 MAX180 DIFF CH2 DIFF CH3 DIFF CH3 DIFF CH4 16 19 21 28 PY ATA LINES ar DIFF GH4 AGND DGND 1 N 20 15 47 Lt CONFIGURATION IS 40 PIN DIP Figure 3 MAX180 Typical Operating Circuit PA AXIA Complete 8 12 Bit Data Acquisition Systems Analog input Track and Hoid Figure 4 shows the equivalent input circuit illustrating the sampling architecture of the ADC s analog comparator The input capacitance acts as the hold capacitor and is charged by the input signal with every A D conversion The capacitance is charged through an internal 1kQ resistor in series with the input Note Figure 4 s switches represents both the mux and hold switches TRACK AND HOLD AND COMPARATOR AIN maan MAX181 RIN ADCIN COMPARATOR AIN_ DIFF R AGND DIFF 20 Figure 4 Equivalent Input Circuit When in single ended input mode and between conver sions BUSY High the selected analog input is con nected to the hold capacitor track mode When a conversion starts CHOLD disconnects from the T H input thus sampling the input see Digital Interface section for percise T H timing When the switch closes at conversion end CHOLD reconnects to the input and charges to the input signal The loading effect of
22. ls this mode Asynchronous Hold Mode MODE Open Asynchronous hold mode is helpful when a precise or repeatable sample timing is required Asynchronous hold is very similar to the 1 O port mode except two write instructions are required The first write with HBEN 1 configures the MAX180 MAX181 and con nects the selected channel to the T H input the second write with HBEN 0 places the T H into hold and starts the conversion In other words the three clock cycle delay for T H acquisition can be changed by controlling when the second write instruction occurs The falling edge of the second WR pulse places the T H into hold Figure 10 13 8LXVW OS LXV 180 181 Complete 8 Channel 12 Bit Data Acquisition Systems External Clock The range for the external clock duty cycle is between 2096 and 8096 A precise square wave is not required Clock and Control Synchronization For best analog performance the MAX180 MAX181 clock should be synchronized to the RD WR and CS inputs Figure 11 with at least 100ns separating convert start from the nearest clock edge This syn chronization ensures that transitions at CLKIN are not coupled to the analog input and sampled by the T H The magnitude of this feedthrough is only a few millivolts If CLKIN and convert start CS WR and RD are asynchronous frequency components caused by mixing of the clock and convert signals can in crease the apparent input noise
23. nsitive to most noise sources especially when the layout bypass and grounding recommendations are followed The following practices should also be considered 1 Minimize digital activity during conversion especially activity that is asynchronous with the MAX180 MAX181 Clock 2 Avoid data bus activity within 20ns of the CLKIN falling edge If the data bus connected to the ADC is active during a conversion coupling from the data pins to the ADC comparator can cause errors Using slow memory mode avoids this problem by placing the uP in a wait state during the conversion In ROM mode the bus should be isolated from the ADC using three state drivers if the data bus is active during the conversion In ROM mode the ADC generates considerable digital noise when RD or CS go high and the output data drivers are disabled after conversion start This noise can affect the ADC comparator and cause large errors if it coincides with the SAR latching a comparator decision To prevent this RD and CS should be active for less than one clock cycle If this is not possible RD or CS should go high on a rising edge of CLKIN because the comparator output is latched on the falling edge of CLKIN Pin 22 Pin 23 Pin24 Pin25 Pin26 Pin27 Pin 28 DIP Pin Pin 16 Pin 17 Pin 18 Pin 19 Pin 21 Pin Label HBEN LOW D10 DO HBEN HIGH LOW LOW Note 011 00 are the ADC data output pin names D11 D
24. on Systems Typical Applications REFADJ OFFADJ 1N4148 ANALOG 4 AIN2 INPUTS AIN3 AINA Our 47uF 1k i AINS ADCIN MUXOUT MA AXIAA MAAXIAA 2 MAX181 2 MODE CS RD WR MAAXIAA MAX328 0 Al M AGND DGND 20 5 Todu T GAIN SELECT LI GAIN 1 TO 128 ADDRESS MUXQUT CONFIGURATION IS FOR DIP Figure 18a MAX181 operating as a 6 channel programmable gain ADC Gains are 1 2 4 8 16 32 64 and 128 Wo MANAK Complete 8 12 Bit Data Acquisition Systems REFADJ OFFADJ MUXOUT REFOUT REFIN ADCIN ANO amp 39 AGND DGND ve MUXOUT 7 FLOATS MUKO iT 558 GROUNDS CONFIGURATION IS FOR DIP Figure 18b 181 operating as a single channel programmable gain ADC Gains are 1 2 4 16 and 32 Pin Configurations continued MA ASXCLAVI 180 181 180 ONLY MAX181 ONLY gt 19 LSLXVW OBLXVM 180 181 Complete 8 12 Bit Data Acquisition Systems _ Ordering Information continued Chip Topography AIN4 AIN2 AINO 2 A0 ERROR PART TEMP RANGE PIN PACKAGE LSBs MAX180CCQH O Cio470C 44PLCC 1 MAX180CC D 70 Dice 1 MAX180AEPL 40 to 85 C 40 Plastic DIP 1 2 MAX180BEQH 40 85 C 44 PLCC 1 AIN5 MUXOUT AIN6
25. r in parallel with a 0 1pF ceramic capacitor The reference source impedance must be less than 0 20 and must be able to sink the internal DAC load of 1mA Connect REFOUT to Vss and REFADJ to VDD to prevent noise If REFIN is driven above AGND during power sequencing latchup can occur Connect a Schottky clamp diode 5817 to prevent REFIN from substantially exceeding AGND LSLEXVW OBLXVM 180 181 Complete 8 12 Bit Data Acquisition Systems Table 1 Address vs Channel Selection see Figure 4 A2 At ao SEDIF o o o O 181 o 1 o 181 o 1 0 0 81 o 1 0 0 0 o smi MAX180 1 1 0 O O O gt IO O 180 181 180 180 181 MUXOUT CONNECTED TO AGND CH 0 5 AND MUXOUT ARE OPEN WRITE X X X X X X X DIFF BIP A2 A1 AO READ 011 010 09 08 D 06 05 D4 D3 D2 D1 DO STATUS OUPUT CONTROL INPUTS DIFF 0 181 MUXOUT gt TO uP DATA BUS Figure 5 Multiplexer channel configuration Figure 6 Input Output Port Mode 12 Bit Wide Data Bus Shown 8 MA AXIS Complete 8
26. se between an internal 110mW Power Consumption or an external reference Futhermore the internal refer ence value and the offset can be adjusted allowing the overall system gain and offset errors to be nulled The Ordering Information multiplexer has high impedance inputs simplifying ana log drive requirements ERROR PART TEMP RANGE LSBs MAX180ACPL to 70 C 40 Plastic DIP 2 MAX180BCPL to 70 C 40 Plastic DIP 1 MAX180CCPL to 70 C 40 Plastic DIP 1 MAX180ACQH 0 C to 70 44 PLCC MAX180BCOH 0 C to 70 C 44 PLCC i1 Applications High Speed Servo Loops Digital Signal Processing High Accuracy Process Control Automatic Testing Systems Ordering information continued on last page Block Diagram Pin Configurations TOP VIEW MUXOUT ADCIN OFFADJ MUXOUT AING ADCIN AIN REFIN AGND REFOUT REFADJ LATCH AND CONTROL OGIC THREE STATE OUTPUT MAX180 ONLY MAX181 ONLY MAX180 ONLY ONLY MA For free samples amp the latest literature http www maxim ic com or phone 1 800 998 8800 Maxim Integrated Products 1 HSHXVMW OBLXVM 180 181 Complete 8 12 Bit Data Acquisition Systems ABSOLUTE MAXIMUM RATINGS VoptoDGND 0 3V 7V Vss
27. the analog inputs on the signal is such that a high speed input buffer is usually NOT needed because the ADC disconnects from the input during the actual conversion The previous explanation applies for the differential input mode if input is replaced by AIN and analog ground is replaced by AIN In the differential input mode 0 2 select the input channel pairs Table 1 Only the signal side of the input channel is held by the T H the return side must remain stable within 0 5LSB 0 1LSB for best results during the conversion For example a common mode signal of 0 33Vp p at 60Hz results in a maximum error of 0 5LSB The T H starts tracking when the ADC is deselected BUSY High Hold mode begins 3 clock cycles after a conversion is initiated in all but the Asynchronous Hold Mode Variation in hold mode delay from one conversion to the next aperture jitter is less than 100ps Figures 7 11 detail the T H and interface timing for the various interface modes MA The time required for the T H to acquire an input signal is a function of how quickly the input capacitance is charged If the input source impedance is high the acquisition time lengthens and more time must be al lowed between conversions Acquisition time is calcu lated by tACQ 10 Rs RIN 20pF but never less than 1 87515 where RIN 1kQ and Rs source impedance of the input signal input Bandwidth The A D s input tracking circuitr
28. y is excellent for tracking large signals and wide bandwidths and does not exhibit the slew rate limitations of many other ADC T Hs The MAX180 MAX181 T H s full power bandwidth is typically 6MHz this allows the measurement of periodic signals with bandwidths exceeding the ADC s sample rate 100kHz using under sampling techniques Important note If under sampling is used to measure high fre quency signals take special care to avoid aliasing errors Without adequate input filtering high frequency noise could be aliased into the measurement band Reference The MAX180 MAX181 operate with either the internal reference or an external 5V reference In both cases REFIN must be bypassed to AGND with a 47 electro lytic capacitor in parallel with a 0 1uF ceramic capacitor to minimize noise and maintain a low impedance at high frequencies REFIN is connected directly to the internal DAC and the current load varies between and 1 during conversion internal Reference The internal reference is buffered through an amplifier whose output connects to REFOUT To operate the MAX180 MAX181 with the internal reference connect REFIN to REFOUT Do not connect a resistor between the bypass capacitors and REFIN The reference buffer plifier can sink 5mA for external loads Adjust the refer ence output at REFADJ Figure 14 External Reference With a 5V external reference bypass REFIN to AGND with a 47uF electrolytic capacito

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