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MITSUBISHI ELECTRIC M37754M8C-XXXGP M37754M8C-XXXHP M37754S4CGP M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1. P90 CS0 5 P67 TB2IN 6 P94 CS4 RTP13 e 0 P93 CS3 A22 RTP12 2 P92 CS2 A21 U RTP11 13 P91 CS1 A20 V RTP10 14 P62 INTo 111 P61 TA4IN 12 P6o TA40UT amp 13 P57 TA3IN KI3 14 P63 INT1 10 P5e TA3OUT KlI2 115 P64 INT2 9 P66e TB1IN 7 P65 TBOIN 8 P55 TA2IN KI1 116 P54 TA2ouT Klo 117 P53 TA1IN W RTPO03 8 P52 TA10UT U RTPO 2 19 P51 TAOIN V RTPO1 20 P50 TA0GoUTAWWIRTP0o c 21 Outline 100P6Q A P44 25 Differences between M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP and M37754S4CHP Product Internal ROM Usable processor mode Package M37754M8C XXXGP Equipped M37754M8C XXXHP 60 Kbytes Single chip mode Memory expansion mode Microprocessor mode 100 pin QFP 100P6S A 100 pin fine pitch QFP 100P6Q A M37754S4CGP Not equipped M37754S4CHP External ROM Microprocessor mode MITSUBISHI ELECTRIC 100 pin QFP 100P6S A 100 pin fine pitch QFP 100P6Q A MITSUBISHI MICROCOMPUTERS ien M37754M8C XXXGP M37754M8C XXXHP ae M37754S4CGP M37754S4CHP ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Data Bus Even Data Bus Odd Data Buffer DBH 8 Bus width select input BYTE Input Output Data Buffer DBL 8 P x Instruction Register 8 Instruction Queue Buffer Qo 8 VREF
2. Fig 12 Interrupt priority detection MITSUBISHI ie ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER As shown in Figure 13 there are three different interrupt priority de tection time from which one is selected by software After the se lected time has elapsed the highest priority is determined and is processed after the currently executing instruction has been com pleted The time is selected with bits 4 and 5 of the processor mode register 0 address 5E16 shown in Figure 14 Table 5 shows the relationship between these bits and the number of cycles After a reset the pro cessor mode register 0 is initialized to 0016 Therefore the longest time is automatically set however the shortest time must be se lected by software Table 4 Value set in processor interrupt level IPL during an interrupt Interrupt types Setting value Reset 0 DBC 7 Watchdog timer 7 Zero divide Not change value of IPL BRK instruction Not change value of IPL Table 5 Relationship between interrupt priority detection time select bit and number of cycles Priority detection time select bit Bit 5 Bit 4 Number of cycles 7 cycles of BIU 4 cycles of BIU 2 cycles of BIU BIU Operation code fetch cycle Sampling pulse Priority detection tim
3. td LA ALE X Note These become a multiplex bus only when all of the following conditions are satisfied Multiplex bus select bit 1 a While the address which corresponds to chip select signal CS4 is accessed Test conditions except Port Pi f XIN e Vcc 5 V 10 Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF Data input ViL 0 8 V VIH 2 5 V Test conditions Port Pi f XIN e Vcc 5 V 10 Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VoL 0 8 V VoH 2 0 V CL 100 pF 104 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS Feat oat M37754M8C XXXGP M37754M8C XXXHP eene esp M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER tw H tw L t t tc m pre rrr tw 9L 1 td o1 RD RD WR tw ALE td ALE RD ALE output m td BHE RD sl th RD BHE BHE output td BHE ALE gt td A RD th RD A Ao A7 output Ai6 A23 output td A ALE CS0 CS4 output tsu DL DH RD Input data tpxz RD DLZ tpzx RD DLZ E th ALE LA tsu DL RD d Do D7 input tsu LA DL th RD DL multiplexbus Note er ee TITI Data tsu PiD RD Port Pi input Input data Note These become a multiplex bus only when all of the following conditions are satisfied BYTE H Multiplex bus select bit 1 While the address which corresponds to chip select
4. A D register 5 A D register 6 A D register 7 UARTO transmit buffer register UARTO receive buffer register UART1 transmit buffer register UART1 receive buffer register Note Do not write to this address Fig 2 Location of peripheral devices and interrupt control registers 8 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT CPU The CPU has ten registers and is shown in Figure 3 Each of these registers is described below ACCUMULATOR A A Accumulator A is the main register of the microcomputer It consists of 16 bits and the low order 8 bits can be used separately The data length flag m determines whether the register is used as 16 bit regis ter or as 8 bit register It is used as a 16 bit register when flag m is 0 and as an 8 bit register when flag m is 1 Flag m is a part of the pro cessor status register PS which is described later Data operations such as calculations data transfer input output etc is executed mainly through the accumulator ACCUMULATOR B B Accumulator B has the same functions as accumulator A but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A INDEX REGISTER X X In
5. wy i TxD DOXDIXDZXDSKDAXDEXDEXD XDYXDIXDZKDIXD4XDSXDEKD7___XD9XD1XD2XDsXD4XDsX DeXD7 TxEPTYj i Fig 60 Clock synchronous serial I O timing MITSUBISHI i ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Note This is available in clock synchronous serial I O using internal clock and transmission mode Fig 61 External connection example in plural output of transmit clock mode Address UARTO Transmit Receive mode register 3016 0 0 1 Clock synchronous 0 Internal clock This bit must be 0 Address UARTO Transmit Receive control register 0 3416 1 Disable CTS RTS Address UARTO Transmit Receive control register 1 3516 0 Disable receive Address A D control register 1 1F16 0 Disable D A output Fig 62 Other registers except special function select register 1 bit configuration in plural output of transmit clock mode Table 6 Output pin of transmit clock select bits and pins function Output pin of trans mit clock select bits TCo P81 CLKo P82 RxDo P8o CTSo RTSo DAo CLKo RxDo P8o CTSo RTSo DA0 CLKo H Note P80 H CLKS2 P80 H H Note CLKS1 Note It outputs
6. Jeynq xy oSEUud A JO ijndino H doy dij 1660 jes Jegynq xy eseud n jo ndino H Auvjod 1ndino 191unoo gy 1eull L lt gt Joyng jas Ayuejod 1ndino eseud A apow es nd 10us euo HQ 043009 ndino woane M euis 1senbei 1dnuu lu zg Jeuul L e Jegyng xy eseud f jo indino H z dol dijj I66o1 jes JejsiDoJ peojay josou A uejod 1ndino 1e1unoo v1eull L lt gt bd Jeyng jes Ajurejod Ind no seud n epoui s nd ous uo o Jd uq 193 s oinos xoojo 1 uull euun peeq 191unoozy Jeu 4 gt pow 1euu LO ul Jeynq jas Ajuejod jo g Indino eseud eeuu yq Jas pemalu 1s nba u 1dnujeju yq 199 s 1ndino Aypi eA 1dnueju Fig 43 Three phase waveform mode block diagram 37 EA MITSUBISHI ELECTRIC a e SM grand 1 SPES ect 9 su MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER When writing data to the dead time timer address 1B 16 the data is written to the reload register shared by three dead time timers When the dead time timers catch the start trigger from the respec tive timers the reload register contents are transferred to its counter a
7. 910000 01 5 o0 er T 910000 80 XxX 0O Ss sexkqy ze sakay ze gt lt o sakay p9 sei qy v9 sakay p9 salAqy p9 SO 9 0008 Z0 gt lt c ESO SO Es SO seqy ze sakay ze 1 S9 SO ____ 910000 0 O seiqy get seKqy 821 seKqy ge seKqy 821 seiqy get seq 821 eo 289 Ese 289 Ese Ese SO ___ 910000 so sevqy 821 sei ay 821 seq 824 seVqy 821 s Vqy 821 saray 821 1S9 iso ISO S9 SO _ 910000 0 ____ 910000 ZO eo seKqy 091 seqy 091 910000 10 sevkay 9 sexkay ovp oso So So 0S9 seq 881 s 1 qy 881 0 0 seiKqyi 061 seiKqy 061 o Es SO 0S 940008 00 salq 82 SO 3 910001 00 se1Aq 0261 bs 29 90030 00 62 eS9 8071 ___ 19800 00 43 SJ ___ 910880 00 9 X 910800 00 2 910000 00 H4S 9 LLL OL L 001 100 oe 0q iq zq 0q Lq eq 0q Ld zq 0q L q eq 0q Lq eq s p SIIq YOUMS Bale 129Jes diuo o 5 ease joujeui eujejur eui pue ndino euis 9812S diuo 10 papau ease y ueuM OJON 1ndino peusis 3oejes diuo 104 pepueiur ease jo NO L s l q gr0z WV IBuj lul poui 10ss 901d01 Sel qM 09 NOU jeujeiul SelAq 9r0z WV eujeiu epoul uoisuedxe Aowa Fig 89 Chip select areas 77 E A MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER MEMOR
8. Reference voltage input Instruction Queue Buffer Q1 8 Instruction Queue Buffer Q2 8 SV AVcc Address Bus A 0V AVss Incrementer 24 Program Address Register PA 24 Data Address Register DA 24 Input Output Input Output Input Output Input Output CNVss D A1 Converter 8 D Ao Converter 8 A D Converter 10 Input Output Incrementer Decrementer 24 OV Vss i Program Counter PC 16 Program Bank Register PG 8 Input Output Data Bank Register DT 8 s Input Buffer Register IB 16 Input Output Timer TB1 16 Timer TB0 16 WatchdogTimer Timer TB2 16 Processor Status Register PS 11 Direct Page Register DPR 16 Reset input RESET Input Output Timer TA4 16 Timer TA3 16 Timer TA2 16 Timer TA1 16 Timer TAO 16 Stack Pointer S 16 Index Register Y 16 Index Register X 16 2048 Bytes Input Output Accumulator B 16 Enable output Accumulator A 16 output XOUT Clock Generating Circuit 60 Kbytes Input Output Arithmetic Logic Unit 16 XIN Input Output BLOCK DIAGRAM Clock input MITSUBIS
9. Stack pointer S Program bank register PG Program counter PC Data bank register DT Direct page register DPR IPL1 D l Processor status register PS Fig 3 Register structure Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER STACK POINTER S Stack pointer S is a 16 bit register It is used during a subroutine call or interrupts It is also used during stack stack pointer relative or stack pointer relative indirect indexed Y addressing mode PROGRAM COUNTER PC Program counter PC is a 16 bit counter that indicates the low order 16 bits of the next program memory address to be executed There is a bus interface unit between the program memory and the CPU so that the program memory is accessed through bus interface unit This is described later PROGRAM BANK REGISTER PG Program bank register is an 8 bit register that indicates the high or der 8 bits of the next program memory address to be executed When a carry occurs by incrementing the contents of the program counter the contents of the program b
10. 13 P641 TA4IN 14 P6o TA40UT t5 P57 TAs3IN KI3 16 P5e TA3oUT Kl2 17 P42 01 29 P41 RDY 30 P55 TA2IN KH 8 P54 TA20UT Klo t9 P53 TA1IN W RTPOS 20 P52 TA1OUT U RTPO2 21 P51 TAoIN V RTPO1 22 P5o TAooUT W RTPOo 23 Outline 100P6S A MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS s M37754M8C XXXGP M37754M8C XXXHP m dl M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER P02 A2 lt gt P01 A1 O P00 A0 lt gt P87 TXD1 P86 RxD1 lt gt P85 CLK1 lt gt P84 CTS1 RTS1 DA1 INT4 gt P83 TxDo lt gt P82 RxDo CLKS0 P81 CLKo lt gt P80 CTS0 RTS0 CLKS1 DAo lt gt P107 D7 LA7 P110 Ds P111 Do P112 D10 P113 D11 P114 D12 P115 D13 P116 D14 P117 D15 P30 WR P31 BHE P77 AN7 ADTRG e P95 INT3 Kl4 e Vcc AVcc VREF gt AVSS Vss P76 AN6 o P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 O M37754M8C XXXHP or M37754S4CHP lt P32 ALE P33 HLDA Voc Vss E RD XOUT XIN lt RESET CNVss lt BYTE P40 HOLD o P41 RDY P42 1 P43
11. 160 5 6 access 65 3 6 access tsu CS DL DH Data setup time with chip select stabilized Note 3 110 4 6 access 160 5 6 access 50 3 access tsu LA DL Data setup time with address stabilized Note 3 100 4 6 access 150 5 6 access k f XIN 20 MHz when the clock source selet bit 1 Notes 1 When the clock source select bit 1 t s minimum limit is 50 ns 2 When the clock source select bit 1 set tw H tc and tw L tc ratios to 45 to 55 96 3 Since the values depend on external clock input frequency f XIN calculate them using the bus timing data formula on the page after the next page MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS Jeet gara M37754M8C XXXGP M37754M8C XXXHP Vaca ase M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Switching characteristics vcc 5 V 10 Vss 0 V Ta 20 to 85 C f XIN 40 MHz when the clock source select bit 0 unless otherwise noted Memory expansion and Microprocessor mode High speed running Symbol Parameter 3 6 access 4 access 5 access Max Max Max tw gH tw 9L high level pulse width low level pulse width td 91 WR WR output delay time 12 12 12 td 1 RD RD output delay time 12 12 12 tw WR WR low level pulse width tw RD RD low level pulse width
12. BASIC FUNCTION BLOCKS The M37754M8C XXXGP contains the following devices on a single chip ROM RAM CPU bus interface unit timers UART A D con verter D A converter I O ports clock generating circuit and others Each of these devices is described below MEMORY The memory map is shown in Figure 1 The address space is 16 Mbytes from addresses 016 to FFFFFF16 The address space is di vided into 64 Kbyte units called banks The banks are numbered from 016 to FF 16 Internal ROM internal RAM and control registers for internal periph eral devices are assigned to bank 016 The 60 Kbyte area from addresses 100016 to FFFFt16 is the internal ROM 00000016 00007F16 00008016 Bank 016 00087F16 Bank 116 00100016 FE00001 Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 Addresses FFD216 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors Refer to the section on interrupts for details The 2048 byte area from addresses 8016 to 87F16 contains the inter nal RAM In addition to storing data the RAM is used as stack during a subroutine call or interrupts Assigned to addresses 016 to 7F16 are peripheral devices such as I O ports A D converter D A converter UART timer and interrupt control registers Additionally the internal ROM area can be modified by software Refer to the section on ROM area modification function for details A 256 byte direct page area can be al
13. When a pin is programmed for output the data is written to its port latch and it is output to the output pin When a pin is programmed for output the contents of the port latch is read instead of the value of the pin Accordingly a previously output value can be read correctly even when the output H voltage is lowered or the output L voltage is raised owing to an external load and others A pin programmed as an input pin is floating and the value input to the pin can be read When a pin is programmed as an input pin the data is written only in the port latch and the pin remains floating Additionally ports P95 P54 to P57 include pull up transistors The pull up function of ports is selected with bits 7 and 6 of the particular function select register 1 Refer to the section on Interrupts for the pull up function Figures 78 and 79 show block diagrams of ports PO to P11 in the single chip mode and E output Ports PO to P4 P10 and P11 are also used as pins of address data and control signals Refer to the section on Processor mode for more details MITSUBISHI 62 ELECTRIC MITSUBISHI MICROCOMPUTERS peer M37754M8C XXXGP M37754M8C XXXHP ae M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Address Port PO direction register 0416 Watchdog timer 6016 Port P1 direction register 0516 Watchdog timer frequency select register 6116 Port P2 direction
14. L tpzx WR DLZ DHZ tpxz WR DLZ DHZ The value of output data is undefined Test conditions VCC 5 V 10 96 Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF MITSUBISHI A ELECTRIC GZZ 8H00 85B 85A0 Mask ROM number ERES 7700 FAMILY MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP 16 BIT MICROCOMPUTER M37754M8C XXXGP Section head Supervisor signature signature M37754M8C XXXHP MITSUBISHI ELECTRIC Note Please fill in all items marked X Responsible Company Supervisor name officer x Customer Date Issuance signatures issued X1 Confirmation Specify the name of the product being ordered Three sets of EPROMs are required for each pattern Check 9 in the appropriate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Checksum code for entire EPROM areas ms hexadecimal notation EPROM Type 1 Set FF1e in the shaded area 2 Address 016 to 1016 are the area for storing the data on model designation and options This area must be written with the data shown below Details for option data are given next in the section describing the STP instruction
15. tpxz WR DLZ DHZ th WR DLQ td WR PiQ Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF MITSUBISHI ELECTRIC 93 MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER td ALE RD f XIN 1 RD WR tw ALE ALE output td BHE RD BHE output td BHE ALE td A RD Ao A7 output As A15 output Ai6 A23 output td A ALE td CS RD CS0 CS4 output td CS ALE tsu CS DL DH tsu A DL DH tsu DL DH RD Do D7 input Hi Z Dg D15 input BYTE L 77777777777777777777771 ere input data td LA RD 2 tpxz RD DLZ LAo LA7 output Do LAo D7 LA7 M qaubaes N I multiplex bus Note y Address td LA ALE th ALE LA tsu DL RD tsu LA DL Do D7 input 4r Dat multiplex bus Note tsu PiD RD Port Pi input Note These become a multiplex bus only when all of the following BYTE H Multiplex bus select bit 1 While the address which corresponds to chip select signal Test conditions except Port Pi f XIN Vcc 5 V 10 Output timing voltage VOL 0 8 V VOH 2 0 V CL 100 pF Data input VIL 0 8 V VIH 2 5 V conditions are satisfied CS4 is accessed Input data
16. Do DrzoUtput 2 zu feces E Soo ta Output data ESL Ds D15 output BYTE L K tpzx WR DLZ DHZ tpxz WR DLZ DHZ th WR DLQ Do LAo D7 LA7 output multiplex bus Note td LA ALE td WR PjQ Port Pi output Y Note These become a multiplex bus only when all of the following conditions are satisfied BYTE H Multiplex bus select bit 1 While the address which corresponds to chip select signal CS4 is accessed 102 Test conditions except Port Pi f XIN Test conditions Port Pi f XIN Vcc 5 V0 96 Vcc 5 V 10 96 Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF Input timing voltage ViL 1 0 V VIH 4 0 V Data input ViL 0 8 V VIH 2 5 V Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER when 3 access in high speed running lt Read gt f XIN 01 RD WR tw ALE lt gt td ALE RD ALE output td BHE RD th RD BHE td BHE ALE td A RD Ao A7 output As A15 output A16 A23 output td A ALE td CS RD CSo CS4 output td CS ALE Do D7 input th RD A ee J th RD CS th RD DL DH W Input data Ds D15 input BYTE L LAo LA7 output Do
17. Figure 58 shows the bit configuration of the UARTi Transmit Receive control register Each communication method is described below Data bus odd Data bus even 0 0 Ds D7 De Ds D4 D3 D2 D1 Do Receive buffer register UARTO 3716 3616 UART1 3F16 3E16 O Bit rate generator Receive control Receive register Receive clock circuit Clock source selection UART0 3116 Pf2 o UART1 3916 PH6 Internal Clock synchronous Clock synchronous Transmission clock 1 n 1 Pos xe Divider Pf512 o External 12 Divider Internal clock 1 2 Divi 2 Divider 9 Clock synchronous External clock Transmit register O Clock synchronous Fd Internal clock Transmit buffer register UART0 3316 3216 UART1 3B16 3A16 D4 Ds D2 D1 Do Data bus Data bus even Fig 54 Serial I O port block diagram Addresses UART 0 Transmit Receive mode register zi B N UART 1 Transmit Receive mode register 3816 Serial I O mode select bit 000 Parallel port 00 1 Clock synchronous 100 7 bit UART 101 8 bit UART 110 9 bit UART Internal External clock select bit 0 Internal clock 1 External clock Stop bit length select bit 0 1 stop bit 1 2 stop bits Even Odd parity select bit 0
18. OOFFD216 OOFFD316 INT3 external interrupt OOFFD416 OOFFD516 A D OOFFD616 OOFFD716 UART1 transmit OOFFD816 OOFFD916 UART1 receive OOFFDA16 OOFFDB16 UARTO transmit OOFFDC16 OOFFDD16 UARTO receive OOFFDE16 OOFFDF16 Timer B2 OOFFE016 OOFFE116 Timer B1 OOFFE216 OOFFE316 Timer BO OOFFE416 OOFFE516 Timer A4 OOFFE616 OOFFE716 Timer A3 OOFFE816 OOFFE916 Timer A2 OOFFEA16 OOFFEB16 Timer A1 OOFFEC16 OOFFED16 Timer AO OOFFEE16 OOFFEF16 INT2 external interrupt OOFFF016 OOFFF116 INT1 external interrupt OOFFF216 OOFFF316 INTo external interrupt OOFFF416 OOFFF516 Watchdog timer OOFFF616 OOFFF716 DBC Do not select OOFFF816 OOFFF916 Break instruction OOFFFA16 OOFFFB16 Zero divide OOFFFC16 OOFFFD16 Reset OOFFFE16 OOFFFF16 Note 1 The A D conversion interrupt request bit becomes undefined after reset Clear this bit to O before use of the A D conversion interrupt a iA Interrupt priority level Interrupt request bit 0 No interrupt 1 Interrupt Polarity select bit level for edge sense level for edge sense Level Edge select bit 0 Edge sense 1 Level sense 00 INT3 interrupt selected 0 1 Do not select 10 Key input interrupt KI3 to Kl
19. k gt th RD PiD IET x Input data D Note These become a multiplex bus only when all of the following conditions are satisfied Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VoL 0 8 V VoH 2 0 V CL 100 pF 96 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS Mao cand M37754M8C XXXGP M37754M8C XXXHP cit NS cesser M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER when 4 access in low speed running lt Write gt tw H tw L t t tc tw oL 01 td 1 WR lt td 1 WR RD WR tw WR W ALE td ALE WR ALE output td BHE WR WNEENE td BHE ALE td A WR t h WR A A0 A7 output A16 A23 output td A ALE td CS WR th WR CS So CS4 output th WR DLQ DHQ Do D7 oUtp l gt mi _ weliteclbosoes tees oes eect cee sted dH Ds D15 output BYTE L tpzx WR DLZ DHZ lt gt tpxz WR DLZ DHZ td WR DLQ t LA WR i lt gt th WR DLQ Do LAo D7 LA7 output utiles bus Note td LA ALE td RD PiQ Port Pi output Note These become a multiplex bus only when all of the following conditions are satisfied BYTE H Multiplex bus select bit 1 While the address which corresponds to chip select signal CS4 is accessed Test conditions except Port Pi f XIN Test conditions Port Pi f XiN e Vcc 5 V 10 96 e Vcc 5 Vt10 Output tim
20. 0 Do to D7 input output separate bus 1 When BYTE pin input is H and accessing CS4 area LAo Do to LA7 D7 input output multiplex bus In condition except above Do to D7 input output separate bus Expansion address output select bits Notes 1 3 0 0 P91 CS1 output P92 CS2 output P93 CS3 output 0 1 P91 A20 output P92 CS2 output P93 CS3 output 1 0 P91 A20 output P92 A21 output P93 CS3 output 1 1 P91 A20 output P92 A21 output P93 A22 output When the expansion function select bit bit 5 of particular function select register 1 Figure 62 is 1 bits 2 5 6 and 7 can be written and changed When accessing the internal memory area CSi is not output When only accessing the external area CSi output is valid Select function of bits 6 and 7 is valid when both the CS1 CS2 function select bit and the CS8 function select bit chip select control register are 1 Fig 88 Chip select area register bit configuration MITSUBISHI 76 ELECTRIC MITSUBISHI MICROCOMPUTERS ease iouieui eUJejul yey 10 BAe euooeg JOU seop 1ndino 1ejes diuo eu pesn s ease fuouieui euJa1ui Jo oo sseooe snq eui Jeujoue euo deano us INvH WOH P pose Aiowaw eula x3 GZ Oa lt m es E 2 gt O Xt 6 Qu 9 Om 5 on N 914334 44 D lt 910000 08 O Q E ____ 910000 OF OO sequ gz sequ gz 910000 02 O 2 SO So soan S Qa 5
21. Direct page register DPR 000016 Timer B1 mode regis 5C16 Data bank register DT 0016 Timer B2 mode regis Di6 Die Contents of other registers and RAM are not initiallzed and must be in BEs6 olo itiallzed by software Processor mode register 0 Processor mode register 1 5F16 0016 Note Bit 0 of chip select control register address 6216 becomes 0 when CNVss pin level is L that bit becomes 1 when the pin level is H Fig 76 Microcomputer internal registers status after reset MITSUBISHI ELECTRIC 63 MITSUBISHI MICROCOMPUTERS w M37754M8C XXXGP M37754M8C XXXHP oa Noe s M37754S4CGP M37754S4CHP e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Port P00 to P07 P10 to P17 P20 to P23 P27 P30 to P33 P43 to P46 P100 to P107 P110to P117 Inside dotted line not included Port P40 P41 P47 P51 P53 P61 to P67 P86 Inside dotted line included Direction register La lt Data bus Port latch Port P70 to P76 Inside dotted line not included Port P77 Inside dotted line included t lt A Analog input Port P42 P83 P87 P90 to P94 Inside dotted line not included Port P50 P52 P60 P82 Inside dotted line included Direction register q e o Output 2_ Data bus Port latch Port P54 P56 Pull up select i4 lt
22. H when bit 2 of the port P8 direction register is 1 and it becomes floating when bit 2 is 0 Pin name 0 1 0 1 Receive Receive starts when bit 2 REk flag of UARTk Transmit Receive control register 1 is set to 1 The RTSk output is H when the REk flag is 0 and goes L when the REk flag changed to 1 and the TIk flag did to 0 It goes back to H when receive starts The TIk flag is cleared to 0 by write dummy data to the transmit buffer register It is ready to receive when RTSk output is L The data from the RxDk pin is retrieved and the contents of the re ceive register is shifted by 1 bit each time when the transmission clock CLKj changes from L to H When an 8 bit data is received the contents of the receive register is transferred to the receive buffer register and bit 3 RIk flag of UARTk Transmit Receive control reg ister 1 is set to 1 In other words the setting 1 to the RIk flag indi cates that the receive buffer register contains the received data When the RIk flag changes from 0 to 1 the interrupt request bit in the UARTK receive interrupt control register is set to 1 Bit 4 OERk flag of UARTk Transmit Receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while RIk flag is 1 and indicates that the next d
23. MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP rd M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER ADDRESSING MODES AND INSTRUCTION SET The M37754M8C XXXGP and M37754M8C XXXHP have 29 pow erful addressing modes 1 addressing mode is added to the basis of the 7700 series Refer to the 7751 Series Software Manual for the details INSTRUCTION SET The M37754M8C XXXGP and M37754M8C XXXHP have the ex tended instruction set 6 instructions are added to the instruction set of 7700 series The object code of this extended instruction set is upwards compatible to that of 7700 series instruction set Refer to the 7751 Series Software Manual for the details SHORTENING NUMBER OF INSTRUCTION EXECUTION CYCLES Shortening number of instruction execution cycles is realized in the M37754M8C XXXGP and M37754M8C XXXHP owing to modifica tions of the instruction execution algorithm and the CPU circuit and others Refer to the 7751 Series Software Manual about the number of in struction execution cycles DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders lt M37754M8C XXXGP gt 1 M37754M8C XXXGP mask ROM order confirmation form 2 100P6S mark specification form 3 ROM data EPROM 8 sets lt M37754M8C XXXHP gt 1 M37754M8C XXXHP mask ROM order confirmation form 2 100P6Q mark specification form 8 ROM data EPROM 3 sets MITSUBISHI ELECTRIC i MIT
24. Outputs H when standby state select bit 1 is 1 and standby state select bit 0 is 0 Outputs ALE Outputs L when multiplex bus select bit 0 Outputs ALE when multiplex bus select bit v Microprocessor mode Note All functions of signal output disable select bit cannot be debugged using an debugger Outputs clock 1 regardless of 1 output select bit Outputs contents of port P42 latch necessary to set its direction register bit to 1 70 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER PROCESSOR MODE Bits 0 and 1 of processor mode register 0 address 5E16 shown in Figure 84 are used to select any mode of the single chip mode the memory expansion mode and the microprocessor mode Ports PO to P3 P10 P11 and a part of port P4 are used as I O pins of address data and control signals in the modes except the single chip mode Figure 85 shows the functions of ports PO to P4 P10 and P11 in each mode The external memory area depends on the mode Figure 86 shows the memory map for each mode Refer to Figure 1 for the addresses of RAM and ROM in the single chip mode The external memory area can be accessed in the modes except the single chip mode The access to the external memory is affected by the BYTE pin BYTE pin When accessing the external memory the level
25. x x Not used in timer mode and may be any Not used in timer mode Clock source select bit 0 0 Select Pf2 0 1 Select Pf16 1 0 Select Pfe4 1 1 Select Pfs12 Fig 36 Timer Bi mode register bit configuration during timer mode Addresses Timer BO mode register 5B16 Timer B1 mode register 5C16 Timer B2 mode register 5D16 0 1 Always 01 in event counter mode 0 0 Count at the falling edge of input signal Count at the rising edge of input signal Count at the both falling edge and rising edge of input signal Not used in event counter mode Fig 37 Timer Bi mode register bit configuration during event counter mode Addresses Timer BO mode register 5B16 Timer B1 mode register 5C16 Timer B2 mode register 5D16 10 Always 10 in pulse period measurement pulse width measurement mode 0 0 Count from the falling edge of input signal to the next falling one 0 1 Count from the rising edge of input signal to the next rising one 1 0 Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one Timer Bi overflow flag Clock source select bit 00 Select Pf2 0 1 Select Pf16 1 0 Select Pfe4 1 1 Select Pf512 Fig 38 Timer Bi mode register bit configuration during pulse period measurement pulse width meas
26. 0 in one shot pulse mode Clock source select 0 0 Select Pf2 0 1 Select Pf16 1 0 Select Pfe4 1 1 Select Pf512 Fig 28 Timer Ai mode register bit configuration during one shot pulse mode Address One shot start register 4216 76543210 Timer A0 one shot start bit Timer A1 one shot start bit Timer A2 one shot start bit Timer A3 one shot start bit Timer A4 one shot start bit Fig 29 One shot start register bit configuration MITSUBISHI 35 ELECTRIC MITSUBISHI MICROCOMPUTERS gO nano M37754M8C XXXGP M37754M8C XXXHP ri M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selected clock source Pfi TAiIN rising edge TAiOUT Example when the contents of the reload register is 000316 Fig 30 Pulse output example when external rising edge is selected Selected clock source Pfi TAiIN rising edge TAioUT Example when the contents of the reload register is 000416 Fig 31 Example when trigger is re issued during pulse output 30 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 Pulse width modulation mode 11 Figure 32 shows the bit configuration of the timer Ai mode register during pulse width modulation mode In pulse width modulation mode bits 0 1 and 2 must be set to 1 Bit 5 is used t
27. 16 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS MT M37754M8C XXXGP M37754M8C XXXHP oa Ng s M37754SACGP M37754SACHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Processor mode register 1 5F16 These bits must be 00 Clock source for peripheral devices select bit Note 0 1 2 1 01 CPU running speed select bit 0 High speed running 1 Low speed running Bus cycle select bits In high speed running 00 5 0 access in high speed running 01 4 6 access in high speed running 10 3 6 access in high speed running 11 Do not select In low speed running 00 Do not select 01 4 6 access in low speed running 10 3 6 access in low speed running 11 2 6 access in low speed running Clock source select bit 0 ot f XIN 2 1 01 f XIN This bit must be 0 Note When 01 gt 12 5 MHz set bit 2 to 0 Fig 9 Processor mode register 1 bit configuration MITSUBISHI i ELECTRIC f pee X ae aaiae M37754S4CGP M37754SACHP yote aem dl SINGLE CHIP 16 BIT CMOS MICROCOMPUTER INTERRUPTS Table 2 Interrupt types and the interrupt vector addresses Table 2 shows the interrupt types and the corresponding interrupt vector addresses Reset is also treated as a type of interrupt and is discussed in this section too DBC is an interrupt used during debugging Interrupts other than reset DBC watchdog timer zero divide and BRK instruction all have interrupt cont
28. 3016 Timer AO interrup rol register 7516 UART 1 Transmit Receive mode register 3816 Timer A1 interrup rol register 7616 UART 0 Transmit Receive control register 344e Timer A2 interrup rol register 7716 UART 1 Transmit Receive control register 3Ct6 Timer A3 interrup rol register 7816 UART 0 Transmit Receive control register 1 3516 Timer A4 interrup rol register 7916 UART 1 Transmit Receive control register 1 3D16 Timer BO interrup rol register 7A16 Count start register 4016 Timer B1 interrup rol register 7B16 One shot start register 4216 Timer B2 interrup rol register 7C16 Up down register 4416 INTo interrupt control register 7D16 Timer A write register 4516 INT1 interrupt control register 7E16 Timer AO mode register 5616 INT interrupt control register 7F16 010 Timer A1 mode regis 5716 Processor status register PS 0 0 0 7 070 Timer A2 mode regis 5816 Program bank register PG 0016 Timer A3 mode regis 5916 Program counter PCH Contents of FFFF16 Timer A4 mode regis 5At6 Program counter PCL Contents of FFFE16 Timer BO mode regis bB 6
29. Address Chip select area register 6316 Chip select area switch bits Notes 1 2 000 CS0 00100016 to O2FFFF16 188 Kbytes CS1 03000016 to O4FFFF16 128 Kbytes CS2 05000016 to O6FFFF16 128 Kbytes CSs 00088016 to 000DFF16 C84 1408 bytes CS4 000E0016 to OOOFFF16 512 bytes 00800016 to O2FFFF16 160 Kbytes 03000016 to O4FFFF16 128 Kbytes 05000016 to O6FFFF16 128 Kbytes 00088016 to 000FFF16 1920 bytes 00100016 to 007FFF16 28 Kbytes 00100016 to O2FFFF16 188 Kbytes 03000016 to O4FFFF16 128 Kbytes 05000016 to O6FFFF16 128 Kbytes 07000016 to 077FFF16 32 Kbytes 07800016 to O7FFFF16 32 Kbytes 00800016 to O2FFFF16 160 Kbytes 1 03000016 to O4FFFF16 128 Kbytes 2 05000016 to O6FFFF16 128 Kbytes 07000016 to 077FFF16 32 Kbytes 07800016 to O7FFFF16 32 Kbytes 0 00088016 to O2FFFF16 190 Kbytes 1 03000016 to O4FFFF16 128 Kbytes 2 05000016 to O6FFFF16 128 Kbytes 3 08000016 to 3FFFFF16 3 5 Mbytes S4 07000016 to O7FFFF16 64 Kbytes 0 00088016 to O2FFFF16 190 Kbytes 1 03000016 to O4FFFF16 128 Kbytes 05000016 to OGFFFF16 128 Kbytes 64 Kbytes 7 5 Mbytes 446 Kbytes CS2 Not available CS3 08000016 to 3FFFFF16 3 5 Mbytes CS4 07000016 to 07FFFF16 64 Kbytes CSo 00088016 to O6FFFF16 446 Kbytes CS1 CS2 Not available CS3 07000016 to 07FFFF16 64 Kbytes CS4 08000016 to 7FFFFF16 7 5 Mbytes Multiplex bus select bit Note 1
30. Functions of other pins are the same as in single chip mode In memory expansion mode P42 can be programmed as I O port P50 P57 I O port P5 In addition to having the same functions as port PO in single chip mode these pins also function as I O pins for timer AO timer A1 timer A2 timer A3 output pins for motor drive waveform and input pins for key input interrupt P60 P67 I O port P6 In addition to having the same functions as port PO in single chip mode these pins also function as I O pins for timer A4 input pins for external interrupt input INTO INT1 and INT2 and input pins for timer BO timer B1 and timer B2 P70 P77 I O port P7 In addition to having the same functions as port PO in single chip mode these pins also function as input pins for A D converter P80 P87 I O port P8 In addition to having the same functions as port PO in single chip mode these pins also function as I O pins for UARTO UART1 output pins for D A converter and input pin for INT4 P90 P95 I O port P9 In addition to having the same functions as port PO in single chip mode these pins also function as input pin for INT3 output pins for motor drive waveform In memory expansion mode and microprocessor mode these pins can be programmed as address A20 A22 or output pins for CSo CS4 Note It is impossible to change the input level of the BYTE pin in each bus cycle In other words bus width ca
31. The width of L level can be also modified by changing the value of timer B2 or timer A2 V W phase waveform and V W phase waveform having their negative phase are similarly output according to the correspond ing timer operation The explanation above is an example of three phase waveform generating due to an triangular wave modulation Three phase waveform due to a saw tooth wave modulation can also be gen erated by fixing each beginning level of phases U phase waveform output Fig 45 U phase waveform output example in three phase mode 0 triangular wave modulation MITSUBISHI ELECTRIC 39 y e SM grand 1 SPES Sec eo MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Three phase mode 1 In selecting three phase waveform mode three phase mode 1 is selected by setting bit 4 of the waveform output mode register ad dress 1A16 to 1 In this mode each of timers AO to A2 can have two timer registers and the contents of those registers are alternately reloaded into the counter each time the counter of timer B2 becomes 000016 About write operation to two timer registers when rewriting to each timer register of timers AO A1 and A2 after writing to each timer register of them the data is written each to timers A01 A11 and A21 When writ ing to each timer register the timer A write register in Figure 46 in dicates
32. o Output t 4 Fig 78 Block diagram for ports P0 to P11 in single chip mode and E output 1 64 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS ie yang M37754M8C XXXGP M37754M8C XXXHP I get Ao cate M37754S4CGP M37754S4CHP woe or gon SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pull up select Port P55 P57 P95 Direction register Data bus Port latch Port P80 Inside dotted line not included Port P84 Inside dotted line included Direction register 1 Data bus Port latch CTSi lt hor l p Analog output o 6 Enable D A output Port P81 P85 Data bus Port latch Hold acknowledge Fig 79 Block diagram for ports PO to P11 in single chip mode and E output 2 MITSUBISHI ds ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The clock generating circuit makes basic clocks which activate the central processing unit CPU bus interface unit BIU and internal peripheral devices of an oscillation circuit output Figure 82 shows the block diagram of the clock generating circuit The clock source 6 1 to activate internal peripheral devices the clock Source BIU to activate the bus interface unit and the clock source CPU to activa
33. sharing one reload register The dead time timer oper ates as a one shot timer As its start trigger both the rising and falling edges of timers AO to A2 s one shot pulses or their falling edge Bit 6 of the waveform output mode register selects it When that is 0 both the rising and falling edges become the start trigger when that is 1 the falling edge becomes it Address TETTE Waveform output mode register 1A16 Waveform output select bits 100 Fix to 100 in three phase waveform mode Valid in three phase mode 1 Three phase output polarity set buffer 0 H output 1 L output Three phase mode select bit 0 Three phase mode 0 1 Three phase mode 1 Not used in three phase waveform mode Dead time timer trigger select bit 0 Both edge of one shot pulse with timers A2 to AO 1 Only the falling edge of one shot pulse with timers A2 to AO Waveform output control bit 0 Waveform output disabled 1 Waveform output enabled Note Only when bit 5 of the particular function select register 1 in Fig 15 is set to 1 this register s contents can be changed from the status during reset in Fig 76 Fig 41 Waveform output mode register bit configuration Address Timer AO mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Fix to 10 in three phase waveform mode Fix to 1 in timers AO A1 in timer A2 0 No one shot puls
34. th WR CS th WR DLQ DHQ tpxz WR DLZ DHZ th WR DLQ td WR PiQ Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VOH 2 0 V CL 100 pF MITSUBISHI ELECTRIC 95 coNO ane odi Is qe se NT e s of MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER when 3 access in low speed running lt Read gt f XIN 1 ALE output HE output A0 A7 output A8 4A15 output A16 4A923 output CS0 CS4 output Do D7 input D8 D15 input BYTE L LAo LA7 output Do LAo D7 LA7 multiplex bus Note Do D7 input multiplex bus Note Port Pi input BYTE H Multiplex bus select bit 1 tw H tw L tr tf tc tw ALE td BHE RD td BHE ALE td A RD td A ALE td CS RD Ape ag ce I td p1 RD td ALE RD th RD A C G o 9 th RD CS th RD DL DH tsu DL RD th RD DL While the address which corresponds to chip select signal CS4 is accessed Test conditions Port Pi f XIN Test conditions except Port Pi f XIN VcC 5 V 10 Output timing voltage VOL 0 8 V VOH 2 0 V CL 100 pF Data input VIL 0 8 V VIH 2 5 V Vcc 5 V 10 96 tsu PiD RD Data yp
35. the CLKi pin can be used as a normal I O pin The selected internal or external clock is divided by n 1 then by 16 and is passed through a control circuit to create the UART trans mission clock or UART receive clock Therefore the transmission speed can be changed by changing the contents n of the bit rate generator If the selected clock is an inter nal clock Pfi or an external clock fEXT Bit Rate Pfi or fEXT n 1 x16 Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits in the data and parity bit is always odd In the even parity mode the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even Bit 6 is the parity bit select bit which indicates whether to add parity bit or not Bits 4 to 6 must be set or reset according to the data format used in the communicating devices Bit 7 is the sleep select bit The sleep mode is described later The UARTi Transmit Receive control register 0 bit 2 is used to deter mine whether to use CTSi input or RTSi output CTSi input is used if bit 2 is 0 and RTSi output is used if bit 2 is 1 If CTSi input is selected the user can control whether to stop or start transmission by external CTSi input Bit 4 of the UART Transmit Receive control register 0 is used to de termine whether to use CTS or RTS signal Bit 4 must be 0 when CTS or RTS signal is used Bit 4 must be 1 when CTS or RTS sig nal is not us
36. 2 212 5 MHz 8 bit mode t Absolute accuracy VREF VCC Comparator 40 250 kHz lt D lt 8 bit mode 3 20 MHz Note 1 Comparator 60 RLADDER Ladder resistance VREF VCC 20 f XIN 4 10 bit mode AD f XIN High speed selected 8 bit mode running Comparator f XIN lt 40 MHz Conversion time prn AD f XIN 2 8 bit mode Note 2 selected Comparator 10 bit mode Low speed running 8 bit mod f XIN lt 25 MHz Note 2 oce Parameter Test conditions Resolution VREF VCC Comparator Reference voltage Analog input voltage Notes 1 This is valid when the high speed running is selected 2 When the clock source select bit 1 f XIN is 20 MHz or less at the high speed running and f XIN is 12 5 MHz or less at the low speed running D A CONVERTER CHARACTERISTICS Vcc 5 V Vss AVss 0 V VREF 5 V Ta 20 to 85 C unless otherwise noted Limits Typ Parameter Test conditions Resolution Absolute accuracy Set time Output resistance Reference power supply input current Note The test conditions are as follows One D A converter is used The D A register value of the unused D A converter is 0016 The reference power supply input current of the ladder resistance of the A D converter is excluded 82 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS aio gn M3
37. 2 or 4 digit decimal Arithmetic operation is performed using four digits when the data length flag m is 0 and with two digits when it is 1 Decimal adjust is automatically per formed Decimal operation is possible only with the ADC and SBC instructions This flag can be set and reset with the SEP and CLP instructions 10 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 5 Index register length flag x The index register length flag determines whether index register X and index register Y are used as 16 bit registers or as 8 bit registers The registers are used as 16 bit registers when flag x is O and as 8 bit registers when it is 1 This flag can be set and reset with the SEP and CLP instructions 6 Data length flag m The data length flag determines whether the data length is 16 bit or 8 bit The data length is 16 bit when flag m is 0 and 8 bit when it is 1 This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions 7 Overflow flag V The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number If data length flag m is 0 the overflow flag is set when the result of addition or subtrac tion is outside the range between 32768 and 32767 If data length flag m is 1 the overflow f
38. 2048 counts the most significant bit of o Pft watchdog timer becomes 0 the watchdog timer interrupt request STP return select bit bit is set to 1 and FFF46 is set again in the watchdog timer Normally a program is written so that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes 0 If this routine is not executed owing to unexpected program ex ecution and others the most significant bit of the watchdog timer becomes 0 and an interrupt is generated Address 6016 Hold request Wachdog timer A Set FFF16 Watchdog timer clock select bit Write to watchdog timer Fig 74 Watchdog timer block diagram The microcomputer can be reset by writing 1 to bit 3 software re Address s Watchdog timer frequency 6116 set bit of processor mode register 0 in the interrupt routine de select register scribed in Figure 16 in the interrupt section and generating a reset pulse 0 Wf512 or Pf512 selected The watchdog timer stops its function when the RESET pin voltage 1 Wf32 or Pf32 selected is raised to double the Vcc voltage The watchdog timer can also be used to return from when the clock is stopped by the STP instruction Refer to the section on the clock generating circuit for more details Fig 75 Watchdog timer frequency select register bit configuration The watchdog timer also becomes
39. ALE output delay time td ALE RD ALE output delay time tw ALE ALE pulse width th WR A Address hold time th RD A Address hold time td WR BHE BHE hold time td RD BHE BHE hold time td WR CS Chip select hold time td RD CS Chip select hold time th WR DLQ DHQ Data hold time tpzx WR DLZ DHZ Floating release delay time f XIN lt 20 MHz when the clock source select bit 1 xk XIN 20 MHz when the clock source select bit 1 108 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS ME M37754M8C XXXGP M37754M8C XXXHP visa sil M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER External bus timing on internal RAM access 2 access in high speed running tw H tw L tr t tc tw H tw L tr tf tc inr 3L EIE Esto af 2 01 RD WR tw WR tw ALE td ALE WR tw ALE td ALE RD ME cr ALE output td BHE WR th WR BHE td BHE RD th RD BHE BHE output td BHE ALE td BHE ALE E aS ta A WR th wR A LL UA RD th RD A Ao A7 output A8 4A15 output Address Address A16 A23 output td A ALE td A ALE td CS WR th wR CS td CS RD thiRD cs CSo CS4 output td CS ALE td CS ALE td WR DLQ DHQ LOWE DEEN Do D7 output A cates EEA LYX Data S ples astana eA cct seb Int E eiu Ds D15 output BYTE
40. Always 1 in pulse width modulation mode Software trigger Trigger at the falling of TAiIN input 1 Trigger at the rising of TAilN input 0 16 bit pulse width modulator 1 8 bit pulse width modulator Clock source select bit 00 Select Pf2 0 1 Select Pf16 1 0 Select Pf64 1 1 Select Pfs12 Fig 32 Timer Ai mode register bit configuration during pulse width modulation mode MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS aio sant M37754M8C XXXGP M37754M8C XXXHP pete g 10 9 ac M37754S4CG P M37754S4CHP noice vae ail SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Therefore if the low order 8 bits of the reload register are n the pe high order 8 bits of the reload register are m the duration H of pulse riod of the generated pulse is is n1 x m 1 x n1 selected clock frequency selected clock frequency The high order 8 bits function as an 8 bit length pulse width modula And the output pulse period is tor using this pulse as input The operation is the same as for 16 bit x n 1 x 28 1 length pulse width modulator except that the length is 8 bits If the Selected clock frequency 1 Pfi x 216 1 Selected clock source Pfi TAiIN rising edge Example when the contents of the reload register is 000316 Fig 33 16 bit length pulse width modulator output pulse example 1 Pfi x n 1 x 28 1 Selected clock Ud source Pfi Lud TAiIN falling
41. Hold state during Hold state and the clock input to it is stopped This bit must be fixed to 0 MITSUBISHI ELECTRIC 81 foot quon je T ale gue MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER RESET CIRCUIT Reset is released when the RESET pin is returned to H level after holding it at L level while the supply voltage is at 5V 10 As the result program execution starts at the address formed by setting the address A23 A16 to 0016 Ai5 As to the contents of address FFFF 16 and A7 A0 to the contents of address FFFE16 Figure 76 shows the status of the internal registers during reset Figure 77 shows an example of a reset circuit When a stabilized clock is input from the external to the oscillation circuit the reset in put voltage must be held 0 9V or lower when the supply voltage reaches 4 5V When connecting a resonator to the oscillation circuit return the reset input voltage from L to H after the main clock os cillation is fully stabilized Power on a 4 5V Fig 77 Reset circuit example perform careful evaluation at system design before using INPUT OUTPUT PINS Ports PO to P11 all have the direction register and each bit can be programmed for input or output A pin becomes an output pin when the corresponding bit of direction register is 1 and an input pin when it is O
42. LAo D7 LA7 multiplex bus Note Do D7 input tsu LA DL multiplex bus Note tsu PiD RD Port Pi input Input data Note These become a multiplex bus only when all of the following conditions are satisfied BYTE H Multiplex bus select bit 1 While the address which corresponds to chip select signal CS4 is accessed Test conditions Port Pi f XIN Vcc 5 V 10 Test conditions except Port Pi f XIN Vcc 5 V 10 Output timing voltage VOL 0 8 V VOH 2 0 V CL 100 pF Data input VIL 0 8 V VIH 2 5 V MITSUBISHI ELECTRIC tpzx RD DLZ th RD DL Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VOH 2 0 V CL 100 pF 103 MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER f XIN 1 ALE output BHE output Ao A7 output A8 A15 output A16 A23 output CS0 CS4 output Do D7 output Ds D15 output BYTE L Do LAo D7 LA7 output multiplex bus Note Port Pi output BYTE H tw ALE l td p1 WR m td o1 WR td BHE WR td ALE WR m td BHE ALE gt td A WR th WR A rs m j td A ALE td CS ALE gt 7 NN JL Output data NN c tpzx WR DLZ DHZ th WR DLQ DHQ E a
43. M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 Repeat mode Repeat mode is selected when bit 3 of A D control register 0 is 1 bit 4 is 0 and bit 2 of A D control register 1 is 0 The operation of this mode is the same as the operation of one shot mode except that when A D conversion of the selected pin is com plete and the result is stored in the A D register conversion does not Stop but is repeated No interrupt request is generated in this mode Furthermore if soft ware trigger is selected the A D conversion start bit is not cleared The contents of the A D register can be read at any time Be sure not to write to the A D register corresponding to the pins se lected for a comparator during operation 3 Single sweep mode Single sweep mode is selected when bit 3 of A D control register 0 is 0 bit 4 is 1 and bit 2 of A D control register 1 is 0 In the single sweep mode the number of analog input pins to be Swept can be selected Analog input pins are selected by bits 1 and 0 of the A D control register 1 address 1F16 Two pins four pins Six pins or eight pins can be selected as analog input pins depend ing on the contents of these bits A D conversion is performed only for selected input pins After A D conversion is performed for input of ANo pin the conversion result is stored in A D register 0 and in the same way A D conversion is performed for selected pins o
44. O RTP03 O RTP02 DD O RTP01 Pulse output data register 0 O RTP00 L3 P L Waveform output control bit 0 Polarity select bit Pe Reset gt o Note Only when bit 5 of the particular function select register 1 in Fig 15 is set to 1 the following registers contents can be changed from the status after reset in Fig 76 Waveform output mode register address 1416 and Pulse output data registers 0 and 1 addresses 1C16 1D16 Fig 48 Pulse output port mode block diagram MITSUBISHI 42 ELECTRIC MITSUBISHI MICROCOMPUTERS pn M37754M8C XXXGP M37754M8C XXXHP MIL M37754S4CGP M37754S4CHP a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Waveform output mode register 1A16 Waveform output select bits 000 Parallel port 001 RTP1 selected Valid in pulse mode 0 010 RTPO selected Valid in pulse mode 0 011 In pulse mode 0 RTP1 and RTPO selected In pulse mode 1 RTP1 RTPO3 RTPO2 RTPO1 RTP00 selected Polarity select bit Valid for RTPO in pulse mode 0 0 Positive polarity 1 Negative polarity Pulse width modulation select bit 0 Valid for RTP1 in pulse mode 0 Valid for RTP1 RTP03 RTPO2 in pulse mode 1 0 No modulation by timer A2 1 Modulation by timer A2 Pulse width modulation select bit 1 Valid in pulse mode 1 0 Modulation by timer A2 1 Modulation for RTP03 RT
45. Odd parity 1 Even parity Parity enable select bit 0 No parity 1 With parity Sleep select bit 0 No sleep 1 Sleep Fig 55 UARTi Transmit Receive mode register bit configuration 46 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP eoe XX E kaiga NS M37754S4CG P M37754S4CH P pore same gp SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Data bus odd Data bus even d Bit Converter Receive buffer register D7 D6 D4 D3 D2 Di Do 8bit 9bit 2 stop bit 7bit 9 bit Synchronous 8bit Stop Iu Stop 9bit a bit bit i EO 1 stop bit parity 7bit Receive register 8bit Synchronous Synchronous Fig 56 Receiver block diagram Data bus odd Data bus even Transmit buffer register D7 De D2 D1 Do 8bit 9bit 7bit Synchronous 8bit 9bit 5 04 8 bit 7 bit Transmit register 1 stop bit Synchronous Fig 57 Transmitter block diagram Addresses UART 0 Transmit Receive control register 0 3416 UART 1 Transmit Receive control register O 3C16 BRG count source select bit 00 Select Pf2 0 1 Select Pf16 1 0 Select Pfe4 1 1 Select
46. Pf512 CTS RTS select bit 0 Select CTS 1 Select RTS Transmit register empty bit CTS RTS enable bit 0 Enable CTS RTS 1 Disable CTS RTS Input Output port Transfer format select bit Note 0 LSB first 1 MSB first Note This bit is valid in clock synchronous mode Fix this bit to 0 in UART mode Addresses UART 0 Transmit Receive control register 1 3516 UART 1 Transmit Receive control register 1 3D16 Transmit enable flag Transmit buffer empty flag Receive enable flag Receive complete flag Overrun error flag Framing error flag Parity error flag Error sum flag Fig 58 UARTi Transmit Receive control register bit configuration MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CLOCK SYNCHRONOUS SERIAL COMMUNI CATION A case where communication is performed between two clock syn chronous serial I O ports as shown in Figure 59 will be described The transmission side will be denoted by subscript j and the receiv ing side will be denoted by subscript k Bit 0 of the UARTj Transmit Receive mode register and UARTk Transmit Receive mode register must be set to 1 and bits 1 and 2 must be 0 The length of the transmission data is fixed at 8 bits Bit 3 of the UARTj Transmit Receive mode register of the clock send ing s
47. The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi type 6 3 Customer s Parts Number can be up to 14 characters Only 0 HEH BEHEEHEEHEHEHHE 9 A Z amp periods commas are usable 4 If the Mitsubishi logo A is not required check the box below Mitsubishi logo is not required RRRERERRRRSRSRRERERE m C Special Mark Required Note1 If the Special Mark is to be Printed indicate the desired 6 layout of the mark in the left figure The layout will be i duplicated as close as possible ES Mitsubishi lot number 6 digit or 7 digit and Mask ROM ES number 3 digit are always marked ES 2 If the customer s trade mark logo must be used in the Special Mark check the box below Please submit a clean original of the logo For the new special character fonts a clean font original ideally logo drawing must be submitted AAARHRRARRRARRRRRRRR Special logo required MITSUBISHI ELECTRIC 100P6Q 100 PIN LQFP MARK SPECIFICATION FORM Please choose one of the marking types below A B C and enter the Mitsubishi catalog name and the special mark if needed A Standard Mitsubishi Mark amp HHMH amp A amp E Mitsubishi IC catalog name HWHU Mitsubishi IC cat
48. and performs two phase pulse signal processing when it is 1 Count is started by setting the count start bit to 1 Data write and read are performed in the same way as for normal event counter mode Note that the direction register of the input port must be set to input mode because two kinds of pulse signals described above are input Also there can be no pulse output in this mode Addresses Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 0 1 Always 01 in event counter mode 0100 Always 0100 when processing two phase pulse signal x x Not used in event counter mode Fig 27 Timer Aj mode register bit configuration when performing two phase pulse signal processing in event counter mode Decrement count Fig 25 Two phase pulse processing operation of timers A2 and timer A3 TA40UT Increment count at each edge Decrement count at each edge PURPLE 11111 Increment count at each edge Decrement count at each edge Fig 26 Two phase pulse processing operation of timer A4 28 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 3 One shot pulse mode 10 Figure 28 shows the bit configuration of the timer Ai mode register during one shot pulse mode In one shot
49. are not affected by the interrupt dis able flag l When an interrupt is accepted the contents of the processor status register PS is saved to the stack and the interrupt disable flag is set to 1 Furthermore the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level IPL in the processor status register PS is replaced by the priority level of the accepted interrupt Therefore multi level priority interrupts are possible by resetting the interrupt disable flag to 0 and enable further interrupts For reset DBC watchdog timer zero divide and BRK instruction in terrupts which do not have an interrupt control register the proces Sor interrupt level IPL is set as shown in Table 4 The interrupt request bit and the interrupt priority level of each inter rupt source are sampled and latched at each operation code fetch cycle while BIU is H However no sampling pulse is generated until the cycles whose number is selected by software has passed even if the next operation code fetch cycle is generated The detec tion of an interrupt which has the highest priority is performed during that time Priority is determined by hardware 4 3 2 1 E timer l A D converter UART etc interrupts Priority can be changed with software inside 4 Fig 11 Interrupt priority Watchdog timer Interrupt disable flag N
50. bit Timer BO count start bit Timer B1 count start bit Timer B2 count start bit Fig 19 Count start flag bit configuration Selected clock source Pfi HLT HULL HL HLT i HI Timer mode register Bit 4 Bit 3 UT II Timer mode register Bit 4 Bit 3 LULL HLT LUE Fig 20 Count waveform when gate function is available MITSUBISHI x ELECTRIC MITSUBISHI MICROCOMPUTERS 10 ane M37754M8C XXXGP M37754M8C XXXHP MC d M37754S4CGP M37754S4CHP ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FFFF16 Count start Count stop Overflow q g Input level to Valid leve ooo TAIIN pin Invalid leve TAi interrupt request bit l l Count start flag I i Cleared by accepting the interrupt request or by software Fig 21 Timer operation example with gate function 0 no reload selected FFFF16 Count start Reloaded eloaded uration Count stop Overflow 4 g Input level to Valid level TAilN pin Invalid level TAi interrupt request bit Count start flag Cleared by accepting the interrupt request or by software Fig 22 Timer operation example with gate function 1 reload selected 26 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 Event counter mode 01 Fi
51. can be output to a maximum of 3 external re ceive devices This is realized under the condition in which the inter nal clock is selected and the transmission clock is output from one of pins CLKo CLKSo multiplexed with RxDo and CLKS1 multiplexed with CTSo RTSo Make sure that do not switch the selection of the clock during transmission Figure 61 shows an external connection example Plural output of transmit clock mode is set with bits 1 and 0 of the particular function select register 1 Additionally it is necessary to se lect the internal clock disable CTS and RTS receive and D A output with the UARTO Transmit Receive mode register UARTO Transmit Receive control registers 0 and 1 and A D control register 1 Figure 62 shows the other registers bit configuration in plural output of trans mit clock mode and Figure 63 shows the particular function select register 1 bit configuration Table 6 shows the function of the particular function select register 1 s bits 1 and 0 which is the output pin of transmit clock select bits TC1 and TCo According to this table select the CLKo CLKSo or CLKS1 pin corresponding to the contents of TC1 and TCo and out put the transmit clock Transmission clock UUUU UU UU UU UU UU LE HEUTE LI UUU UU UU UU TEj Tlj Write in transmit buffer register CTSj lt 1 Pfi x n 1 x 2 CLKj Transmit register Transmit buffer register Stopped because TEj 0 TENDj _ 0 c 77 q
52. circuit block diagram 67 EA MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS des an M37754M8C XXXGP M37754M8C XXXHP CV enden M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Particular function select register 0 6C16 This bit must be fixed to 0 External clock input select bit Notes 1 2 0 Actuated oscillation circuit connecting resonator 1 Stopped oscillation circuit inputting externaly genarated clock Memory allocation select bit Note 2 0 ROM 60 Kbytes RAM 2048 Bytes ROM 00100016 to 00FFFF46 RAM 00008016 to 00087F 6 1 ROM 56 Kbytes RAM 2048 Bytes ROM 00200016 to 00FFFF46 RAM 00008016 to 00087F 6 Standby state select bit 0 Notes 1 3 in execution of WIT or STP instruction in memory expansion or microprocessor mode 0 External bus for PO to P3 P10 P11 1 Port Input Output for PO to P3 P10 P11 Standby state select bit 1 Notes 1 4 in execution of WIT or STP instruction 0 H or L output for pins E RD WR 1 H output for pins E RD WR STP rerurn select bit 0 Wachdog timer is used when returning from Stop mode 1 Wachdog timer is not used when returning from Stop mode the maicrocomputer returns at once After the expansion function select bit bit 5 of particular function select register 1 Figure 62 is 1 bits 1 5 and 6 can be written and changed To set bits 1 and 2 continuous tw
53. function select bit Fig 69 Comparator function select register bit configuration Address Comparator result register 6616 0 ANi input level is lower than set digital value 1 ANI input level is higher than set digital value ANo pin comparator result bit AN pin comparator result bit AN pin comparator result bit ANG pin comparator result bit AN4 pin comparator result bit AN5 pin comparator result bit AN6 pin comparator result bit AN7 pin comparator result bit Note Do not access with the SEB or CLB instruction Fig 70 Comparator result register bit configuration MITSUBISHI a ELECTRIC co and sco no eNO 10 ane se Ed s OC o 9 VS NR qwe m Ace e ow yet e MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Operation mode The operation mode is selected by bits 3 and 4 of A D control regis ter 0 and bit 2 of A D control register 1 The available operation modes are one shot repeat single sweep repeat sweep 0 and re peat sweep 1 Either an A D converter or a comparator can be se lected respectively for every pin in the following 5 modes The following description applies to the case where the bit of the com parator function select register is 0 and an A D converter is se lected It also applies to a comparator s operatio
54. in the micro processor mode Similarly when accessing the internal memory in the memory expansion and microprocessor modes RD and WR output can be fixed to H Refer to Table 8 for details MITSUBISHI 72 ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Processor modes are explained bellow Memory expansion Microprocessor mode mode 216 to 916 1616 to 1916 8016 FFFFFFi6 The shaded area is the external memory area Fig 86 External memory area for each mode 1 Single chip mode 00 The microcomputer enters the single chip mode by connecting the CNVss pin to Vss and starting from reset Ports PO to P4 P10 and P11 all function as normal I O ports Port P42 can output clock Source 6 1 by setting bit 7 of the processor mode register 0 to 1 In this mode enable signal E is output from pin E RD Signal E out put can be stopped by setting the signal output disable select bit bit 4 of particular function select register 1 to 1 and it is possible to switch the output to L level Table 8 shows the function of the signal output disable select bit s function 2 Memory expansion mode 01 The microcomputer enters the memory expansion mode by setting the processor mode bits to 01 after connecting the CNVss pin to Vss and starting from reset Pin E RD becomes the RD output pin RD is an read signal
55. is stabilized Even though clocks are input from the external make sure to clear the STP return select bit to 0 if the external clock is unstable for a short time when returning from STP state Operation at WIT STP state Instruction Slop bita yI Oscillation circuit 9 Pf2 to Pf512 Internal peripheral devices using Pf2 to Pf512 Wf32 W512 Wie Wf512 BIU CPU Operating Note 1 Operating Operating Operation enabled Watchdog timer operating Operating Note 2 Operation disabled Operating Stopped Note 1 H Stopped H i Watchdog timer stopped Notes 1 When the clock external input select bit is 1 the clock oscillation circuit stops An external clock can be input 2 When the watchdog timer clock select bit is 1 Wf32 and Wf512 stop The watchdog timer operates with Pf32 or Pf512 Watchdog timer stopped Operation disabled Stopped MITSUBISHI ELECTRIC en MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Bus cycle in WIT STP When the WIT STP instruction is executed with the standby state se lect bit 1 bit 6 of particular function select register 0 0 the clock Sources BIU and CPU or oscillation stop without waiting for completion of the bus cycle being executed Accordingly the micro computer may enter WIT STP sta
56. mA or less the sum of lOL peak for ports P4 P5 P6 P7 and P9 must be 110 mA or less the sum of lOH peak for ports P4 P5 P6 P7 and P9 must be 80 mA or less 3 When the clock source select bit is 1 f XIN s maximum limit is 12 5 MHz at low speed running and is 20 MHz at high speed running MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS AiO san M37754M8C XXXGP M37754M8C XXXHP ew ec xO aaa e ses M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS vcc 5 V Vss 0 V Ta 20 to 85 C f XIN 40 MHz Note n Limits Parameter Test conditions Typ High level output voltage PO00 P07 P10 P17 P20 P23 P27 P31 P33 P40 P47 P50 P57 P60 P67 P70 P77 loH 10 mA P80 P87 P90 P92 P95 P100 P107 P110 P117 High level output voltage PO00 P07 P10 P17 P20 P23 P27 P31 P33 P90 P92 loH 400 uA P100 P107 P110 P117 High level output voltage E P30 P32 loH 10 mA loH 400 uA High level output voltage P93 P94 loH 15 mA IOH 600 uA Low level output voltage P0o P07 P1o P17 P20 P23 P27 P31 P33 P40 P47 P54 P5r P60 P67 P70 P77 lol 10 mA P80 P87 P90 P95 P100 P107 P110 P117 Low level output voltage P0o P07 P10 P17 P20 P23 P27 P31 P33 P90 IOL 2 mA P100 P107 P110 P117 Low level output voltage E P30 P32 loL 10 mA loL 2 2mA Low level output voltage P5o P53 P91 P94 loL 20 mA IO
57. modulation to every two ports Accordingly actuate the respective timers in the pulse width modulation mode When any bit of pulse output data is 1 the pulse to which pulse width modulation is applied is output from the pulse output port when the contents of timer A1 counter become 000016 Pulse width modulation by corresponding timers is applied when set ting the pulse width modulation select bit 0 of waveform output mode register to 1 and the corresponding pulse width modulation data bits bits 7 to 5 of pulse output data register O to 1 The polarity select bit bit 3 of waveform output mode register must be 0 to select the positive polarity The other operations are the same as that of pulse mode 0 Figure 53 shows example waveforms in the pulse mode 1 In ports selecting the pulse mode 1 output of RTPO1 and RTPOo is controlled by the waveform output control bit O bit 6 of waveform output mode register output of RTP13 RTP12 RTP11 RTP10 RTPO03 and RTPO 2 is done by the waveform output control bit 1 bit 7 When setting the waveform output control bit to 1 waveform is out put from the corresponding port When clearing that bit to 0 wave form output from the corresponding port stops and the port becomes floating The waveform output control bits are cleared to 0 by reset other than clearing with instructions Address Pulse output data register 1 1C16 RTP
58. odd X xX Address even Data even Data odd Invalid data X A Invalid data X Address odd X Address even x Data even Data odd Invalid data MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS AiO 0 M37754M8C XXXGP M37754M8C XXXHP MEC M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Instruction code read data read and data write are described below Instruction code read will be described first The CPU obtains instruction codes from the instruction queue buffer and executes them The CPU notifies the bus interface unit that CPU is requesting an instruction code during an instruction code request cycle If the requested instruction code is not yet stored in the instruc tion queue buffer the bus interface unit halts the CPU until it can Store more instructions than requested in the instruction queue buffer Even if there is no instruction code request from the CPU the bus interface unit reads instruction codes from memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle This is referred to as instruction pre fetching Normally when reading an instruction code from memory if the ac cessed address is even the next odd address is read together with the instruction code and stored in the instruction queue buffer However in
59. output delay time th ALE LA Address hold time tpzx RD DLZ Floating release delay time sz f XIN lt 12 5 MHz when the clock source select bit 1 Note When the clock source select bit is 1 regard f XIN in tables as 2 f XIN 92 MITSUBISHI SN quoe oC io MON eoe eck giv are Ew lt iJ wie a ace Lael or par ome MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER when 2 access in low speed running lt Write gt tw H tw L t t tc f XIN 1 RD WR tw WR tw ALE td ALE WR ALE output Milne a th WR BHE td BHE ALE pir ie e e td A WR th WR A Ao to A7 output A16 toA23 output td A ALE CSo to CS4 output Do to D7 output Ds to D15 output BYTE L Do LAo to D7 LA7 output multiplex bus Note Port Pi output Note These become a multiplex bus only when all of the following conditions are satisfied BYTE H Multiplex bus select bit 1 Q tpzx WR DLZ DHZ td WR DLQ While the address which corresponds to chip select signal CS4 is accessed Test conditions Port Pi f XIN e Vcc 5 Vt10 96 Test conditions except Port Pi f XIN Voc 5 V 10 96 Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF Data input ViL 0 8 V VIH 2 5 V th WR DLQ DHQ
60. port The waveform output se lect bits bits 0 to 2 of waveform output mode register address 1A16 Figure 49 select use of pulse output port The 8 bit pulse out put port is divided into 4 bits and 4 bits or 6 bits and 2 bits with the pulse output mode select bit bit 4 of pulse output data register 1 address 1C16 Figure 51 each of them can be individually con trolled Pulse width modulation select bit 1 Pulse width modulation output of timer A4 Pulse width modulation output of timer A3 Er Pulse width modulation output of timer A2 Pulse width modulation data bit Set timers A1 and A0 to the timer mode because they are used in the pulse output mode Additionally set bit 2 of the corresponding timer Ai mode register to 1 to use a pulse output port because the pulse output port are multiplexed with the TAiouT i 0 to 4 Figure 50 shows the bit configuration of timer A1 and AO mode registers in the pulse output port mode Timers A1 and AO start count when setting the corresponding timer count start flag to 1 and they stop it when clearing that flag to 0 Pulse width modulation select bit 0 EJ Waveform output control bit 0 Mo O RTP13 O RTP12 O RTP11 O RTP10 Pulse output mode select bit
61. pulse mode bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1 The trigger is enabled when the count start bit is 1 The trigger can be generated by software or it can be input from the TAIIN pin Soft ware trigger is selected when bit 4 is 0 and the input signal from the TAiIN pin is used as the trigger when it is 1 Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise The trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1 Software trigger is generated by setting the bit in the one shot start bit corresponding to each timer Figure 29 shows the bit configuration of the one shot start register As shown in Figure 30 when a trigger signal is received the counter counts the clock selected by bits 6 and 7 If the contents of the counter is not 000016 the TAioUT pin goes H when a trigger signal is received The count direction is decrement When the counter reaches 000116 The TAiOUT pin goes L and count is stopped The contents of the reload register is transferred to the counter At the same time an interrupt request signal is gener ated and the interrupt request bit in the timer Ai interrupt control reg ister is set This is repeated each time a trigger signal is received The output pulse width is 1 pulse frequency of the selected clock x counter s value at the time of trigger If
62. reg ister bit 3 at address 7016 before using the A D interrupt It is because the interrupt request bit is undefined just after reset MITSUBISHI a ELECTRIC MITSUBISHI MICROCOMPUTERS 10 sant M37754M8C XXXGP M37754M8C XXXHP get Avo d Keo ot AS M37754S4CGP M37754S4CHP woe cae il SINGLE CHIP 16 BIT CMOS MICROCOMPUTER D A CONVERTER When A D or D A conversion is not performed current from the VREF The D A converter is an 8 bit R 2R method D A converter and con sists of two independent D A converters Figure 72 shows the block diagram of the D A converter and Figure 73 shows the bit configura tion of A D control register 1 D A conversion is performed by writing a value in the corresponding D A register The conversion result is output by bits 6 and 7 of A D control register 1 address 1F16 When bit 7 is 1 the conversion result is output from DAo pin When bit 6 is 1 the conversion result is output from DAtpin The output analog voltage V is determined according to the value n n is a decimal number set in the D A register V VREF x n 256 n 0 to 255 VREF Reference voltage The D A output enable bit is cleared to 0 at reset Whether to con nect the reference voltage input VREF with the ladder network or not depends on bit 5 of the A D control register 1 The VREF pin is con nected when bit 5 is 0 and is disconnected when bit 5 is 1 High impedance state pin to the ladder
63. required MITSUBISHI ELECTRIC Keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials All information contained in these materials including product data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product i
64. source is f XIN 4 in high speed running f XIN lt 40 MHz and when the count source is f XIN 2 in low speed running f XiN lt 25 MHz At this time the clock source select bit is 0 Timer A input External trigger input in one shot pulse mode Parameter f XiN x 40 MHz TAiIN input cycle time f XIN lt 25 MHz TAiIN input high level pulse width TAiIN input low level pulse width Timer A input External trigger input in pulse width modulation mode Parameter TAIIN input high level pulse width TAiIN input low level pulse width Timer A input Up down input in event counter mode Limits Min Max Symbol Parameter tc UP TAioUT input cycle time tw UPH TAioUT input high level pulse width tw UPL TAiour input low level pulse width tsu UP Tin TAiOUT input setup time th TiN UP TAiOUT input hold time MITSUBISHI a ELECTRIC MITSUBISHI MICROCOMPUTERS p M37754M8C XXXGP M37754M8C XXXHP Cao M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A input Two phase pulse input in event counter mode Limits Symbol Parameter Max tc TA TAIIN input cycle time tsu TAjiN TAjoUT TAJIN input setup time tsu TAjout TA IN TAjour input setup time Count input in event counter mode Gating input in timer mode External trigger input in one shot pulse mode External trigger i
65. td A WR Address output delay time Address output delay time Address output delay time BHE output delay time BHE output delay time BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time td WR DLQ DHQ Data output delay time tpxz WR DLZ DHZ Floating start delay time td ALE WR ALE output delay time td ALE RD ALE output delay time tw ALE ALE pulse width th WR A Address hold time th RD A Address hold time h WR BHE BHE hold time BHE hold time h WR CS Chip select hold time h RD BHE th RD CS Chip select hold time th WR DLQ DHQ Data hold time tpzx WR DLZ DHZ Floating release delay time td LA WR Address output delay time td LA RD Address output delay time td LA ALE Address output delay time th ALE LA Address hold time tPXZ RD DLZ Floating start delay time tPZX RD DLZ Floating release delay time td WR PiQ Port Pi data output delay time i 4 9 11 X f XIN 20 MHz when the clock source selet bit 1 Note Since the values depend on external clock frequency f XIN calculate them by using the bus timing data formulas on the next page 100 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C X
66. the conversion result is stored in the even address of the cor responding A D register and the high order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding A D register Bits 2 to 7 of the A D register odd address are 0000002 when read When the conversion result is used as 8 bit data the high order 8 bits of the 10 bit A D conversion result are stored in even address of the corresponding A D register In this case the value at the A D register s odd address is 0016 when read Whether to connect the reference voltage input VREF with the lad der network or not depends on bit 5 of the A D control register 1 The VREF pin is connected when bit 5 is 0 and is disconnected when bit 5 is 1 High impedance state When A D or D Aconversion is not performed current from the VREF pin to the ladder network can be cut off by disconnecting ladder net work from the VREF pin Before starting A D or D A conversion wait for 1 us or more after clearing bit 5 to O Address Comparator function select register 6416 0 Select A D converter 1 Select comparator ANo pin comparator function select bit AN1 pin comparator function select bit AN2 pin comparator function select bit AN3 pin comparator function select bit AN4 pin comparator function select bit AN5 pin comparator function select bit AN6 pin comparator function select bit AN7 pin comparator
67. the count start flag is 0 TAioUT goes L Therefore the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start bit As shown in Figure 31 a trigger signal can be received before the operation for the previous trigger signal is completed In this case the contents of the reload register is transferred to the counter by the trigger and then that value is decremented Except when retriggering while operating the contents of the reload register is not transferred to the counter by triggering When retriggering there must be at least one timer count source cycle before a new trigger can be issued Data write is performed in the same way as for timer mode When data is written in timer Ai halted it is also written to the reload register and the counter When data is written to timer Ai which is busy the data is written to the reload register but not to the counter The counter is reloaded with new data from the reload register at the next reload time Undefined data is read when timer Ai is read Addresses Timer AO mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 Always 10 in one shot pulse mode Always 1 in one shot pulse mode x Software trigger Trigger at the falling edge of TAiIN input Trigger at the rising edge of TAiIN input 0 Always
68. to 6 are set to the address of the subordinate microcomputer to be com municated with Then all subordinate microcomputers receive this data Each subordinate microcomputer checks the received data clears the sleep bit to 0 if bits 0 to 6 are its own address and sets the sleep bit to 1 if not Next the main microcomputer sends data with bit 7 cleared Then the microcomputer which cleared the sleep bit will receive the data but the microcomputers which set the sleep bit to 1 will not In this way the main microcomputer is able to com municate only with the designated microcomputer Stop bit Start bit Start bit k sas Check to be L level Receive Clock Starting at the falling edge of start bit RIi Data fetched L Fig 67 Receive timing example when 8 bit asynchronous communication with no parity and 1 stop bit selected MITSUBISHI Es ELECTRIC MITSUBISHI MICROCOMPUTERS 10 sant M37754M8C XXXGP M37754M8C XXXHP MEC M37754S4CGP M37754S4CHP ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D CONVERTER The A D converter is a 10 bit successive approximation converter The use of A D converter or the use of comparator can be selected for each A D input pin The contents of the comparator function se lect register specify it Figure 68 shows a block diagram of the A D converter VREF connection select bit Vref Ladder network Comparator function selec
69. waveform output mode register address 1416 to 000 The timing of Hold start and termination is the same as that of addresses Ao to A19 Refer to sec tion on processor mode Address Chip select control register 6216 CSo function select bit Note 1 0 Port P90 function 1 CS0 output CS1 CS2 function select bit Note 2 0 Port P91 P92 function 1 CS1 CS2 output or A20 A21 output CS3 function select bit Note 2 0 Port P93 function 1 CS3 output or A22 output C84 function select bit 0 Port P94 function 1 CS4 output us cycle select bits In high speed In low speed 5 0 access Do not select 4 0 access 4 4 access 3 0 access 34 access Do not select 24 access o ag o og8 Cy y S EA g bus cycle select bits 6 Inhigh speed In low speed o 5 0 access Do not select 4 paccess 4 access 3 0 access 3 access Do not select 2 0 access i O oO Notes 1 At reset bit 0 becomes 0 when the CNVss pin s level is L bit 0 becomes 1 when the CNVss pin s level is H 2 Bits 6 and 7 of chip select area register address 6316 specify whether the chip select signal or address is output Fig 87 Chip select control register bit configuration MITSUBISHI ELECTRIC 79 MITSUBISHI MICROCOMPUTERS M M37754M8C XXXGP M37754M8C XXXHP este 10 ae M37754S4CGP M37754S4CHP uoi MC sow SINGLE CHIP 16 BIT CMOS MICROCOMPUTER
70. 10 pulse output data bit RTP11 pulse output data bit RTP12 pulse output data bit RTP13 pulse output data bit Pulse output mode select bit 0 Pulse mode 0 1 Pulse mode 1 X Not used in pulse output port mode Address Pulse output data register 0 1D16 RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit RTPOS3 pulse output data bit In pulse mode 0 Pulse width modulation data bit of RTP1 In pulse mode 1 Pulse width modulation data bit of RTP03 RTPO2 In pulse mode 1 Pulse width modulation data bit of RTP11 RTP10 se mode 1 Pulse width modulation data bit of RTP13 RTP12 Note Only when bit 5 of the particular function select register 1 in Fig 15 is set to 1 this register s contents can be changed from the status after reset in Fig 76 Fig 51 Bit configuration of pulse output data registers 1 and 0 in pulse output port mode MITSUBISHI a ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP rd M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pulse outpu port RTP1 example Signal output each time timer A1 becomes 000016 I RTP1s i i RTP12 RTP11 RTP10 Example of pulse width modulation for above pulse output port using timer A2 Signal output each time timer A1 becomes 000016 I STT IJ I I mL mL I ee ANANN RT
71. 7754M8C XXXGP M37754M8C XXXHP ae NS ae M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER PERIPHERAL DEVICE INPUT OUTPUT TIMING vcc 5 V 10 Vcc 0 V Ta 20 to 85 C unless otherwise noted If the values depends on external clock frequency f XIN formulas of the limits are shown below Also the values at f XIN 40 MHz in high speed running and at f XIN 25 MHz in low speed running are shown in At this time the clock source select bit is 0 When the clock Source select bit is 1 regard f XIN in tables as 2 f XIN The rise and fall time of input signal must be 100 ns or less respectively unless otherwise noted Timer A input Count input in event counter mode Symbol Parameter Eu c TA TAiIN input cycle time tw TAH TAiIN input high level pulse width tw TAL TAiIN input low level pulse width te Timer A input Gating input in timer mode Parameter f XIN lt 40 MHz TAiIN input cycle time XIN lt 25 MHz f XIN lt 40 MHz TAIIN input high level pulse width f XIN 25 MHz f XIN 40 MHz TAIIN input low level pulse width f XIN lt 25 MHz Note The TAilN input cycle time requires 4 or more cycles of count source The TAIIN input high level pulse width and the TAilN input low level pulse width respectively require 2 or more cycles of the count source The limits in the table are the values when the count
72. 8C XXXGP M37754M8C XXXHP coe M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 0 0 1 0 1 0 Single chip mode Memory expansion mode Note 1 Microprocessor mode Note 1 RD E Note 1 E RD RD Note 2 Same as left Port PO Port P1 Same as left Port P2 X l O port X X Address Ao to A19 A23 X BYTE L Same as left X l O port X Same as left odd even When multiplex bus select bit is 1 and accessing CS4 area BYTE H J Same as left LAo to LA7 odd even BYTE L E Same as left I O port BYTE H Same as left X l O port X X Same as left HOLD input 1 O port O Clock t is output from P42 regardless of Port P4 RDY input bit 7 of processor mode register 0 others Clock 1 is output from P42 when bit 7 of are the same as left Note 2 processor mode register 0 is 1 X I O port X Clock 1 is output from P42 when bit 7 of processor mode register 0 is 1 Fig 85 Processor modes and ports PO to P4 P10 and P11 Notes 1 E signal is not output in the memory expansion and microprocessor modes 2 The signal output stop disable bit bit 4 of particular function select register 0 can stop E output in the single chip mode and 61 output
73. C16 Pulse output data register 0 1D16 Timer A write flag 4516 INT4 interrupt control register Notes 1 Bits 2 3 and 4 can be re write after bit 5 expansion function select bit is set to 1 2 After bit 5 is set to 1 once bit 5 cannot be cleared to 0 except external reset and software reset 3 Bits 6 and 7 are write only bits and undefined at read Do not use SEB or CLB insturuction when setting bits 0 7 Fig 63 Particular function select register 1 bit configuration MITSUBISHI ELECTRIC 6E16 MITSUBISHI MICROCOMPUTERS IS aant M37754M8C XXXGP M37754M8C XXXHP aoe M37754S4CGP M37754S4CHP ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selection of transfer format In clock synchronous serial communication transfer format can be transmit buffer register and the receive buffer register when writing selected by bit 7 of the Transmit Receive control register 0 When bit transmit data to the transmit buffer register or reading receive data 7 is 0 transfer format is LSB first When bit 7 is 1 transfer format from the receive buffer register Accordingly the transmitter s opera is MSB first tion is the same in both transfer formats This function is realized by changing connection relation between the Figure 64 shows the connection relation Bit 7 in Transmit Receive Write to transmit Read from receive control register 0 buffer register buffer register Transmit buffer Receive b
74. ERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Figure 69 shows the comparator function select register address 6416 bit configuration Bits 7 to O correspond to channels 7 to 0 re spectively Each channel can be selected as either an A D converter or a comparator When the bit is 0 the channel corresponding to it functions as a 10 bit or an 8 bit A D converter When the bit is 1 the channel functions as a comparator When selecting an A D converter an input voltage to a selected ana log input pin is A D converted and the result is stored into the A D register When selecting a comparator D A conversion is performed to the value of which high order 8 bits are the value stored in an even ad dress of the A D converter and of which low order 2 bits are 102 Then this D A converted value is compared with the voltage sup plied to an analog input pin After the comparison when the voltage supplied to an analog input pin is higher 1 is stored into the com parator result register address 6616 shown in Figure 70 When it is lower 0 is stored into that register Be sure to perform only read to the A D register of which channel is selected as an A D converter and perform only write to the A D reg ister of which channel is selected as a comparator Additionally do not write to the comparator function select register and the A D reg ister while an A D converter or
75. HI ELECTRIC 40 e m over e MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FUNCTIONS OF M37754M8C XXXGP Parameter Functions Number of basic machine instructions 109 Instruction execution time 100 ns the fastest instruction at external clock 40 MHz frequency ROM Note 1 60 Kbytes M emory size RAM 2048 bytes PO P1 P4 P8 P10 P11 8 bit x 9 P2 5 bit x 1 Input Output ports Note 2 P3 4 bit x 1 P9 TAO TA1 TA2 TA3 TA4 6 bit x 1 16 bit x 5 Multiple function timers TBO TB1 TB2 16 bit x 3 Serial I O UART or clock synchronous serial I O x 2 A D converter 10 bit x 1 8 channels D A converter 8 bit x 2 Watchdog timer 12 bit x 1 Short circuit prevention time set timer Interrupts 5 external types 16 internal types Each interrupt can be set to priority levels 0 7 Clock generating circuit Built in externally connected to a ceramic resonator or quartz crystal resonator Supply voltage 5 V 10 Power dissipation 125 mW at external clock 40 MHz frequency dE Input Output withstand voltage Input Output characteristic 5V Output current 5 mA Memory expansion Maximum 16 Mbytes Operating temperature range 20 to 85 C Device structure CMOS high performa
76. I 2 ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pulse output function When bit 2 of the timer Ai mode register is 1 the output is gener ated from TAiOUT pin The output is toggled each time the contents of the counter reaches to 000016 When the contents of the count start bit is 0 L is output from TAiOUT pin When bit 2 is 0 TAiOUT can be used as a normal port pin When bit 4 is 0 TAilN can be used as a normal port pin Gate function When bit 4 is 1 counting is performed only while the input signal from the TAiIN pin is H or L as shown in Figure 20 Therefore this can be used to measure the pulse width of the TAiIN input signal Whether to count while the input signal is H or while it is L is de termined by bit 3 If bit 3 is 1 counting is performed while the TAiIN pin input signal is H and if bit 3 is 0 counting is performed while it is L When bit 5 is 0 counting restarts from the value which is contained at restarting gate function 0 no reload and an overflow occurs n 1 cycles of the count source later Figure 21 shows that operation When bit 5 is 1 counting restarts from the value which is obtained by reload at restarting gate function 1 reload and the first overflow occurs n 2 cycles of the count source later Fi
77. L 2 mA Hysteresis HOLD RDY TAOIN TAAIN TBOIN TB2IN INTo INT4 ADTRG CTSo CTS1 CLKo CLK1 RxDo RxD1 Hysteresis RESET HOLD RDY Hysteresis XIN High level input current POo PO7 P10 P17 P2o P23 P27 P30 P33 P40 P47 P5o P57 P6o P67 P70 P77 P80 P87 P90 P95 P100 P107 P110 P117 XIN RESET CNVss BYTE Low level input current POo PO7 P10 P17 P20 P23 P27 P30 P33 P40 P47 P5o P53 P6o P67 P70 P77 P80 P87 P90 P95 P100 P107 P110 P117 XIN RESET CNVss BYTE Low level input current P54 P57 P95 Vi 0 V No pull up transistor Vi 0 V Pull up transistor used RAM hold voltage When clock is stoped Power supply current target value Output only pin is f XIN 40 MHz square open and other waveform Note pins are Vss during Ta 25 C when clcock reset is stopped Ta 85 C when clcock is stopped Note f XIN 20 MHz when the clock source select bit 1 MITSUBISHI 81 ELECTRIC MITSUBISHI MICROCOMPUTERS e M37754M8C XXXGP M37754M8C XXXHP oso eS a ae M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D CONVERTER CHARACTERISTICS Vcc AVcc 5 V 10 Vss AVSS 0 V Ta 20 to 85 C the clock source select bit 0 unless otherwise noted Limits Typ Max A D converter selected 10 Comparator selected zi VREF 10 bit mode 3 250 kHz lt AD bi
78. MITSUBISHI MICROCOMPUTERS wre M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER DESCRIPTION The M37754M8C XXXGP is a single chip microcomputer designed with high performance CMOS silicon gate technology This is housed in a 100 pin plastic molded QFP This microcomputer has a CPU and a bus interface unit The CPU is a 16 bit parallel processor that can also be switched to perform 8 bit parallel processing and the bus interface unit enhances the memory access efficiency to execute instructions fast In addition to the 7700 Family basic instructions the M37754M8C XXXGP has 6 special instructions which contain instructions for signed multiplication division these added instructions improve the servo arithmetic performance to control hard disk drives and so on This microcomputer also include the ROM RAM multiple function timers motor control function serial I O A D converter D A con verter and so on The differences between M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP and M37754S4CHP are listed in the table on the next page the internal ROM usable processor mode and package Therefore the following descriptions will be for the M37754M8C XXXGP unless otherwise noted DISTINCTIVE FEATURES e Number of basic machine instructions 103 basic instructions of 7700 Family 6 special instructions e Memory size ROM mz cas Ie c E 60 Kbytes RAM su anasu nt iere meo 2048 byte
79. OMPUTER High speed running lt 20 MHZ Internal memory access External memory access 2 6 access Note 3 access Write Read 3 6 access Note 4 access Read Read UUU l l L l l l I l I T l l l 1bus cycle 30 1bus cycle 30 R SS 5 access Read FLU LU UL Note Refer to internal memory access bus cycle select bit bit 2 of processor mode register 0 Figure 14 ADRS Address R D Read data W D Write data Fig 7 Bus cycle selection high speed running MITSUBISHI M ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP MEC M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Access from even address Access from odd address 1 byte Read Write 8 bits External data bus width 9 o o cc o ES 2 A 1 byte Read Write Note i Dm cic ro External data bus width 16 bits 2 byte Read Write Notes 1 It becomes Hi Z when reading and it outputs undefined data when writing 2 When the external data bus width is 8 bits the function to output the low order address from the Di pin while RD or WR is H can be selected only in special area access cycle Refer to the section on the processor mode for details Fig 8 Output signals at 3 access in high speed running
80. P12 1 i RTP11 i T Tl 1 RTP10 LLLI Pulse outpu port RTPO example in the case of polarity select bit 1 Signal output each time timer AO becomes 000016 I RTP03 RTP02 RTP01 RTP0o Fig 52 Example waveforms in pulse mode 0 Pulse outpu port 6 bits example Signal output each time timer A1 becomes 000016 RTP1s TP12 TP11 TP10 TPO0s TP02 Example of pulse width modulation for above pulse output port using timer A2 Signal output each time timer A1 becomes 000016 I I we LILI J x TP11 TP10 TPO3 m OUUU Fig 53 Example waveforms in pulse mode 1 MITSUBISHI ELECTRIC 49 NO and MESA ok X NO E e NS y 2 5 not E se v TS aic co e ow aN e eo MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER SERIAL I O PORTS Two independent serial I O ports are provided Figure 54 shows a block diagram of the serial I O ports Bits 0 1 and 2 of the UARTi i 0 1 Transmit Receive mode register shown in Figure 55 are used to determine whether to use port P8 as parallel port clock synchronous serial I O port or asynchronous UART serial I O port using start and stop bits Figures 56 and 57 show the connections of receiver transmitter ac cording to the mode
81. P8 register 000052 000013 Port P9 register 000053 000014 Port P8 direction register 000054 000015 Port P9 direction register 000055 000016 Port P10 register 000056 Timer AO mode register 000017 Port P11 register 000057 Timer A1 mode register 000018 Port P10 direction register 000058 Timer A2 mode register 000019 Port P11 direction register 000059 Timer A3 mode register 00001A Waveform output mode register 00005A Timer A4 mode register 00001B Dead time timer 00005B Timer BO mode register 00001C Pulse output data register 1 00005C Timer B1 mode register 00001D Pulse output data register 0 00005D Timer B2 mode register 00001E A D control register 0 00005E Processor mode register 0 Timer AO register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer BO register Timer B1 register Timer B2 register 00001F A D control register 1 00005F Processor mode register 1 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 000060 Watchdog timer register 000061 Watchdog timer frequency select register 000062 Chip select control register 000063 Chip select area register 000064 Comparator function select register 000065 Reserved area Note 000066 Comparator result register 000067 Reserved a
82. PO2 by timer A2 Modulation for RTP11 RTP10 by timer A3 Modulation for RTP13 RTP12 by timer A4 when selecting pulse mode 0 fix this bit to 0 Waveform output control bit O 0 In pulse mode 0 Disable RTPO waveform output In pulse mode 1 Disable RTPO1 RTP00 waveform output 1 In pulse mode 0 Enable RTPO waveform output In pulse mode 1 Enable RTP01 RTP00 waveform output Waveform output control bit 1 0 In pulse mode 0 Disable RTP1 waveform output In pulse mode 1 Disable RTP1 RTP03 RTPO2 waveform output In pulse mode 0 Enable RTP1 waveform output In pulse mode 1 Enable RTP1 RTP03 RTP02 waveform output Pulse mode 0 This mode divides a pulse output port into 4 bits and 4 bits and indi vidually controls them When setting the pulse output mode select bit to 0 and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits four of RTP13 RTP12 RTP11 and RTP10 become the pulse output ports with RTP1 selected When setting the pulse output mode select bit to 0 and setting bits 2 and 0 to 0 and bit 1 to 1 of the waveform output select bits four of RTP03 RTP02 RTP01 RTP00 become the pulse output ports with RTPO selected When setting the pulse output mode select bit to 0 and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits the following two groups become the pulse output ports with RTP1 and RTPO selected Four of RTP13
83. PUTERS M37754M8C XXXGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER The INT3 interrupt can function as the key input interrupt by setting bits 7 and 6 of the INT3 interrupt control register The key input inter rupt uses inputs KI3 to Klo or inputs Kl4 to Klo Figure 10 shows the interrupt control register bit configuration Figure 15 shows the par ticular function select register 1 bit configuration and Figure 16 shows the INT3 key input interrupt input circuit block diagram When the INT3 interrupt control register s bit 7 is 0 and its bit 6 is 0 a signal from the INT3 pin is connected to the INT3 interrupt con trol circuit and INT3 external interrupt is normally performed When the INT3 interrupt control register s bit 7 is 1 and its bit 6 is 0 signals from the KI3 to Klo pins which correspond to ports P57 to P54 are inverted and then the logical sum of these signals is con nected to the INTs interrupt control circuit In this case the external interrupt which uses the KI3 to Klo pins is performed When the INT3 interrupt control register s bit 7 is 1 and its bit 6 is 1 signals from the Kl4 pin which corresponds to port P95 KI3 to Klo pins which correspond to ports P57 to P54 are inverted and then the logical sum of these signals is connected to the INT3 interrupt control circuit In this case the external interrupt which uses the Kl4 Pull up select b
84. RTP12 RTP11 RTP10 Four of RTP03 RTP02 RTP01 RTPOo Each time the contents of timer A1 counter become 000016 the contents of pulse output data register 1 low order 4 bits at address 1C16 corresponding to RTP13 RTP12 RTP11 RTP10 are output from ports Each time the contents of timer AO counter become 000016 the contents of pulse output data register O low order 4 bits at address 1D16 corresponding to RTP03 RTPO2 RTP01 RTP00 are output from ports When writing 0 to the specified bit of pulse output data register L level is output from the pulse output port when the contents of cor responding timer counter become 000016 when writing 1 to it H level is output from the pulse output port Address Timer AO mode register 5616 Timer A1 mode register 5716 100 Fix to 100 in pulse output port mode X Not used in pulse output port mode 00 Fix to 00 in pulse output port mode Clock source select bit 00 Pf2 selected 01 Pf16 selected 10 Pfe4 selected 11 Pf512 selected Fig 50 Bit configuration of timer A1 and AO mode registers in pulse output port mode Note Only when bit 5 of the particular function select register 1 in Fig 15 is set to 1 this register s contents can be changed from the status after reset in Fig 76 Fig 49 Bit configuration of waveform output mode register in pulse output port mode MITSUBISHI ELECTRIC 43 MITSUBISHI MICROCOMPUTERS M37754M8C XX
85. SUBISHI MICROCOMPUTERS AiO sane M37754M8C XXXGP M37754M8C XXXHP ew e xO ana M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Parameter Ratings Power source voltage 0 3 to 7 Analog power source voltage 0 3 to 7 Input voltage RESET CNVss BYTE 0 3 to 12 Input voltage POo PO7 P10 P17 P20 P23 P27 P30 P33 P40 P47 P50 P57 P60 P67 P70 P77 P80 P87 P90 P95 0 3 to Vcc 0 3 P100 P107 P110 P117 VREF XIN Output voltage POo P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 P50 P57 P60 P67 P70 P77 P80 P87 P90 P95 0 3 to Vcc 0 3 P100 P107 P110 P117 XOUT E Power dissipation 300 Operating temperature 20 to 85 Storage temerature 40 to 150 RECOMMENDED OPERATING CONDITIONS vcc 5 V 10 Ta 20 to 85 C unless otherwise noted Limits Typ Supply voltage 5 0 Analog supply voltage Vcc Supply voltage 0 Analog supply voltage 0 High level input voltage POo P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 P50 P57 P60 P67 P70 P77 P80 P87 P90 P95 XIN RESET CNVss BYTE High level input voltage P100 P107 P110 P117 in single chip mode High level input voltage P100 P107 P110 P117 in memory expansion mode and microprocessor mode Low level input voltage P00 P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 VIL P50 P57 P60 P67 P70 P77 P80 P87 P90 P95 XIN 0 2
86. T CMOS MICROCOMPUTER 2 0 access 3 6 access 4 access tsu A DL DH tsu CS DL DH Data setup time with address stabilized Data setup time with chip select stabilized 9 3x 10 60 X 5 x 109 7 x 109 fX 90 X 90 tw 9H tw 9L high level pulse width f low level pulse width WR RD low level pulse width x x x Address output delay time Address output delay time x SX gt td BHE WR Address output delay time BHE output delay time x x gt td BHE RD td BHE ALE BHE outupt delay time BHE output delay time x gt td CS WR td CS RD Chip select output delay time Chip select output delay time x gt td CS ALE Chip select output delay time ALE pulse width x x X x th RD A Address hold time Address hold time x x 1 x td WR BHE td RD BHE BHE hold time BHE hold time x x x gt td WR CS td RD CS Chip select hold time Chip select holt time x x x gt th WR DLQ DHQ Data hold time toxz WR DLZ DHZ Floating start delay time gt tsu LA DL Data setup time with address stabilized Alo FIX td LA WR Address output delay time x gt td LA RD Address output delay time xXx td LA ALE Address
87. Vcc RESET CNVss BYTE VIL Low level input voltage P100 P107 P110 P117 in single chip mode 0 2 Vcc Low level input voltage P100 P107 P110 P117 in memory expansion mode and microprocessor mode High level peak output current P00 P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 IOH peak P50 P57 P60 P67 P70 P77 P80 P87 P90 P92 P95 P100 P107 P110 P117 Parameter VIL 0 16 Vcc loH peak P93 P94 High level average output current POo P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 loH avg P50 P57 P60 P67 P70 P77 P80 P87 P90 P92 P95 P100 P107 P110 P117 lOH avg P93 P94 Low level peak output current P00 P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 lOL peak P54 P57 P60 P67 P70 P77 P80 P87 P90 P95 P100 P107 P110 P117 lOL peak P50 P53 P91 P94 Low level average output current P00 P07 P10 P17 P20 P23 P27 P30 P33 P40 P47 lOL avg P54 P57 P60 P67 P70 P77 P80 P87 P90 P95 P100 P107 P110 P117 lOL avg P50 P53 P91 P94 f XIN External clock frequency input Note 3 Low speed running High speed running Notes 1 Average output current is the averaage value of a 100 ms interval 2 The sum of lOL peak for ports PO P1 P2 P3 P8 P10 and P11 must be 80 mA or less the sum of lOH peak for ports PO P1 P2 P3 P8 P10 and P11 must be 80
88. When setting the waveform output control bit to 1 waveform is out put from the corresponding port When clearing that bit to 0 wave form output from the corresponding port stops and the port becomes floating The waveform output control bits are cleared to 0 by reset other than clearing with instructions Pulse mode 1 This mode divides a pulse output port into 6 bits and 2 bits and indi vidually controls them When setting the pulse output mode select bit to 1 and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits the following two groups become the pulse output ports Six of RTP13 RTP12 RTP11 RTP10 RTP03 RTP02 Two of RTPO1 RTPOo Timer A1 controls six of RTP13 RTP12 RTP11 RTP10 RTPOS3 and RTPO2 timer AO controls two of RTP01 RTPOo Additionally pulse width modulation can be applied for the pulse out put ports RTP1 RTPO3 RTPO02 The pulse width modulation select bit 1 bit 5 of waveform output mode register selects the type of modulation the common modulation to six of RTP13 RTP12 RTP11 RTP10 RTP03 and RTP02 or the modulation to every two ports of RTP13 and RTP12 RTP11 and RTP10 RTP03 and RTPO2 When setting that bit to 0 the common modulation to six ports is applied when setting that bit to 1 the modulation to every two ports is applied The timer A2 is used for the common modulation to six ports the timers A2 A3 and A4 are used for the
89. XGP M37754M8C XXXHP M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Additionally pulse width modulation can be applied for the pulse out put port RTP1 Because the timer A2 is used for pulse width modula tion actuate timer A2 in the pulse width modulation mode When any bit of pulse output data is 1 the pulse to which pulse width modula tion is applied is output from the pulse output port when the contents of timer A1 counter become 000016 Pulse width modulation by timer A2 is applied when setting the pulse width modulation select bit O bit 4 of waveform output mode regis ter to 1 pulse width modulation select bit 1 bit 5 to 0 and the pulse width modulation data bit of RTP1 bit 5 of pulse output data register 0 to 1 RTPO03 RTPO2 RTP01 and RTPOo can output the contents of pulse output data register 0 by setting the polarity select bit bit 3 of wave form output mode register When the polarity select bit is 1 the re versed contents of pulse output data register 0 is output when that bit is 0 the contents of pulse output data register O are output as it is Figure 52 shows example waveforms in the pulse mode 0 In ports selecting the pulse mode 0 output of RTPO3 RTP02 RTPO1 and RTPOo is controlled by the waveform output control bit O bit 6 of waveform output mode register output of RTP13 RTP12 RTP11 and RTP10 is done by the waveform output control bit 1 bit 7
90. XIN th WR A Address hold time 15 lt th RD A Address hold time 15 lt td WR BHE BHE hold time 15 td RD BHE BHE hold time 15 td WR CS Chip select hold time 15 td RD CS Chip select hold time 15 th WR DLQ DHQ Data hold time 10 m toxz WR DLZ DHZ Floating start delay time 5 lt tsu LA DL Data setup time with address stabilized 75 7x109 XN 9 td LA WR Address outuput delay time 35 3x109 XN 99 td LA RD Address outuput delay time 35 3 x 10 fX 9 td LA ALE Address outuput delay time 2 x 109 20 f XIN td ALE LA Address hold time 15 lt tpzx RD DLZ Floating release delay time 3k f XIN lt 20 MHz when the clock source select bit 1 Note When the clock source select bit is 1 regard f XIN in tables as 2 f XIN MITSUBISHI q MITSUBISHI MICROCOMPUTERS n M37754M8C XXXGP M37754M8C XXXHP eese M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER tw H tw L tr tf tc tw oL o1 l td o1 WR lt td o1 WR RD WR tw WR lt tw ALE d ALE WR ALE output td BHE WR AW td BHE ALE td A WR WRA Ao A7 output am A16 A23 output td A ALE CS0 CS4 output td WR DLQ DHQ th WR DLQ DHQ 77
91. XXHP cose quon Qe mer M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Bus timing data formulas Memory expansion and Microprocessor mode High speed running Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f XIN lt 40 MHz when the clock source select bit 0 unless otherwise noted Symbol Parameter 3 6 access 4 9 access 5 access tsu A DL DH Data setup time with address stabilized 5 x 109 f XIN 60 7 x10 9 x 10 XN 99 fX 99 tsu CS DL DH Data setup time with chip select stabilized 5 x 109 60 9 x 109 XN 99 tw gh tw oL high level pulse width low level pulse width 20 lt A tw WR tw RD WR RD low level pulse width xn 20 6 x 109 XN 20 td A WR Address output delay time Ua 25 td A RD Address output delay time 25 td A ALE Address output delay time 15 f XIN td BHE WR BHE outuput delay time 25 3x109 f XIN td BHE RD BHE outuput delay time Fyn 20 3 x10 f XIN td BHE ALE BHE outuput delay time 2 x10 15 f XIN td CS WR Chip select output delay time yn 25 3 x10 f XIN id CS RD Chip select output delay time 25 3x109 f XIN td CS ALE Chip select output delay time 15 2x109 fXN tw ALE ALE pulse width 15 2x109 f
92. Y MODIFICATION FUNCTION The M37754M8C XXXGP s internal memory size and address area can be modified by set of bit 2 memory allocation select bit of the particular function select register 0 Figure 90 shows the memory al location when modifying the internal memory area When ordering a mask ROM Mitsubishi Electric corp produces the mask ROM using the data within 60 Kbytes between addresses 00100016 to OOFFFF 16 It is regardless of the selected ROM size refer to MASK ROM ORDER CONFIRMATION FORM Therefore on the EPROM tendered for ordering a mask ROM program data FF16 to addresses which correspond to the area out of the selected ROM area Additionally address 00FFFF16 of the microcomputer corresponds to the lowest address of the tendered EPROM Memory allocation select bit 1 Memory allocation select bit 0 ROM size 60 Kbytes RAM size 2048 bytes RAM size 2048 bytes 00 000016 SFR 00 000016 SFR 00 008016 Internal RAM 2048 bytes 00 008016 Internal RAM 2048 NS ROM size 56 Kbytes 00 087F 6 00 087F 6 00 100016 00 200016 Internal ROM 60 Kbytes Internal ROM 56 Kbytes 00 FFFF16 00 FFFF16 External memory area External memory area Note The internal ROM area becomes external memory area in microprocessor mode FF FFFF16 FF FFFF16 Fig 90 Memory allocation when modifying internal memory area with memory allocation select bit MITSUBISHI 78 ELECTRIC
93. Y input is always sampled at the falling edge of 1 just before the RD and WR signals rise regardless of the bus mode and the number of waits HOLD input 1 tsu HOLD 01 th o1 HOLD HOLD input td o1 HLDA td o1 HLDA HLDA output tpxz HLDA RDZ iL thex HLDA RDZ tpzx HLDA WRZ lpzx gt Hi Z DT LUUD unururcacUx A R A ee ef ee ee r tpxz HLDA BHE tpzx HLDA BHE e E Hi Z BHE oUt PDF a pn ge ge eee T S QUEANT EET MAN r tpzx HLDA AZ lt gt gt A0 A7 output Hi Z A8 A15 output 2 222 2 2 2 2 2 2 22 2 2 2 l2 2 22 2 2 2 2 2 2 L A16 A23 output tpxz HLDA DLZ DHZ tpzx HLDA DLZ DHZ ste Do D7 output AN I I I I I I Ike amada Doce rd m Mes Ane Ds D15 output PO BYTE L Test conditions e Vcc 5 V 10 96 RDY input HOLD input VIL 1 0 V VIH 4 0 V HLDA output VOL 0 8 V VOH 2 0 V CL 100 pF MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS A Sn e M37754M8C XXXGP M37754M8C XXXHP Can ses M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f XIN 40 MHz when the clock source select bit 0 unless otherwise noted The rise and fall time of input signal must be 100 ns or less respectively unless otherwise noted Single chip mode Limits Min Max External clock input cycle time Not
94. a comparator is operating Port direction register s bits corresponding to pins to be A D con verted must be 0 input mode because analog input ports are mul tiplexed with port P7 Figure 71 shows the bit configuration of the A D control register 0 address 1E16 and the A D control register 1 address 1F16 An operation clock Ap of an A D converter or a comparator can be selected with bit 7 of the A D control register O and bit 4 of the A D control register 1 When bit 4 frequency select flag 1 of the A D control register 1 is 0 AD becomes Pfs when bit 7 frequency select flag 0 of the A D control register 0 is 0 9AD becomes Pf4 when bit 7 of the A D con trol register 0 is 1 When the frequency select flag 1 is 1 9AD becomes Pf2 when the frequency select flag 0 is 0 AD becomes 61 when the frequency select flag 0 is 1 The last case is used when 1 is forcibly used as AD in high speed running f XIN gt 1 gt 12 5 MHz However this se lection is available only in 8 bit resolution mode AD during A D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier Bit 3 of A D control register 1 is used to select whether to regard the conversion result as 10 bit or as 8 bit data The conversion result is regarded as 10 bit data when bit 3 is 1 and as 8 bit data when bit 3 is 0 When the conversion result is used as 10 bit data the low order 8 bits of
95. a programmable port P11 similarly in the single chip mode Ports P30 P31 P32 and P33 become WR BHE ALE and HLDA output pins respectively and lose their I O port functions WR is a write signal which indicates a write when it is L BHE is a byte high enable signal which indicates that an odd ad dress is accessed when it is L Therefore two bytes at even and odd addresses are accessed si multaneously when address Ao is L and BHE is L ALE is an address latch enable signal The latch is open while ALE is H so that the address signal passes through the address is held while ALE is L HLDA is a hold acknowledge signal and is used to indicate to the external that the microcomputer accepts HOLD input and enters Hold state Ports P40 and P41 become HOLD and RDY input pins respectively and their I O port function are lost HOLD is a hold request signal It is an input signal used to make the microcomputer enter Hold state HOLD input is accepted when the BIU has fallen from H to L level while the bus is not used In Hold state CPU stops at L Ao to A19 A23 Do to D7 Ds to D15 at BYTE L RD WR and BHE become floating then These pins become floating one cycle of BIU later than HLDA signal becomes L level When terminating Hold state these pins are terminated from floating state one cycle of BIU later than HLDA signal becomes H level RDY is a ready signal When this signal goe
96. alog name Mitsubishi lot number 6 digit or 7 digit AAAARARARRARARAAARARRAARA Arrr B Customer s Parts Number Mitsubishi catalog name 6 ARAAAAARRARRAAARRARAAARARA zo Customer s Parts Number EM Note The fonts and size of characters are standard Mitsubishi type Em En ova V ya Mitsubishi IC catalog name Notel The mark field should be written right aligned saa OES E I 2 The fonts and size of characters are standard Mitsubishi type ES 6 digit or 7 digit E 3 Customer s Parts Number can be up to 12 characters Only 0 9 A Z amp periods commas are usable os ne 4 If the Mitsubishi logo is not required check the box below Mitsubishi logo is not required C Special Mark Required Note1 If the Special Mark is to be Printed indicate the desired layout of the mark in the left figure The layout will be duplicated as close as possible 69 Mitsubishi lot number 6 digit or 7 digit and Mask ROM number 3 digit are always marked 2 If the customer s trade mark logo must be used in the Special Mark check the box below E Please submit a clean original of the logo E pe For the new special character fonts a clean font original E E ideally logo drawing must be submitted F 69 Special logo
97. and read is performed during it is L level When the internal memory area is read the RD output can be fixed to H by setting the signal output disable select bit to 1 Ports PO P1 and P2 become the output pins of addresses Ao to A19 and A23 and their I O port function are lost Port P10 becomes I O pins of data Do to D7 and loses its I O port function When the BYTE pin s level is L those pins function as data I O pins at an even address When the level is H those pins function as data I O pins at even and odd addresses However if an internal memory area is read external data is not input When the BYTE pin s level is H and the multiplex bus select bit bit 5 of chip select area register Figure 88 is 1 port P10 functions as follows during the bus cycle in which the external memory area cor responding to the chip select CS4 are accessed Output pins of addresses LAo to LA7 same as low order addresses Ao to A7 during H of RD or WR Data input output pins at even and odd addresses during L of RD or WR That is it functions as a multiplex bus during that bus cycle Port P11 has two functions depending on the level of the BYTE pin When the BYTE pin level is L those pins function as data D8 to D15 I O pins at an odd address The I O port function is lost However if an internal memory area is read external data is not input When the BYTE pin level is H port P11 functions as
98. ank register PG is increased by 1 Also when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter PC using the branch instruction the contents of the program bank regis ter PG is increased or decreased by 1 so that programs can be written without worrying about bank boundaries DATA BANK REGISTER DT Data bank register DT is an 8 bit register With some addressing modes the data bank register DT is used to specify a part of the memory address The contents of data bank register DT is used as the high order 8 bits of a 24 bit address Addressing modes that use the data bank register DT are direct indirect direct indexed X indi rect direct indirect indexed Y absolute absolute bit absolute in dexed X absolute indexed Y absolute bit relative and stack pointer relative indirect indexed Y DIRECT PAGE REGISTER DPR Direct page register DPR is a 16 bit register Its contents is used as the base address of a 256 byte direct page area The direct page area is allocated in bank 016 but when the contents of DPR is FF0116 or greater the direct page area spans across bank 016 and bank 116 All direct addressing modes use the contents of the direct page register DPR to generate the data address If the low order 8 bits of the direct page register DPR is 0016 the number of cycles required to generate an address is minimized Normally the low order 8 bits o
99. ata was transferred to the receive register before the contents of the re ceive buffer register was read Rik flag is automatically cleared to 0 when the low order byte of the receive buffer register is read or when the REk flag is cleared to 0 The OERK flag is cleared when the REk flag is cleared or port P8 is set to a parallel port Bit 5 FERK flag bit 6 PERk flag and bit 7 SUMk flag are ignored in clock synchro nous mode When reading the contents of the receive buffer register the received data is pulled from the least significant bit LSB in the received order if bit 7 TEM of the UARTj Transmit Receive control registers O is 0 If bit 7 TEM is 1 the received data is pulled from the most signifi cant bit MSB As shown in Figure 54 with clock synchronous serial communica tion data cannot be received unless the transmitter is operating be cause the receive clock is created from the transmission clock Therefore the transmitter must be operating even when there is no need to sent data from UARTk to UART 50 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 1 sant M37754M8C XXXGP M37754M8C XXXHP MEC M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Particular function select register 1 6D16 Transmit clock output pin select bit 00 Normal mode output only to CLKo 01 Plural clocks specified output to CLKo 10 Plural clocks spe
100. be 100 ns or less respectively unless otherwise noted Limits Symbol Parameter Max tsu RDY 61 RDY input setup time tsu HOLD 1 HOLD input setup time th g1 RDY RDY input hold time th g1 HOLD HOLD input hold time X f XiN 20 MHz when the clock source select bit 1 Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f XIN 40 MHz when the clock source select bit 0 unless otherwise noted Symbol Parameter td 1 HLDA HLDA output delay time tpxz HLDA RDZ Floating start delay time at hold state tpxz HLDA WRZ Floating start delay time at hold state tpxz HLDA BHEZ Floating start delay time at hold state tpxz HLDA AZ Floating start delay time at hold state tpxz HLDA DLZ DHZ Floating start delay time at hold state tpzx HLDA RDZ Floating release delay time at hold state tpzx HLDA WRZ Floating release delay time at hold state tpzx HLDA BHEZ Floating release delay time at hold state tpzx HLDA AZ Floating release delay time at hold state tpzx HLDA DLZ DHZ Floating release delay time at hold state X f XiN 20 MHz when the clock source select bit 1 MITSUBISHI 87 ELECTRIC MITSUBISHI MICROCOMPUTERS n M37754M8C XXXGP M37754M8C XXXHP Keren M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER tsu RDY 61 th o1 RDY RD
101. cified output to CLKSo 11 Plural clocks specified output to CLKS1 Internal clock stop select bit at WIT Note 1 0 Clock for peripheral function and watchdog timer are operating at WIT 1 Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT Watchdog timer s select bit Note 1 0 Exclusive clock deviding circuit output Wfs12 Wf32 is used as clock for watchdog timer Clock Wfs12 Wf32 for watchdog timer does not change in hold 1 Clock for peripheral device deviding circuit output Pf512 Pf32 is used as clock for watchdog timer Clock Pf512 Pf32 for watchdog timer changes in hold Watchdog timer exclusive clock dividing circuit is stopped Signal output stop select bit Note 1 Refer to Table 8 Expansion function select bit Note 2 Refer to Figure 62 Pull up select bit 0 Note 3 0 With no pull up for P57 P5e P55 P54 1 With pull up for P57 P56 P55 P54 Pull up select bit 1 Note 3 0 With no pull up for P95 1 With pull up for P95 Control registers affected by expansion function select register Control bits affected by expansion function select bit Register i Register Address A D control register 1 Chip select area register Particular function select register 0 Particular function select register 1 Waveform output mode register 1A16 Dead time timer 1B16 Pulse output data register 1 1
102. d A3 and the other uses timer A4 In both processing operations two pulses described above are input to the TAjOUT j 2 to 4 pin and TAJIN pin respectively When timers A2 and A3 are used as shown in Figure 25 the count is incremented when a rising edge is input to the TAKIN pin after the level of TAKOUT k 2 3 pin changes from L to H and when the fall ing edge is input the count is decremented For timer A4 as shown in Figure 26 when a phase related pulse with a rising edge input to the TA4IN pin is input after the level of TA40UT pin changes from L to H the count is incremented at the respec tive rising edge and falling edge of the TA40UT pin and TA4IN pin When a phase related pulse with a falling edge input to the TA40UT pin is input after the level of TA4IN pin changes from H to L the count is decremented at the respective rising edge and falling edge of the TA4IN pin and TA4oUT pin When performing this two phase pulse signal processing timer Aj mode register bit 0 and bit 4 must Increment Increment Increment Decrement Decrement count count count count count be set to 1 and bits 1 2 3 and 5 must be 0 Bits 6 and 7 are ig nored Note that bits 5 6 and 7 of the up down register 4416 are the two phase pulse signal processing select bits for timers A2 A3 and A4 respectively Each timer operates in normal event counter mode when the corresponding bit is 0
103. dex register X consists of 16 bits and the low order 8 bits can be used separately The index register length flag x determines whether the register is used as 16 bit register or as 8 bit register It is used as a 16 bit register when flag x is 0 and as an 8 bit register when flag x is 1 Flag x is a part of the processor status register PS which is described later In index addressing mode register X is used as the index register and the contents of this address is added to obtain the real address Index register X functions as a pointer register which indicates an address of data table in instructions MVP MVN RMPA Repeat MultiPly and Accumulate INDEX REGISTER Y Y Index register Y consists of 16 bits and the low order 8 bits can be used separately The index register length flag x determines whether the register is used as 16 bit register or as 8 bit register It is used as a 16 bit register when flag x is O and as an 8 bit register when flag x is 1 Flag x is a part of the processor status register PS which is described later In index addressing mode register Y is used as the index register and the contents of this address is added to obtain the real address Index register Y functions as a pointer register which indicates an address of data table in instructions MVP MVN RMPA Repeat MultiPly and Accumulate Accumulator A Accumulator B Index register X Index register Y
104. dth f XIN 25 MHz f XiN lt 40 MHz TBilN input low level pulse width f XIN lt 25 MHz Note The TBilN input cycle time requires 4 or more cycles of count source The TBIIN input high level pulse width and the TBilN input low level pulse width respectively require 2 or more cycles of the count source The limits in the table are the values when the count source is f XIN 4 in high speed running f XIN lt 40 MHz and when the count source is f XIN 2 in low speed running f XIN 25 MHz At this time the clock source select bit is 0 Timer B input Pulse width measurement mode Limits Parameter f XIN lt 40 MHz TBIIN input cycle time f XIN lt 25 MHz f XiN lt 40 MHz TBIIN input high level pulse width f XIN 25 MHz f XIN lt 40 MHz TBIIN input low level pulse width f XIN lt 25 MHz Note The TBilN input cycle time requires 4 or more cycles of count source The TBIIN input high level pulse width and the TBilN input low level pulse width respectively require 2 or more cycles of the count source The limits in the table are the values when the count source is f XIN 4 in high speed running f XIN lt 40 MHz and when the count source is f XIN 2 in low speed running f XIN 25 MHz At this time the clock source select bit is 0 A D trigger input Symbol Parameter c AD ADTRG input cycle time min
105. e 0 Select one from 0 to 2 with bits 4 and 5 of processor 1 mode register 0 Fig 13 Interrupt priority detection time 20 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 10 sant M37754M8C XXXGP M37754M8C XXXHP ooa to crate si M37754S4CGP M37754S4CHP gree ie W 2 ove PEG so SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Processor mode register 0 5E16 Processor mode bits 00 Single chip mode 01 Memory expansion mode 10 Microprocessor mode 11 Do not select Internal memory access bus cycle select bit Note Internal memory access condition in high speed running 0 2 access for internal RAM 3 9 access for internal ROM and SFR 1 2 6 access for internal RAM internal ROM SFR Software reset bit The microcomputer is reset when this bit is set to 1 Interrupt priority detection time select bit 0 0 Select 0 in Figure 13 0 1 Select 1 in Figure 13 10 Select 2 in Figure 13 Test mode bit This bit must be 0 Clock 1 output select bit 0 No 1 output 1 61 output Note When selecting low speed running set bit 2 to 0 Fig 14 Processor mode register 0 bit configuration TCo Particular function select register 1 6D16 Transmit clock output pin select bit Normal mode output only to CLKo Plural clocks specified output to CLKo Plural clocks specified output to CLKSo Plura
106. e 1 25 External clock input high level pulse width Note 2 tc 2 8 External clock input low level pulse width Note 2 tc 2 8 External clock rise time External clock fall time tsu PiD E Port Pi input setup time i 0 11 th E PiD Port Pi input hold time i 0 11 k f XIN 20 MHz when the clock source select bit 1 Notes 1 When the clock source select bit 1 tc s minimum limit is 50 ns 2 When the clock source select bit 1 set tw H tc and tw L tc ratios to 45 to 55 96 Parameter Switching characteristics Vcc 5 V 10 96 Vss 0 V Ta 20 to 85 C f XIN 40 MHz when the clock source select bit 0 unless otherwise noted Single chip mode Limits Min Max Parameter Port Pi data output delay time i 0 11 60 k f XIN 20 MHz when the clock source select bit 1 w H tw L td E PiQ Port Pi output i 2 0 11 tsu PiD E th E PiD Port Pi input I i 0 11 Test conditions e Vcc 5 V 10 96 e Intput timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VoH 2 0 V CL 100 pF MITSUBISHI m ELECTRIC MITSUBISHI MICROCOMPUTERS M37754M8C XXXGP M37754M8C XXXHP oso eS a ae M37754S4CGP M37754S4CHP SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f XIN 25 MHz wh
107. e input signal from the TBiIN pin is counted when the count start flag is 1 and counting is stopped when it is 0 Count is performed at the fall of the input signal when bits 2 and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is EU When bit 3 is 1 and bit 2 is 0 count is performed at the rise and fall of the input signal Data write data read and timer interrupt are performed in the same way as for timer mode 3 Pulse period measurement pulse width measurement mode 10 Figure 38 shows the bit configuration of the timer Bi mode register during pulse period measurement pulse width measurement mode In pulse period measurement pulse width measurement mode bit 0 must be 0 and bit 1 must be 1 Bits 6 and 7 are used to select the clock source The selected clock is counted when the count start flag is 1 and counting stops when it is 0 The pulse period measurement mode is selected when bit 3 is 0 In pulse period measurement mode the selected clock is counted dur ing the interval starting at the fall of the input signal from the TBilN pin to the next fall or at the rise of the input signal to the next rise the result is stored in the reload register In this case the reload register acts as a buffer register When bit 2 is 0 the clock is counted from the fall of the input signal to the next fall When bit 2 is 1 the clock is counted from the rise of the input sig
108. e output 1 One shot pulse output Fix to 011 in three phase waveform mode Clock source select bit 0 0 Select Pf2 1 Select Pf16 1 0 Select Pfe4 1 Select Pfs12 Address Timer B2 mode register 5D16 Fix to 00 in three phase waveform mode Not used in three phase waveform mode Clock source select bit 0 0 Select Pf2