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ICSI IS61C632A 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

1. OE Com 5 5 Ind 10 10 POWER SUPPLY CHARACTERISTICS Over Operating Range 4 5 6 7 8 Symbol Parameter Test Conditions Typ Max Max Max Max Unit Icc AC Operating Device Selected Com 150 180 140 170 130 160 120 150 110 140 mA Supply Current All Inputs Vit or Vin Ind 140 170 130 160 120 150 pA OE Cycle Time gt tkc min IsB Standby Current Device Deselected Com 15 45 15 45 15 45 15 45 15 45 Vcc Max Ind 20 50 20 50 20 50 pA All Inputs or Vi CLK Cycle Time gt min 77 Power Down Mode ZZ Vcca CLK Running Com 1 10 1 10 1 10 1 10 1 10 Current All Inputs lt GND 0 2V Ind 2 20 2 20 2 20 mA or 2 Vcc 0 2V Note 1 MODE pin has an internal pull up ZZ pin has an internal pull down These pins may be a No Connect tied to GND or tied to Vcca 2 MODE pin should be tied to Vcc or GND They exhibit 10 A maximum leakage current when tied to lt GND 0 2V gt Vcc 0 2V 6 Integrated Circuit Solution Inc 55 001 0 1561 632 CAPACITANCE Symbol Parameter Conditions Max Unit Input Capacitance Vin OV 6 pF Cour Input Output Capacitance Vour OV 8 pF Notes 1 Tested initially and after any design or process changes that may affect these parameters 2 Test conditions TA 25 C f 1 MHz Vcc 3 3V AC TEST CONDITIONS Parameter Unit
2. 15 ns Clock High Time 4 6 ns Clock Low Time 4 6 ns tas Address Setup Time 25 25 25 25 25 ns tss Address Status Setup Time 25 25 25 25 25 ns tws Write Setup Time 2 5 25 25 25 25 ns tps Data In Setup Time 25 25 25 25 25 ns tcEs Chip Enable Setup Time 25 25 25 25 25 ns tavs Address Advance Setup Time 25 25 25 25 25 ns tAH Address Hold Time 05 05 05 05 05 ns tsH Address Status Hold Time 05 05 05 05 05 ns Data In Hold Time 0 5 05 0 5 0 5 0 5 ns twH Write Hold Time 05 05 05 05 05 ns Chip Enable Hold Time 05 05 05 05 05 ns Address Advance Hold Time 05 05 05 05 05 ns tcre Configuration Setup 25 35 45 52 60 ns Notes 1 Configuration signal MODE is static and must not change during normal operation 10 Integrated Circuit Solution Inc 55 001 0 1561 632 S WRITE CYCLE TIMING gt CLK tss ae mer ADSP is blocked by inactive ADSP ADSC initiate Write ADV must be inactive for ADSP Write 1AVS tws XR 1 Masks ADSP nd only sampled with ADSP or ADSC Unselected with CE2 DATAN HighZ lt
3. Input Pulse Level OV to 3 0V Input Rise and Fall Times 1 5 ns Input and Output Timing 1 5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS Output Buffer Figure 1 Integrated Circuit Solution Inc SSR001 0B 5 pF p Including jig and Scope Figure 2 1561 632 READ CYCLE SWITCHING CHARACTERISTICS Over Operating Range Symbol Parameter s Max Min fiis Min Unit 8 10 12 13 15 ns Clock High Time 4 6 ns Clock Low Time 4 4 6 6 ns tka Clock Access Time 4 5 6 7 8 ns tkax Clock High to Output Invalid 15 15 2 2 2 ns tkaz Clock High to Output Low Z 0 0 0 0 0 ns tkauz Clock High to Output High Z 1 5 4 1 5 5 2 6 2 6 2 6 ns Output Enable to Output Valid 4 5 6 6 6 ns toeax Output Disable to Output Invalid 0 0 0 0 0 ns toez Output Enable to Output Low Z 0 0 0 0 0 ns toEHzC Output Disable to Output High Z 45 48 6 6 6 ns tas Address Setup Time 25 25 25 25 25 ns tss Address Status Setup Time 25 25 25 25 25 ns tws Write Setup Time 25 25 25 25 25 ns tcEs Chip Enable Setup Time 25 25 25 25 25 ns tavs
4. 0 1561 632 sS SNOOZE AND RECOVERY CYCLE TIMING C n EN EV m c m DATAOUT High DATAN High Single Read Snooze with Data Retention gt lt Read Integrated Circuit Solution Inc 15 SSR001 0B 1561 632 ORDERING INFORMATION Commercial Range 0 C to 70 C Speed ns Order Part Number Package 4 1IS61C632A 4TQ 14 20 1 4 LQFP 4 IS61C632A 4PQ 14 20 2 7mm PQFP 5 IS61C632A 5TQ 14 20 1 4 LQFP 5 1561 632 5 14 20 2 7mm PQFP 6 IS61C632A 6TQ 14 20 1 4 LQFP 6 1IS61C632A 6PQ 14 20 2 7mm PQFP 7 1561 632 7 14 20 1 4mm LQFP 7 1561 632 7 14 20 2 7mm PQFP 8 861C632A 8TQ 14 20 1 4 LQFP 8 IS61C632A 8PQ 14 20 2 7mm PQFP Industrial Range 40 to 85 C Speed ns Order Part Number Package 6 1561 632 6 14 20 1 4mm LQFP 6 1561 632 6 14 20 2 7mm PQFP 7 1561 632 7 14 20 1 4mm LQFP 7 1561 632 7 14 20 2 7mm PQFP 8 1561 632 8 14 20 1 4mm LQFP 8 1561 632 8 14 20 2 7mm PQFP CSI Integrated Circuit Solution Inc HEADQUARTER NO 2 TECHNOLOGY RD V SCIENCE BASED INDUSTRIAL PARK HSIN CHU TAIWAN R O C TEL 886 3 5780333 Fax 886 3 5783000 BRANCH OFFICE 106 SEC 1 HSIN TAI 5 ROAD HSICHIH TAIPEI COUNTY TAI
5. 0 0 ns tkauz Clock High to Output High Z 1 5 4 1 5 5 2 6 2 6 2 6 ns Output Enable to Output Valid 45 5 6 6 6 ns toeEax Output Disable to Output Invalid 0 0 0 0 0 ns 2 9 Output Enable to Output Low Z 0 0 0 0 ns 2 9 Output Disable to Output High Z 45 48 6 6 6 ns tas Address Setup Time 25 25 25 25 25 ns tss Address Status Setup Time 25 25 25 25 25 ns tcEs Chip Enable Setup Time 25 25 25 25 25 ns Address Hold Time 05 05 05 05 05 ns tsH Address Status Hold Time 05 05 05 05 05 ns Chip Enable Hold Time 0 5 05 05 05 05 ns tzzs ZZ Standby tzzrec ZZ Recovery tcre Configuration Setup 25 35 45 52 60 ns Notes 1 2 3 4 5 1 4 The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified Data retention is guaranteed when ZZ is asserted and clock remains active ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state Configuration signal MODE is static and must not change during normal operation Guaranteed but not 100 tested This parameter is periodically sampled Tested with the load in Figure 2 Integrated Circuit Solution Inc 55 001
6. Address Advance Setup Time 25 25 25 25 25 ns tAH Address Hold Time 05 05 05 05 05 ns tsH Address Status Hold Time 05 05 05 05 05 ns twH Write Hold Time 05 05 05 05 05 ns Chip Enable Hold Time 0 5 05 05 0 5 05 ns tAVH Address Advance Hold Time 05 0 5 05 05 05 ns tcre Configuration Setup 25 35 45 66 7 80 ns Notes 1 Configuration signal MODE is static and must not change during normal operation 2 Guaranteed but not 10096 tested This parameter is periodically sampled 3 Tested with the load in Figure 2 Integrated Circuit Solution Inc 55 001 0 1561 632 s i READ CYCLE TIMING lt tkC CLK tss Taani ADSP is blocked by CE inactive tss ADSC initiate read AVS tAVH Suspend Burst Masks ADSP nd CE3 only sampled with ADSP or ADSC Unselected with DATAOUT High Z DATAN lt Pipelined Read gt lt lt Single Read Burst Read gt lt Unselected Integrated Circuit Solution Inc 9 SSR001 0B 1561 632 WRITE CYCLE SWITCHING CHARACTERISTICS Over Operating Range Symbol Parameter sie Ki ux Min fiis Min Unit 8 10 12 13
7. Single Write Burst Write r Write gt Unselected gt Integrated Circuit Solution Inc 11 SSR001 0B 1561 632 READ WRITE CYCLE SWITCHING CHARACTERISTICS Over Operating Range Symbol Parameter s Max i ex Min Min Unit 8 10 12 13 15 ns Clock High Time 4 6 ns Clock Low Time 4 4 6 6 ns tka Clock Access Time 4 5 6 7 8 ns tkax Clock High to Output Invalid 15 15 2 2 2 ns tkaz Clock High to Output Low Z 0 0 0 0 0 ns tkauz Clock High to Output High Z 1 5 4 1 5 5 2 6 2 6 2 6 ns Output Enable to Output Valid 45 48 6 6 6 ns toeax Output Disable to Output Invalid 0 0 0 0 0 ns toez Output Enable to Output Low Z 0 0 0 0 ns toEHzC Output Disable to Output High Z 45 48 6 6 6 ns tas Address Setup Time 25 25 25 25 25 ns tss Address Status Setup Time 25 25 25 25 25 ns tws Write Setup Time 25 25 25 25 25 ns Chip Enable Setup Time 25 25 25 25 25 ns tAH Address Hold Time 05 05 05 05 05 ns tsH Address Status Hold Time 05 05 05 05 05 ns twH Write Hold Time 05 05 05 05 05 ns tc
8. 1561 632 lt SI 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM FEATURES Fast access time 4ns 125 MHZ 5 ns 100 MHz 6 ns 83 MHz 7 ns 75 MHz 8 ns 66 MHz Internal self timed write cycle control Pentium or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power down control by ZZ input JEDEC 100 Pin LQFP and PQFP package Single 3 3V power supply Two Clock enables and one Clock disable to eliminate multiple bank bus contention Control pins mode upon power up MODEin interleave burst mode ZZ normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power up state Individual Byte Write Control and Global Write Clock controlled registered address data and DESCRIPTION The CSI 1S61C632A is a high speed low power synchro nous static RAM designed to provide a burstable high perfor mance secondary cache for the i486 Pentium 680X0 and PowerPC microprocessors It is organized as 32 768 words by 32 bits fabricated with CST s advanced CMOS technology The device integrates a 2 bit burst counter high speed SRAM core and high drive capability outputs into a single monolithic circuit All synchronous inputs pass through registers controlled by a positive edge triggered single clock input Write cycles are internally self tim
9. EH Chip Enable Hold Time 05 05 05 05 05 ns tcre Configuration Setup 25 35 45 52 60 ns Notes 1 Configuration signal MODE is static and must not change during normal operation 2 Guaranteed but not 10096 tested This parameter is periodically sampled 3 Tested with the load in Figure 2 12 Integrated Circuit Solution Inc 55 001 0 1561 632 S READ WRITE CYCLE TIMING gt CLK iss T sds d ADSP is blocked by CET inactive ADSP ADSC CES Masks ADSP CES CE2 and only sampled with ADSP or ADSC CE2 Unselected with CE3 DATAOUT High Z DATAN High Z Single Read gt lt Single Write gt Burst Read Unselected Integrated Circuit Solution Inc 13 SSR001 0B 1561 632 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Over Operating Range Symbol Parameter ae a Max Mi es Min ix Min 7n Unit 8 10 12 13 15 ns Clock High Time 4 6 ns Clock Low Time 4 4 6 6 ns tka Clock Access Time 4 5 6 7 8 ns tkaxX Clock High to Output Invalid 15 15 2 2 2 ns tkaz 9 Clock High to Output Low Z 0 0 0
10. K 2 Wait states are inserted by suspending burst 3 X means don t care WRITE L means any one or more byte write enable signals BW1 BW4 and BWE are LOW GW is LOW WRITE H means all byte write enable signals are HIGH 4 For a Write operation following a Read operation OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time 5 ADSP LOW always initiates an internal READ at the Low to High edge of clock A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L H edge of clock PARTIAL TRUTH TABLE FUNCTION GW BWE BWI BW2 BW4 READ H H X X X X READ H X H H H H WRITE Byte 1 H L L H H H WRITE All Bytes X L L L L L WRITE All Bytes L X X X X X Integrated Circuit Solution Inc 55 001 0 1561 632 INTERLEAVED BURST ADDRESS TABLE Vcca or No Connect External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE MODE GNDa 7 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit TBIAS Temperature Under Bias 10 to 85 TsTG Storage Temperature 55 to 150 Power Dissipation 1 8 W louT Output Current per I O 100 mA Vin Vout Voltage Relative to GND for I O Pins 0 5 to Vcca 0 3 V VIN Volta
11. NTER 32K x 32 MEMORY ARRAY ADDRESS REGISTER D Q DQ32 DQ25 BYTE WRITE REGISTERS D Q DQ24 DQ17 BYTE WRITE REGISTERS D Q DQ16 DQ9 BYTE WRITE REGISTERS D Q 008 001 BYTE WRITE REGISTERS D Q INPUT OUTPUT ENABLE REGISTERS REGISTERS DATA 32 1 REGISTER ENABLE DELAY REGISTER 2 Integrated Circuit Solution Inc 55 001 0 1561 632 CONFIGURATION 100 LQFP PQFP View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Room cL o OC RC 21 22 O 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN DESCRIPTIONS 0 14 Address Inputs OE Output Enable CLK Clock DQ1 DQ32 Data Input Output ADSP Processor Address Status ZZ Sleep Mode ADSC Controller Address Status MODE Burst Sequence Mode ADV Burst Address Advance Vcc 3 3V Power Supply BW1 BW4 Synchronous Byte Write Enable GND Ground BWE Byte Write Enable Isolated Output Buffer Supply GW Global Write Enable CE2 Synchronous Chip Enable GNDa Isolated Output Buffer Ground Integrated Circuit
12. Solution Inc SSR001 0B 1561 632 TRUTH TABLE ADDRESS OPERATION USED ADSP ADSC ADV WRITE OE Deselected Power down None H X X X L X X X High Z Deselected Power down None L L X L X X X X High Z Deselected Power down None L X H L X X X X High Z Deselected Power down None L L X H L X X X High Z Deselected Power down None L X H H L X X X High Z Read Cycle Begin Burst External L H L L X X X L Q Read Cycle Begin Burst External L H L L X X X H High Z Write Cycle Begin Burst External L H L H L X L X D Read Cycle Begin Burst External L H L H L X H L Q Read Cycle Begin Burst External L H L H L X H H High Z Read Cycle Continue Burst Next X X X H H L H L Q Read Cycle Continue Burst Next X X X H H L H H High Z Read Cycle Continue Burst Next H X X X H L H L Q Read Cycle Continue Burst Next H X X X H L H H High Z Write Cycle Continue Burst Next X X X H H L L X D Write Cycle Continue Burst Next H X X X H L L X D Read Cycle Suspend Burst Current X X X H H H H L Q Read Cycle Suspend Burst Current X X X H H H H H High Z Read Cycle Suspend Burst Current H X X X H H H L Q Read Cycle Suspend Burst Current H X X X H H H H High Z Write Cycle Suspend Burst Current X X X H H H L X D Write Cycle Suspend Burst Current H X X X H H L X D Notes 1 All inputs except OE must meet setup and hold times for the Low to High transition of clock CL
13. WAN R O C TEL 886 2 26962140 FAX 886 2 26962252 http www icsi com tw 16 Integrated Circuit Solution Inc 55 001 0
14. ed and are initiated by the rising edge of the clock input Write cycles can be from one to four bytes wide as controlled by the write control inputs Separate byte enables allow individual bytes to be written BW1 controls DQ1 DQ8 BW2 controls DQ9 DQ16 BW3 controls DQ17 DQ24 BW4 controls DQ25 DQ32 conditioned by BWE being LOW A LOW on GW input would cause all bytes to be written Bursts can be initiated with either ADSP Address Status Processor or ADSC Address Status Cache Controller input pins Subsequent burst addresses can be generated internally by the IS61C632A and controlled by the ADV burst address advance input pin Asynchronous signals include output enable OE sleep mode input ZZ clock CLK and burst mode input MODE A HIGH input on the ZZ pin puts the SRAM in the power down state When ZZ is pulled LOW or no connect the SRAM normally operates after three cycles of the wake up period LOW input i e GNDa on MODE pin selects LINEAR Burst A Vcca or no connect on MODE pin selects INTERLEAVED Burst ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product We assume no responsibility for any errors which may appear in this publication Copyright 2000 Integrated Circuit Solution Inc Integrated Circuit Solution Inc 55 001 0 1561 632 Sr BLOCK DIAGRAM 90 gt CLK BINARY COU
15. ge Relative to GND for 0 5 to 5 5 V for Address and Control Inputs Notes 1 Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 This device contains circuity to protect the inputs against damage due to high static voltages or electric fields however precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit 3 This device contains circuitry that will ensure the output devices are in High Z at power up Integrated Circuit Solution Inc 55 001 0 1561 632 Gr OPERATING RANGE Range Ambient Temperature Vcc Commercial 0 C to 70 C 3 3V 10 5 Industrial 40 to 85 C 3 3V 10 596 DC ELECTRICAL CHARACTERISTICS Over Operating Range Symbol Parameter Test Conditions Min Max Unit VoH Output HIGH Voltage loH 2 5 0 mA 2 4 V VoL Output LOW Voltage lo 5 0 mA 0 4 V ViH Input HIGH Voltage 20 0 3 V ViL Input LOW Voltage 0 3 0 8 V Input Leakage Current GND lt Vin lt Vcca 5 5 Ind 10 1 ILo Output Leakage Current GND x Vout lt

ICSI IS61C632A 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

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