FDT IDT54/74FCT162H272AT/CT/ET handbook
Contents
1. CEA1B 1 CE1B CEA2B 2 55 CE2B 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 Vcc 7 50 Vcc A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 SO56 1 43 2B12 SO56 2 A7 15 SO56 3 42 1B12 As 16 41 1B11 Ag 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 Voc 22 35 Vcc 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 82 GND 1B3 26 31 1B4 OEA 27 30 OEB SEL 28 29 CLK SSOP 3071 drw 02 TSSOP TVSOP TOP VIEW MILITARY AND COMMERCIAL TEMPERATURES RANGES CEA1B 1 56 CE1B CEA2B 2 55 CE2B 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 Vcc 7 50 Vcc A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 E56 1 43 2B12 A7 15 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 Vcc 22 35 Vcc 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 OEA 27 30 OEB SEL 28 29 CLK 3071 drw 03 CERPACK TOP VIEW 5 5 2 IDT54 74FCT162H272AT CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMP2. FAST CMOS IDT54 74FCT162H272AT CT ET 12 BIT SYNCHRONOUS BUS EXCHANGER FEATURES e 0 5 MICRON CMOS Technology e Typical tsK o Output Skew c 250ps Low input and output leakage lt 11 A max e ESD gt 2000V per MIL STD 883 Method 3015 gt 200V using machine model C 200pF R 0 Packages include 25 mil pitch SSOP 19 6 mil pitch TSSOP 15 7 mil pitch TVSOP and 25 mil pitch Cerpack s Extended commercial range of 40 C to 85 C e Balanced Output Drivers 24mA commercial 16mA military e Reduced system switching noise Typical VOLP Output Ground Bounce lt 0 6V at Vcc 5V TA 25 C e Bus Hold retains last active bus state during 3 state Eliminates the need for external pull up resistors multiplexers for use in synchronous memory interleaving applications All registers have a common clock and use a clock enable CExxx on each data register to control data sequencing The output enables and mux select OEA OEB and SEL are also under synchronous control allowing direc tion changes to be edge triggered events The tri port bus exchanger has three 12 bit ports Data may be transferred between the A port and either both of the B ports The clock enable CE1B CE2B CEA1B and CEA2B inputs control the data storage Both B ports have acommon output enable OEB to aid in synchronously loading the B registers from the B port The FCT162H272AT CT E
3. ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS Poe 7 0V Vcc 5009 VIN V OUT Pulse GA fo 4 Generator D U T 50pF R as 5002 T CL 3071 Ink 04 SET UP HOLD AND RELEASE TIMES 3V RAT AXX ov tsu tH wa gt iu INPUT ov ASYNCHRONOUS CONTROL m t REM PRESET 3V CLEAR 1 5V ETC OV SYNCHRONOUS CONTROL PRESET 3V CLOCK ENABLE tH ov ETC ol eel 3071 Ink 05 PROPAGATION DELAY 3V SAME PHASE 1 5V INPUT TRANSITION ov tPLH tPHLJf VOH OUTPUT 1 5V VOL tPLH tPHL 3V OPPOSITE PHASE 1 5V INPUT TRANSITION OV 3071 Ink 07 5 5 MILITARY AND COMMERCIAL TEMPERATURES RANGES SWITCH POSITION Test Switch O Open Drain Disable Low Closed Enable Low All Other Tests DEFINITIONS 3032 tbl 11 CL Load capacitance includes jig and probe capacitance Rt Termination resistance should be equal to Zour of the Pulse Generator PULSE WIDTH LOW HIGH LOW PULSE 1 5V a tw gt 1 5V HIGH LOW HIGH PULSE 3071 Ink 06 ENABLE AND DISABLE TIMES ENABLE DISABLE 3V CONTROL 1 5V INPUT Il gy gt PZL gt tPLZ OUTPUT Wie T 5V 3 5V SWITCH A CLOSED 1 5V 2 VOL gt PZH gare VOH OUTPUT SWITCH HORMA T OPEN J a HIGH ov 3071 drw 08 NOTES 1 Diagram shown for input Control Enable LOW and inp
4. CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES NETT SUPPLV CHARACTERISTICS Test Conditions Ta Inputs HIGH Vin 3 4V 9 Dynamic Power Supply Current Vcc Max VIN Vcc Outputs Open VIN GND One Output Port Enabled CExx GND One Input Bit Toggling One Output Bit Toggling 50 Duty Cycle Total Power Supply Current 6 Vcc Max VIN Vcc Outputs Open VIN GND fi 10MHz 50 Duty Cycle VIN 3 4V One Output Port Enabled Vin GND CExx GND One Input Bit Toggling One Output Bit Toggling Vcc Max VIN Vcc Outputs Open VIN GND fi 2 5MHz 50 Duty Cycle VIN 3 4V One Output Port Enabled Vin GND CExx GND Twelve Input Bits Toggling Twelve Output Bits Toggling NOTES 3071 tbl 09 For conditions shown as Max or Min use appropriate value specified under Electrical Characteristics for the applicable device type Typical values are at Vcc 5 0V 25 C ambient Per TTL driven input Vin 3 4V All other inputs at Vcc or GND This parameter is not directly testable but is derived for use in Total Power Supply Calculations Values for these conditions are examples of the Icc formula These limits are guaranteed but not tested Ic QUIESCENT INPUTS IDYNAMIC Ic lcc Alcc DHNT Icen fcPNcp 2 fiNi Icc Quiescent Current IccL lccH and Iccz Alcc Power Supply Current for a TTL High Input VIN 3 4V DH Duty Cycle for TTL Input
5. ERATURES RANGES PIN DESCRIPTION Signal 1 0 Description A 1 12 O l Bidirectional Data Port A Usually connected to the CPU s Address Data bus 1 1B 1 12 VO Bidirectional Data Port 1B Usually connected to the even path or even bank of memorv 1 2B 1 12 O Bidirectional Data Port 2B Usually connected to the odd path or odd bank of memorv 1 CLK Clock Input CEAIB Clock Enable Input for the A 1B Register If CEA1B is LOW during the rising edge of CLK data will be clocked into register A 1B Active LOW CEA2B Clock Enable Input for the A 2B Register If CEA2B is LOW during the rising edge of CLK data will be clocked into register A 2B Active LOW CE1B Clock Enable Input for the 1B A Register If CE1B is LOW during the rising edge of CLK data will be clocked into register 1B A Active LOW CE2B Clock Enable Input for the 2B A Register If CE2B is LOW during the rising edge of CLK data will be clocked into register 2B A Active LOW SEL 1B or 2B Path Selection When HIGH during the rising edge of CLK SEL enables data transfer from 1B Port to A Port When LOW during the rising edge of CLK SEL enables data transfer from 2B Port to A Port OEA l Synchronous Output Enable for A Port Active LOW OEB l Synchronous Output Enable for 1B Port and 2B Port Active LOW NOTES 3071 tbl 01 1 On FCT162H272T these pins have Bus Hold All other pins are standard inputs outputs
6. T have balanced output drive with current limiting resistors This offers low ground bounce minimal undershoot and controlled output fall times reducing the need for external series terminating resistors The FCT162H272AT CT ET have Bus Hold which re tains the input s last state whenever the input goes to high impedance This prevents floating inputs and eliminates the need for pull up down resistors DESCRIPTION The FCT162H272AT CT ET synchronous tri port bus ex changers are high speed bidirectional 12 bit registered bus FUNCTIONAL BLOCK DIAGRAM CEA1B CEs A 4B CLK REGISTER 1B1 IMMA Ll l i l CE1B CE 1B A REGISTER 15 p D 12 See CONTROL Q OEB REGISTER 12 OEA A1 12 lt CE2B CE 2B A REGISTER 12 E 7e 12 CEA2B CE A 2B EGISTER Q gt Q mr gt 2B1 12 3071 drw 01 The IDT logo is a registered trademark of Integrated Device Technology Inc MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996 1996 Integrated Device Technology Inc 5 5 DSC 3071 3 1 IDT54 74FCT162H272AT CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER PIN CONFIGURATIONS NI s6
7. Unless Otherwise Specified Commercial TA 40 C to 85 C Vcc 5 0V 10 Military TA 55 C to 125 C Vcc 5 0V 10 symbot Parameter Test Conditions Min Typ 2 Max Unit PVH jmuiGileel Sanese Level OO eo ve Pinto it Funes vt Pas HIGH Standard 1 0 Input Standard Input Low Bus Hold Bus Hold Input Vcc Min Sustain Current 4 High Impedance Output Current 3 State pupi pins 56 Input Hvsteresis Quiescent Power Supply Current Vcc Max VIN GND or Vcc OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T symbol Parameter Test Conditions Output LOW Current Vcc 5V VIN VIH or VIL VouT 1 5V 9 Output HIGH Current Vcc 5V VIN VIH or VIL VouT 1 5V 3 Output HIGH Voltage Vcc Min lOH 16mA MIL VIN VIH or VIL IOH 24mA COM L Output LOW Voltage Vcc Min loL 16mA MIL 0 3 0 55 V VIN VIH or VIL IOL 24mA COM L NOTES 3071 Ink 08 For conditions shown as Max or Min use appropriate value specified under Electrical Characteristics for the applicable device type Typical values are at Vcc 5 0V 25 C ambient Not more than one output should be tested at one time Duration of the test should not exceed one second Pins with Bus Hold are identified in the pin description The test limit for this parameter is 5uA at Ta 55 C Does not include Bus Hold I O pins Oaronw gt s 5 5 4 IDT54 74FCT162H272AT
8. or I Os ABSOLUTE MAXIMUM RATINGS FUNCTION TABLES VTERM 2 Terminal Voltage with Respect to 9 5 to 7 0 V GND VtTERM 3 Terminal Voltage with Respect to 0 5 to GND Vcc 40 5 Storage Temperature 65 to 150 DC Output Current 60 to 120 NOTES 3071 tbl 02 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RAT INGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operational sections of this specifica tion is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 All device terminals except FCT162XXXT Output and I O terminals 3 Output and I O terminals for FCT162XXXT lt 3071 tbl 04 Outputs CAPACITANCE Ta 25 C F 1 0MHz Input Capacitance ald ka ka Capacitance NOTE 3071 tbl 03 1 This parameter is measured at characterization but not tested NOTES 3071 tbl 05 1 Output level before the indicated steady state input conditions were established 2 H HIGH Voltage Level L LOW Voltage Level X Don t Care Z High Impedance T LOW to HIGH Transition 5 5 3 IDT54 74FCT162H272AT CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE BUS HOLD Following Conditions Apply
9. s High Nt Number of TTL Inputs at DH Iccb Dynamic Current Caused by an Input Transition Pair HLH or LHL fcp Clock Frequency for Register Devices Zero for Non Register Devices NcP Number of Clock Inputs at fcP fi Input Frequency Ni Number of Inputs at fi PARON 5 5 5 IDT54 74FCT162H272AT CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE a oa a i RL 500Q ag i ad Ma al a Delay CEXxB Enabled CLKto Ax SEL Changing 4 1 CEXB Disabled SEL Changing 1 5 7 6 1 5 7 9 1 5 6 6 1 5 7 0 1 5 CExB Enabled Output Enable Time CLK to Ax CLK to 1Bx or CLK to 2Bx Output Disable Time CLK to Ax CLK to 1Bx or CLK to 2Bx el Data to CLK Set Up Time OEA to CLK OEB to CLK Set Up Time SEL to CLK Set Up Time CEA1B to CLK CE1B to CLK CE2B to CLK or CEA2B to CLK tH Hold Time CLK to Data tH Hold Time CLK to OEA CLK to OEB CLK to SEL Hold Time CLK to CEA1B CLK to CE1B CLK to CE2B CLK to CEA2B tw Pulse Width CLK HIGH tsk o Output Skew NOTES 3071 tbl 10 1 See test circuits and waveforms 2 Minimum limits are guaranteed but not tested on Propagation Delays 3 Skew between any two outputs of the same package switching in the same direction This parameter is guaranteed by design 4 This parameter is guaranteed but not tested 5 5 6 IDT54 74FCT162H272AT CT
10. ut Control Disable HIGH 2 Pulse Generator for All Pulses Rate lt 1 0MHz tF lt 2 5ns tR lt 2 5ns IDT54 74FCT162H272AT CT ET FAST CMOS 12 BIT SYNCHRONOUS TRI PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES ORDERING INFORMATION IDT XX FCT xX X XXXX X X Temp Range Drive Bus Hold Device Type Package Process Blank Commercial B MIL STD 883 Class B PV Shrink Small Outline Package SO56 1 PA Thin Shrink Small Outline Package S056 2 PF Thin Very Small Outline Package SO56 3 E CERPACK E56 1 272AT 12 Bit Synchronous Tri Port Bus Exchanger 272CT 272ET H Bus Hold 162 16 Bit Balanced Drive 54 55 C to 125 C 74 40 C to 85 C 3071 drw 09 5 5 8
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FDT IDT54/74FCT162H272AT/CT/ET handbook