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TEMIC Semiconductor e1217D 32 kHz Standard Watch CMOS IC

1. 5 i8 e1217D HIV EMIC Semiconductors e1217D 32 kHz Standard Watch CMOS IC Features 32 kHz oscillator 1 3 1 8 V operating voltage range 180 nA typical current consumption Voltage regulator Pad Configuration e1217D Integrated capacitors mask selectable Mask options for pad designation motor period and motor pulse width Low resistance outputs for bipolar stepping motor Motor fast test function General Description The e1217D is an integrated circuit in CMOS Silicon Gate Technology for analog watches It consists of a 32 kHz oscillator frequency dividers down to 1 64 Hz output pulse formers and push pull motor drivers For tuning of the crystal integrated capacitors are provided selectable mask option Low current consumption and high oscillator stability are enabled by an on chip voltage regulator Pin Symbol Function 1 4 Vss Negative supply voltage 3 6 5 6 8 Vpp Positive supply voltage 1 to 4 OSCIN Oscillator input output 4 5 OSCOUT o 7 5 or 7 6 MOT 1 2 Motor drive outputs 95 9979 1to 5 8 RESET Reset input 1 to 5 8 TEST _ Test input output Figure 1 Chip size 1 06 mm x 1 02 mm Pad size 112 um x 112 um pad window 100 x 100 Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage Vss 0 3 to 5 V Input v
2. an be used to reduce the amount of time re quired for testing the mechanical parts of the watch Cycle time TM Motor pulse width tm Motor test cycle time Tyr 2 4 6 8 10 12 20 24 30 40 60 80 120 s 0 98 to 14 65 ms in increments of 0 98 ms 250 125 62 5 ms 2 4 TELEFUNKEN Semiconductors Rev Al 08 May 96 TEMIC Semiconductors e1217D Operating Characteristics Vpp 0 V Vss 1 55 V Tamb 25 C CTR 15 pF unless otherwise specified All voltage levels are measured with reference to Vpp Test crystal as specified below Parameters Test Conditions Pins Symbol Min Typ Max Unit Operating voltage Functional test figure 2 Vss 1 3 1 8 V Operating current Coscout 16 pF RL Iss 180 300 nA RESET input current RESET Vpp Ir 8 nA Motor outputs Motor output current Ry 2 KQ Vss 1 55 V IM 0 7 mA Motor period TM s Motor pulse width TM Mask option ms Motor test period TMT ms Oscillator Stability AVss 100 mV Af f 0 1 ppm CTR 5 pF startup within 2 s Start up voltage VsT 1 3 V Integrated input capaci Cosc IN 12 pF tance ae output capaci CoscouTmax 24 pF Pe Nias option Note 1 Typical parameters represent the statistical mean values Vss RESET Range of trimmer capacitance Crp 5 pF to 30 pF mmi Test Crystal S
3. es arising out of directly or indirectly any claim of personal damage injury or death associated with such unintended or unauthorized use TEMIC TELEFUNKEN microelectronic GmbH P O B 3535 D 74025 Heilbronn Germany Telephone 49 0 7131 67 2831 Fax number 49 0 7131 67 2423 4 4 TELEFUNKEN Semiconductors Rev A1 08 May 96
4. oltage range all inputs VIN Vss 0 3 V lt Vin lt Vpp 0 3 V V Output short circuit duration indefinite Power dissipation DIL package Piot 125 mW Operating ambient temperature range Tamb 20 to 70 C Storage temperature range Tstg 40 to 70 C Lead temperature during soldering at 2 mm Tsld 260 C distance 10 s Absolute maximum ratings define parameter limits which if exceeded may permanently change or damage the device All inputs and outputs on TEMIC circuits are protected against electrostatic discharges However precautions to minimize the build up of electrostatic charges during handling are recommended The circuit is protected against supply voltage reversal for typically 5 minutes TELEFUNKEN Semiconductors Rev A1 08 May 96 14 e1217D TEMIC Semiconductors Functional Description Voltage Regulator An integrated voltage regulator provides the oscillator with a well controlled negative supply voltage VREG This improves the stability of the oscillator and keeps cur rent consumption at a minimum Oscillator An oscillator inverter with feedback resistor is provided for generation of the 32768 Hz clock frequency A total capacitance of 24 pF is integrated This can be selected for CoscoutT in 2 pF increments via a mask option Frequency Divider A 21 bit binary counter is provided dividing the oscillator frequency down to 1 64 Hz The leading six stages are connec
5. pecification N TEST MOTI 5 E requency f 32768 Hz e1217 Series resistance Rs 30 kQ Static capacitance Co 1 5 pF Dynamic capacitance C 3 fF CTR Ce 6 ne Load ne Ci 8 pF Za a Ri Additional Notes 1 Itis recommended to connect the quartz case to Vpp OSCOUT Vpp by conductive epoxy Q 2 Capacitive coupling of TEST to OSCIN must be minimized by appropriate layout of the PCB to avoid Figure 2 Functional test circuit disturbance of the oscillator TELEFUNKEN Semiconductors Rev A1 08 May 96 3 4 e1217D TEMIC Semiconductors TEST TT N A T MT ja M gt lt gt MOTI tM tM Mor LI LL a Tw 2 95 9981 Figure 3 Motor drive outputs in normal mode and motor test T lt tRIN T gt tRIN lt _ gt lt _ gt open 35 RESET tM S MOTI M Tw 2 tM k aS j _ S MOT2 nm gt TM 95 9982 Figure 4 Motor drive outputs and RESET We reserve the right to make changes to improve technical design and may do so without further notice Parameters can vary in different applications All operating parameters must be validated for each customer application by the customer Should the buyer use TEMIC products for any unintended or unauthorized application the buyer shall indemnify TEMIC against all claims costs damages and expens
6. ted to Vpp and Vprgc while the remaining 15 stages are connected to Vpp and Vss Motor Drive Output The e1217D contains two push pull output buffers for driving bipolar stepping motors During a motor pulse the n channel device of one buffer and the p channel de vice of the other buffer are activated The p channel devices of both buffers are active figure 3 between two the pulses Cycle time and pulse width can be chosen via a metal mask option table 1 Table 1 Motor options RESET A debounced RESET input is provided Connecting the RESET input to Vpp resets the low order 12 stages of the frequency divider thus disabling further motor pulses Motor pulses in progress when the reset function is ap plied are completed After releasing the RESET pad from Vpn the next motor pulse appears with a delay of one half motor cycle on the drive output opposed to the former figure 4 Due to the debounce circuitry on the RESET input Vpp must be applied for at least 31 2 ms During RESET the input current is limited to 8 nA typically Test A test frequency of 512 Hz is output to this pad which can be measured with a high resistance probe R 10 MQ C lt 20 pF This signal can be used for testing and tuning the oscillator Connecting TEST to Vpp for at least 4 ms changes the motor cycle time from the selected value to the test cycle time mask options while the motor pulse width remains unchanged figure 3 This feature c

TEMIC Semiconductor e1217D 32 kHz Standard Watch CMOS IC

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