ROHM BR9080AF-W BR9080ARFV-W BR9080ARFVM-W
Contents
1. BR9080ARFV BR9016ARFV SSOP B8 12 12 Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO LTD The contents described herein are subject to change without notice The specifications for the product described in this document are for reference only Upon actual use therefore please request that specifications to be separately delivered Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set Any data including but not limited to application circuit diagrams information described herein are intended only as illustrations of such devices and not as the specifications for such devices ROHM CO LTD disclaims any warranty that any use of such devices shall be free from infringement of any third party s intellectual property rights or other proprietary rights and further assumes no liability of whatsoever nature in the event of any such infringement or arising from or connected with or related to the use of such devices Upon the sale of any such devices other than for buyer s right to use such devices itself resell or otherwise2. HIGH during power up BR9O80AF W ARFV W ARFVM W BR9016AF W ARFV W ARFVM W comes up in the write disabled WDS state In order to be programmable it must receive a write enable WEN instruction The device remains programmable until a disable WDS instruction is entered or until it is powered down 2 It is unnecessary to add the clock after 16th clock 6 12 BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W 3 Read cycle BR9080AF W jana W ARFVM W ee H cs L J n N ij STANDBY i HIGH Z HIGH Z E MIH H cy Read Data n Read Data n 1 R B WC High or LOW Fig 4 BR9O080AF W ARFV W ARFVM W BR9016 AF W pie W ARFVM W H cs H L c o STANDBY o 30000 Gere L HIGH Z HIGH Z bo Zonar gt lt lt toH H T e F Read ce n 1 R B WGC High or LOW Fig 5 BR9016AF W ARFV W ARFVM W 1 After the fall of the 16th clock pulse 16 bit data is output from the DO pin in synchronization with the falling edge of the SK signal DO output changes at a time lag of trpo tep1 because of internal circuit delay following the falling edge of the SK signal During the troo and tep timing the trp time should be assured before data is read to avoid the previous data being lost See the synchronized data input output timing chart in Fig 2 2 The data stored in the next address is clocked out o
3. dispose of the same no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO LTD is granted to any such buyer Products listed in this document use silicon as a basic material Products listed in this document are no antiradiation design The products listed in this document are designed to be used with ordinary electronic equipment or devices such as audio visual equipment office automation equipment communications devices electrical appliances and electronic toys Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life such as medical instruments transportation equipment aerospace machinery nuclear reactor controllers fuel controllers and other safety devices please be sure to consult with our sales representative in advance About Export Control Order in Japan Products described herein are the objects of controlled goods in Annex 1 Item 16 of Export Trade Control Order in Japan In case of export from Japan please confirm if it applies to objective criteria or an informed by MITI clause on the basis of catch all controls for Non Proliferation of Weapons of Mass Destruction Appendix1 Rev1 0
4. power supply is turned on in this state erroneous operations and erroneous writing can occur because of noise and other factors To avoid this make sure CS is set to HIGH Vcc before turning on the power supply Good example Here the CS pin is pulled up to Vcc When tuming off the power supply wait at least 10msec before tuming it on again Failing to observe this condition can result in the internal circuit failing to be reset when the power supply is turned on Bad example CS is LOW when the power supply is turned on or off In this case because CS remains LOW the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors Please be aware that the case shown in this example can also occur if CS input is HIGH Z Vcc GND Bad example Fig 9 2 Noise countermeasures 1 SK noise If noise occurs at the rise of the SK dock input the clock is assumed to be excessive and this can cause malfunction because the bits are out of alignment 2 WC noise During a writing operation noise at the WC pin can be erroneously judged to be data and this can cause writing to be forcibly interrupted 3 Vcc noise Noise and surges on the power supply line can cause malfunction We recommend installing a bypass capacitor between the power supply and ground to eliminate this problem 10 12 BR9080AF W BR9O80ARFV W BR9080ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W 3 Ca
5. 9O080ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W Block diagram INSTRUCTION DECODE CONTROL Ser SUPPLY CLOCK GENERATION VOLTAGE HIGH WRITE VOLTAGE DISABLE GENERATOR ADD DECORDER 8 192 bit EEPROM BR9016A is 10bit 16 384bit BR9080A is 9bit 8 192bit Pin descriptions Vcc R B WC GND wc GND DO ODI Vcc R B WC GND E j cs SK DI pO R B Voc CS SK cs sk DI BO SEEOODAREVM sore SEED sopp BRSORAREV sop Fig 1 Pin No USOR LSSOP SOP Pin name Function 1 3 CS Chip Select Control 2 4 SK Serial Data Clock Input 3 5 DI Op code address Serial Data Input 4 6 DO Serial Data Output 5 7 GND Ground OV 6 8 WC Write Control Input 7 1 R B READY BUSY Output 8 2 Vcc Power supply 2 12 BR9080AF W BR9O80ARFV W BR9080ARFVM W Memory ICs BR9016AF W BR9016AREV W BR9016AREVM W Absolute maximum ratings Ta 25 C Parameter Symbol Limits Unit Supply voltage Vcc 0 3 7 0 V SOP8 450 Power dissipation Pd SSOP B8 300 mW MSOP8 310 3 Storage temperature Tstg 65 125 C Operation temperature Topr 40 85 C Input voltage 0 3 Vcc 0 3 V 1 Reduced by 4 5mW for each increase in Ta of 1 C over 25 C 2 Reduced by 3 0mW for each increase in Ta of 1 C over 25 C 3 Reduced by 3 1mW for each increase in Ta of 1 C over 25 C Recommended operating conditions Ta 25 C Paramete
6. BR9080AF W BR9080ARFV W BR9080ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W 8k 16k bit EERPROMs for direct connection to serial ports BR9080AF W BR9O80ARFV W BR9080ARFVM W BR9016AF W BR9016ARFV W BR9016ARFVM W The BR9080A and BR9016A series are serial EEPROMs that can be connected directly to a serial port and can be erased and written electrically Writing and reading is performed in word units using four types of operation commands Communication occurs though CS SK DI and DO pins WC pin control is used to initiate a write disabled state enabling these EEPROMs to be used as one time ROMs During writing operation is checked via the internal status check Applications Movie camera cordless telephones car stereos VCRs TVs DIP switches and other battery powered equipment requiring low voltage and low current Features 1 BR9080AF W ARFV W ARFVM W 8k bit 512 words x16 bits BR9016AF W ARFV W ARFVM W 16k bit 1024 words x 16bits 2 Single power supply operation 3 Serial data input and output 4 Automatic erase before write 5 Low current consumption Active 5V 5mA max Standby 5V 3uA max 6 Noise filter built into SK pin 7 Write protection when Vcc is low Inhibition on inadvertant write with the WC pin SOP8 SSOP B8 MSOP8 High reliability CMOS process 100 000 ERASE WRITE cycles 10 years Data Retention 8 9 0 1 Sa 1 1 w aS 1 12 BR9080AF W BR
7. e internal status signal the R B pin outputs the HIGH or LOW status at all times The display can also be output from the DO pin Following completion of the writing command if CS falls while SK is LOW either HIGH or LOW is output The display can also be output without using the R B pin leaving it open 2 When writing data to a memory cell the READY BUSY display is output from the rise of the 32nd clock pulse of the SK signal after tSV from the R B pin R B display LOW writing in progress The intemal timer circuit is activated and after the tE W timing has been created the timer circuit stops automatically Writing of data to the memory cell is done during the tE W timing during which time other commands cannot be received R B display HIGH command standby state Writing of data to the memory cell has been completed and the next command can be received i READY BUSY READY Fig 8 R B Status Output timing chart 1 DO will output R B status after CS is held low during SK L until CS is held high Note The document may be strategic technical data subject to COCOM regulations 9 12 BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W Operation notes 1 Turning the power supply on and off 1 When the power supply is turned on and off CS should be set to HIGH Vcc 2 When CS is LOW the command input reception state active is entered If the
8. e twcH 0 ns Timing chart Synchronous Data Input Output Timing cs tois lt gt t i i T N tPD i lt gt tPD lt gt ton lt gt 2 lt oS gt Fig 2 Input data are clocked in to DI at the rising edge of the clock Sk Output data will toggle on the falling edge of the SK clock The WC pin does not have any effect on the READ EWEN and EWDS operations 5 12 BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W Circuit operation 1 Command mode BR9080A Instruction Start Bit Op Code Address Data Read READ 1010 100 AO A1 A2 A3 A4 A5 A6 A7 A8 Write WRITE 1010 010 AO A1 A2 A3 A4 A5 A6 A7 A8 DO D1 D14 D15 Write enable WEN 1010 0011 CEE Rk E E kk Write disable WDS 1010 0000 e E E E E E Means either VIH or VIL Address and data are transferred from LSB BR9016A Instruction Start Bit Op Code Address Data Read READ 1010 10 AO A1 A2 A3 A4 A5 A6 A7 A8 A9 Write WRITE 1010 01 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 DO D1 D14 D15 Write enable WEN 1010 0011 eR RK koko kokok Write disable WDS 1010 0000 Boko okoo k okoo Means either VIH or VIL Address and data are transferred from LSB 2 Writing enabled disabled SK 1 4 8 12 16 L UUUUUULUUUUU aa ENABLE 11 A DISABLE 00 cs DI HIGH Z DO H R B WC High or LOW Fig 3 1 When CS is
9. f the device on the falling edge of 32nd clock The data stored in the upper address every 16 clocks is output sequentially by the continual SK input Also the read operation is reset by CS High 7 12 BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W 4 Write cycle BR9080AF W ARFV W ARFVM W 5 A _ J gua EA 0 CO C2 00 3 S HIGH Z At lt gt i tcs HIGH Z it H Fig 6 BR9080AF W ARFV W ARFVM W BR9016 AF W ARFV W ARFVM W Fig 7 BR9016AF W ARFV W ARFVM W 1 At the rising edge of 32nd clock R B pin will be come out LOW after the specified time delay tSV 2 From above edge R B will indicate the ready busy status of the chip LOW indicated programming is all in progress HIGH indicates the write cycle is complete and this part is ready for another instruction 3 During the input of Write command CS must be LOW However once the write operation started CS could be either HIGH or LOW 4 If WC becomes HIGH during Write Cycle the write operation is halted In this case the address data in writing is no guaranteed It is necessary to rewrite it 8 12 BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W 5 READY BUSY display R B pin and DO pin BR9080AF W ARFV W ARFVM W BR9016AF W ARFV W ARFVM W 1 This display outputs th
10. nceling modes 1 Read commands 32 Clock i DI i Start bit Operating code 4 bits 4 bits 8 bits 16 bits DO Cancel can be performed for the entire read mode space gt WC HIGH or LOW Fig 10 Cancellation method CS HIGH 2 Write commands SK i cs DI i Operating code Address DO i Data D15 i 4 bits 4bits 8bits 16bits i lt E W gt i R B S S lt a gt i lt 4 b ri lt c gt lt d gt WC Fig 11 Canceling methods __ a Canceled by setting CS HIGH The WC pin is not involved a b If the WC pin goes HIGH for even a second writing is forcibly interrupted Cancellation occurs even if the CS pin is HIGH At this point data has not been written to the memory so the data in the designated address has not yet been changed c The operation is forcibly canceled by setting the WC pin to HIGH or turning off the power supply although we do not recommend using this method The data in the designated address is not guaranteed and should be written once again 2 d If CS is set to HIGH while the R B signal is HIGH following the tE W timing the IC is reset internally and waits for the next command to be input 11 12 BR9080AF W BR9O80ARFV W BR9080ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W External dimension Units mm BR9080ARFVM W BR9080AF BR9016ARFVM W f BR9016AF 0 29 0 15 bo 3 i D4 bS bo 0 6 0 2
11. r Symbol Min Typ Max Unit WRITE 2 7 5 5 V Power supply voltage Vcc READ 2 7 5 5 V Input voltage Vin 0 Vcc V 3 12 nonm BR9080AF W BR9O80ARFV W BR9O80ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W Electrical characteristics BR9080AF W ARFV W ARFVM W BR9016AF W ARFV W ARFVM W 5V Unless otherwise noted Ta 40 85 C Vcc 2 7V 5 5V Parameter Symbol Min Typ Max Unit Conditions Input low level voltage 1 Vii 0 3xVcc V DI pin Input high level voltage 1 Vint 0 7xVcc V DI pin Input low level voltage 2 Vive 0 2xVcc V CS SK WC pin Input high level voltage 2 Vine 0 8xVcc V CS SK WC pin Output low level voltage VoL 0 0 4 V loc 2 1mA Output high level voltage Vou Vcc 0 4 Vcc V lon 0 4MA Input leak current lu 1 1 HA Vin 0V Vcc Output leak current ILo 1 1 uA Vout 0V Voo CS Vec Opetating current Icc1 5 mA fsk 2MHz tE W 10ms WRITE Icc2 3 mA f amp K 2MHz READ Standby current Isp 3 uA CS SK DI WC Vcc DO R B OPEN SK frequency fsk 2 MHz BR9080AF W ARFV W ARFVM W BR9016AF W ARFV W ARFVM W 3V Unless otherwise noted Ta 40 85 C Vcc 2 7V 3 3V Parameter Symbol Min Typ Max Unit Conditions Input low level voltage 1 Vit 0 3xVec V DI pin Input high level voltage 1 Vim 0 7xVcc V DI pin Input low level vol
12. tage 2 Viz 0 2xVec V CS SK WC pin Input high level voltage 2 Vine 0 8xVcc V CS SK WC pin Output low level voltage VoL 0 0 4 V loc 100pHA Output high level voltage Von Vcc 0 4 Vcc V lon 100uA Input leak current lu 1 1 uA Vin 0V Voc Output leak current ILo 1 z 1 uA Vour 0V Vcc CS Vcc Operating current lcc1 3 mA fsk 2MHz tE W 10ms WRITE loc2 0 75 mA fsx 2MHz READ Standby current Isp 2 uA CS SK DI WC Vcc DO R B OPEN SK frequency fsk 2 MHz Not designed for radiation resistance 4 12 BR9080AF W BR9O080ARFV W BR9080ARFVM W Memory ICs BR9016AF W BR9016ARFV W BR9016AREVM W Operating timing characteristics BR9080AF W ARFV W ARFVM W BR9016AF W ARFV W ARFVM W Unless otherwise noted Ta 40 85 C Vcc 2 7V 5 5V Parameter Symbol Min Typ Max Unit CS setup time fcss 100 ns CS hold time tcsH 100 ns Data setup time tois 100 ns Data hold time tolH 100 ns DO rise delay time tpp1 150 ns DO fall delay time tPDo 150 ns Self timing programming cycle te w 10 ms CS minimum high level time tcs 250 ns READY BUSY display valid time tsv 150 ns Time when DO goes HIGH Z via CS toH 0 150 ns Data clock high level time twH 230 ns Data clock low level time twe 230 ns Write control setup time twcs 0 ns Write control hold tim
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