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MICROCHIP PIC24H Family Data Sheet

1. ui UMOUS 19598 0 pea s y uo X pu B 1 0000 SOL s 0 L2SdMO L 31v91L gt E NOL 2610 NO961 0000 Lx SOL cel lt 0 1 gt 5 1 31v91L NOL VELO 0581 dada 6 15 8510 dada 9 Ja sIBay 9610 83 velo GNL XXXX Ajuo suone1edo 1q z BUIPIOH 2610 T IHeHIALL XXXX 0610 8 4 0000 Lei SOL m zx 0 L2SdMO L 31v91L 5 2 za NOL 3210 NOOZL 0000 SOL cel 0 L2SdMO L 31v91L NOL 2010 0991 dada 1 1981694 Zed ERE 9 J9 sIB9yY POLISH 8210 9d Jouu 9210 Auo suonesado 1q z BUIPIOH 710 TIHZHIALL 9Jouul 2010 0000 SOL 0 L2SdMO L 31V9OL E II NOL 0210 0991 0000 a SOL cel 0 L2SdMO L 31v91L NOL ALLO dada Ja sIBay Sud dada
2. FIGURE 13 1 INPUT CAPTURE BLOCK DIAGRAM From 16 bit Timers TMRy TMRz ICxCON lt 7 gt Prescaler Edge Detection Logic FIFO DT Counter and R W 1 4 16 Clock Synchronizer Logic ICx Pin V 3 ICM lt 2 0 gt ICxCON lt 2 0 gt Mode Select 9 ICOV ICBNE ICxCON lt 4 3 gt ICxBUF 1 lt 1 0 gt Y Y Interrupt ICxCON Logic System Bus Set Flag ICxIF in IFSn Register Note An x in a signal register or bit name denotes the number of the capture channel 2006 Microchip Technology Inc Advance Information DS70175A page 143 PIC24H 13 1 REGISTER 13 1 Input Capture Registers ICxCON INPUT CAPTURE x CONTROL REGISTER U 0 U 0 R W 0 U 0 U 0 U 0 U 0 U 0 ICSIDL bit 15 bit 8 R W 0 R W 0 R W 0 R 0 HC R 0 HC R W 0 R W 0 R W 0 ICTMR ICI lt 1 0 gt ICOV ICBNE ICM lt 2 0 gt bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 bit 13 bit 12 8 bit 7 bit 6 5 bit 4 bit 3 bit 2 0 Note 1 Unimplemented Read as 0 ICSIDL Input Capture Module Stop in Idle Contro
3. UMOUS 1 4 0 SE 1 pajuawa dunun puaba7 0000 lt 0 L gt ASIN84 0 L 4SIN64 0 L SIAO LJ 0 L SIWN LL 0 L SINZL lt 0 L gt ASINE LA 0 51114 lt 0 L gt ASNGLA 150 ZTASHSN14Z9 0000 lt 0 L gt HSNO14 0 L 4SINL 0 51124 0 951164 0 5114 0 5114 lt 0 L gt ASIN94 lt 0 L gt HSWNZ4 8190 LIISASINIZO 0000 ON3114 ZN3114 FN3114 2 803114 MNAL 7 50 0000 lt 0Z gt D3SYd lt 0 2 gt Hd LAS WYS 51 92995 lt 0 2 gt 45 IIA 2190 294929 0000 lt 0 9 gt lt 0 L gt MPS 0190 94020 0000 lt 0 1 gt 1NOY 438 lt 0 gt 1NOY 831 3090 0000 381 31 1088 4044 31843 0090 ALNIZO 0000 481 4194 410414 arya dMVA NSVM3 HVMXH HVMXL 1 OSXL voso ALNIZO 0000 0 G 8HN lt 0 5 gt 484 8090 011479 0000 lt 0 gt 5 4 0 z SaviNa 9090 7919425 0000 lt 0 9 gt 30091 lt 0 gt 7050 0000 lt 0 7 gt LNONG 2090 ZTHLOZO 0870 NIM dvONVO lt 0 7 gt 30OWdO l
4. 5 M PGC1 EMUC1 AN6 OCFA RB6 PGD1 EMUD1 AN7 RB7 VREF RA9 VREF RA10 AVDD AVss AN8 RB8 AN9 RB9 AN10 RB10 AN11 RB11 Vss VDD TCK RA1 U2RTS RF13 Vss VDD 1C7 U1CTS CN20 RD14 AN12 RB12 1C8 U1RTS CN21 RD15 AN13 RB13 AN14 RB14 U2CTS RF12 AN15 0CFB CN12 RB15 U2RX CN17 RF4 U2TX CN18 RF5 Vss PGC2 EMUC2 SOSCO T1CKICNO RC14 PGD2 EMUD2 SOSCI CN1 RC13 OC1 RDO IC4 RD11 IC3 RD10 IC2 RD9 IC1 RD8 INT4 RA15 INT3 RA14 Vss OSC2 CLKO RC15 OSC1 CLKIN RC12 VDD TDO RA5 TDI RA4 SDA2 RA3 SCL2 RA2 SCL1 RG2 SDA1 RG3 SCK1 INTO RF6 SDI RF7 SDO1 RF8 U1RXIRF2 U1TX RF3 2006 Microchip Technology Inc Advance Information DS70175A page 9 PIC24H Table of Contents 1 0 Device OVenViGW A sin ase A 13 20 sub 17 3 0 Memory Organization 2 25 4 0 Flash Program Memory 55 5 0 Resets 61 6 0 Interrupt ann a awayu dd nine 65 7 0 Direct Memory Access DMA iere remite here nter pedet usps peat dents 109 8 0 Oscillator
5. R W 0 R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 CHEN SIZE DIR HALF NULLW bit 15 bit 8 U 0 U 0 R W 0 R W 0 U 0 U 0 R W 0 R W 0 AMODE lt 1 0 gt MODE lt 1 0 gt bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 CHEN Channel Enable bit 1 Channel enabled 0 Channel disabled bit 14 SIZE Data Transfer Size bit 1 Byte 0 Word bit 13 DIR Transfer Direction bit source destination bus select 1 Read from DMA RAM address write to peripheral address 0 7 Read from peripheral address write to DMA RAM address bit 12 HALF Early Block Transfer Complete Interrupt Select bit 1 Initiate block transfer complete interrupt when half of the data has been moved 0 7 Initiate block transfer complete interrupt when all of the data has been moved bit 11 NULLW Null Data Peripheral Write Mode Select bit 1 Null data write to peripheral in addition to DMA RAM write DIR bit must also be clear 0 Normal operation bit 10 6 Unimplemented Read as 0 bit 5 4 AMODE lt 1 0 gt DMA Channel Operating Mode Select bits 11 Reserved will act as Peripheral Indirect Addressing mode 10 Peripheral Indirect Addressing mode 01 Register Indirect without Post Increment mode 00 Register Indirect with Post Increment mode bit 3 2 Unimplemented
6. PWM Frequency 7 6 Hz 61 Hz 122 Hz 977 Hz 3 9 2 31 3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh OFFFh O3FFh 007Fh 001Fh Resolution bits 16 16 15 12 10 7 5 TABLE 14 2 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS Fcv 16 MHz PWM Frequency 30 5 Hz 244 Hz 488 Hz 3 9 kHz 15 6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh OFFFh O3FFh 007Fh 001Fh Resolution bits 16 16 15 12 10 7 5 TABLE 14 3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS Fcv 40 MHz PWM Frequency 76 Hz 610 Hz 1 22 Hz 9 77 kHz 39 kHz 313 kHz 1 25 MHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh OFFFh O3FFh 007Fh 001Fh Resolution bits 16 16 15 12 10 7 5 FIGURE 14 1 OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit lt lt ocxns Tt Output 5 OCxR Y p ocx Logic R YY 3 Output Enable NZ OCM2 OCM0 2 Comparator Mode Select X OCFA or OCTSEL 0 1 1 register inputs Period match signals from time 3 from time bases 9 Note 1 Where 15 shown reference is made to the registers associated with the respective output compare channels 1 through 8 2 OCFA pin controls 1 4 channels OCFB pin controls OC5 OC8 channels 3 Each output compare channel can use one of two selectable time bases Refer to the device da
7. TSS AM S K 1 1 155 1 1 1 1 1 1 1 1 1 Buffer o HE PERE C 0 2 GER U NET ER Et 1 1 155 1 1 1 1 1 1 55 1 1 1 1 1 55 55 55 55 Buffer 1 _ _ _ iL Sampling starts after discharge period TSAMP is described in the dsPIC30F Family Reference Manual DS70046 Section 17 Convert bit 9 Convert bit 8 00 00000 O Software sets ADXCON ADON to start AD operation 5 Convert bit O One for end of conversion 0 Begin conversion of next channel Sample for time specified by SAMC lt 4 0 gt DS70175A page 264 Advance Information 2006 Microchip Technology Inc PIC24H TABLE 23 34 A D CONVERSION 10 BIT MODE TIMING REQUIREMENTS Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 Symbol Characteristic Min Typ Max Units Conditions Clock Parameters AD50 TaD AID Clock Period 70 ns AD51 A D Internal RC Oscillator Period 700 900 1100 ns Conversion Rate AD55 tcoNv Conversion Time 12 TAD AD56 FCNV Throughput Rate 1 1 Msps AD57 Sample Time
8. Configuration TBLPAG lt 7 0 gt Data EA lt 15 0 gt 1 XXXX Program Space Visibility User 0 PSVPAG lt 7 0 gt Data lt 14 0 gt 1 Block Remap Read 0 XXXX Note 1 Data EA lt 15 gt is always 1 this case but is not used calculating the program space address Bit 15 of the address is lt 0 gt DS70175A page 50 Advance Information 2006 Microchip Technology Inc PIC24H FIGURE 3 6 DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter 0 Program Counter 0 lt 23 bits EA 1 0 Table Operations 1 0 TBLPAG 4 gt 8 bits 16 bits gt 24 bits Select Program Space Visibility Remapping 0 PSVPAG 4 gt 8 bits 15 bits ho 2 A 23 bits User Configuration Byte Select Space Select Note 1 The LSb of program space addresses is always fixed as o in order to maintain word alignment of data in the program and data spaces 2 Table operations are not required to be word aligned Table read operations are permitted in the configuration memory space O 2006 Microchip Technology Inc Advance Information DS70175A page 51 PIC24H 3 4 2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a dir
9. um Symbol Characteristic Min Typ Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1000 40 to 85 0131 VPR VDD for Read VMIN 3 6 V VMIN Minimum operating voltage D132B VPEW VDD for Self Timed Write VMIN 3 6 V VMIN Minimum operating voltage D133A Self Timed Write Cycle Time 1 5 ms D134 TRETD Characteristic Retention 10 20 Year Provided no other specifications are violated D135 IDDP Supply Current during 10 mA Programming Note 1 Data in column is at 3 3V 25 C unless otherwise stated TABLE 23 11 INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions 40 C TA lt 85 C unless otherwise stated P Symbol Characteristics Min Typ Max Units Comments CEFC External Filter Capacitor 1 10 uF Capacitor must be low Value series resistance DS70175A page 240 Advance Information 2006 Microchip Technology Inc PIC24H 23 2 AC Characteristics and Timing Parameters The information contained in this section defines PIC24H AC characteristics and timing parameters TABLE 23 12 TEMPERATURE AND VOLTAGE SPECIFICATIONS AC Standard Operating Conditions 3 0V to 3 6V unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 for Industrial Operating voltage VDD range as describe
10. 2790 Bled pe eroes 0750 9024 9443 9gyv1 91vav 20884 4448 28877 lt 0 1 gt 1949 1 9N3 LH XL XL XL XL 9N3X L 0 L IHdZX L N33 L3 1 1 1 1 ZNAXL 9680 NO9 9H129 vOJY veya vauv1 vlvav SOdH 9448 SdHVl S1vav 0000 lt 0 1 gt 1947 1 1 1 1 1 vNAXL lt 0 1 gt 1 9 SN3 LH XL XL XL XL SN3XL v S0 NOOSYHLZI cOdH 2448 cauv1 20884 2443 tHHVl 1vav 0000 0 L2 lHdeX L XL XL XL XL cN3X L 0 L IHd X L 14 XL XL XL XL N3XL 2290 NODEZHLZO 002 og v1 01vav 1033 Vua Layv1 0000 lt 0 1 gt 1940 1 ON LH XL XL XL XL ON3X L 1 1 1 1 0690 NOOLOYLZO 0000 9LIAOXY 14 81 4 614 OCJAOX 6 CHAOX 6 98 4 16 82 JNOXY 6 OEJAOXY LEJAOXY VZSO ZINOXYZO 0000 FOJAOX LIAOXY SHAOXH ZINOXY 1804 604 0LJAOX 2 4 LHAOX 914 8290 L IAOXYZO 0000 9 1014 6 02 103X ec 103X8 2103X8 81014 92 103X8 Z INIXY 8 1 1 6 5 LEINAXY 2290 2104
11. Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 Symbol Characteristic Min Typ Max Units Conditions SP10 TscL SCKx Output Low Time 2 ns SP11 TscH SCKx Output High Time 2 ns SP20 TscF SCKx Output Fall Time ns See parameter 0032 SP21 TscR SCKx Output Rise Time ns See parameter D031 SP30 TdoF SDOx Data Output Fall ns See parameter D032 Time 4 SP31 TdoR SDOx Data Output Rise ns See parameter D031 Time 4 SP35 TscH2doV SDOx Data Output Valid after ns TscL2doV SCKx Edge SP36 TdoV2sc SDOx Data Output Setup to 30 ns TdoV2scL First SCKx Edge SP40 TdiV2scH Setup Time of SDIx Data 20 ns TdiV2scL Input to SCKx Edge SP41 TscH2diL Hold Time of SDIx Data Input 20 ns TscL2diL to SCKx Edge Note 1 These parameters are characterized but not tested in manufacturing 2 Data Typ column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 3 The minimum clock period for SCKx is 100 ns Therefore the clock generated in Master mode must not violate this specification 4 Assumes 50 pF load on all SPIx pins FIGURE 23 11 SPIx MODULE SLAVE MODE CKE 0 TIMING CHARACTERISTICS NX EN SCKx CKP 0 SDOX MSb Bit 14 3 X
12. TABLE 6 1 INTERRUPT VECTORS vaciar Interrupt Number Request IRQ IVT Address AIVT Address Interrupt Source Number 8 0 0x000014 0x000114 INTO External Interrupt O 9 1 0x000016 0x000116 IC1 Input Compare 1 10 2 0x000018 0x000118 OC1 Output Compare 1 11 3 0x00001A 0x00011A T1 Timer1 12 4 0x00001C 0x00011C DMAO DMA Channel 0 13 5 0x00001E 0x00011E IC2 Input Capture 2 14 6 0x000020 0x000120 OC2 Output Compare 2 15 7 0x000022 0x000122 T2 Timer2 16 8 0x000024 0x000124 T3 Timer3 17 9 0x000026 0x000126 SPI1E SPI1 Error 18 10 0x000028 0x000128 SPI1 SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX UART1 Receiver 20 12 0x00002C 0x00012C U1TX UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 Converter 1 22 14 0x000030 0x000130 DMA1 DMA Channel 1 23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A CN Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 External Interrupt 1 29 21 0x00003E 0x00013E ADC2 A D Converter 2 30 22 0x000040 0x000140 IC7 Input Capture 7 31 23 0x000042 0x000142 IC8 Input Capture 8 32 24 0x000044 0x000144 DMA2 DMA Channel 2 33 25 0x000046 0x000146 OC3 Output Compare 3 34 26 0x000048 0x000148 OCA Output Compare 4 35 27 0x00004A 0x00014A 4 Timer4 36 28 0x00004C 0x00014C 5 T
13. DS70175A page 228 Advance Information 2006 Microchip Technology Inc PIC24H TABLE 21 2 INSTRUCTION SET OVERVIEW CONTINUED 221 Assembly Syntax Description Noel ane 47 PWRSAV PWRSAV 1 Go into Sleep or Idle mode 1 1 WDTO Sleep 48 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 49 REPEAT REPEAT 114 Repeat Next Instruction lit14 1 times 1 1 None REPEAT Wn Repeat Next Instruction Wn 1 times 1 1 None 50 RESET RESET Software device Reset 1 1 None 51 RETFIE RETFIE Return from interrupt 1 3 2 None 52 RETLW RETLW lit10 Wn Return with literal in Wn 1 3 2 None 53 RETURN RETURN Return from Subroutine 1 3 2 None 54 RLC RLC f Rotate Left through Carry f 1 1 2 RLC WREG WREG Rotate Left through Carry f 1 1 C NZ RLC Ws Wd Wd Rotate Left through Carry Ws 1 1 2 55 RLNC RLNC Rotate Left No Carry f 1 1 N Z RLNC WREG WREG Rotate Left No Carry f 1 1 N Z RLNC Ws Wd Wd Rotate Left No Carry Ws 1 1 2 56 RRC RRC Rotate Right through Carry f 1 1 C N Z RRC WREG WREG Rotate Right through Carry f 1 1 C NZ RRC Ws Wd Wd Rotate Right through Carry Ws 1 1 2 57 RRNC RRNC f Rotate Right No Carry f 1 1 N Z RRNC WREG WREG Rotate Right No Carry f 1 1 N Z RRNC Ws Wd Wd Rotate Right
14. 65 Interrupts Coincident with Power Save Instructions 132 J JTAG Boundary Scan Interface 217 M 25 Microchip Internet Web 279 Modes of Operation Disable Initialization 5 Listen All Messages 177 Liste Only coat 177 Loopback 5 Normal Operation a uu test memes 177 MPLAB ASM30 Assembler Linker 232 MPLAB ICD 2 In Circuit 233 MPLAB ICE 2000 High Performance Universal InFCircuit Emulator etre cent rere 233 MPLAB ICE 4000 High Performance Universal liz Circuit Emulator certet eee ttes 233 MPLAB Integrated Development Environment SONWALE PED MPLAB PM3 Device Programmer ai MPLINK Object Linker MPLIB Object Librarian 232 Multi Bit Data Shifter 23 N NVM Module Register are rere dedo 47 Open Drain Configuration 134 Compare te eese 145 REIS 148 P PACKAGING en Rue son rr MED lees Peripheral Module Disable PICSTART Plus Development Programmer Pinout I O Descriptions table DS70175A page 276 Advance Information
15. R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F15BP lt 3 0 gt F14BP lt 3 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F13BP lt 3 0 gt F12BP lt 3 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 F15BP lt 3 0 gt RX Buffer Written when Filter 15 Hits bits bit 11 8 F14BP lt 3 0 gt RX Buffer Written when Filter 14 Hits bits bit 7 4 F13BP lt 3 0 gt RX Buffer Written when Filter 13 Hits bits bit 3 0 F12BP lt 3 0 gt RX Buffer Written when Filter 12 Hits bits DS70175A page 194 Advance Information 2006 Microchip Technology Inc PIC24H REGISTER 18 16 CiRXFnSID ECAN FILTER STANDARD IDENTIFIER 0 1 15 R W x R W x R W x R W x R W x R W x R W x R W x SID10 SID9 SID8 SID7 06 05 104 5103 bit 15 bit 8 R W x R W x R W x U 0 R W x U 0 R W x R W x SID2 SID1 SIDO EXIDE ElD17 ElD16 bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 5 SID lt 10 0 gt Standard Identifier bits 1 Message address bit SIDx must be 1 to match filter Message address bit SIDx must be o to match filter
16. 197 CiRXMnSID ECAN Acceptance Filter Mask n Standard 197 CiRXOVF1 ECAN Receive Buffer Overflow 1 199 CiRXOVF2 ECAN Receive Buffer Overflow 2 199 CiTRBnDLC ECAN Buffer n Data Length Control lil 202 CiTRBnDm ECAN Buffer n Data Field CN 0 202 CiTRBnEID ECAN Buffer n Extended se ir an qa 201 CiTRBnSID ECAN Buffer Standard Identifier vocacion is CiTRBnSTAT ECAN Receive Buffer n Status CiTRmnCON ECAN TX RX Buffer m Control CiVEC ECAN Interrupt Code CLKDIV Clock Divisor CORCON Core Control DMACSO DMA Controller Status 0 118 DMACS1 DMA Controller Status 1 120 DMA Channel x Transfer Count 117 DMAxCON DMA Channel x Control 114 DMAxPAD DMA Channel x Peripheral Add ESS redeat tet etes 117 DMAxREQ DMA Channel x IRQ Select 115 DMAxSTA DMA Channel x RAM Start Address A eco al 116 DMAxSTB DMA Channel x RAM Start Address B eerte DSADR Most Recent DMA RAM Address I2CxCON I2Cx Control I2CxMSK I2Cx Slave Mode Address Mask I2CxSTAT I2Cx Status T ICxCON
17. 918 1 818 618 0L Wig el ua vL ua ua Appy AVN Y31SIDIY 31404 92 e A 2006 Microchip Technology Inc PIC24H ui UMOUS jasay 0 se pea josey uo X pueba7 0000 ancdav s i i Lx aol QNS ANGL 7 40 0000 QWcOO AW990 ANZIO anzol QNEOI QNSOI ANSII 2440 0000 antay anto 6 5 m ANGL 0220 Vaid c sjosoy m 08 yug cung tH 918 Zug 618 pl ua si ua Jppv 9114 dVIN 4211S1934 L 319 O euin eu je Jo jo ejejs eu uo juepuedep si sejejs Jeujo uo 7440 YOd 10 UMOYS L ui UMOUS 0 Se pea S Y uo UMOUYU
18. 159 Slope Control iicet stre creata zat 160 Software Controlled Clock Stretching STREN rette rte 159 Module I2C1 Register Map 12 2 Register Map eet In Circuit Debuggel carm oerte a In Circuit Emulation 217 In Circuit Serial Programming ICSP 217 221 Infrared Support Built in IrDA Encoder and Decoder 169 External IrDA IrDA Clock Output 169 Input Capture ROgIStO Sc criei aa sa ena idas 144 Input Change Notification Module 134 Instruction Addressing 48 File Register Instructions 48 Fundamental Modes 49 MCU Instructions Instruction Set Overview 226 Smet Tugu m uyu gaa 223 Instruction Based Power Saving Modes 131 A uqa qu E TE qaqaqa 132 BIRD aayqa qua akati 131 Internal RC Oscillator Use WINWDT S u 220 Interrupt Setup Procedures IriitialiZation Interrupt Disable Lentes Interrupt Service Routine 108 Trap Service 108 Interrupt Vector Table IVT
19. 111111 10111011 LIE D 22 5839 x x gt ono O gt 60020 oa gt S NOGA oQoooouunoaOoooooooQo D m Y gt gt O O O M CGN O UO UO LO LO LO LO 10 10 10 10 st 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 PIC24HJ64GP206 41 9 PIC24HJ128GP206 pa PIC24HJ256GP206 12 37 13 36 14 35 15 34 16 33 O O NN st L QO F lt O O CGN GN GN CGN GN GN GN GN GN M 8999gorogseozomro gt mmm S lt lt 2 2 2 O s NOYANSS lt lt lt Z 2232265 D lt lt EER A E 22 Q Z8 52 5 59 29 Go lt 5 a PGC2 EMUC2 SOSCO T1CK CNO RC14 PGD2 EMUD2 SOSCI TACK CN1 RC13 OC1 RDO IC4 INT4 RD11 IC3 INT3 RD10 IC2 U1CTS INT2 RD9 IC1 INT1 RD8 Vss OSC2 CLKO RC15 OSC1 CLKIN RC12 VDD SCL1 RG2 SDA1 RG3 U1RTS SCK1 INTO RF6 U1RX SDM RF2 U1TX SDO1 RF3 The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins DS70175A page 4 Advance Information 2006 Microchip Technology Inc PIC24H Pin Diagrams Continued 64 Pin RG15 16 2 7 1 AN17 T3CK T6CK RC2 SCK2 CN8 RG6 SDI2
20. 2006 Microchip Technology Inc Advance Information DS70175A page 181 PIC24H REGISTER 18 1 CiCTRL1 ECAN CONTROL REGISTER 1 U 0 U 0 R W 0 R W 0 R W 0 R W 1 R W 0 R W 0 CSIDL ABAT CANCKS REQOP lt 2 0 gt R 0 R 0 U 0 R W 0 U 0 U 0 R W 0 OPMODE lt 2 0 gt CANCAP WIN bit 7 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 bit 13 bit 12 bit 11 bit 10 8 bit 7 5 bit 4 bit 3 bit 2 1 bit 0 Unimplemented Read as 0 CSIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode Continue module operation in Idle mode ABAT Abort All Pending Transmissions bit Signal all transmit buffers to abort transmission Module will clear this bit when all transmissions are aborted CANCKS CAN Master Clock Select bit 1 CAN FCAN clock is Fcy CAN FCAN clock is FOSC REQOP lt 2 0 gt Request Operation Mode bits 000 Set Normal Operation mode 001 Set Disable mode 010 Set Loopback mode 011 Set Listen Only Mode 100 Set Configuration mode 101 Reserved do not use 110 Reserved do not use 111 Set Listen All Messages mode OPMODE lt 2 0 gt Operation Mode bits 000 Module is in Normal Operation mode 001 Module is in
21. JojeJeuac ajey pneg gezo Sugzn 0000 JejsiGes gezo vezo yeso a34 lt gt agan Naxin otasxin anxin zezo 1620 0000 13518 0 1 13d Houa anvav wm onan ansis oezo aqowzn 59594 ova eva na suma PPV Iv uss was dVW Y31SIOIY ZLHAVAN OL C TIAVL ui UMOUS Josey 0 se peas uo puabeq 0000 Je eoseJg Joje1euec ajey pneg 8220 0000 Lv 9220 own yeso wuss wea na lt o gt 13SIXUN exin onasan anan rispan 2220 VLSIN 0000 18515 lt 0 L gt 13SUd Hoya anvav onan iman Nain ozo aqomin exa sue 918 sua
22. VSLO NO9 91 du 8810 309 51 0000 0 Z INOI OOI 0 L 1OI HALOI 9910 9991 JaysiBay 9 du 910 37890 0000 lt 0 Z gt WOI OOI lt 0 1 gt 101 2810 NOOSOI JaysiBay 9 ndul 0810 509921 0000 0 Z INOI OOI lt 0 1 gt 101 HALOI Arlo NOOO JaysiBay 9 L0 3ngvol 0000 lt 0 Z gt WOI OOI 0 L 1OI 9851 du 8910 30955 0000 0 Z INOI OOI 0 L 1OI 9vLO z du 3ngzol 0000 lt 0 Z gt WOI OOI lt 0 L gt 191 ZYLO JaysiBay ynduy 0910 ANGLO Av Lug eng zaa sua VAS owen us dVW 431SI93Y 34N1dV9 1 9 2 3 18vL 2006 Microchip Technology Inc Advance Information DS70175A page 33 PIC24H ui UMOUS 0 se peeJ jes
23. VIO 8110 S amp IA L XXXX Ajuo 1q z BUIPIOH 9110 QIHSHA L XXXX LLO 0000 SOL 0 L2SdMO L 31v91L NOL ZLLO NOOEL 0000 Fra SOL cel lt 0 1 gt 5 1 31v91L Ex Ex NOL OLLO 961 dada Ja siIBay 3010 d dada 2 5 200 cud XXXX VOLO Ajuo Jeuun 19 22 Ja SIBay gaw 8010 TIHEMIALL 9010 0000 SOL ONASL 0 L2SdMO L AYOL TdISL NOL YOLO NOOLL dada JajsiBay pou q 2010 Jouut 00 0 LYALL T oud cua tH yug sua 918 618 zL ua el ua ua si ua UE SUN uds dVW3lsioO3H 319VL 2006 Microchip Technology Inc Advance Information DS70175A page 32 PIC24H ui UMOUS 19594 0 Se ped yesoy uo UMOUXUN X puaba7 0000 0 Z INOI OOI lt 0 1 gt 101 3910 9851 JaysiBay g du 29 0 509821 0000 lt 0 Z gt WOI OOI 0 L 1OI
24. eL 556556525000 53350 88 FES BERR SES 200006660600 CN lt ODO N e O CO RG15 1 75 1 Vss VoD 2 74 PGC2 EMUC2 SOSCO T1CK CNO RC14 AN29 RE5 3 73 PGD2 EMUD2 SOSCI CN1 RC13 AN30 RE6 4 72 OC1 RDO AN31 RE7 5 71 1C4 RD11 AN16 T2CK T7CK RC1 6 70 IC3 RD10 AN17 T3CK T6CK RC2 7 69 IC2 RD9 AN18 TACKIT9CK RC3 8 68 IC1 RD8 AN19 T5CK T8CK RC4 9 67 INT4 RA15 SCK2 CN8 RG6 10 66 INT3 RA14 SDI2 CN9 RG7 11 65 Vss SDO2 CN10 RG8 12 64 OSC2 CLKO RC15 PIC24HJ64GP510 ves M PIC24HJ128GP510 TDOIRAS VDD 16 60 TDI RA4 TMS RAO 17 59 SDA2 RA3 201 1 18 58 SCL2 RA2 AN21 INT2 RE9 19 57 SCL1 RG2 AN5 CN7 RB5 20 56 SDA1 RG3 AN4 CN6 RB4 21 55 SCK1 INTO RF6 ANS CNS RB3 22 54 SDI1 RF7 AN2 SS1 CN4 RB2 23 53 SDO1 RF8 PGC3 EMUC3 AN1 CN3 RB1 24 52 U1RX RF2 PGD3 EMUD3 ANO CN2 RBO 25 51 U1TXIRF3 D Or LO O O CN N M CO sr sb b 0 re 5225588 DONS FA LES lt lt gt gt F k 5 ZZ xx 2266 5 lt lt lt lt lt 0 OO 3 2 O ox 55 5 8 55 9 2 o9 PGC1 EMUC1 AN6 OCFA RB6 DS70175A page 8 Advance Information 2006 Microchip Technology Inc PIC24H Pin Diagr
25. 0000 O Software sets SAMP to start sampling Sampling starts after discharge period TSAMP is described in Section 17 in the dsPIC30F Family Reference Manual DS70046 Software clears SAMP to start conversion Sampling ends conversion sequence starts Convert bit 9 8 Convert bit 8 7 Convert bit 0 One TAD for end of conversion 2006 Microchip Technology Inc Advance Information DS70175A page 263 PIC24H FIGURE 23 19 A D CONVERSION 10 BIT MODE TIMING CHARACTERISTICS CHPS lt 1 0 gt 01 SIMSAM 0 ASAM 1 SSRC lt 2 0 gt 111 SAMC lt 4 0 gt 00001 AD50 E Le Instruction Xu unu Execution Set ADON 1 i 1 1 1 1 1 1 1 1 i 1 1 1 i SAMP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 55 55 chO dischrg 1 1 1 1 1 1 1 1 1 1 1 1 E HEINE END TE CERE ch0_samp 1 1 15 T T 1 ch1_dischrg 1 1 1 1 1 1 1 1 1 cht_samp tt S is NE ye 3 Tim ee MENEE O Es 055 gt lt AD55 TCONV CONV
26. 0000 lt 0 51 gt 1 VISPVING 0000 lt 0 9 gt 714504 80404 2860 0000 0 L23GON lt 0 1 gt 30ONv m MTINN 31VH 3715 N3H9 0860 NOOYrvVIAG 0000 0 62 1NO Aveo LNOEVIAG 0000 lt 0 91 gt QvdeviNa 0000 lt 0 91 gt 815 VV 0 9158 0000 lt 0 SL gt VLS 8960 VLSEVING 0000 lt 0 9 gt 714504 80404 9W 0 DIYJEVINO 0000 0 L23GON lt 0 1 gt 30ONv m MTINN 31VH 3715 N3HO 750 NODEVINO 0000 0 62 1NO LNOCVING 0000 lt 0 9 gt 0000 lt 0 91 gt 815 3620 815 0000 lt 0 51 gt 1 2660 VLSCVING 0000 0 9 145041 19401 V6 0 DIYZVINO 0000 0 L23GON lt 0 L gt 3QOWY MTINN 41VH 3715 N3HO 86 0 NOOZ VINO 0000 0 62 1NO 9650 LNOLVING 0000 0 8 L2 dvd 7650 val via 0000 lt 0 91 gt 918 2660 4LSIVNA 0000 lt 0 SL gt VLS 0650 VLSLVING 0000 0 9 14504 19401 3850 DIYIVINO 0000 0 L23GON m lt 0 1 gt 30ONv x Ls S MTINN 31VH 3715 N3H9 98 0 NOOLVWG 0000 0 62 1NO gt LNDOOVING 0000 0 4 8820 0000 lt 0 91 gt 918 9860 81S0VING 0000 lt 0 SL gt VLS VLSOVING 0000 lt 0 9 gt 13SDl gt m 194041 2860 OdHOVING 0000 0 L23GON lt 0 1 gt 30ONv
27. 310413 31443 9070 0000 3181 3184 JIAOSH 310313 11443 JDIVA SIYAl NSVM3 HVMXL daxx OSXL 070 ALNILO 0000 lt 0 6 gt 0 4 484 8070 031419 0000 0 54 lt 0 z gt SavWa 9070 71419419 0000 lt 0 9 gt 3009 lt 0 7 gt LIH 14 7070 3AL9 0000 lt 0 7 gt LNONG T coro 613191 0870 NIM dVONVO lt 0 Z gt 300NdO 0 C dOO3MH SMONVO 1vav 10IS9 00 0 VIHIOLO iia 018 yug zd 18 y Ha sua 2 9 0L 18 LL vd cl ua L ua 4 9 14 T YO 0 NIW TINLLO N3HM 31SIOSH LNVIA 91 318VL UMOUS josey 0 se peal puaba7 0000 lt 0 S1 gt 4qvsa v320 uavsa 0000 01544 1544 21844 61544 vlSdd SISdd 91Sdd 11544 0 6 151 2320 LSOVNNG 0000 01OOMX 1 E1TOOMX SIOIMX ZIOOMX 0109Md L109Md 1OOMd 9109Md Z109Md 03 0 0SOVMWG 0000 0 62 1NO E 30 0 LNOZVWd 0000 lt 0 51 gt 0 0000 lt 0 91 gt 815 60 0000 lt 0 91 gt 715 8060 VISZVING 0000 lt 0 9 gt 71980 39Y03 90 0 O3HZVIAG 0000 lt 0 L gt 300N lt 0 L gt 3QOWY MTINN 3215 Q 0 000
28. TE Control Signals to Various Blocks Lai Instruction Control lt Instruction Reg X Data Bus 16 16 Data Latch DMA X RAM RAM 16 Address Latch 16 DMA Address Generator Units Controller ROM Latch Literal Data 17 17 Multiplier i 16 x 16 4 E W Register Arra Divide Support lt 16 16 bit ALU 16 To Peripheral Modules DS70175A page 18 Advance Information 2006 Microchip Technology Inc PIC24H FIGURE 2 2 PIC24H PROGRAMMER S MODEL D15 DO WO WREG W1 W2 DO Shadow W3 Legend WA W5 W6 W7 ws gt Working Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer J SPLIM Stack Pointer Limit Register PC22 PCO 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 CORCON Core Configuration Register DC IPL2 IPLTIPLO RA OV Z C STATUS Register lt SRH gt lt SRL gt 2006 Microchip Technology Inc Advance Information DS70175A page 19 P
29. I SDOx SDIx I SDIx lt q SDOx Serial Clock _ l SCK SCKx Sox 55 Frame Sync Pulse 1 FIGURE 15 4 SPI MASTER FRAME SLAVE CONNECTION DIAGRAM PIC24H SPI Master Frame Slave SDIx SDOx Serial Clock SCKx LI 1 1 SSx lt Frame Sync Pulse d L SCKx SSx PROCESSOR 2 isle deum uices ss ne 2006 Microchip Technology Inc Advance Information DS70175A page 151 PIC24H FIGURE 15 5 SPI SLAVE FRAME MASTER CONNECTION DIAGRAM 1 PIC24H PROCESSOR 2 SPI Slave Frame Slave 1 I SDOx gt SDIx I 1 I l SDIx lt q SDOx Serial Clock SCKx SCKx Sox 55 Frame Sync Pulse i E FIGURE 15 6 SPI SLAVE FRAME SLAVE CONNECTION DIAGRAM PIC24H SPI Master Frame Slave PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse E p EQUATION 15 1 RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED FSCK Fcv Primary Prescaler Secondary Prescaler TABLE 15 1 SAMPLE SCKx FREQUENCIES Secondary Prescaler Settings Fcv 40 MHz 1 1 2 1 4 1 6 1 8 1 Primary Prescaler Settings 1 1 Invalid Invalid 10000 6666 67 5000 4 1 10
30. SUId uod JO 195 jene ay p 00 10 UMOUS 0 se peel Jesay uo UMOUHUN 5 04940 114900 24000 64000 84040 94000 24000 84040 64000 3090 1940 2 041V1 4lV1 S4lV1 9 1 1 431V1 841 1 21311 2320 lt 044 1813 2484 SJH 944 134 844 2144 oazo ALYOd HATE 045141 148141 ZASIML 6 58 1 vdSlHL 848141 945841 48041 835101 ZlASINL 513911 49141 sjesedlV Od yug 18 vua 918 138 818 618 0L ya Ll ua eL xa Appy AVI 431SID3Y 341404 2 Buipuodse1109 eu 19jeJ 1 euo WO SUId uod JO 196 jene y p 00 10 UMOUS 0 se pea pejueujejduiiun Josey uo UMOUHUN pueBe1 031V1 131v1 31V1 e31v1 931v1 631V1 oazo 03H Vae dd yay 954 93H 824 63H vazo 214Od 450 O03SIWL bASIML Z3SR41 58141 v3SIWL 64541 93SlHL 3SlHL 835141 63811 i ii 2 2 3514 81959 018
31. 390 394 398 9 90 10 00 10 10 Molded Package Length D1 390 394 398 9 90 10 00 10 10 Lead Thickness 005 007 009 0 13 0 18 0 23 Lead Width B 007 009 011 0 17 0 22 0 27 Pin 1 Corner Chamfer CH 025 035 045 0 64 0 89 1 14 Mold Draft Angle Top 5 10 15 5 10 15 Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side REF Reference Dimension usually without tolerance for information purposes only See ASME Y14 5M JEDEC Equivalent MS 026 Revised 07 22 05 Drawing No 04 085 DS70175A page 270 Advance Information 2006 Microchip Technology Inc PIC24H 100 Lead Plastic Thin Quad Flatpack PT 12 12 1 mm Body 1 0 0 10 mm Lead Form TQFP Et leads n1 0101 2 La Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 100 100 Pitch 016 BSC 0 40 Pins per Side n1 25 25 Overall Height A 039 043 047 1 00 1 10 1 20 Molded Package Thickness A2 037 039 041 0 95 1 00 1 05 Standoff A1 002 004 006 0 05 0 10 0 15 Foot Length L 018 024 030 0 45 0 60 0 75 Footprint Reference F 039 REF 1 00 REF
32. L Clock Stretching lt k 12CxTRN LSB Shift Clock Reload 22 Control lt BRG Down Counter 2 I2CxBRG DS70175A page 158 Advance Information 2006 Microchip Technology Inc PIC24H 16 5 Module Addresses The I2CxADD register contains the Slave mode addresses The register is a 10 bit register If the bit 12CxCON lt 10 gt is o the address is interpreted by the module as a 7 bit address When an address is received