Marconi 54 HST 630 handbook
Contents
1. Devices Any two bit error will change the sense of an even number of check bits The two bit error is not correctable since the parity tree can only identify single bit errors Both error flags are set high when any two bit error is Error correction is accomplished by identifying the bad bit and inverting it Identification of the erroneous bit is achieved by comparing the 16 bit word and 6 bit checkword from memory with the new checkword with detected one checkword error or three data word error inverted bits Three or more simultaneous bit errors can fool the EDAC into believing that no error a correctable error or an uncorrectable error has occurred and produce erroneous results all three cases As the corrected word is made available on the data word port the checkword port presents a 6 bit syndrome error code This syndrome code can be used to identify the corrupted bit in memory see Table 4 below TABLE 3 CHECK WORD GENERATION 16 BIT DATA WORD Cou LL 291 The six check bits are parity bits derived from the matrix of data bits as indicated by X for each bit TABLE 4 ERROR SYNDROME CODES ERROR LOCATION ERROR SYNDROME ERROE Powered by ICminer com Electronic Library Service CopyRight 2003 54 HST 630 Radiation Hard 16 Bit Parallel Error Detection amp Correction APPLICAT2. Electronic Devices FEATURES e Radiation Hard to 1 MRad Si e High SEU immunity latch up free e CMOS SOS technology e All inputs amp outputs fully TTL amp CMOS compatible e Low power e Detects and corrects single bit errors e Detects and flags dual bit errors e High speed Write cycle Generate checkword in 40ns typ Read cycle Flags errors in 20ns typ GENERAL DESCRIPTION The 54HST630 is a 16 bit parallel Error Detection and Correction circuit It uses a modified Hamming code to generate a 6 bit check word from each 16 bit data word The check word is stored with the data word during a memory write cycle During a memory read cycle a 22 bit word is taken from memory and checked for errors Single bit errors in data words are flagged and corrected Single bit errors in check words are flagged but not corrected The position of the incorrect bit is pinpointed in both cases by the 6 bit error syndrome code which is output during the error correction cycle The information presented herein is to the best of our knowledge true and accurate No warranty expressed or implied is made regarding the capacity performance or suitability of any product You are strongly urged to ensure that the information given has not been supersede more up to date version p E om Marconi Electronic Devices Inc 45 Davids Drive Hauppauge NY 11788 516 231 7710 54 HST 630 Radiation Hard 16 Bit Parallel Error Detectio
3. IONS Although most semiconductor memories have separate input and output pins it is possible to design the error detection and correction function using a single EDAC EDAC data and check bit pins function as inputs or outputs dependent upon the state of control signals SO and S1 It becomes necessary to use wired AND logic with fairly complex system timing to control the EDAC and data bus This scheme becomes difficult to implement both in terms of board layout and timing System performance is also adversely affected See Figure 2 Optimized systems can be implemented using two EDAC s in parallel One of the units is used strictly as an encoder during the memory write cycle Both controls SO and S1 are grounded The encoder chip will generate the 6 bit check word for memory storage along with the 16 bit data The second of the two EDAC s will be used as a decoder during the memory read cycle 22 BI1 MEMORY SEPARATE INPUT amp OUTPUT BUSES Electronic Devices This decoder chip does require timing pulses for proper operation Control SI is set low and SO high as the memory read cycle begins After the memory output data is valid the control 51 input is moved from the low to a high This low to high transition latches the 22 bit word from memory into internal registers of this second EDAC and enables the two error flags If no error occurs the CPU can accept the 16 bit word directly from memory If a single error has o
4. Radiation hard processing USA Standards note 1 B1 Class B9 Class B SEM inspection and PIND screening SO Class without internal visual inspection by customer S2 Class ESA SCC 9000 note 2 T1 level B Lat 1 T2 level B Lat 2 T3 level B Lat 3 TA level C Lat 1 T5 level C Lat 2 T6 level C Lat 3 GB Commercial 70 GC Commercial 55 to 125 Electronic Devices PACKAGE Ceramic DIL Flatpack Leadless Chip Carrier J Lead Chip Carrier ernn i QUALITY LEVEL 1 Marconi Electronic Devices quality levels conform to 2 Marconi s specifications for European Space MIL STD 883C class B S screening method 5004 and Quality Conformance Inspection method 5005 This does not imply DESC certification however MIL M 38510 qualified product listing is being sought TOTAL DOSE RADIATION TESTING For product procured to guaranteed total dose radiation levels each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test The sample devices will be subjected to the total dose radiation level Cobalt 60 Source defined by the ordering code and must continue to meet the electrical parameters specified in the data sheet Electrical tests pre and post irradiation will be read and recorded Marconi Electronic Devices can provide radiation testing compliant with MIL STD 883C remote sensing method 1019 notice 5 manufacturing flows includi
5. a memory write cycle six check bits 5 are generated by eight input parity generators using the data bits as defined in Table 3 overleaf During a memory read cycle the 6 bit checkword is retrieved along with the actual data Error detection is accomplished as the 6 bit checkword and the 16 bit data word from memory are applied to internal parity generators checkers If the parity of all six groupings of data and check bits are correct it is assumed that no error has occurred and both error flags will be low tt should be noted that the sense of two of the CONTROL maer EE EDACFUNCTION CHECKWORD se o Output Corrected Data ERROR FLAGS Electronic Devices Output Syndrome Bits check bits bits CBO and CB1 is inverted to ensure that the gross error condition of all lows and all highs is detected If the parity of one or more of the check groups is incorrect an error has occurred and the proper error flag or flags will be set high Any single error in the 16 bit data word will change the sense of exactly three bits of the 6 bit checkword Any single error in the 6 bit checkword changes the sense of only that one bit In either case the single error flag wil be set high while the dual error flag will remain tow Powered by ICminer com Electronic Library Service CopyRight 2003 54 HST 630 Radiation Hard 16 Bit Parallel Error Detection amp Correction Electronic
6. ccurred the CPU must move the control SO input from the high to a low to output corrected data and the error syndrome bits Any dual error should be an interrupt condition In most applications status registers will be used to keep tabs on error flags and error syndrome bits If repeated patterns of error flags and syndrome bits occur the CPU will be able to recognize these symptoms as a hard error The syndrome bits can be used to pinpoint the faulty memory chip See Figure 3 16 BIT DATA 805 NERONE T 6 Figure 2 Error Detection and Correction using a single EDAC Unit EE FUNCTION L Start REAL H Latch data amp flag errors H Correct data amp output syndrome bits 22 BIT MEMORY DECODER SEPARATE INPUT amp OUTPUT BUSES 16 BIT DATA BUS HST630 STATUS REGISTERS amp HARD CPU ERROR DETECT Figure 3 Error Detection and Correction using two EDAC Units 4 Powered by ICminer com Electronic Library Service CopyRight 2003 Marconi 54 HST 630 Electronic Devices Radiation Hard 16 Bit Parallel Error Detection amp Correction ABSOLUTE MAXIMUM RATINGS Stresses above those listed may cause permanent damage to the device This ts a stress rating only and functional operation of the device at these or any other condition above those indicated in the operations section of this specification is not implied Exposure to absolute maximum rating conditions for exten
7. ded periods may effect device reliability OPERATING DC ELECTRICAL CHARACTERISTICS Vpp 5 10 Over full operating temperature range TOTAL DOSE 1 MRAD 51 SYMBOL PARAMETER UNITS CONDITION V 5 5 0 3 10 TTL Output High Voltage TTL Output low Voltage E lo 12mA CB or DB lg 4MACSEF or DEF m 50 amp 1 at 4 5V amp DB pins grounded DEF amp SEF open Power Supply Current Powered by ICminer com Electronic Library Service CopyRight 2003 Marconi Radiation Hard 16 Bit Parallel Error Electronic Devices Detection amp Correction AC ELECTRICAL CHARACTERISTICS Vpp 5V 1096 Cc 50pF Over full operating temperature range FROM TO PARAMETER UNITS CONDITIONS CB m mnn ec ose Propagation delay time low to high level output note 4 SEF 9 9 or pm fel mme wr pem pomme or saves weeeumesterstt lt ty Hold time after 517 1 Input Pulse Vss to 3 0 Volts 2 Times Measurement Reference Level 1 5 Volts 3 These parameters describe the time intervals taken to generate the check word during the memory write cycle 4 These parameters describe the time intervals taken to flag errors during memory read cycle 5 These parame
8. n amp Correction FLAG ENABLE FUNCTION SELECTOR 50 DATA ENABLE CHECK ENABLE 51 LATCH DATA ENABLE CHECK ENABLE LATCH LATCH PARITY CHECK WORD GENERATOR vo ERROR DETECTOR D8 15 0 5 0 SEF ERROR CORRECTION FLAG ENABLE Figure 1 Two bit errors are flagged but not corrected Any combination of two bit errors occurring within the 22 bit word read from memory ie two errors in the 16 bit data word two bits in the 16 bit check word or one error in each will be correctly identified The gross errors of all bits low or high will be deleted The contro signals S1 and SO select the function to be performed by the EDAC They control the generation of check words and the latching and correction of data see table 1 When errors are detected flags are placed on outputs SEF and DEF see table 2 bya Regional Offices Colorado 719 593 1555 California 714 894 9313 C600D Issue 1 Nov 1988 Powered by ICminer com Electronic Library Service CopyRight 2003 54 HST 630 Radiation Hard 16 Bit Parallel Error Detection amp Correction TABLE 1 CONTROL FUNCTIONS Input Data READ Read Data amp Checkword READ Latch amp Flag Error READ High Low Correct Data Word amp Generate Syndrome Bits Latch Data TABLE 2 ERROR FUNCTIONS TOTAL NUMBER OF ERRORS 16 BIT DATA 6 BIT CHECKWORD During
9. ng their associated screening procedures conform to ESA SCC Generic Specification No 9000 A Process Identification Document describing the manufacture of these devices has been approved by the European Space Agency RADIATION PERF Total Dose Function to spec 3x10 Rad Si Total Dose Function to 1MRad 51 spec 1 106 Rad Si Transient Upset stored data loss Transient Upset survivability Neutron Hardness Function to spec Latch up Powered by ICminer com Electronic Library Service CopyRight 2003
10. ters describe the time intervals taken to correct and output the data word and to generate and output the syndrome error code during the memory read cycle 6 These parameters describe the time intervals taken to disable the CB amp DB buses in preperation for a new data word during the memory read Parameter Measurement Information Output of Circuit 6800 6800 Output of Circuit i SOpF SOpF Figure 4 Output Load Circuit Figure 5 Output Load Circuit Powered by ICminer com Electronic Library Service CopyRight 2003 e 54 HST 630 Marconi Electronic Devices Radiation Hard 16 Bit Parallel Error Detection amp Correction Voo SEF j 1 50 CBO 1 CB2 CB3 CBA CB5 DB15 DB14 DB13 DB12 5 60 0 220 0 83 0 015 1 53 0 060 0 35 0 014 0 59 0 023 0 36 0 014 0 20 0 008 36 02 1 418 2 54 0 100 typ 15 24 0 600 typ 4 71 0 185 5 38 0 212 15 90 0 626 1 27 0 050 1 53 0 060 Powered by ICminer com Electronic Library Service CopyRight 2003 54 HST 630 Radiation Hard 16 Bit Parallel Error Detection amp Correction ORDERING IN FORMATION designator 5AxHST630xxx RADIATION TOLERANCE Blank No tolerance implied 5 Radiation hard processing R 100 kRads Si guaranteed Q H 300 kRads Si guaranteed 1000 kRads Si guaranteed Blank Notolerance implied 5
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