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intel 82C288 Data Sheet

1. 24 a pry A O o Test Condition 1 0V to 3 6V 3 6V to 1 0V Note 4 Note 4 EE 2 163 820288 i ntel 7 A C CHARACTERISTICS Voc 5V 5 Tcase 0 C to 85 C AC timings are referenced to 0 8V and 2 0V points of signals as illustrated in data sheet waveforms unless otherwise noted Continued emma tome 125042 pop Parameter 8 Condition Max 25 DEN Inactive from CEN DEN Active from 24 CEN 27 DT R HIGH from CLK when CEN LOW DEN Active from AEN gt fns AA A a from CLK CMD Inactive Delay from CLK CMD Active from CEN Mb nace nomoen MD inactive Enable om AEN CR Float Delay rom AEN Mo Seuptime a Ma koa Time o si En 3 b 37 Command Inactive Enable from MB Command Float Time from MB T DEN Inactive from MB T 40 DEN Active from MB J Ta is guaranteed from 0 C to 70 C as long as Tcasg is not exceeded NOTES 3 AEN is an asynchronous input This specification is for testing purposes only to assure recognition at a specific CLK edge 4 Control output load Cl 150 pF 5 Command output load Cl 300 pF 6 Float condition occurs when output current is less than ILo in magnitude i ntel a 820288 4 0v CLK INPUT lt x XX Note 8 AC Test Loading on Outputs WAVEFORMS CLK CHARACTERISTICS 2 165 820288 WAVEFORMS Contin
2. The T bus state occurs when no bus cycle is cur rently active on the 80286 local bus This state may be repeated indefinitely When control of the local bus is being passed between masters the bus re mains in the T state READY NEW CYCLE Figure 4 82C288 Bus States TOO Figure 5 Bus Cycle Definition 82C288 Bus Cycle Definition The ST and 50 inputs signal the start of a bus cycle When either input becomes LOW a bus cycle is started The Tg bus state is defined to be the two CLK cycles during which either S7 or SO are active see Figure 5 These inputs are sampled by the 82C288 at every falling edge of CLK When either S1 or SO are sampled LOW the next CLK cycle is considered the second phase of the internal CPU clock cycle The local bus enters the Tc bus state after the Ts state The shortest bus cycle may have one Ts state and one Tc state Longer bus cycles are formed by repeating Tc state A repeated Tc bus state is called a wait state The READY input determines whether the current Tc bus state is to be repeated The READY input has the same timing and effect for all bus cycles READY is sampled at the end of each Tc bus state to see if it is active If sampled HIGH the Tc bus state is repeated This is called inserting a wait state The control and command outputs do not change during wait states When READY is sampled LOW the current bus cy cle is terminated Note that the bus c
3. HIGH between the bus cycles see Figure 8 The command and ALE output timing does not change Figures 9 and 10 show a MULTIBUS cycle with MB 1 AEN and CMDLY are connected to GND The effects of CMDLY and AEN are described later in the section on control inputs Figure 9 shows a read cycle with one wait state and Figure 10 shows a write cycle with two wait states The second wait state of the write cycle is shown only for example purposes and is not reguired The READY input is shown to illustrate how wait states are added Figure 9 Idie Read Idie Bus Cycles with 1 Walt State and with MB 1 2 157 82C288 Figure 10 Idle Write Idle Bus Cycles with 2 Wait States and with MB 1 The MB control input affects the timing of the com mand and DEN outputs These outputs are automat ically delayed in MULTIBUS mode to satisfy three reguirements 1 50 ns minimum setup time for valid address be fore any command output becomes active 2 50 ns minimum setup time for valid write data before any write command output becomes ac tive 3 65 ns maximum time from when any read com mand becomes inactive until the slave s read data drivers reach 3 state OFF Three signal transitions are delayed by MB 1 as compared to MB 0 1 The HIGH to LOW transition of the read com mand outputs ORC MRDC and INTA are de layed one CLK cycle 2 The HIGH to LOW transition of the write com mand outputs IOWC and MWTC
4. quiring only one of them use the bus at a time Systems with multiple and shared buses use two control input signals of the 82C288 bus controller CENL and see Figure 12 CENL enables the bus controller to control the current bus cycle The AEN input prevents a bus controller from driving its command outputs AEN HIGH means that another bus controller may be driving the shared bus In Figure 12 two buses are shown a local bus and a MULTIBUS Only one bus is used for each CPU bus cycle The CENL inputs of the bus controller select which bus controller is to perform the bus cy cle An address decoder determines which bus to use for each bus cycle The 82C288 connected to the shared MULTIBUS must be selected by CENL and be given access to the MULTIBUS by AEN before it will begin a MULTIBUS 1 operation 82C288 CENL must be sampled HIGH at the end of the Ts bus state see waveforms to enable the bus control ler to activate its command and control outputs If sampled LOW the commands and DEN will not go active and DT R will remain HIGH The bus control ler will ignore the CMDLY CEN and READY inputs until another bus cycle is started via 31 and 50 Since an address decoder is commonly used to identify which bus is required for each bus cycle CENL is latched to avoid the need for latching its input The CENL input can affect the DEN control output When MB 0 DEN normally becomes active dur ing Phase 2 of Ts in write bus c
5. ENABLE controls the command and DEN outputs of the bus controller CEN AEN inputs may be asynchronous to CLK Setup and hold times are given to assure a guaranteed response to synchronous inputs This input may be connected to Vcc or GND When MB is HIGH this pin has the AEN function AEN is an active LOW input which indicates that the CPU has been granted use of a shared bus and the bus contoller command outputs may exit 3 state OFF and become inactive HIGH AEN HIGH indicates that the CPU does not have control of the shared bus and forces the command outputs into 3 state OFF and DEN inactive LOW When MB is LOW this pin has the CEN function CEN is an unlatched active HIGH input which allows the bus controller to activate its command and DEN outputs With MB LOW CEN LOW forces the command and DEN outputs inactive but does not tristate them ADDRESS LATCH ENABLE controls the address latches used to hold an address stable during a bus cycle This control output is active HIGH ALE will not be issued for the halt bus cycle and is not affected by any of the control inputs MASTER CASCADE ENABLE signals that a cascade address from a master 8259A interrupt controller may be placed onto the CPU address bus for latching by the address latches under ALE control The CPU s address bus may then be used to broadcast the cascade address to slave interrupt controllers so only one of them will respond t
6. N makes a LOW to HIGH transition the commands and DEN outputs immediately go to the appropriate state see timing waveforms READY must still become active to terminate a bus cycle if CEN remains LOW for a selected bus controller CENL was latched HIGH CLK READY wid 51 50 intel Some memory or I O systems may require more ad dress or write data setup time to command active than provided by the basic command output timing To provide fiexibie command timing the CMDLY in put can delay the activation of command outputs The CMDLY input must be sampled LOW to activate the command outputs CMDLY does not affect the control outputs ALE MCE DEN and DT R COMMANDOS Figure 12 System Use of AEN and CENL 2 160 intel CMDLY is first sampled on the falling edge of the CLK ending Ts If sampled HIGH the command out put is not activated and CMDLY is again sampled on the next falling edge of CLK Once sampled LOW the proper command output becomes active immediately if MB 0 If MB 1 the proper com mand goes active no earlier than shown in Figures 9 and 10 READY can terminate a bus cycle before CMDLY allows a command to be issued In this case no commands are issued an the bus controller will de activate DEN and DT R in the same manner as if a command had been issued Waveforms Discussion The waveforms show the timing relationships of in puts and outputs and do not show all possible tran 820288 sitions
7. are delayed two CLK cycles 3 The LOW to HIGH transition of DEN for write cy cles is delayed one CLK cycle l 2 158 Back to back bus cycles with MB 1 do not change the timing of any of the command or control outputs DEN always becomes inactive between bus cycles with MB 1 Except for a halt or shutdown bus cycle ALE will be issued during the second half of Ts for any bus cy cle ALE becomes inactive at the end of the Ts to allow latching the address to keep it stable during the entire bus cycle The address outputs may change during Phase 2 of any Tc bus state ALE is not affected by any control input Figure 11 shows how MCE is timed during interrupt acknowledige INTA bus cycles MCE is one CLK cycle longer than ALE to hold the cascade address from a master 8259A valid after the falling edge of ALE With the exception of the MCE control output an INTA bus cycle is identical in timing to a read bus cycle MCE is not affected by any control input 240042 13 Figure 11 MCE Operation for an INTA Bus Cycle Control Inputs The control intputs can alter the basic timing of com mand outputs allow interfacing to multiple buses and share a bus between different masters For many 80286 systems each CPU will have more than one bus which may be used to perform a bus cycle Normally a CPU will only have one bus controller active for each bus cycle Some buses may be shared by more than one CPU i e MULTIBUS re
8. ate from DC to the appropriate upper frequency limit 2 153 820288 The clock may be stopped in either state HIGH LOW and held there indefinitety Power dissipation is directly related to operating fre quency As the system frequency is reduced so is the operating power When the clock is stopped to the 82C288 power dissipation is at a minimum This is useful for low power and portable applications FUNCTIONAL DESCRIPTION Introduction The 82C288 bus controller is used in 80286 systems to provide address latch control data transceiver control and standard level type command outputs The command outputs are timed and have sufficient drive capabilities for large TTL buses and meet all IEEE 796 reguirements for MULTIBUS 1 A special MULTIBUS mode is provided to satisfy all address data setup and hold time requirements Command timing may be tailored to special needs via a CMDLY input to determine the start of a command and to determine the end of a command Connection to multiple buses are supported with a latched enable input CENL An address decoder can determine which if any bus controller should be enabled for the bus cycle This input is latched to allow an address decoder to take full advantage of the pipelined timing on the 80286 local bus intel Buses shared by several bus controllers are sup ported An AEN input prevents the bus controller from driving the shared bus command and data signals except
9. intel i 82C288 BUS CONTROLLER FOR 80286 PROCESSORS 82C288 12 82C288 10 82C288 8 m Provides Commands and Controls for m Fully Static Device Local and System Bus m Available in 20 Pin PLCC Plastic m Wide Flexibility in System Leaded Chip Carrier and 20 Pin Cerdip Configurations Packages m High Speed CHMOS III Technology A OI Fully Compatible with the HMOS 82288 The Intel 820288 Bus Controller is a 20 pin CHMOS III component for use in 80286 microsystems The 820288 is fully compatible with its predecessor the HMOS 82288 The bus controller is fully static and supports a low power mode The bus controller provides command and control outputs with flexible timing options Separate command outputs are used for memory and I O devices The data bus is controlled with separate data enable and direction control signals Two modes of operation are possible via a strapping option MULTIBUS compatible bus cycles and high speed bus cycles STATUS Ll status w OU DECODER 240042 1 Figure 1 82C288 Block Diagram September 1989 Order Number 240042 003 2 149 820288 i ntel z 20 Pin Cerdip Package 240042 2 P C Board Views As viewed from the compo Component Pad Views As viewed from under nent side of the P C board side of component when mounted on the board 20 Pin PLCC Package Figure 2 820288 Pin Configuration 2 150 intel A 82C288 Table 1 Pin Description The following pin function desc
10. it becomes inactive MEMORY READ COMMAND instructs the memory device to place data onto the data bus This command output is active LOW The MB and CMDLY inputs control when this output becomes active READY controls when it becomes inactive 2 152 820288 Table 1 Pin Description Continued Name and Function INTERRUPT ACKNOWLEDGE tells an interrupting device that its interrupt request is being acknowledged This command output is active LOW The MB and CMDLY inputs control when this output becomes active READY controls when it becomes inactive ve System Power 5V Power Supply DE System Ground OV Command Activated None Idle Operating Modes Two types of buses are supported by the 82C288 MULTIBUS and non MULTIBUS 1 When the MB input is strapped HIGH MULTIBUS timing is used In MULTIBUS mode the 82C288 delays command and data activation to meet IEEE 796 requirements on address to command active and write data to command active setup timing MULTIBUS mode requires at least one wait state in the bus cycle since the command outputs are delayed The non MULTIBUS mode does not delay any outputs and does not require wait states The MB input affects the timing of the command and DEN outputs Command and Control Outputs The type of bus cycle performed by the local bus master is encoded in the M TO 31 and 50 inputs Different command and con
11. o the interrupt acknowledge cycle This control output is active HIGH MCE is only active during interrupt acknowledge cycles and is not affected by any control input Using MCE to enable cascade address drivers requires latches which save the cascade address on the falling edge of ALE DATA ENABLE controls when data transceivers connected to the local data bus should be enabled DEN is an active HIGH control output DEN is delayed for write cycles in the MULTIBUS mode DATA TRANSMIT RECEIVE establishes the direction of data flow to or from the local data bus When HIGH this control output indicates that a write bus cycle is being performed A LOW indicates a read bus cycle DEN is always inactive when DT R changes states This output is HIGH when no bus cycle is active DT R is not affected by any of the control inputs 1 0 WRITE COMMAND instructs an I O device to read the data on the data bus This command output is active LOW The MB and CMDLY inputs control when this output becomes active READY controls when it becomes inactive 1 0 READ COMMAND instructs an I O device to place data onto the data bus This command output is active LOW The MB and CMDLY inputs control when this output becomes active READY controls when it becomes inactive MEMORY WRITE COMMAND instructs a memory device to read the data on the data bus This command output is active LOW The MB and CMDLY inputs control when this output becomes active READY controls when
12. of all signals in all modes Instead all signal timing relationships are shown via the general cas es Special cases are shown when needed The waveforms provide some functional descriptions of the 82C288 however most functional descriptions are provided in Figures 5 through 11 To find the timing specification for a signal transition in a particular mode first look for a special case in the waveforms If no special case applies then use a timing specification for the same or related func tion in another mode 2 161 82C288 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Voltage on Any Pin with Respect to GND 0 5V to 7V Power Dissipation 1 Watt NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability D C CHARACTERISTICS Vcc 5V 5 Tcase 0 C to 85 C Syme Parameter vu iron Votago ee CLK Input HIGH Voltage Output LOW Voltage Command Outputs Control Outputs Output HIGH Voltage Command Outputs Control Outputs ILO Output Leakage Current Min 08 In
13. ontroller may enter the Ts bus state directly from Tc if the status lines are sampled active at the next falling edge of CLK Ma 240042 7 2 155 82C288 Figures 6 through 10 show the basic command and control output timing for read and write bus cycles Halt bus cycles are not shown since they activate no outputs The basic idle read idle and idle write idle bus cycles are shown The signal label CMD repre sents the appropriate command output for the bus cycle For Figures 6 through 10 the CMDLY input is connected to GND and CENL to Vcc The effects of CENL and CMDLY are described later in the section on control puts Figures 6 7 and 8 show non MULTIBUS cycles MB is connected to GND while CEN is connected to Vcc Figure 6 shows a read cycle with no wait states while Figure 7 shows a write cycle with one wait state The READY input is shown to illustrate how wait states are added Figure 7 Idle Write Idle Bus Cycles with MB 0 2 156 i ntel N 82C288 Bus cycles can occur back to back with no Tj bus states between Tc and Ts Back to back cycles do not affect the timing of the command and control outputs Command and control outputs always reach the states shown for the same clock edge within Ts Tc or following bus state of a bus cycle 18T WRITE CYCLE 2ND WRITE CYCLE A special case in control timing occurs for back to back write cycles with MB 0 In this case DT R and DEN remain
14. pond to the current bus cycle being initiated CENL is an active HIGH input latched internally at the end of each Ts cycle CENL is used to select the appropriate bus controller for each bus cycle in a system where the CPU has more than one bus it can use This input may be connected to Vcc to select this 820288 for all transfers No control inputs affect CENL Setup and hold times must be met for proper operation COMMAND DELAY allows delaying the start of a command CMDLY is an active HIGH input If sampled HIGH the command output is not activated and CMDLY is again sampled at the next CLK cycle When sampled LOW the selected command is enabled If READY is detected LOW before the command output is activated the 82C288 will terminate the bus cycle even if no command was issued Setup and hold times must be Satisfied for proper operation This input may be connected to GND if no delays are required before starting a command This input has no effect on 82C288 control outputs READY indicates the end of the current bus cycle READY is an active LOW input MULTIBUS mode requires at least one wait state to allow the command outputs to become active READY must be LOW during reset to force the 82C288 into the idle state Setup and hold times must be met for proper operation The 82C284 drives READY LOW during RESET 2 151 82C288 i ntel a Table 1 Pin Sa Continued Symbol Type Nameandfuncti n CEN AEN COMMAND ENABLE ADDRESS
15. put HIGH Voltage 20 e a EEE ai Test Conditions lo 32 mA Note 1 loL 16 mA Note 2 lod 5 mA Note 1 loH 1 mA Note 1 loH 1 mA Note 2 lon 0 2 mA Note 2 Y V V V 110 pA OV lt VN lt Voc pA ma ma pF 0 45V lt Vout lt Vcc a MEA ro re EEEL Ta is guaranteed from 0 C to 70 C as long as Tcage is not exceeded NOTES 1 Command Outputs are INTA IORC IOWC MRDC and MWAC 2 Control Outputs are DT R DEN ALE and MCE 3 Tested while outputs are unloaded and inputs at Voc or Vss 2 162 intel A C CHARACTERISTICS 82C288 Voc 5V 5 Tcase 0 C to 85 C AC timings are referenced to 0 8V and 2 0V points of signals as illustrated in data sheet waveforms unless otherwise noted aos 63 4 CLK Rise Time CLK Fall Time M IO and Status Setup Time M IO and Status Hold Time CENL Setup Time CENL Hold Time READY Setup Time READY Hold Time CMDLY Setup Time CMDLY Hold Time AEN Setu ALE MCE Active Delay from CLK DEN Write Inactive from CENL DT R LOW from CLK DEN Read ActiveR from DT DEN Read Inactive Dly from CLK DT R HIGH from DEN Inactive DEN Write Active Delay from CLK DEN Write Inactive Dly from CLK Ta is guaranteed from 0 C to 70 C as long as Tcase is not exceeded 7 _ 14 p Time 6 o 17 EE 19 21
16. riptions are for the 82C288 bus controller Name and Function SYSTEM CLOCK provides the basic timing control for the 82C288 in an 80286 microsystem Its freguency is twice the internal processor clock freguency The falling edge of this input signal establishes when inputs are sampled and command and control outputs change BUS CYCLE STATUS starts a bus cycle and along with M 10 defines the type of bus cycle These inputs are active LOW A bus cycle is started when either S1 or 50 is sampled LOW at the falling edge ot CLK Setup and hold times must be met for proper operation 80286 Bus Cycle Status Definition M 15 50 Type of Bus Cycle 0 0 Interrupt Acknowledge I O Read 1 0 Write None Idle Halt or Shutdown Memory Read Memory Write None Idle MEMORY OR 1 0 SELECT determines whether the current bus cycle is in the memory space or I O space When LOW the current bus cycle is in the I O space Setup and hold times must be met for proper operation MULTIBUS MODE SELECT determines timing of the command and control outputs When HIGH the bus controller operates with MULTIBUS compatible timings When LOW the bus controller optimizes the command and control output timing for short bus cycles The function of the CEN AEN input pin is selected by this signal This input is typically a strapping option and not dynamically changed COMMAND ENABLE LATCHED is a bus controller select signal which enables the bus controller to res
17. trol outputs are activat ed depending on the type of bus cycle Table 2 indi cates the cycle decode done by the 82C288 and the effect on command DT R ALE DEN and MCE out puts Bus cycles come in three forms read write and halt Read bus cycles include memory read 1 0 read and interrupt acknowledge The timing of the associated read command outputs M TORC and INTA control outputs ALE DEN DT R and control inputs CEN CENL CMDLY MB and are identical for ail read bus cycles Read cycles differ only in which command output is acti vated The MCE control output is only asserted dur ing interrupt acknowledge cycles Write bus cycles activate different control and com mand outputs with different timing than read bus cy cles Memory write and 1 O write are write bus cy cles whose timing for command outputs MWTC and TOWC control outputs ALE DEN DT R and con trol inputs CEN AEN CENL CMDLY MB and READY are identical They differ only in which com mand output is activated Hait bus cycles are different because no command or control output is activated All control inputs are erred until the next bus cycle is started via ST and Static Operation All 82C288 circuitry is of static design Internal regis ters and logic are static and require no refresh as with dynamic circuit design This eliminates the mini mum operating frequency restriction placed on the HMOS 82288 The CHMOS III 82C288 can oper
18. ued STATUS ALE MCE CHARACTERISTICS 240042 20 240042 21 2 166 intel n 82C288 WAVEFORMS Continued WRITE CYCLE CHARACTERISTIC WITH MB 0 AND CEN 1 240042 23 2 167 82C288 i ntel A WAVEFORMS Continued AEN CHARACTERISTICS WITH MB 1 NOTE 1 AEN is an asynchronous input AEN setup and hold time is specified to guarantee the response shown in the waveforms MB CHARACTERISTICS WITH AEN CEN HIGH 240042 25 2 168 j ntel A 82C288 WAVEFORMS Continued MB CHARACTERISTICS WITH AEN CEN HIGH Continued NOTES 1 MB is an asynchronous input MB setup and hold times specified to guarantee the response shown in the waveforms 2 If the setup time t35 is met two clock cycles will occur before CMD becomes active after the falling edge of MB DATA SHEET REVISION REVIEW The following list represents key differences between this and the 002 data sheet Please review this summa ry carefully 1 The Iccs specification was changed from 1 mA to 3 MA maximum 2 The PRELIMINARY markings have been removed from the data sheet 2 169
19. when enabied by an external MULTIBUS 1 type bus arbiter Separate DEN and DT R outputs control the data transceivers for all buses Bus contention is eliminat ed by disabling DEN before changing DT R The DEN timing allows sufficient time for tristate bus driv ers to enter 3 state OFF before enabling other driv ers onto the same bus The term CPU refers to any 80286 processor or 80286 support component which may become an 80286 local bus master and thereby drive the 82C288 status inputs Processor Cycle Definition Any CPU which drives the local bus uses an internal clock which is one half the frequency of the system clock CLK see Figure 3 Knowledge of the phase of the local bus master internal clock is required for proper operation of the 80286 local bus The local bus master informs the bus controller of its internal clock phase when it asserts the status signals Status signals are always asserted beginning in Phase 1 of the local bus master s internal clock ONE PROCESSOR CLOCK CYCLE ONE BUS T STATE PHASE 1 OF PROCESSOR CLOCK CYCLE 820284 FOR REFERENCE PHASE 2 OF PROCESSOR CLOCK CYCLE Figure 3 CLK Relationship to the Processor Clock and Bus T States 2 154 intel Bus State Definition The 82C288 bus controller has three bus states see Figure 4 Idle T Status Ts and Command To Each bus state is two CLK cycles long Bus state phases correspond to the internal CPU processor clock phases
20. ycles This transition occurs before CENL is sampled If CENL is sampled LOW the DEN output will be forced LOW during Tc as shown in the timing waveforms When MB 1 CEN AEN becomes AEN AEN con trols when the bus controller command outputs en ter and exit 3 state OFF AEN is intended to be driv en by a MULTIBUS type bus arbiter which assures only one bus controller is driving the shared bus at any time When AEN makes a LOW to HIGH tran sition the command outputs immediately enter 3 state OFF and DEN is forced inactive An inactive DEN should force the local data transceivers con nected to the shared data bus into 3 state OFF see Figure 12 The LOW to HIGH transition of should only occur during T or Ts bus states The HIGH to LOW transition of AEN signals that the bus controller may now drive the shared bus com mand signals Since a bus cycle may be active or be in the process of sae AEN can become active during any T state N LOW immediately allows DEN to go to the appropriate state Three CLK edg es later the command outputs will go active see timing waveforms The MULTIBUS requires this delay for the address and data to be valid on the bus before the command becomes active When MB 0 CEN AEN becomes CEN CEN is an asynchronous input which immediately affects the command and DEN outputs When CEN makes a HIGH to LOW transition the commands and DEN 2 159 82C288 are immediately forced inactive When CE

intel 82C288 Data Sheet

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