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CRYSTAL CS4923/4/5/6/7/8/9 DATA SHEET

1. DC Start DC Stop AEL ad gem ea RE ic y o i Min gg SCDIO AD6 AD5 AD4 AD3 AD2 AD1 ADO R W ACK D7 D6 D5 D4 D3 D2 DI DO ACK D7 De DS D4 D3 D2 D1 DO ACK D7 DE DS D4 D3 D2 DI DO ACK DC Write Functional Timing 12C Start DC Stop sese Elke L Ll EIERE AS AA EE FU SCDIO AD6 AD5 AD4 AD3 AD2 AD1 ADO R W ACK D7 D6 DS D4 D3 D2 DI DO ACK D7 D6 DS D4 D3 D2 DI DO JACK D7 D6 DS D4 D3 D2 D1 DO Nac INREQ E il AT de 1 uS ep Note 4 Note 5 Note 4 DC Read Functional Timing Notes 1 The ACK for the address byte is driven by the CS4923 4 5 6 7 8 9 2 The ACKs for the data bytes being read from the CS4923 4 5 6 7 8 9 should be driven by the host 3 INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to be transferred out of the CS4923 4 5 6 7 8 9 4 ANOACK should be sent by the host after the last byte read to indicate the end of the read cycle 5 INTREQ is guaranteed to stay high until the next rising edge of SCCLK for the ACK NACK bit at which point it may go low again if there is new data to be read The condition of INTREQ going low at this point should be treated as a n
2. do ee oe sea 4 a NOTE Only AUDATAO connection applies for the CS4929 Sl Ss S 93 Dc ARA beze 33 sok H3 9 T SYSTEM o lt gt gt NTREG ABOOT iur gt DACs x N gt H sono ii a le AUDATAO gt MICRO ui li sowas La E 18 75 z Si aix AUDATA2 HE gt CONTROLLER o gt reset e CMPDAT cupouk a gt 4 DIR or CMPREO EXTERNAL CS4923 4 5 6 7 8 9 ADCs ROM al spray Heel gt WR apo BK o gt Mr 1 T 1 lt AA Mim SLRCLKN E SEI M ELE d XMT958 H J M EMADT EMADS 33 OCTAL F F OCTAL F F E oun lt A OSCILLATOR EMADA EMADS aki HL 3 18 Q7 0 Q 7 0 we 6 P wo qii Poema D Bu Dus Bib 888 s A 7 0 33 22uF D 7 0 ozu z Y Y Figure 14 PC Control with External Memory 26 DS262F2 MY S EN AW AW AU Y Zem Gees SNAM CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is simply 3 3VD after filt ering through the ferrite bead Pin 32 must be referenced to 3 3VA FERRITE BEAD 3 3VA tur OiuF tur ua tur 0 1 uF tor 0 1 uF 47uF E 4 4 NOTE Only AUDATAO connection applies for the CS4929 E om 88 s 3 8 gt gt gt MCLK H
3. RD WR PSEL Host Interface Mode Pin 5 Pin 4 Pin 19 1 1 1 8 bit Motorola 1 1 0 8 bit Intel 0 1 X Serial 12C 1 0 X Serial SPI Table 2 Host Modes Whichever host communication mode is used host control of the CS4923 4 5 6 7 8 9 is handled through the application software running on the DSP Configuration and control of the CS492X decoder and its peripherals are indirectly executed through a messaging protocol supported by the downloaded application code In other words successful communication can only be accomplished by following the low level hardware communication format and high level messaging protocol The specifications of the messaging protocol can be found in any of the application code user s guides It should be noted that when using the CS4926 or CS4928 for DTS decoding an external memory interface must be used for DTS tables that are required for decoding see section 6 5 for information on external memory The external memory interface and the parallel interface modes can not be used together For this reason the system designer must use one of the serial communication modes with external memory if designing with the DS262F2 CS4926 or CS4928 for DTS decode An image of the DTS tables is available from the factory Below is a brief discussion of each of the communication modes available for the CS4923 4 5 6 7 8 9 For a complete description of these communication modes along wi
4. gt LRCLK Lie m9 AUDATAO AUDATA D AUDATA2 LAS CMPDAT F L DACs CMPCLK FAB cuneo H2 SDATAN 2 SCLKN 25 ANA SLRCLKN lt T gt XMT958 cLKIN HE CLKSEL L 4 4 pS Fl pur HA 24 0 22 uF co oo lt gt 10k Figure 18 Motorola Parallel Control Mode 30 DS262F2 AE S IN EE Y e 7 HE GG V HHA EW IF I AW AW I I NEN CS4923 4 5 6 7 8 9 4 POWER The CS492X requires a 3 3V digital power supply for the digital logic within the DSP and a 3 3V analog power supply for the internal PLL There are three digital power pins VD1 VD2 and VD3 along with three digital grounds DGND1 DGND2 and DGND3 There is one analog power pin VA and one analog ground AGND The DSP will perform at its best when noise has been eliminated from the power supply The recommendations given below for decoupling and power conditioning of the CS492X will help to ensure reliable performance 4 1 Decoupling It is good practice to decouple noise from the power supply by placing capacitors directly between the power and ground of the CS492X Each pair of power pins VDI DGND VD2 DGND VD3 DGND VA AGND should have its own decoupling capacitors The recommended procedure is to place both a 0 1uF DS262F2 and a luF capacitor as close as physical
5. Audio Decoder The CS4923 is the original member of the family and is intended to be used if only Dolby Digital decoding is required For Dolby Digital post processing includes bass management delays and Dolby Pro Logic decoding Separate downloads can also be used to support stereo to 5 1 channel effects processing and stereo MPEG decoding CS4924 Dolby Digital Source Product Decoder The CS4924 is the stereo version of the CS4923 designed for source products such as DVD HDTV and set top boxes Separate downloads are available for stereo decode of Dolby Digital and MPEG audio CS4925 International Multi Channel DVD Audio Decoder The CS4925 supports both Dolby Digital and MPEG 2 multi channel formats For both Dolby Digital and MPEG 2 multi channel post processing includes bass management and Dolby Pro Logic decoding Separate downloads are available for decode of Dolby Digital and MPEG DS262F2 audio Another code load can be used to support stereo to 5 1 channel effects processing CS4926 DT S Dolby Multi Channel Audio Decoder The CS4926 supports both Dolby Digital and DTS or Digital Theater Surround For Dolby Digital post processing includes bass management and Dolby Pro Logic The Dolby Digital code and DTS code take separate code downloads Separate downloads can also be used to support stereo to 5 1 channel effects processing and stereo MPEG decoding CS4927 MPEG 2 Multi Channel Decoder The CS4927
6. C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF z CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS RESET Parameter Symbol Min Max Unit RESET minimum pulse width low Trstl 100 ns All bidirectional pins high Z after RESET low Trst2z 50 ns Configuration bits setup before RESET high Trstsu 50 ns Configuration bits hold after RESET high Trsthld 15 ns RESET RD WR PSEL ABOOT All Bidirectional A Outputs p Trstsu Trsthld Trst2z ad ka gt Ta la a Figure 1 RESET Timing DS262F2 AE EA II IN EE Y e 7 E GU U V HHA BEP IF I AW AW S SUN Ey CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS CMPDAT CMPCLK Ta 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Unit Serial compressed data clock CMPCLK period Tompelk 37 ns CMPDAT setup before CMPCLK high Tempsu 5 ns CMPDAT hold after CMPCLK high Temphld ns CMPCLK CMPDAT Tempsu Ka Tomphld Tempelk a Figure 2 Serial Compressed Data Timing DS262F2 AE EA II IN EE Y e ZS ees HANE CS4923 4 5 6 7 8 9 EE E SWITCHING CHARACTERISTICS CLKIN TA 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Unit CLKIN period for internal DSP clock mode Telki 20 3800 ns CLKIN high time for internal DSP cloc
7. u 9 We oer DACs l LL DATA 41 y cc AUDATAO gt CH Mu MM AUDATA1 H gt ud z Rin AUDATA2 32 S Z E DATA3 l2 O z DES CMPDAT lt DATA1 Kg Los 5 T Gare CMPREQ DATAO S Am CS4923 4 5 6 7 8 9 o GPIO8 SDATAN 42 Lm SCLKN LR 6 OPT TX RD SLRCLKN PE M di v 3 AN Sa XMT958 gt A0 33 gt os e EM OSCILLATOR gt 25 RESET cLKSEL Hi SL PSEL GPIO9 588388 Fr 3 3VA 2 P 288582 eo Hi AW 434335 2 2uF w T 0 22 uF Y Figure 17 Intel Parallel Control Mode DS262F2 29 AE S IN AW AW AUN Y 7 4 A S HHH EW I I AW AW I AA Ep CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is simply 3 3VD after filt ering through the ferrite bead Pin 32 must be referenced to 3 3VA 3 3VA 47 uF FERRITE BEAD COCA 0 1 uF tur 0 1 uE 0 1 uF tur 0 1 uF tur MICROCONTROLLER 10k 10k 10k 10k 4 70K Resistor Pack 10k 4 70K 4 70K 1 34 NTERFACE MOT INTREG DATA DATA6 DATAS DATA4 DATA3 DATA2 DATA DATAO GPIO8 PSEL_GPIO9 R W__RD DS WR VD DGND1 DGND2 DGND3 CS4923 4 5 6 7 8 9 AGND VA MCLK NOTE Only AUDATAO connection applies for the CS4929 i sci HI
8. lt gt 20 mro xr LRCLK Lie DACs x 19 Sle 4 SCDOUT m ES gt sco AUDATAO gt M IC RO Lu ia Je aupatat L gt zi S M AUDATA2 32 gt CONTROLLER a gt it FE SET U CMPDAT lt CMPCLK H E S 4 DIR or cupreg PLE gt S CS4923 4 5 6 7 8 9 ADCs X AL poe T i em podra m OPT_TX ICE m erior SLRCLKN HE gt 3 M OE lt ds XxMT958 H H M EMAD6 33 OCTAL F F OCTAL F F GE on lt dd OSCILLATOR EMAD4 EMAD3 os EL E 8 l 0o 7 0 ND Wk iiis S m rue 2 3 3VA z D 7 0 D 7 0 EMADO 8 8 8 8 pm FAL L A 7 0 d 3 S 220F D 7 0 T oar Y Figure 16 SPI Control with External Memory 28 DS262F2 MY S EN AW AW AU Y Zem Gees SNAM CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD T NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is simply 3 3VD after filt ering through the ferrite bead Pin 32 must be referenced to 3 3VA FERRITE BEAD A gt tor o1uF tor O4uF tor 0 1 uF tor 04uF 47 uF i i I SCH 3 3VD 3 3VD ne m c4 ed TA Se 4 NOTE Only AUDATA0 connection applies for the CS4929 E a S 8 z lt E n li S Z 2 7 mek Le 5 scuk H2 gt 4 LU 42
9. 27 Tadsm 10 ns Slave Mode Note 28 Time from active edge of SCLKN1 2 to LRCLKN1 2 transition Tstr 10 ns Time from LRCLKN1 2 transition to SCLKN1 2 active edge Tirts 10 ns AUDATA2 0 delay from SCLK transition Note 27 29 Tadss 15 ns Notes 24 MCLK can be an input or an output These specifications apply for both cases 25 Master mode timing specifications are characterized not production tested 26 Master mode is defined as the CS4923 driving both SCLK and LRCLK When MCLK is an input it is divided to produce SCLK and LRCLK 27 This timing parameter is defined from the non active edge of SCLK The active edge of SCLK is the point at which the data is valid 28 Slave mode is defined as SCLK and LRCLK being driven by an external source 29 This specification is characterized not production tested 18 DS262F2 AE S IN EE Y e 7 ER TZ U E HHH SE I I A AP E HUM CS4923 4 5 6 7 8 9 MCLK Input N N M N Tmelk SCLK Output Tsami MCLK Output J N Tmelk SCLK Output X Tsdmo MASTER MODE SCLK v Y Y Y b Tscik gt Tiras LRCLK x p A A Tadsm 4 AUDATA2 0 V Y N SLAVE MODE ir END WEEDS jE Ts Tscik WS ple Ta LRCLK V Y Tadss lt gt AUDATA2 0 Y Figure 12 Digital Audio Output Data and Clock Timing DS262F2 19 AE S IN EE Y e 7 E GU U V AA BEP IN I AW AW I I NUM CS4923 4 5 6 7 8 9 2 FAMILY
10. 46 7 4 Parallel Digital Audio Data Input sss sese 46 7 5 Digital Audio Output Port oo ee eee eee 47 EDA 1EC60958 QUIDUL aia aaa RY HN aay ert 48 M Nelle lee SX 49 9 PAGKAGE DIMENSIONS 1n encino CERS EES 54 LIST OF FIGURES Eigure l RESET Timiligs i iod inne ied E et CA Hed cubos o de a de ed alt 5 Figure 2 Serial Compressed Data Timing 6 Figure 3 CLKIN with CLKSEL VSS PLL Enable wel Figure 4 CLKIN with CLKSEL VD PLL Bypass sss sees eee eee eee 7 Figure 5 Intel Parallel Host Mode Read Cycle 9 Figure 6 Intel Parallel Host Mode Write Cycle AA 9 Figure 7 Motorola Parallel Host Mode Read Cycle see 11 Figure 8 Motorola Parallel Host Mode Write Cwcle A 11 Figure 9 SPI Control Port Timing 13 Figure 10 C Control Port nu e m 15 Figure 11 Digital Audio Input Data and Clock Tmimg nn 17 Figure 12 Digital Audio Output Data and Clock Timing eee 19 Figure 13 EES Control ET 25 Figure 14 12C Control with External Memor EE RH HF FR HRN ete 26 Figure 15 PI Controli ie ect eege EY Go and O IU 27 Figure 16 SPI Control with External Memory sese e eee eee eee eee ee eee 28 Figure 17 Intel Parallel Control Mode oooonoonnnon none onen en nn 29 Figure 18 Motorola Parallel Control Mode AAA 30 ais ES RES d RR Ile RE 38 Figure 20 ZC mq LE E Id cu M M i Ls 40 Figure 21 External Memory Interface A 42 Figure 22 Run Time Memory A
11. EW RSA AP HE SS 4 CS4923 4 5 6 7 8 9 Host Message HOSTMSG Register A 1 0 00b 7 6 5 4 3 2 1 0 HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG4 HOSTMSG3 HOSTMSG2 HOSTMSG1 HOSTMSGO HOSTMSG7 0 Host data to and from the DSP A read or write of this register operates handshake bits between the internal DSP and the external host This register typically passes multibyte messages car rying microcode control and configuration data HOSTMSG is physically implemented as two independent registers for input and output Read and write Host Control CONTROL Register A 1 0 01b 7 6 5 4 3 2 1 0 Reserved CMPRST PCMRST MFC MFB HINBSY HOUTRDY Reserved Reserved Always write a 0 for future compatibility CMPRST When set initializes the CMPDATA compressed data input channel Writing a one to this bit holds the port in reset Writing zero enables the port This bit must be low for normal operation Write only PCMRST When set initializes the linear PCM input channel This bit is toggled to indicate the first sample of the left channel for a PCM stream Writing a one to this bit holds the port in reset Writing zero enables the port This bit must be low for normal operation Write only MFC When high indicates that the PCMDATA input buffer is almost full The input buffer threshold level is application code dependent Read only MFB When high indicates that the CMPDATA inpu
12. begins an 8 bit write cycle The address A 1 0 must be valid a minimum time before either CS or WR goes low On the first rising edge of CS or WR the write cycle ends and DATA 7 0 are latched internally by the CS492X Data must be held sufficiently to satisfy the hold time as given in the timing section The HINBSY bit is set when the host writes the HOSTMSG register This bit is cleared when the byte in the HOSTMSG register is read by the DSP During RESET low all control signals have no effect and DATA 7 0 are high impedance PCMDATA _ 8 bit linear PCM data to input unit write only CONTROL Multi bit control regis ter for setup and handshaking R W 8 bit control pipe message register HOSTMSG R W Table 3 Host Memory Map 6 2 1 Intel Parallel Host Mode Intel parallel host mode is accomplished with CS RD WR A 1 0 and DATA 7 0 Table 4 shows the pin name pin description and pin number of 34 Pin Name Pin Description Pin Number CS Chip Select 18 RD Output Enable 5 WR Write Enable 4 A1 Register Address 1 6 AO Register Address 0 7 INTREQ Interrupt Request 20 DATA7 Data Bit 7 8 DATA6 Data Bit 6 9 DATA5 Data Bit 5 10 DATA4 Data Bit 4 11 DATA3 Data Bit 3 14 DATA2 Data Bit 2 15 DATA1 Data Bit 1 16 DATAO Data Bit 0 17 Table 4 Intel Parallel Host Mode Pin Assignments DS262F2 AE S IN EE Y e 7 EG U Z HHH
13. covers the features available in the 22 MPEG Multi Channel code including delays bass management Pro Logic and MPEG processing features ANI22 DTS User s Guide for the CS4926 CS4928 This document covers the features available in the DTS code including bass management and DTS processing features ANI23 Surround User s Guide for the CS4923 4 5 6 7 8 This code covers the different Stereo PCM to surround effects processing code Optional appendices are available that document Crystal Original Surround Circle Surround and Logic 7 ANI40 Broadcast Systems Guide for the CS4923 4 5 6 7 8 9 This guide describes all application code e g Dolby Digital MPEG AAC designed for broadcast systems such as HDTV and set top box receivers This document also provides a discussion of broadcast system considerations and dependencies such as A V synchronization and channel change procedures 2 3 Using the CS4923 4 5 6 7 8 9 No matter what application is being used on the chip the following four steps are always followed to use the CS4923 4 5 6 7 8 9 in system 1 Reset and or Download Code information in AN115 Detailed 2 Hardware Configuration Detailed information in AN115 3 Application configuration Detailed information in the appropriate Application Code User s guide 4 Kickstart This is the Go command to the CS492X once the system is properly configured Information can be found in the appropriat
14. for the last data bit If there is more data to be read from the DSP before the rising edge of SCCLK for the second to last data bit then INTREQ remains asserted low Immediately following the falling edge of SCCLK for the last data bit of the current byte the next data byte loads into the internal serial shift register The host should continue to read this new byte It is important to note that once the data is in the shift register clocks on the SCCLK line shift the data bits out of the shift register as long as CS is low For a thorough look at SPI communication and critical additional comments on INTREQ behavior reference the CS4923 4 5 6 7 8 9 Hardware User s Guide 37 8 c4c9cSd SCCLK MN LILI Le Ee EN rep A E SCDIN ADG AD5 AD4 AD3 AD2 JAD1 ADO R W D7 De D5 D4 D3 D2 DI DO D7 D6 DS DA D3 D2 DI DO D7 D6 DS D4 D3 D2 D1 DO es SPI Write Functional Timing SCCLK PLU LILI ASAS 2 A o ME s Ce IOa HS SCDIN AD6 AD5 AD4 AD3 AD2 AD1 ADO R W SCDOUT D7 D6 D5 D4 D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO D7 DE D5 DA D3 D2 D1 DO cs po INTREG A SPI Rea
15. memory configuration can be used for autoboot The higher order address byte simply shifts out of the memory latch and is discarded If desired a three latch interface could also be used with the CS4923 4 5 7 9 but it is not necessary For more information about autoboot and for a thorough description of different external memory architectures reference the CS4923 4 5 6 7 8 9 Hardware User s Guide EXTMEM EMOE EMWR EMAD7 0 MA23 16 MA15 8 MA7 0 Data7 0 E Figure 23 Autoboot Timing Diagram DS262F2 43 AE S IN EE Y e 7 HE GG U V HHA BEP IF I AW AW I I NEN CS4923 4 5 6 7 8 9 7 DIGITAL INPUT amp OUTPUT The CS4923 4 5 6 7 8 9 supports a wide variety of data input and output mechanisms through various input and output ports Hardware availability is entirely dependent on whether the software application code being used supports the required mode This data sheet presents most of the modes available with the CS4923 4 5 6 7 8 9 hardware This does not mean that all of the modes are available with any particular piece of application code Both the CS4923 4 5 6 7 8 9 Hardware User s Guide and the application code user s guide for the particular code being used should be referenced to determine if a particular mode is supported 7 1 Digital Audio Formats This subsection will describe some common audio formats that the CS4923 4 5 6 7 8 9 supports It should be noted that the input ports
16. on the CS4923 4 5 6 7 8 9 In Motorola host interface mode the host interface pins act as an active low chip select CS an active low data strobe DS and a R W control signal Internally to the CS492X DS and CS are logically ANDED Therefore in some cases DS and CS can be externally tied together with a common active low strobe Otherwise in long decoder delay scenarios read or write cycles can be terminated earlier by connecting the microprocessor active low data strobe signal to the CS492X DS and a delayed final active low chip select independently to the CS pin When the DSP writes a byte to the HOSTMSG register the HOUTRDY bit in the CONTROL register is set to indicate that there 1s data to be read During read cycles DATA 7 0 are driven when R W is high and DS and CS are both low DATA 7 0 are released with the earliest of CS or DS going high The HOUTRDY bit of the CONTROL register is cleared after the host reads from the HOSTMSG register Write cycles occur with R W low followed by DS and CS both going low The A 1 0 address pins select the specific address of the register to be written and DATA 7 0 carry the data to be written For write cycles the first of CS and DS going high latches data Data must be held sufficiently to satisfy the hold time as given in the timing section The HINBSY is set when the host writes the HOSTMSG register This bit is cleared when the byte in the HOSTMSG 1s internally read by the DS
17. thdst flow thdd thigh to tsca INTREO f s D Figure 10 PC Control Port Timing NN NS AW AW I M AEE EE H AMADO S o M EW AW AU ff Gl 4p 6 8 2 9 S V EC6VSD MY A EN EN AW AU AU Y Zem EN A a I HE CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS DIGITAL AUDIO INPUT TA 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Unit SCLKN1 2 period for both Master and Slave mode Note 19 Tsciki 40 ns SCLKN1 2 duty cycle for Master and Slave mode Note 19 45 55 Master Mode Note 19 20 LRCLKN1 2 delay after SCLKN1 2 transition Note 21 Tiras 10 ns SDATAN1 2 setup to SCLKN1 2 transition Note 22 Tsdsum 10 ns SDATAN1 2 hold time after SCLKN1 2 transition Note 22 Tsdhm 5 ns Slave Mode Note 23 Time from active edge of SCLKN1 2 to LRCLKN1 2 transition Totir 10 ns Time from LRCLKN1 2 transition to SCLKN1 2 active edge Tirts 10 ns SDATAN1 2 setup to SCLKN1 2 transition Note 22 Tsdsus 5 ns SDATAN 2 hold time after SCLKN1 2 transition Note 22 Tedhs 5 ns Notes 19 Master mode timing specifications are characterized not production tested 20 Master mode is defined as the CS4923 driving LRCLKN1 2 and SCLKN1 2 Master or Slave mode can be programmed 21 This timing parameter is defined from the non active edge of SCLKN1 2 The active edge of SCLKN 1 2 is the po
18. use up to 24 bit PCM resolution and 16 bit compressed data word lengths The output port of the CS492X provides up to 20 bit PCM resolution PS Figure 24 shows the DS format For I S data is presented most significant bit first one SCLK delay after the transition of LRCLK and is valid on the rising edge of SCLK For the PS format the left subframe is presented when LRCLK is low and the right subframe is presented when LRCLK is high SCLK is required to run at a frequency of 48Fs or greater on the input ports Left Justified Figure 25 shows the left justified format with a rising edge SCCLK Data is 44 presented most significant bit first on the first SCLK after an LRCLK transition and is valid on the rising edge of SCLK For the left justified format the left subframe is presented when LRCLK is high and the right subframe is presented when LRCLK is low The left justified format can also be programmed for data to be valid on the falling edge of SCLK SCLK is required to run at a frequency of 48Fs or greater on the input ports Right Justified Figure 26 shows the right justified format The right justified format is similar to the left justified format except the least significant bit is right justified to be valid on the last transition of SCLK before an LRCLK transition Data is still presented most significant bit first For the right justified format the left subframe is presented when LRCLK is high and the right subframe i
19. with CS492X for readability Unless otherwise specified CS492X should be interpreted as applying to the CS4923 CS4924 CS4925 CS4926 CS4927 CS4928 and CS4929 There are two revisions of silicon commercially available The features available on Revision D are a super set of those features available on Revision B Differences between the revisions are pointed 20 out when features are discussed within this document The silicon revision for any chip can be determined by referencing Table 1 below Revision B Revision D CS492301 CS492305 CS492401 CS492405 CS492501 CS492505 CS492603 CS492604 CS492705 CS492804 CS492906 Table 1 Silicon Revisions These parts are generally targeted at two different market segments The broadcast market where audio video A V synchronization is required and the outboard decoder markets where audio video synchronization is not required The important differentiation is the format in which the data will be received by the CS4923 4 5 6 7 8 9 In systems where A V synchronization is required from the CS4923 4 5 6 7 8 9 the incoming data is typically PES encoded In an outboard decoder application the data typically comes in the IEC61937 format as specified by the DVD consortium An important point to remember is that the CS4923 4 5 6 7 8 9 will support both environments but different downloads are required depending on the input data type Broadcast applicati
20. 0 650 0 656 15 925 16 662 E2 0 590 0 630 14 455 16 002 e 0 040 0 060 0 980 1 524 54 DS262F2 e Notes e
21. 0 ns Notes 5 The specification f indicates the maximum speed of the hardware The system designer should be aware that the actual maximum speed of the communication port may be limited by the software The relevant application code user s manual should be consulted for the software speed limitations 6 Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK 7 SCDOUT should not be sampled during this time period 8 INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the second to last bit of the last byte of data during a read operation as shown 9 If INTREQ goes high as indicated in Note 8 then INTREQ is guaranteed to remain high until the next rising edge of SCCLK If there is more data to be read at this time INTREQ goes active low again Treat this condition as a new read transaction Raise chip select to end the current read transaction and then drop it followed by the 7 bit address and the R W bit set to 1 for a read to start a new read transaction 10 With a 4 7k Ohm pull up resistor this value is typically 215ns As this pin is open drain adjusting the pull up value will affect the rise time 11 This time is by design and not tested 12 DS262F2 c4ic9csa EL dl cs d d tess tscl 0 1 2 6 7 0 ECH 7 fa V V SCCLK NJ j kod CX d yal Es K C LL L
22. 1 External Memory Interface EXTMEM EMOE EMAD 7 0 MA15 8 MA7 0 Data7 0 X Figure 22 Run Time Memory Access 42 DS262F2 AE S IN EE Y e 7 E GU U V HH BEP IF I AW AW IU I NEN CS4923 4 5 6 7 8 9 Although the memory can use more address bits typically only 16 bits of address space are used For this reason the memory example shown incorporates a 2 latch memory architecture The two latch external memory architecture is required for the CS4926 or CS4928 when using DTS A three latch architecture can not be used with the CS4926 or CS4928 running DTS since the run time memory access uses only 2 address cycles 6 5 1 External Memory and Autoboot To configure the CS4923 4 5 6 7 S 9 to automatically load its code from external memory the ABOOT signal should be driven low at the rising edge of RESET Once again this mode can only be chosen if either SPI or PC serial communication is being used In serial control port mode holding the ABOOT pin low as the CS492X leaves the reset state enables an automatic boot RESET A ABOOT ABOOT can be released following the rising edge of RESET During the automatic boot cycle the serial control port should remain idle Figure 23 shows an autoboot functional timing example The autoboot cycle actually is a 24 bit or three address byte cycle It should be noted that for autoboot the most significant byte is always zero For this reason a two latch external
23. 4923 4 5 6 7 8 9 Family Data Sheet This document describes the electrical characteristics of the device from timing to base functionality This is the hardware designers tool to learn the part s electrical and systems requirements ANIIS CS4923 4 5 6 7 8 9 Hardware User s Guide describes the functional aspects of the device An in depth description of communication boot procedure external memory and hardware configuration are given in this document This document will be valuable to both the hardware designer and the system programmer 2 2 2 CS4923 4 5 6 7 8 9 Application Code User s Guides The following application notes describe the application codes used with the CS4923 4 5 6 7 8 9 Whenever an application code user s guide is referred to it should be assumed that one or more of the below documents are being referenced The following list covers currently released application notes This list will grow with each new application released For a current list of released user s guides please see www crystal com and search for the part number ANI20 Dolby Digital User s Guide for the CS4923 4 5 6 This document covers the features available in the Dolby Digital code including delays pink noise bass management Pro Logic PCM pass through and Dolby Digital processing features Optional appendices are available that document code for Dolby Virtual Q Surround and VMAx ANI21 MPEG User s Guide for the CS4925 This document
24. 6 7 8 9 A1 0 Tma 7 lt 777 7777 DATATO DD DK 17 gt Tmanr cs Tmaa Tmrwsu lt Tmedr TT i Tmais ES A Tmrpw Tmrd lt Kla DS x Figure 7 Motorola Parallel Host Mode Read Cycle A1 0 Tmas Tmah DATA7 0 by K Tmasu Tmdhw A gt Tmedw Tmwpw jm RW Tm rwsu Tmwd Tmwtrd DS Figure 8 Motorola Parallel Host Mode Write Cycle DS262F2 11 MY S EN AU AU a Y Zem Gees Z Zeie CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS SPI CONTROL PORT Ta 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Units SCCLK clock frequency Note 5 fsck S 2000 kHz CS falling to SCCLK rising tess 20 ns Rise time of SCCLK line Note 11 tr 50 ns Fall time of SCCLK lines Note 11 tt 50 ns SCOLK low time tsel 150 a ns SCCLK high time tsch 150 ns Setup time SCDIN to SCCLK rising tedisu 50 ns Hold time SCCLK rising to SCDIN Note 6 tedih 50 ns Transition time from SCCLK to SCDOUT valid Note 7 tscdov 40 ns Time from SCCLK rising to INTREQ rising Note 8 Lech s 200 ns Rise time for INTREQ Note 8 is Note ns 10 Hold time for INTREQ from SCCLK rising Note 9 11 Leen 0 ns Time from SCCLK falling to CS rising tscesh 20 ns High time between active CS tesht 200 ns Time from CS rising to SCDOUT high Z Note 11 toscdo 1
25. AAN a eg sc k PL gt LLI 42 P m ore INTREG mak lt gt DA C S o u S GU AUDATAO HH gt a i ZS AUDATA1 HL gt E z E AUDATA2 32 gt gt SCCLK Q 5 dl curvar He cuecuk P E gt S DIR or o CS4923 4 5 6 7 8 9 CG CMPREO HE gt A D C S o RD__GPI011 e Los WR__GPIO10 ee lt gt OPT_TX gt SLRCLKN FES M GPIOB XMT958 LZ AM GPIO7 um E OSCILLATOR GPIOS GPIO4 GPIO3 CLKSEL XL 4 GPIO2 a ses aly ies riz H 3 3VA 2 GPIO1 338385 2222 GPIO0 88882 nm HH a 4 2 2uF x 0 22 uF d y Figure 15 SPI Control DS262F2 27 MY S EN AW AW AU Y Zem Gees SNAM CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is simply 3 3VD after fil tering through the ferrite bead Pin 32 must be referenced to 3 3VA FERRITE BEAD IRVA tor Ten RES Tow ner Er RES ET 47 uF ps i ii LT 3 3VD 3 3VD a9 ie FL RER J 4 NOTE Only AUDATAO connection applies for the CS492 i 22400 3883 lt 33 2 a gt gt gt MCLK E seik HE NA SYSTEM E
26. AUDATAO WR DS EMWR GPIO10 I RD R W EMOE GPIO11 5N A1 SCDIN lt gt AUDATA1 AO SCCLK AE bd dubi OAUDATAS DATA7 EMAD7 GPIO7 Ta E 6 5 4 3 2 1 44434241 40 DC DATA6 EMAD6 GPIO6 5 g aer DD DATA5 EMAD5 GPI de 37 0 RESET SEMADSGPIOS 9 37 17 RES DATA4 EMAD4 GPIO4 i ss AGND CS4923 CL 2 VA NDE HMP 44 pin PLCC ae DGND2 3 1 SEEN DATA3 EMAD3 GPIO3 1 15 Tope 31 D gt FILT2 DATA2 EMAD2 GPIO2 P 27 CLKSEL 7 DATA1 EMAD1 GPIO1 1819202122232425262728 CLKIN DATAO EMADO GPIOO cs SCDIO SCDOUT PSEL GPIO9 ABOOT INTREO EXTMEM GPIO8 SDATAN1 CMPREQ LRCLKN2 E O CMPCLK SCLKN2 CMPDAT SDATAN2 LRCLKN1 SCLKN1 STCCLK2 DGND3 VD3 VA Analog Positive Supply Pin 34 Analog positive supply for clock generator Nominally 3 3 V AGND Analog Supply Ground Pin 35 Analog ground for clock generator PLL VD1 VD2 VD3 Digital Positive Supply Pins 1 12 23 Digital positive supplies Nominally 3 3 V DGND1 DGND2 DGND3 Digital Supply Ground Pins 2 13 24 Digital ground FILT1 Phase Locked Loop Filter Pin 33 Connects to an external filter for the on chip phase locked loop This pin does not meet Cirrus Logic s ESD tolerance of 2000 V using the human body model This pin will t
27. LRCLKN2 npu 1 t Buffer RAM RAM SR SCLKN1 ini gt Controller Program Data Output Digital MIU STCCLK2 A P t Memory Memory Formatter EROLK LRCLKN1 Input ROM ROM y AUDATA 2 0 SDATANI Interface RAM Input Program Data Buffer Memory Memory CLKIN PLL STC f lt MT958 CLKSEL Clock Manager FILT2 FILT1 VA AGND DGND 3 1 VD 3 1 This document contains information for a new product Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice 33 CIRRUS LOGIC l TEER ht L Inc 1 P O Box 17847 Austin Texas 78760 Da ee 37 AUG 99 512 445 7222 FAX 512 445 7581 DS262F2 http www cirrus com 1 AE S IN EE Y e 7 E GU U V ANNA FEE L TABLE OF CONTENTS 1 CHARACTERISTICS AND SPECIFICATIONS oorononnnnnnnnn nen tn nt enrere 4 ABSOLUTE MAXIMUM RATINGS osn nn nn 4 RECOMMENDED OPERATING CONDITIONS A 4 DIGITAL D O CHARACTERISTICS ico concibe 4 POWER SUPPLY CHARACTERISTICS eee eee 4 SWITCHING CHARACTERISTICS RESET esent nennen nennen nnn 5 SWITCHING CHARACTERISTICS CMPDAT CMPOLK eese 6 SWITCHING CHARACTERISTICS CLKIN eere nennen 7 SWITCHING CHARACTERISTICS INTEL9 HOST MODEL 8 SWITCHING CHARACTERISTICS MOTOROLA HOST MODE ss
28. N pin directly to the DSP clock Care should be taken to note the minimum CLKIN requirements when bypassing the PLL 32 The PLL reference clock has three possible sources that are routed through a multiplexer controlled by the DSP SCLKN2 SCLKNI and CLKIN Typically in audio video environments like set top boxes the CLKIN pin is connected to 27 MHz In other scenarios such as an A V receiver design the PLL can be clocked through the CLKIN pin with even multiples of the desired sampling rate or with an already available clock source CLKIN is typically a multiple of a standard sampling frequency in this scenario e g 11 2896 MHz The clock manager is controlled by the DSP application software Please refer to the Hardware User s Guide for the CS4923 4 5 6 7 8 9 AN115 and all relevant application code user s guides for information on supported CLKIN frequencies and how to set up and control the internal PLL DS262F2 AE S IN EE Y e 7 E GU U z HHH BEP HU AW AW I I MUN CS4923 4 5 6 7 8 9 6 CONTROL Control of the CS4923 4 5 6 7 8 9 can be accomplished through one of four methods The CS492X supports PC and SPI serial communication In addition the CS492X supports both a Motorola and Intel byte wide parallel host control mode Only one of the four communication modes can be selected for control The states of the RD WR and PSEL pins at the rising edge of RESET determine the interface type as shown in table 2
29. OVERVIEW The CS4923 CS4924 CS4925 CS4926 CS4927 CS4928 and the CS4929 are system on a chip solutions for multi channel or stereo in the case of the CS4929 audio decompression and digital signal processing Because the parts are primarily RAM based a download of application software is required each time the CS4923 4 5 6 7 8 9 1s powered up This document uses download and code load interchangeably These terms should be interpreted as meaning the transfer of application code into the internal CS4923 4 5 6 7 8 9 memory from either an external microcontroller or through the autoboot procedure This document focuses on the electrical features and characteristics of these parts The different features are described from a hardware design perspective It should be understood that not all of the features portrayed in this document are supported by all of the versions of application code available The application user s guides see section 2 2 2 should be consulted to confirm which hardware features are supported by the software This document will be valuable to both the hardware designer and the system programmer This data sheet covers the CS4923 CS4924 CS4925 CS4926 CS4927 CS4928 and CS4929 These parts are identical from an external electrical perspective Internally each device has been tailored for supporting different decoding standards For this document CS4923 4 5 6 7 8 9 has been replaced in certain places
30. P 36 CS4923 4 5 6 7 8 9 Pin Name Pin Description Pin Number CS Chip Select 18 DS Data Strobe 4 R W Read or Write Enable 5 Al Register Address 1 6 AO Register Address 0 7 INTREQ Interrupt Request 20 DATA7 Data Bit 7 8 DATA6 Data Bit 6 9 DATA5 Data Bit 5 10 DATA4 Data Bit 4 11 DATA3 Data Bit 3 14 DATA2 Data Bit 2 15 DATA1 Data Bit 1 16 DATAO Data Bit O 17 Table 6 Motorola Parallel Host Mode Pin Assignments 6 3 SPI Serial Host Interface For SPI communications the CS4923 4 5 6 7 8 9 always acts as a slave Serial SPI communication with the CS4923 4 5 6 7 8 9 is accomplished with 5 communication lines CS SCCLK SCDIN SCDOUT and INTREQ Table 7 shows the pin name pin description and pin number of each signal on the CS4923 4 5 6 7 8 9 CS is an active low chip select and must be held low for writes to and reads from the part SCCLK is an input to the CS492X that clocks data in and out of the device on its rising edge SCDIN is the data input and should be valid on the rising edge of SCCLK SCDOUT is the data output and will be valid on the rising edge of SCCLK INTREQ is an open drain active low interrupt request signal that is driven low by the CS492X when there is data to be read out Pin Name Pin Description Pin Number CS Chip Select 18 SCDIN Serial Data Input 6 SCCLK Serial Control Clock 7 SCDOUT Serial Data Output 19 INTREQ Inter
31. RCLK sok III MEA S EE E E E A SDATA vwep _ LSB MSB LSB MSB L p MsB LsB msB _ LSB MSB _ LSB MSB lw Lei M Clocks M Clocks M Clocks M Clocks M Clocks M Clocks Per Channel Per Channel Per Channel Per Channel Per Channel Per Channel AE S EU EE Y e 7 MEU U V AA EM IN I AW AW S SUN UV CS4923 4 5 6 7 8 9 7 2 Digital Audio Input Port The digital audio input port or DAI is used for both compressed and PCM digital audio data input In addition this port supports a special clocking mode in which a clock can be input to directly drive the internal 33 bit counter Table 10 shows the pin names mnemonics and pin numbers associated with the DAI Pin Name Pin Description Pin Number SDATAN1 Serial Data In 22 SCLKN1 Serial Bit Clock 25 LRCLKN1 Frame Clock 26 Table 10 Digital Audio Input Port The DAI can be programmed to support PS left justified and right justified data input In addition the DAI can be programmed for slave clocks where LRCLKN1 and SCLKNI are inputs or master clocks where LRCLKNI and SCLKNI are outputs In order for clocks to be master the internal PLL must be used STCCLK2 can also be programmed to drive the internal 33 bit counter This counter would typically be driven by a 90kHz clock The internal counter is used by certain application code for audio video synchronization purposes 7 3 Compressed Data Input Port The compressed data input port or CDI ca
32. Y e 7 E GU U V MN BEP HE AW AW S SUN Ey CS4923 4 5 6 7 8 9 guides to determine which modes are supported by the download code being used Serial digital audio data bit placement and sample alignment is fully configurable in the CS4923 4 5 6 7 8 9 including left justified right justified delay bits or no delay bits variable sample word sizes variable output channel count and programmable output channel pin assignments and clock edge polarity to integrate with most digital audio interfaces If a mode is needed which is not supported please consult your Crystal Representative as to its availability 48 7 5 1 IEC60958 Output The XMT958 output provides a CMOS level bi phase encoded output The XMT958 function can be internally clocked from the PLL or from an MCLK input if MCLK is 256Fs or 512Fs All channel status information can be used when using software which supports this functionality This output can be used for either 2 channel PCM output or compressed data output in accordance with IEC61937 To be fully IEC60958 compliant this output would need to be buffered through an RS422 device or an optocoupler as its outputs are only CMOS Please consult the CS4923 4 5 6 7 8 9 Hardware User s Guide and an application code user s guide to determine if this pin is supported by the download code being used DS262F2 MY S EN AU AU a Y Zem EA a Z Zeie CS4923 4 5 6 7 8 9 8 PIN DESCRIPTIONS MCLK SCLK gt gt LRCLK lt
33. ace of the CS492X supports application code download communication for hardware and application configuration compressed data input and PCM data input When using either Intel or Motorola modes the parallel interface is implemented using four 8 bit internal registers which are selectable using inputs Al and AO as shown in table 3 Table 5 shows the individual registers and their bit mapping In either the Intel or Motorola mode the INTREQ pin can be used to interrupt the host when the DSP has unsolicited outgoing messages to be read For specific details on the behavior of INTREQ in one of the parallel modes please see the CS4923 4 5 6 7 8 9 Hardware User s Guide A1 A0 Pin 6 Pin 7 Register Name Register Function 1 1 CMPDATA _ 8 bit compressed data to input unit write only each signal on the CS4923 4 5 6 7 8 9 RD and WR have no effect when CS is held high When the DSP writes a byte to the HOSTMSG register the HOUTRDY bit in the CONTROL register is set to indicate that there is data to be read To initiate a read cycle the host should drive CS low When CS is low RD becomes the output enable for DATA 7 0 When CS and RD are low the contents of register address A 1 0 are driven on the DATA 7 0 bus The address A 1 0 must be valid a minimum time before either CS or RD goes low The HOUTRDY bit of the CONTROL register is cleared after the host reads from the HOSTMSG register Driving both CS and WR low
34. al signal processors DSPs incorporate a large amount of flexibility into a 44 pin package Because of the high degree of integration many of these pins are internally multiplexed to serve multiple purposes DS262F2 Some pins are designed to operate in one mode at power up and serve a different purpose when the DSP is running Other pins have functionality which can be controlled by the application running on the DSP In order to better explain the behavior of the part the pins which are multiplexed have been given multiple names Each name is specific to the pin s operation in a particular mode An example of this would be the use of pin 20 in one of the serial control modes During the boot period of the CS492X pin 20 is called ABOOT ABOOT is sampled on the rising edge of RESET If ABOOT is high the host must download code to the DSP If ABOOT is low when sampled the CS492X goes into autoboot mode and loads itself with code by generating addresses and reading data on EMAD 7 0 When the device has been loaded with code and is running an application however pin 20 is called INTREQ INTREQ is an open drain output used to inform the host that the DSP has an outgoing message which should be read In this document pins will be referred to by their functionality The section Pin Descriptions on page 49 describes each pin of the CS492X and lists all of its names Please refer to the Pin Descriptions section when exact pin nu
35. ata Input Number One Pin 22 Digital audio data input that can accept from one to six channels of compressed or PCM data SDATANI can be sampled with either edge of SCLKNI depending on how SCLKNI has been configured INPUT CMPCLK SCLKN2 PCM Audio Input Bit Clock Pin 28 Bidirectional digital audio bit clock that is an output in master mode and an input in slave mode In slave mode SCLKN2 operates asynchronously from all other CS492X clocks In master mode SCLKN2 is derived from the CS492X internal clock generator In either master or slave mode the active edge of SCLKN2 can be programmed by the DSP If the CDI is configured for bursty delivery CMPCLK is an input used to sample CMPDAT BIDIRECTIONAL Default INPUT CMPREQ LRCLKN2 PCM Audio Input Sample Rate Clock Pin 29 When the CDI is configured as a digital audio input this pin serves as a bidirectional digital audio frame clock that is an output in master mode and an input in slave mode LRCLKN2 typically is run at the sampling frequency In slave mode LRCLKN2 operates asynchronously from all other CS492X clocks In master mode LRCLKN2 is derived from the CS492X internal clock generator In either master or slave mode the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP When the CDI is configured for bursty delivery or parallel audio data delivery is being used CMPREO is an output which serves as an internal FIFO monitor CMPREO is an active low sig
36. ation will not be possible 6 3 2 SPI Read The CS4923 4 5 6 7 8 9 will always indicate that it has data to be read by asserting the INTREQ line low The host must recognize the request and start a read transaction with the CS492X The same protocol will be used whether reading a byte or multiple bytes Figure 19 also illustrates the relative timing of a three byte SPI read DS262F2 The host initiates an SPI read by driving CS low followed by a 7 bit address and the read write bit set high to indicate a read The CS492X internal 7 bit address is initially assigned to 000 0000b following a reset The 7 bit address sent to the CS492X must match its internal address or the incoming data will be ignored Address checking can be disabled or the actual address can be changed if desired Address checking configuration is documented in the hardware configuration section of the CS4923 4 5 6 7 8 0 Hardware User s guide After the address byte the host should clock data out of the device one byte at a time until INTREQ is no longer low The host shifts data using the rising edge of SCCLK The data is valid on the rising edge of SCCLK and transitions occur on the falling edge In SPI mode the INTREQ pin is deasserted immediately following the rising edge of the second to last data bit of the current byte being transferred if there is no more data to be read The INTREQ pin is guaranteed to stay deasserted high until the rising edge of SCCLK
37. ccess esse sees sees eee seene enen 42 Figure 23 Autoboot Timing Diagram sese sees eee eee eee eee 43 Figure 24 E EE 45 Fig re 25 Left Justified Fora eei ec etiaro EENS ee EE 45 Figure 26 Right Justified sl as da dou aaa 45 Figure 27 Multi Channel Format M 20 o oooonn oonnn r o enne ennt 45 LIST OF TABLES Fable T SIliCOnREVISIONS s 2 aia 20 Table 2 Host Modes 5 eee ste ef Exe e tex Dex eer ees al 33 Table 3 Host Memory Map 34 Table 4 Intel Parallel Host Mode Pin Aesiommente A 34 Table 5 Parallel Input Output Hegeters AA 35 Table 6 Motorola Parallel Host Mode Pin Assignments see 36 Table 7 SPI Serial Mode Pin Assignments oooooooonoonnnnonnnnonrnnonnnnn error 36 Table 8 CC Serial Mode Pin Ee Lulu 39 Table 9 Memory Interface Pins ecu ere xe De rn hnal deefe ge 41 Fable 10 Digital Audio Input Port iiit et etre din 46 Table 11 Compressed Data Input Port nennen nene 46 Table t2 Digital Audio Utput Port irn tna De ER etui nr ER E eer eR 47 Table 13 MCLK SCLK Master Mode Ratios sese 47 DS262F2 3 AE S IN EE Y e 7 HE GU U EN ME EW IF I AW AW MU I NEN ABSOLUTE MAXIMUM RATINGS AGND DGND 0 V all voltages with respect to 0 V CS4923 4 5 6 7 8 9 1 CHARACTERISTICS AND SPECIFICATIONS Parameter Symbol Min Max U
38. d Data Bit 6 9 EMAD5 Address and Data Bit 5 10 EMAD4 Address and Data Bit 4 11 EMAD3 Address and Data Bit 3 14 EMAD2 Address and Data Bit 2 15 EMAD1 Address and Data Bit 1 16 EMADO Address and Data Bit 0 17 These pins must be configured appropriately to select a serial host communication mode for the CS4923 4 5 6 7 8 9 at the rising edge of RESET Table 9 Memory Interface Pins The external memory address is capable of addressing between 64 kilobytes and 16 megabytes through a 16 to 24 bit addressing scheme The address comes from the DSP writing two or three initial bytes of address consecutively on EMAD 7 0 Each byte of address is externally latched with the rising edge of EMOE while EXTMEM is high After the 2 or 3 byte address is latched externally the CS4923 4 5 6 7 8 9 then drives EXTMEM and EMOE low simultaneously to select the external memory During this time the data is read by the CS492X 41 MY S EN AW AU AU Y Zem Gees I HE CS4923 4 5 6 7 8 9 3 3V ADDR 7 0 ADDR 15 8 EMAD 7 0 ADDR 7 0 DATA 7 0 ADDR 15 8 CS4923 4 5 6 7 8 9 oF 64K X 8 e ROM Only one of R1 and R2 should be stuffed Only one of R3 and R4 should be stuffed The state of EMOE and EMWR at the rising edge of RESET will determine the serial mode that the part comes up in while using external memory Please see section 2 Serial Communication for R4 more details R3 Figure 2
39. d Functional Timing Oie Note 2 Notes 1 INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second to last bit of the last byte to be transferred out of the CS4923 4 5 6 7 8 9 2 INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may go low again if there is new data to be read The condition of INTREQ going low at this point should be treated as a new read condition and a new start condition followed by an address byte should be sent Figure 19 SPI Timing ANN UN AW AW I M sa EE H o HG S o M EW AW AU ff Gl 4p 6 8 Z 9 S V EC6VSD AE S IN EE Y e 7 E GU U V ASA EW IN I AW AW HU SUN Ep CS4923 4 5 6 7 8 9 64 PC Serial Host Interface For LC communications the CS4923 4 5 6 7 8 9 always acts as a slave Serial PC communication with the CS4923 4 5 6 7 8 9 is accomplished with 3 communication lines SCCLK SCDIO and INTREQ Table 8 shows the mnemonic pin name and pin number of each signal on the CS4923 4 5 6 7 8 9 SCCLK is an input to the CS492X that clocks data in and out of the device on its rising edge It should be noted that the timing specifications for SCCLK are more stringent than certain DC requirements so care should be taken that the rise and fall specifications for SCCLK are met as stated in the timing portion of this data sheet SCDIO is a bidirectional data line whose data must be valid on the rising edge of SCCLK INTREQ is an open drain active low request sig
40. des since there are shared pins that are needed by each mode If using the CS4926 or CS4928 for DTS decode external memory is required for external DTS tables The external memory interface was designed primarily for two purposes 1 Autoboot and or 2 real time external data access The hardware implementation for either mode can be the same but the ROM access time requirements may differ The CS4923 4 5 6 7 8 9 Hardware User s Guide should be referenced for more information including memory paging options to support both autoboot and real time access as well as ROM speed requirements DS262F2 The external memory interface is implemented on the CS4923 4 5 6 7 8 9 with the following signals EMAD 7 0 EXTMEM and EMOE Table 9 shows the pin name pin description and pin number of each signal on the CS4923 4 5 6 7 8 9 EMAD 7 0 serve as a multiplexed address and data bus EMOE is an active low external memory data output enable as well as the address latch strobe EXTMEM serves as the active low chip select output Figure 21 illustrates one possible external memory architecture for the CS4923 4 5 6 7 8 9 Figure 22 shows the functional timing of a run time memory access Pin Pin Name Pin Description Number EMOE External Memory Output 5 Enable amp Address Latch Strobe EMWR External Memory Write 4 Strobe EXTMEM External Memory Select 21 EMAD7 Address and Data Bit 7 8 EMAD6 Address an
41. e 10 SWITCHING CHARACTERISTICS DIGITAL AUDIO INPUT enm 16 SWITCHING CHARACTERISTICS DIGITAL AUDIO OUTPUT eem 18 2 FAMILY OVERVIEW ec rrurcen reru inrer un anne 20 2 1 Multi channel Decoder Family of Parts sse 21 2 2 Document Strategy eu certat Aa 21 2 2 4 Hardware Documentation seen 22 2 2 2 CS4923 4 5 6 7 8 9 Application Code User s Guides 22 2 3 Using the G94923 4 5 6 7 8 9 EE 22 3 TYPICAL CONNECTION DIAGRAMS c eeeeeeeeeeeeeee enne enne renacer nn rra rana 23 3 1 Multiplexed PINS ue ee e Der ERU E EPI E PIDE 23 3 2 Termination Requirements sss esse sees sees sees sees eee sees sees serere eenn nenen 24 3 3 Phase Locked Loop Filter ooonoononnnon no nen nn 24 LEN A id 31 4 1 Beco plinig eI 31 4 2 Analog Power Conditioning sss sees see sees eee ee eee eee eee eee nn 31 E E EE 31 Be CLOCKING E 32 ues pg ERR 33 6 1 Boot and Control Mode Overview esse eee eee eee eee eee 33 6 2 Parallel Host Interface x 2 50 eie a it tle atto etd 34 6 2 1 Intel Parallel Host Mode emen nennen 34 6 2 2 Motorola Parallel Host Mode emen 36 6 3 SPI Serial Host Interface ueu A Ten tote d te Dd e atoms 36 OSs SPI EE 37 6 312 SP ROAU eig p i ae te eee hele Woh Sie DP 37 Contacting Cirrus Logic Support For a complete listing of Direct Sales Distributor and Sales Representative contacts visit the C
42. e Application Code User s guide DS262F2 AE S EU EE Y e 7 EEF GU U V AA EM IF I AW AW HU I NEI CS4923 4 5 6 7 8 9 3 TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the device with the different communication modes available They are as follows Figure 13 IC Control Figure 14 C Control with External Memory Figure 15 SPI Control Figure 16 SPI Control with External Memory Figure 17 Intel Parallel Control Mode Figure 18 Motorola Parallel Control Mode The following should be noted when viewing the typical connection diagrams The pins are grouped functionally in each of the typical connection diagrams Please be aware that the CS4923 4 5 6 7 8 9 symbol may appear differently in each diagram The external memory interface is only supported when a serial communication mode has been chosen The typical connection diagrams demonstrate the PLL being used CLKSEL is pulled low To enable external CLKIN CLKSEL should be pulled high The system designer must be aware that certain software features may not be available if external CLKIN is used as the DSP must run slower when external CLKIN is used The system designer should also be aware of additional duty cycle requirements when using external CLKIN mode It is highly suggested that the system designer take advantage of the PLL and pull CLKSEL low 3 1 Multiplexed Pins The CS4923 4 5 6 7 8 9 family of digit
43. e actual maximum speed of the communication port may be limited by the software The relevant application code user s manual should be consulted for the software speed limitations 13 Data must be held for sufficient time to bridge the 300 ns transition time of SCCLK This hold time is by design and not tested 14 This rise time is shorter than that recommended by the ke specifications For more information see the section on SCP communications 15 INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the last data bit of the last byte of data during a read operation as shown 16 IF INTREQ goes high as indicated in Note 8 then INTREQ is guaranteed to remain high until the next rising edge of SCCLK If there is more data to be read at this time INTREQ goes active low again Treat this condition as a new read transaction Send a new start condition followed by the 7 bit address and the R W bit set to 1 for a read This time is by design and is not tested 17 With a 4 7k Ohm pull up resistor this value is typically 215ns As this pin is open drain adjusting the pull up value will affect the rise time 18 This time is by design and not tested 14 DS262F2 c4ic9csa SI stop start de LZ za d d y de Y V ye BID Leo Y A6 AS ao RW ACK MSB CL E Zug Am x i N d tsud scsd d 0 1 8 7 8 0 T V SCCLK EE l j IE li MN M U
44. e first sample of the left channel In this fashion the CS492X can translate successive byte writes into a variable number of channels with a variable PCM sample size In the most simple case the CS492X can receive stereo 8 bit PCM one byte at a time with the internal DSP assigning the first 8 bit write after PCMRST to the left channel and the second 8 bit write to the right channel For 16 bit PCM 1t assigns the first two 8 bit writes after PCMRST to the left channel and the next two writes to the right channel 7 5 Digital Audio Output Port The Digital Audio Output port or DAO is the port used for digital output from the DSP Table 12 shows the signals associated with the DAO As there are many modes that are firmware configurable on the DAO please consult the Hardware User s Guide and the application code user s guides to determine which modes are supported by the download code being used Pin Name Pin Description Pin Number AUDAT2 Serial Data In 39 AUDAT1 Serial Data In 40 AUDATO Serial Data In 41 LRCLK Frame Clock 42 SCLK Serial Bit Clock 43 MCLK Master Clock 44 XMT958 IEC60958 Transmitter 3 Table 12 Digital Audio Output Port DS262F2 MCLK is the master clock and is firmware configurable to be either an input or an output If MCLK is to be used as an output the internal PLL must be used As an output MCLK can be configured to provide a 128Fs 256Fs or 512Fs clock where F
45. edance inputs and will be prone to oscillation if they are left floating The specific termination requirements may vary since the state of some of the GPIO pins will determine the communication mode at the rising edge of reset please see section 6 for more 24 information For the explicit termination requirements of each communication mode please see the typical connection diagrams Generally a 4 7k Ohm resistor is recommended for open drain pins while a 10k Ohm resistor is sufficient for the GPIO pins and unused inputs AA Phase Locked Loop Filter The internal phase locked loop PLL of the CS4923 4 5 6 7 8 9 requires an external filter for successful operation The topology of this filter and component values are shown in the typical connection diagrams Care should be taken when laying out the filter circuitry to minimize trace lengths and to avoid any close routing of high frequency signals Any noise coupled on to the filter circuit will be directly coupled into the PLL which could affect performance DS262F2 MY S EN AW AW AU Y Zem Gees SNAM CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is si
46. ems from any Cirrus Logic website or disk may be printed for use by the user However no part of the printout or electronic files may be copied reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photographic or otherwise without the prior written consent of Cirrus Logic Inc Furthermore no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic Inc The names of products of Cirrus Logic Inc or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions A list of Cirrus Logic Inc trade marks and service marks can be found at http Avww cirrus com 2 DS262F2 AE S IN EE Y e 7 MEU U V HHA A AAA A wm X X c M H e B4 FC Soral Hast Interla6d cenis eege D Debet 39 Bd dq WB as equus iM ul UD uM Y 39 B42 e ROAR tee Ee 39 6 5 External Memory actora dei Le De Ene toe Leere Ente Ir ire NE 41 6 5 1 External Memory and Autoboot A 43 7 DIGITAL INPUT amp OUTPUT eeeeeeeeeeeenennn nennen entr nnn nnns nnns RH HERE RE nn 44 7 1 Digital Audio Forirjals ict edid de iet bites 44 7 2 Digital Audio Input Port sissien inania nennen rennen iiia 46 7 3 Compressed Data Input Port enne nre neret
47. ew read condition and a new start condition followed by an address byte should be sent Figure 20 C Timing NN NS AW AW I M sa EE H o HG S o M EW AW AU ff Gl 4p 6 8 Z 9 S V EC6VSD AE S IN EE Y e 7 HE GU U EN HHA BEP IF I AW AW S SUN Ep CS4923 4 5 6 7 8 9 Following the address byte the host must clock out an acknowledge from the part After the address byte the host should clock out data from the device one byte at a time until INTREQ is no longer low The host shifts data using the rising edge of SCCLK The data is valid on the rising edge of SCCLK and transitions on the falling edge After each byte the host must send an acknowledge ACK to the CS492X While reading from the CS492X an acknowledge is defined as SCDIO being driven low by the host for one SCCLK period after each byte In PC mode the INTREO pin is deasserted immediately following the rising edge of the last data bit of the current byte being transferred if there is no more data to be read The INTREQ pin is guaranteed to stay deasserted high until the rising edge of SCCLK for the acknowledge bit For a more thorough look at PC communication and critical additional information on INTREQ behavior reference the CS4923 4 5 6 7 8 9 Hardware User s Guide 6 5 External Memory If using one of the serial modes i e SPI or PC the system designer has the option of using external memory The external memory interface is not compatible with the parallel mo
48. ins that can be individually configured and controlled by the DSP BIDIRECTIONAL Default INPUT AO SCCLK Host Parallel Address Bit Zero or Serial Control Port Clock Pin 7 In parallel host mode this pin serves as one of two address input pins used to select one of four parallel registers In serial host mode this pin serves as the serial control clock signal specifically as the SPI clock input or the PC clock input INPUT A1 SCDIN Host Parallel Address Bit One or SPI Serial Control Data Input Pin 6 In parallel host mode this pin serves as one of two address input pins used to select one of four parallel registers In SPI serial host mode this pin serves as the data input INPUT RD R W EMOE GPIO11 Host Parallel Output Enable or Host Parallel R W or External Memory Output Enable or General Purpose Input amp Output Number 11 Pin 5 In Intel parallel host mode this pin serves as the active low data bus enable input In Motorola parallel host mode this pin serves as the read high write low control input signal In serial host mode this pin can serve as the external memory active low data enable output signal Also in serial host mode this pin can serve as a general purpose input or output bit BIDIRECTIONAL Default INPUT 50 DS262F2 MY S EN AU AU a Y Zem Gees Z Zeie CS4923 4 5 6 7 8 9 WR DS EMWR GPIO10 Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input amp Ou
49. int at which the data is valid 22 This timing parameter is defined from the active edge of SCLKN1 2 The active edge of SCLKN1 2 is the point at which the data is valid 23 Slave mode is defined as SCLKN1 2 and LRCLKN1 2 being driven by an external source 16 DS262F2 MY S EN AU AU a Y Zem Gees I Zeie CS4923 4 5 6 7 8 9 MASTER MODE SCLKN1 Y V Vy SCLKN2 IN AN JN Tiras lt Tsciki LRCLKN1 V y Y LROLKN2 L NN SDATAN1 VW T Le SDATAN2 NAM A SLAVE MODE SCLKN1 Y Y V Ny SCLKN2 A Tirts T gt _ gt str LRCLKN1 y V V Y LRCLKN2 A Wo A SDATAN yo vv y SDATAN2 JN LLL 0 A Figure 11 Digital Audio Input Data and Clock Timing DS262F2 17 MY A EN EN AW AU AU Y Zem EN A a I HE CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS DIGITAL AUDIO OUTPUT TA 25 C VA VD 3 3 V 596 measurements performed under static conditions Parameter Symbol Min Max Unit MCLK period Note 24 Tmelk 40 ns MCLK duty cycle Note 24 40 60 96 SCLK period for Master or Slave mode Note 25 Tech A0 ns SCLK duty cycle for Master or Slave mode Note 25 45 55 Master Mode Note 25 26 SCLK delay from MCLK rising edge MCLK as an input Tsdmi 15 ns SCLK delay from MCLK rising edge MCLK as an output Tsdmo 5 10 ns LRCLK delay from SCLK transition Note 27 Tirds 10 ns AUDATA2 0 delay from SCLK transition Note
50. irrus Logic web site at http www cirrus com corporate contacts Dolby Dolby Digital and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation Intel is a registered trademark of Intel Corporation Motorola is a registered trademark of Motorola Inc 12C is a registered trademark of Philips Semiconductor All other names are trademarks registered trademarks or service marks of their respective companies Preliminary product information describes products which are in production but for which full characterization data is not yet available Advance product infor mation describes products which are in development and subject to development changes Cirrus Logic Inc has made best efforts to ensure that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied No responsibility is assumed by Cirrus Logic Inc for the use of this information nor for infringements of patents or other rights of third parties This document is the property of Cirrus Logic Inc and implies no license under patents copyrights trademarks or trade secrets No part of this publication may be copied reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photographic or otherwise without the prior written consent of Cirrus Logic Inc It
51. k mode Telkih 8 ns CLKIN low time for internal DSP clock mode Tekil 8 ns CLKIN period for external DSP clock mode Tolke 20 25 ns CLKIN high time for external DSP clock mode Tolkeh 9 ns CLKIN low time for external DSP clock mode Telkel 9 ns CLKIN a Tolkin Taa bw Tak Figure 3 CLKIN with CLKSEL VSS PLL Enable CLKIN Token gt t Tokel Toke Figure 4 CLKIN with CLKSEL VD PLL Bypass DS262F2 7 MY A EN EN AW AU AU Y d A a I HE CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS INTEL HOST MODE Ta 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Unit Address setup before CS and RD low or CS and WR low Tias 5 ns Address hold time after CS and RD low or CS and WR low Tiah 5 ns Delay between RD then CS low or CS then RD low Ticar 0 co ns Data valid after CS and RD low Tidd 20 ns CS and RD low for read Note 1 Timw DCLK 10 ns Data hold time after CS or RD high Tidhr 5 ns Data high Z after CS or RD high Note 2 Tidis 15 ns CS or RD high to CS and RD low for next read Note 1 Tid 2 DCLK 10 ns CS or RD high to CS and WR low for next write Note 1 Tae 2 DCLK 10 ns Delay between WR then CS low or CS then WR low Tou 0 co ns Data setup before CS or WR high ip 20 ns CS and WR low for write Note 1 Tiwpw DCLK 10 ns Data hold after CS or WR high Thaw 5
52. l or Motorola Parallel host interface mode the system designer can also choose to deliver data through the byte wide parallel port The compressed data input register receives bytes of data when the host interface writes to address 11b A1 and AO are both high The host interface port also utilizes the CMPREQ pin and the MER and MFC flags in the CONTROL register which are configurable to supply a data request flag at different input buffer thresholds CMPREQ acts as an almost full flag The CS4923 4 5 6 7 8 9 can safely receive different size blocks of data depending on the level of the input buffer threshold The threshold level is programmable and the default level may differ between applications This mode reduces the polling burden associated with hand feeding the compressed data DS262F2 AE S EU EE Y e 7 MEU U V AA EW HU AW AW S SUN Ep CS4923 4 5 6 7 8 9 In parallel host mode the CS4923 4 5 6 7 8 9 can accept PCM data written through the byte wide host interface to address 10b A1 high A0 low In this mode there is a close connection between the CS4923 4 5 6 7 8 9 application code and the host processor that is delivering the PCM data The PCMRST bit of the CONTROL register provides absolute software hardware synchronization by initializing the input channel to uniguely recognize the first write to the byte wide PCMDATA port Toggling PCMRST high and low informs the DSP that the next sample read from the PCMDATA port is th
53. lave Cirrus Logic s Crystal Audio Division provides a complete set Optional external memory and auto boot of audio decoder and auxiliary audio DSP application programs for various applications For all complementary 3 3 V CMOS low power 44 pin package analog and digital audio I O Crystal Audio also provides a e CS4923 4 5 6 features complete set of high quality audio peripherals including Capable of Dolby Digital Group A Performance multimedia CODECs stereo A D and D A converters and Dolby bass manager and crossover filters IEC60958 interfaces Of special note the CS4226 is a i complementary CODEC providing a digital receiver stereo Dolby Surround Pro Logic Decoding H p GE A D converters and six 20 bit DACs in one package e CS4925 7 MPEG 2 Multi Channel Decoder ORDERING INFORMATION e C54926 8 DTS Multi Channel Decoder CS4923xx CL 44 pin PLCC xx ROM revision e CS4929 AAC 2 Channel Low Complexity CRD4923 Reference design with CS4226 and MPEG 2 Stereo Decoder CDB4923 Evaluation board RD WR SODIO DATA7 0 RW DS SCDOUT EMAD7 0 EMOE EMWR PSEL AO A1 ABOOL EXTMEM RESET GPIO7 0 CS GPIO11 GPIO10_GPIO9 SCCLK SCDIN INTREQ GPIOB CMPDAT SDATAN2 Compressed Parallel or Serial Host Interface J a Data Input CMPCLK Interface Framer SCLKN2 Shifter 24 Bit CMPREQ 4 Lean DSP Processing MCLK
54. ly possible to each power pin The 0 1uF capacitor should be closest to the device typically 5mm or closer 4 2 Analog Power Conditioning In order to obtain the best performance from the CS4923 4 5 6 7 8 9 s internal PLL the analog power supply VA must be as clean as possible A ferrite bead should be used to filter the 3 3V power supply for the analog portion of the CS492X This power scheme is shown in the typical connection diagrams 4 3 Pads Revision D and all subsequent revisions incorporate 5V tolerant pads This means that while the CS492X power supplies require 3 3 volts 5 volt signals can be applied to the inputs without damaging the part The I O pads for Revision B of the CS4923 4 5 6 are not 5 volt tolerant Input levels for revision B of the CS4923 4 5 6 should be no greater than 3 3 31 AE S IN EE Y e 7 E GU U V HHH EW IF I AW AW MU I NEN CS4923 4 5 6 7 8 9 5 CLOCKING Revision D of the CS4923 4 5 6 7 8 9 also incorporates a programmable phase locked loop PLL clock synthesizer The PLL takes an input reference clock and produces all the internal clocks required to run the internal DSP and to provide master mode timing to the audio input output peripherals The clock manager also includes a 33 bit system time clock STC to support audio and video synchronization in broadcast applications The PLL can be internally bypassed by connecting the CLKSEL pin to VD This connection multiplexes the CLKI
55. mbers are in question The device has 12 general purpose input and output GPIO 11 0 pins that all have multiple functionality While in one of the parallel communication modes see section 6 2 these pins are used to implement the parallel host communication interface While in one of the serial host modes these pins are used to implement an external memory interface Alternatively while in one of the serial host modes these pins could be used for another general purpose if the application code has been programmed to support the special purpose In this document the pins are referenced by the name corresponding to their particular use Sometimes GPIO 11 0 or some subset thereof 1s used when referring to the pins in a general sense 23 AE S IN EE Y e 7 HE GU U EN HHH BEP IF I AW AW MU I NEN CS4923 4 5 6 7 8 9 3 2 Termination Requirements The CS4923 4 5 6 7 8 9 incorporates open drain pins which must be pulled high for proper operation INTREQ pin 20 is always an open drain pin which requires a pull up for proper operation When in the PC serial communication mode the SCDIO signal pin 19 is open drain and thus requires a pull up for proper operation Due to the internal multiplexed design of the pins certain signals may or may not require termination depending on the mode being used If a parallel host communication mode is not being used GPIO 11 0 must be terminated or driven as these pins will come up as high imp
56. mply 3 3VD after fil tering through the ferrite bead Pin 32 must be referenced to 3 3VA FERRITE BEAD 3 3VA yy 4 tur 0 1 uF tur 0 1 uF tur 0 1 uF tour 0 1uF 47uF Se t E GC 3 3VD 3 3VD E J 4 NOTE Only AUDATAO connection applies for the CS4929 E ui S SS S wok gt me scuk PHI gt wi 4 S oc Ge LRCLK LEES DAC S UU LL SCDIO JJ GC AUDATAD Ht gt o uu a AUDATA 22 gt GC N AUDATA2 32 gt m SCCLK Z Ex ma CMPDAT PIE O cmpcik F gt DIR or o CS4923 4 5 6 718 9 e gt ADU S EE SDATAN P2 o WR__GPI010 WD een mx OPT TX SLRCLKN 39 AM SE XMT958 M GPIO7 GPIO6 33 eios oun Y OSCILLATOR GPIO4 GPIO3 CLKSEL Hi pi Ri Bun Ge 3 3VA GPIO0 88882 id L 4 2 2 uF 0 22 uF S Y T Y Figure 13 UC Control DS262F2 25 MY S EN AW AW AU Y Zem Gees SNAM CS4923 4 5 6 7 8 9 3 3V Supply 3 3VD NOTE A capacitor pair 1 uF and 0 1 uF must be supplied for each power pin NOTE 3 3VA is simply 3 3VD after filt ering through the ferrite bead Pin 32 must be referenced to 3 3VA FERRITE BEAD 3 3VA tor ua tur ua 1uF 0 1 uF tor 0 1 uF 47uF
57. n be used for both compressed and PCM data input Table 11 shows the mnemonic pin name and pin number of the pins associated with the CDI port on the CS4923 4 5 6 7 8 9 Pin Name Pin Description Pin Number SDATAN2 Serial Data In 27 CMPDATA Compressed Data In SCLKN2 Serial Bit Clock 28 CMPCLK LRCLKN2 Frame Clock 29 CMPREQ Data Request Out Table 11 Compressed Data Input Port 46 The CDI can be configured to support IS left justified and right justified formats The CDI can also be programmed for slave clocks where LRCLKN2 and SCLKN2 are inputs or master clocks where LRCLKN2 and SCLKN2 are outputs In order for clocks to be mastered the internal PLL must be used In addition the CDI can be configured for bursty compressed data input Bursty audio delivery is a special format in which only clock CMPCLK and data CMPDAT are used to deliver compressed data to the CS4923 4 5 6 7 8 9 i e no frame clock or LRCLK A third line CMPREQ is used to request more data from the host It is an indicator that the CS492X internal FIFO is low on data and can accept another burst Typically this mode is used for compressed data delivery where asynchronous data transfer occurs in the system i e in a system such as a set top box or HDTV PCM data can not be presented in this mode since data is interpreted as a continuous stream with no word boundaries 7 4 Parallel Digital Audio Data Input If using the Inte
58. n is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus In SE host mode after the bus mode has been selected the pin can function as a general A input or output pin BIDIRECTIONAL Default INPUT F C mode this pin is an OPEN DRAIN I O and requires a 4 7k Pull Up EXTMEM GPIO8 External Memory Chip Select or General Purpose Input amp Output Number 8 Pin 21 In serial control port mode this pin can serve as an output to provide the chip select for an external byte wide ROM In parallel and serial host mode this pin can also function as a general purpose input or output pin BIDIRECTIONAL Default INPUT INTREQ ABOOT Control Port Interrupt Request Automatic Boot Enable Pin 20 Open drain interrupt request output This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by the host Also in serial host mode this signal initiates an automatic boot cycle from external memory if it is held low through the rising edge of reset OPEN DRAIN I O Requires 4 7k Ohm Pull Up AUDATA2 Digital Audio Output 2 Pin 39 PCM multi format digital audio data output capable of two channel 20 bit output This PCM output defaults to DGND as output until enabled by the DSP software OUTPUT DS262F2 51 MY S EN AU AU a Y Zem Gees NEA CS4923 4 5 6 7 8 9 AUDATA1 Digital Audio Output 1 Pin 40 PCM multi format digital audio data outpu
59. nal that indicates when another block of data can be accepted BIDIRECTIONAL Default INPUT CMPDAT SDATAN2 PCM Audio Data Input Number Two Pin 27 Digital audio data input that can accept from one to six channels of compressed or PCM data SDATANZ2 can be sampled with either edge of SCLKN2 depending on how SCLKN2 has been configured Similarly CMPDAT is the compressed data input pin when the CDI is configured for bursty delivery When in this mode the CS4923 4 5 6 7 8 9 internal PLL is driven by the clock recovered from the incoming data stream INPUT DC Reserved Pin 38 This pin is reserved and should be pulled up with an external 4 7k resistor DD Reserved Pin 37 This pin is reserved and should be pulled up with an external 4 7k resistor DS262F2 53 MY S EN AU AU a Y Zem Gees NEA CS4923 4 5 6 7 8 9 9 PACKAGE DIMENSIONS 44L PLCC PACKAGE DRAWING A di my e AS i D2 E2 E1 E zz AZ ebe o ID y Y La D1 A1 La D gt A INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 165 0 180 4 043 4 572 A1 0 090 0 120 2 205 3 048 B 0 013 0 021 0 319 0 533 D 0 685 0 695 16 783 17 653 D1 0 650 0 656 15 925 16 662 D2 0 590 0 630 14 455 16 002 E 0 685 0 695 16 783 17 653 E1
60. nal that is driven low by the CS492X when there is data to be read out Pin Name Pin Description Pin Number SCCLK Serial Control Clock 7 SCDIO Serial Data Input and 19 Output INTREQ Interrupt Request 20 Table 8 C Serial Mode Pin Assignments 6 4 1 PC Write When writing to the device in re the same protocol can be used for sending a byte a word or an entire download image as long as transfers occur on byte boundaries Figure 20 illustrates the relative timing necessary for a three byte transfer to the CS492X The host initiates a transfer with an PC start condition followed by a 7 bit address and the read write bit set low to indicate a write The start condition is defined as the SCDIO falling with SCCLK held high The CS492X internal 7 bit address is initially assigned to 000 0000b following a reset The 7 bit address sent to the CS492X must match its internal address or the incoming data will be ignored Address checking can be disabled or DS262F2 the actual address can be changed if desired Address checking configuration is documented in the hardware configuration section of the CS4923 4 5 6 7 8 9 Hardware User s guide After the address byte the host should then clock an acknowledge ACK from the part During a write an ACK is defined as SCDIO being driven low by the CS492X for one SCCLK period after each byte Data should be shifted into the CS492X most significant byte first with data bei
61. ng valid at the rising edge of SCCLK The host should then clock out the acknowledge ACK bit bit from the CS492X After the last byte to be sent is acknowledged the host should send an C stop condition which is defined as the rising edge of SCDIO while SCCLK is held high If the CS492X fails to acknowledge a byte the host should re transmit the same byte If the CS492X does not acknowledge back to back bytes then the host should reset the part 6 4 2 PC Read The CS4923 4 5 6 7 8 9 will always indicate that it has data to be read by asserting the INTREQ line low The host must recognize the request and start a read transaction with the CS492X The same protocol will be used whether reading a byte or multiple bytes Figure 20 also illustrates the relative timing of a three byte PC read The host initiates a read with an C start condition followed by a 7 bit address and the read write bit set high for a read The start condition is defined as the SCDIO falling with SCCLK held high The CS492X internal 7 bit address is initially assigned to 000 0000b following a reset The 7 bit address sent to the CS492X must match its internal address or the incoming data will be ignored Address checking can be disabled or the actual address can be changed if desired Address checking configuration is documented in the hardware configuration section of the CS4923 4 5 6 7 8 9 Hardware User s guide 39 or c4c9cSd
62. nit DC power supplies Positive digital VD 0 3 3 63 V Positive analog VA 0 3 3 63 V IVA VD 0 4 V Input current any pin except supplies lin 10 mA Digital input voltage VIND 0 3 5 5 V Ambient operating temperature power applied Tamax 55 125 C Storage temperature Tstg 65 150 C WARNING Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes RECOMMENDED OPERATING CONDITIONS AGND DGND 0 V all voltages with respect to 0 V Parameter Symbol Min Typ Max Unit DC power supplies Positive digital VD 3 13 3 3 3 47 V Positive analog VA 3 13 3 3 3 47 V VA VD 0 4 V Ambient operating temperature TA 0 70 C DIGITAL D C CHARACTERISTICS Ta 25 C VA VD 3 1 3 3 V 5 measurements performed under static conditions Parameter Symbol Min Typ Max Unit High level input voltage Vu 2 0 S S V Low level input voltage Vu E 0 8 V High level output voltage at lg 4 0 mA Vou VD x 0 9 V Low level output voltage at lo 4 0 mA VoL VD x 0 1 V Input leakage current lin 1 0 uA POWER SUPPLY CHARACTERISTICS Ta 25 C VA VD 3 1 3 3 V 5 measurements performed under operating conditions Parameter Symbol Min Typ Max Unit Power supply current Digital operating VD 3 1 225 435 mA Analog operating VA E 4 8 mA DS262F2 AE EA II IN EE Y e 7 HE GU U V HHA BEP HU A AW S SUN Ey Ta 25
63. ns CS or WR high to CS and RD low for next read Note 1 Tud 2 DCLK 10 ns CS or WR high to CS and WR low for next write Note 1 Tiwd 2 DCLK 10 ns Notes 1 Certain timing parameters are normalized to the DSP clock DCLK in nanoseconds The DSP clock can be defined as follows External CLKIN Mode DCLK CLKIN 3 before and during boot DCLK CLKIN after boot Internal Clock Mode DCLK 10MHz before and during boot i e DCLK 100ns DCLK 60 MHz after boot i e DCLK 16 7ns this speed may depend on CLKIN please see CS4923 4 5 6 7 8 9 Hardware User s Guide for more information 2 This specification is characterized but not production tested 8 DS262F2 MY S EN AU AU a Y Zem Gees I Zeie CS4923 4 5 6 7 8 9 Figure 5 Intel Parallel Host Mode Read Cycle ANY X NN 2 AWN d Tiatw 4 gt Tidsu Tiwpw Tiwd Tiwtrd ka Wa y 1 Figure 6 Intel Parallel Host Mode Write Cycle DS262F2 9 MY A EN EN AW AU AU Y d A a I HE CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS MOTOROLA HOST MODE TA 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Unit Address setup before CS and DS low Tmas 5 ns Address hold time after CS and DS low Timah 5 ns Delay between DS then CS low or CS then DS low E 0 co
64. ns Data valid after CS and DS low with R W high Todd 20 ns CS and DS low for read Note3 Tmrpw DCLK 4 10 ns Data hold time after CS or DS high after read gen 5 3 ns Data high Z after CS or DS high low after read Note 4 Tmais 15 ns CS or DS high to CS and DS low for next read Note 211 Tmra 2 DCLK 10 ns CS or DS high to CS and DS low for next write Note 3 Tmr w 2 DCLK 10 ns Delay between DS then CS low or CS then DS low E 0 co ns Data setup before CS or DS high Tias 20 ns CS and DS low for write Note3 Tmwpw DCLK 10 ns R W setup before CS or DS low uy 5 ns R W hold time after CS or DS high Tmrwhld 5 ns Data hold after CS or DS high EN 5 ns CS or DS high to CS and DS low with R W high for next read Tata 2 DCLK 10 ns Note 3 CS or DS high to CS and DS low for next write Note 3 Tmwd 2 DCLK 10 ns Notes 3 Certaintiming parameters are normalized to the DSP clock DCLK in nanoseconds The DSP clock can be defined as follows External CLKIN Mode DCLK CLKIN 3 before and during boot DCLK CLKIN after boot Internal Clock Mode DCLK 10MHz before and during boot i e DCLK 100ns DCLK 60 MHz after boot i e DCLK 16 7ns this speed may depend on CLKIN please see CS4923 4 5 6 7 8 9 Hardware Users Guide for more information 4 This specification is characterized but not production tested 10 DS262F2 MY S EN AU AU a Y Zem Gees I Zeie CS4923 4 5
65. olerate ESD of 1000 V using the human body model DS262F2 49 MY S EN AU AU a Y Zem EA a I Zeie CS4923 4 5 6 7 8 9 FILT2 Phase Locked Loop Filter Pin 32 Connects to an external filter for the on chip phase locked loop This pin does not meet Cirrus Logic s ESD tolerance of 2000 V using the human body model This pin will tolerate ESD of 1000 V using the human body model CLKIN Master Clock Input Pin 30 CS4923 4 5 6 7 8 9 clock input When in internal clock mode CLKSEL DGND this input is connected to the internal PLL from which all internal clocks are derived When in external clock mode CLKSEL VD this input is connected to the DSP clock INPUT CLKSEL DSP Clock Select Pin 31 This pin selects the clock mode of the CS4923 4 5 6 7 8 9 When CLKSEL is low CLKIN is connected to the internal PLL from which all internal clocks are derived When CLKSEL is high CLKIN is connected to the DSP clock INPUT DATA7 EMAD7 GPIO7 Pin 8 DATA6 EMAD6 GPIO6 Pin 9 DATAS EMADS GPIO5 Pin 10 DATA4 EMAD4 GPIO4 Pin 11 DATA3 EMAD3 GPIO3 Pin 14 DATA2 EMAD2 GPIO2 Pin 15 DATA1 EMAD1 GPIO1 Pin 16 DATA EMADO GPIO0 Pin 17 In parallel host mode these pins provide a bidirectional data bus If a serial host mode is selected these pins can provide a multiplexed address and data bus for connecting an 8 bit external memory Otherwise in serial host mode these pins can act as general purpose input or output p
66. ons include but are not limited to set top box applications DVDs and digital TVs Outboard decoder applications include standalone decoders and audio video receivers Often times a system may be a hybrid between an outboard decoder and a broadcast system depending on its functionality As discussed above compressed audio can be packed in IEC61937 PES or elementary formats depending on the decoder environment Each for mat is supported by a separate download of appli cation code Consult the relevant Application Code DS262F2 AE S EU EE Y e 7 E GU U V HHH EW HE AW AW S SUN Ep CS4923 4 5 6 7 8 9 User s Guide to determine which formats are sup ported by a particular application A brief descrip tion of each format is presented below Elementary an elementary bitstream consists only of compressed audio data e g strictly the Dolby Digital bitstream used primarily in broadcast en vironments PES a Packetized Elementary Stream PES bit stream contains the elementary compressed audio stream and additional header information which can be used for A V synchronization used primari ly in broadcast environments 1EC61937 a method of packing compressed audio such that it can be delivered using a bi phase en coded signal e g S PDIF output signal from DVD player used primarily for outboard decoders where A V synchronization is not required 2 1 Multi channel Decoder Family of Parts CS4923 Dolby Digital
67. rupt Request 20 Table 7 SPI Serial Mode Pin Assignments DS262F2 AE S EU EE Y e 7 EEF GG U V AA EW HU AW AW MU I HED CS4923 4 5 6 7 8 9 6 3 1 SPI Write When writing to the device in SPI the same protocol can be used for sending a byte a word or an entire download image as long as transfers occur on byte boundaries Figure 19 illustrates the relative timing necessary for a three byte transfer to the CS492X The host initiates an SPI write by driving CS low followed by a 7 bit address and the read write bit set low to indicate a write The CS4923 4 5 6 7 8 9 internal 7 bit address is initially assigned to 000 0000b following a reset The 7 bit address sent to the CS492X must match its internal address or the incoming data will be ignored Address checking can be changed either disabled or an actual address change if desired Address checking configuration is documented in the hardware configuration section of the CS4923 4 5 6 7 8 9 Hardware User s guide Data should be shifted into the CS492X most significant bit first with data being valid at the rising edge of SCCLK It should be noted that data is internally transferred to the DSP on the falling edge of the eighth SCCLK after the eighth data bit of a byte For this reason SCCLK must transition from high to low on the last bit of each byte or a loss of data will occur If this final transfer of SCCLK does not occur the final byte will be lost and successful communic
68. s presented when LRCLK is low The right justified format can also be programmed for data being valid on the falling edge of SCLK SCLK is required to run at a frequency of 48Fs or greater on the input ports Multi Channel Figure 27 shows the multi channel format In this format up to 6 channels of audio are presented on one data line with 20 bits per channel Channels 0 2 and 4 are presented while the LR CLK is high and channels 1 3 5 are presented while the LRCLK is low Data is valid on the rising edge of SCLK and is presented most significant bit first Because each of the ports is fully configurable there may be modes that can be supported which are not presented DS262F2 CS4923 4 5 6 7 8 9 DS262F2 Figure 27 Multi Channel Format M 20 AE A JI IN AW AW A Y a HE GE TU EN MN EW IN Il AW AW MI NY LRCK Left Right POLK ee L 1 te ees E EE EI SDATA MSR LSB MSB LSB Figure 24 DS Format LRCK EN Left Right SCLK AAA A EMANAN SDATA MSB LSB MSB LSB MSB Figure 25 Left Justified Format LRCLK Left Right SCLK AR EIA EEN SDATA LSB MSB LSB MSB LSB Figure 26 Right Justified L
69. s is the output sample rate SCLK is the bit clock used to clock data out on AUDATAO AUDATAI and AUDATA2 LRCLK is the data framing clock whose frequency is typically equal to the sampling frequency Both LRCLK and SCLK can be configured as either inputs Slave mode or outputs Master mode When LRCLK and SCLK are configured as inputs MCLK is a don t care as an input When LRCLK and SCLK are configured as outputs they are derived from MCLK Whether MCLK is configured as an input or an output an internal divider from the MCLK signal is used to produce LRCLK and SCLK The ratios shown in table 13 give the possible SCLK values for different MCLK frequencies all values in terms of the sampling frequency Fs MCLK SCLK Fs Fs 32 48 64 128 256 512 128 X X 384 X X X 256 X X X X 512 X X X X X For MCLK as an input only Table 13 MCLK SCLK Master Mode Ratios AUDATO is configurable to provide six four or two channels AUDATI and AUDAT 2 can both output two channels of data Typically all three AUDAT outputs are used in left justified DS or right justified modes In this way all six channels of surround Left Center Right Left Surround Right Surround and Subwoofer are provided Alternatively the multi channel mode can be configured to provide single data line multi channel support Please consult the Hardware Users Guide and the application code user s 47 AE S IN EE
70. sek CS4923 4 5 6 7 8 9 Multi Channel Digital Audio Decoders e CS4923 4 5 6 7 8 features Description Optional Virtual 3D Output The CS4923 4 5 6 7 8 is a family of multi channel digital Simulated Surround and Programmable Effects audio decoders with the exception of the CS4929 as the Real Time Autodetection of Dolby Digital only stereo digital audio decoder The CS4923 4 5 6 are DTS9 MPEG Multi Channel and PCM designed for Dolby Digital and MPEG 2 Stereo decoding In addition the CS4925 adds MPEG 2 multi channel decoding Flexible 6 channel master or slave output capability and the CS4926 provides DTS decoding The e CS4923 4 5 6 7 8 9 features CS4927 is an MPEG 2 multi channel decoder and the EC60958 61937 transmitter for compressed CS4928 is a DTS multi channel decoder The CS4929 is an data or linear PCM output AAC 2 channel and MPEG 2 stereo decoder Each one of Dedicated 8 kilobyte input buffer the CS4923 4 5 6 7 8 9 provides a complete and flexible solution for multi channel or stereo in the case of the DAC clock via analog phase locked loop CS4929 audio decoding in home A V receiver amplifiers Dedicated byte wide or serial host interface DVD movie players out board decoders laser disc players Multiple compressed data input modes HDTV sets head end decoders set top boxes and similar PES layer decode for A V synchronization products 96 kHz capable PCM I O master or s
71. supports MPEG 2 multi channel decoding and should be used in applications where Dolby Digital decoding is not necessary For MPEG 2 multi channel decoding post processing includes bass management and Dolby Pro Logic decoding Another code load can be used to support stereo to 5 1 channel effects processing CS4928 DTS Multi Channel Decoder The CS4928 supports DTS multi channel decoding and should be used in applications where Dolby Digital decoding is not necessary For DTS multi channel decoding post processing includes bass management Separate downloads can also be used to support stereo to 5 1 channel effects processing and stereo MPEG decoding CS4929 AAC 2 Channel Low Complexity and MPEG 2 Stereo Decoder The CS4929 is capable of decoding both 2 channel AAC and MPEG 2 audio The CS4929 supports elementary and PES formats 2 2 Document Strategy Multiple documents are needed to fully define understand and implement the functionality of the CS4923 4 5 6 7 8 9 They can be split up into two basic groups hardware and application code documentation It should be noted that hardware and application code are co dependent and one can not successfully use the device without an 21 AE S EU EE Y e 7 E GU U V AA EW IF I AW AW S SUN Ep CS4923 4 5 6 7 8 9 understanding of both The ANXXX notation denotes the application note number under which the respective user s guide was released 2 2 1 Hardware Documentation CS
72. t capable of two channel 20 bit output This PCM output defaults to DGND as output until enabled by the DSP software OUTPUT AUDATA0 Digital Audio Output 0 Pin 41 PCM multi format digital audio data output capable of two four or six channel 20 bit output This PCM output defaults to DGND as output until enabled by the DSP software OUTPUT MCLK Audio Master Clock Pin 44 Bidirectional master audio clock MCLK can be an output from the CS4923 4 5 6 7 8 9 that provides an oversampled audio output clock at either 128 Fs 256 Fs or 512 Fs MCLK can be an input at 128 Fs 256 Fs 384 Fs or 512 Fs MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS492X BIDIRECTIONAL Default INPUT SCLK Audio Output Bit Clock Pin 43 Bidirectional digital audio output bit clock SCLK can be an output that is derived from MCLK to provide 32 Fs 64 Fs 128 Fs 256 Fs or 512 Fs depending on the MCLK rate and the digital output configuration SCLK can also be an input and must be at least 48Fs or greater As an input SCLK is independent of MCLK BIDIRECTIONAL Default INPUT LRCLK Audio Output Sample Rate Clock Pin 42 Bidirectional digital audio output sample rate clock LRCLK can be an output that is divided from MCLK to provide the output sample rate depending on the output configuration LRCLK can also be an input As an input LRCLK is independent of MCLK BIDIRECTIONAL Default INPUT XMT958 SPDIF Transmit
73. t buffer is almost full The input buffer threshold level is application code dependent Read only HINBSY Set when the host writes to HOSTMSG Cleared when the DSP reads data from the HOSTMSG register The host reads this bit to determine if the last host byte written has been read by the DSP Read only HOUTRDY Set when the DSP writes to the HOSTMSG register Cleared when the host reads data from the HOSTMSG register The DSP reads this bit to determine if the last DSP output byte has been read by the host Read only Reserved Always write a 0 for future compatibility PCM Data Input PCMDATA Register A 1 0 10b 7 6 5 4 3 2 1 0 PCMDATA7 PCMDATA6 PCMDATA5 PCMDATA4 PCMDATA3 PCMDATA2 PCMDATA1 PCMDATAO PCMDATA7 0 The host writes PCM data to the DSP input buffer at this address Write only Compressed Data Input CMPDATA Register A 1 0 11b 7 6 5 4 3 2 1 0 CMPDATA7 CMPDATA6 CMPDATA5 CMPDATA4 CMPDATA3 CMPDATA2 CMPDATA1 CMPDATAO CMPDATA7 0 The host writes compressed data to the DSP input buffer at this address Write only DS262F2 Table 5 Parallel Input Output Registers 35 AE S IN EE Y e 7 E GU U EN ME BEP HE AW AW S SUN Ep 6 2 2 Motorola Parallel Host Mode Motorola parallel host mode is accomplished with CS DS R W A 1 0 and DATA 7 0 Table 6 shows the pin name pin description and pin number of each signal
74. t tsch WAANNM V o V E sceoin JU aw A LAS A A RW SB LSB tcdisu tcdih yee SCDOUT K MSB Aj pee ES bE A tscdov tsedov lcscdo PM N INTREO y tscrl Figure 9 SPI Control Port Timing ri state NN LD AW I M sa EE H AMA S o M EW AW AU ff Gl 4p 6 8 Z 9 S V EC6VSD MY S EN AU AU a Y Zem Gees Z Zeie CS4923 4 5 6 7 8 9 SWITCHING CHARACTERISTICS HCH CONTROL PORT Ta 25 C VA VD 3 3 V 5 Inputs Logic 0 DGND Logic 1 VD C 20 pF Parameter Symbol Min Max Units SCCLK clock frequency Note 12 fsal 400 kHz Bus free time between transmissions tout 4 7 us Start condition hold time prior to first clock pulse thast 4 0 us Clock low time Dou 1 2 us Clock high time thigh 1 0 us SCDIO setup time to SCCLK rising lsud 250 ns SCDIO hold time from SCCLK falling Note 13 thdd 0 us Rise time of SCCLK Note 14 Note 18 tr 50 ns Fall time of SCCLK Note 18 L 300 ns Time from SCCLK falling to CS4923 4 5 6 7 8 9 ACK tsca 40 ns Time from SCCLK falling to SCDIO valid during read operation acsdv 40 ns Time from SCCLK rising to INTREQ rising Note 15 tscrh 200 ns Hold time for INTREQ from SCCLK rising Note 16 tson 0 ns Rise time for INTREG trr Note ns 17 Setup time for stop condition tsusp 4 7 us Notes 12 The specification f indicates the maximum speed of the hardware The system designer should be aware that th
75. ter Output Pin 3 CMOS level output that contains a biphase encoded clock for synchronously providing two channels of PCM digital audio or a IEC61937 compressed data interface or both This output typically connects to the input of an RS 422 transmitter or to the input of an optical transmitter OUTPUT SCLKN1 STCCLK2 PCM Audio Input Bit Clock Pin 25 Bidirectional digital audio bit clock that is an output in master mode and an input in slave mode In slave mode SCLKNI operates asynchronously from all other CS492X clocks In master mode SCLKNI is derived from the CS492X internal clock generator In either master or slave mode the active edge of SCLKNI can be programmed by the DSP For applications supporting PES layer synchronization this pin can be used as STCCLK2 which provides a path to the internal STC 33 bit counter BIDIRECTIONAL Default INPUT 52 DS262F2 MY S EN AU AU a Y Zem Gees I Zeie CS4923 4 5 6 7 8 9 LRCLKN1 PCM Audio Input Sample Rate Clock Pin 26 Bidirectional digital audio frame clock that is an output in master mode and an input in slave mode LRCLKNI typically is run at the sampling frequency In slave mode LRCLKNI operates asynchronously from all other CS492X clocks In master mode LRCLKNI is derived from the CS492X internal clock generator In either master or slave mode the polarity of LRCLKNI for a particular subframe can be programmed by the DSP BIDIRECTIONAL Default INPUT SDATAN1 PCM Audio D
76. th flow charts pseudocode and restrictions please consult the CS4923 4 5 6 7 8 9 Hardware User s Guide A complete understanding of the decoder and its operation can not be accomplished without consulting the CS4923 4 5 6 7 8 9 Hardware Users Guide and the application code user s guides 6 1 Boot and Control Mode Overview Regardless of which communication mode is used the CS4923 4 5 6 7 8 9 must be booted and loaded with code at run time The general sequence from a hardware perspective is as follows 5 RESET Low 6 Set Communication Configuration Pins 7 RESET High 8 Download Code 9 Configure Hardware 10 Configure Application Code 11 Kickstart the Decoder The host has three options for code download e Parallel Download through the parallel host in terface Serial download through either the SPI or PC interface e Autoboot with external memory when using a serial communication mode Once again the CS4923 4 5 6 7 8 9 Hardware User s Guide should be consulted for a complete description of the boot and download procedure including the necessary communication handshaking Hardware configuration is also 33 AE S EU EE Y e 7 MEU U V AA EW HE AW AW S SUN Ep CS4923 4 5 6 7 8 9 covered in the C S4923 4 5 6 7 8 9 Hardware Users Guide Application configuration is described in the application code user s guide for the code being used 6 2 Parallel Host Interface The byte wide parallel host interf
77. tput Number 10 Pin 4 In Intel parallel host mode this pin serves as the active low data write input strobe In Motorola parallel host mode this pin serves as the active low data strobe input signal In serial host mode this pin can serve as the external memory active low write enable output signal Also in serial host mode this pin can serve as a general purpose input or output bit BIDIRECTIONAL Default INPUT CS Host Parallel Chip Select Host Serial SPI Chip Select Pin 18 In parallel host mode this pin serves as the active low chip select input signal In serial host SPI mode this pin is used as the active low chip select input signal INPUT RESET Master Reset Input Pin 36 Asynchronous active low master reset input Reset should be low at power up to initialize the CS4923 4 5 6 7 8 9 and to guarantee that the device is not active during initial power on stabilization periods At the rising edge of reset the host interface mode is selected contingent on the state of the RD WR and PSEL pins Additionally an autoboot sequence can be initiated if a serial control mode is selected and ABOOT is held low If reset is low all bidirectional pins are high impedance inputs INPUT SCDIO SCDOUT PSEL GPIO9 Serial Control Port Data Input and Output Parallel Port Type Select Pin 19 In C mode this pin serves as the open drain bidirectional data pin In SPI mode this pin serves as the data output pin In parallel host mode this pi

CRYSTAL CS4923/4/5/6/7/8/9 DATA SHEET

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