AMIC - A25L40P Series handbook
Contents
1. D Msg Y Yooo QQ MSB X X PRELIMINARY May 2007 Version 0 4 4 AMIC Technology Corp AMIC OPERATING FEATURES Page Programming To program one data byte two instructions are required Write Enable WREN which is one byte and a Page Program PP sequence which consists of four bytes plus data This is followed by the internal Program cycle of duration tpp To spread this overhead the Page Program PP instruction allows up to 256 bytes to be programmed at a time changing bits from 1 to 0 provided that they lie in consecutive addresses on the same page of memory Sector Erase and Bulk Erase The Page Program PP instruction allows bits to be reset from 1 to 0 Before this can be applied the bytes of memory need to have been erased to all 1s FFh This can be achieved a sector at a time using the Sector Erase SE instruction or throughout the entire memory using the Bulk Erase BE instruction This starts an internal Erase cycle of duration tse Or tse The Erase instruction must be preceded by a Write Enable WREN instruction Polling During a Write Program or Erase Cycle A further improvement in the time to Write Status Register WRSR Program PP or Erase SE or BE can be achieved by not waiting for the worst case delay tw tpp tse or tae The Write In Progress WIP bit is provided in the Status Register so that the application program can moni2. PONS PRELIMINARY May 2007 Version 0 4 34 AMIC Technology Corp A25L40P Series Package Information SOP 8L 209mil Outline Dimensions unit mm 8 i Gos i i H i GAGE PLANE 2 a SEATING PLANE ae en b lt ho 0 25 Ce os o2 o o f se sa es Ce as Do e De Notes Maximum allowable mold flash is 0 15mm at the package ends and 0 25mm between leads PRELIMINARY May 2007 Version 0 4 35 AMIC Technology Corp A25L40P Series Package Information SOP 16L 300mil Outline Dimensions unit inch 0 008 typ J 0 02 x 482 1 0 016 typ 0 050 typ gt 5 osos A 0 004max IH l SEATING PLANE Fs 5 Notes 1 Dimensions D does not include mold flash protrusions or gate burrs 2 Dimensions E does not include interlead flash or protrusions PRELIMINARY May 2007 Version 0 4 36 AMIC Technology Corp Package Information QFN 8L 6 X 5 X 0 8mm Outline Dimensions J 0 25 C D2 C0 30 S E2 1 Controlling dimension millimeters 2 Leadframe thickness is 0 203mm 8mil PRELIMINARY May 2007 Version 0 4 a
3. XE KEXA KKZ AI KOAT XEXE KAA XZ XO XT MSB MSB MSB Note Address bits A23 to A19 are Don t Care PRELIMINARY May 2007 Version 0 4 15 AMIC Technology Corp AMIC Page Program PP The Page Program PP instruction allows bytes to be programmed in the memory changing bits from 1 to 0 Before it can be accepted a Write Enable WREN instruction must previously have been executed After the Write Enable WREN instruction has been decoded the device sets the Write Enable Latch WEL The Page Program PP instruction is entered by driving Chip Select S Low followed by the instruction code three address bytes and at least one data byte on Serial Data Input D If the 8 least significant address bits A7 AO are not all zero all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page from the address whose 8 least significant bits A7 AO are all zero Chip Select S must be driven Low for the entire duration of the sequence The instruction sequence is shown in Figure 12 If more than 256 bytes are sent to the device previously latched data are discarded and the last 256 data bytes are guaranteed to be Figure 12 Page Program PP Instruction Sequence S 23 4 5 6 7 8 9 10 Instruction BEONE DataByte 1 as D EHEN AEX AK OXTHEXE MAX SHAK AV MSB ol 1 A25L40P Series programmed correctly within the same page If less than 256 D
4. ooo 0750 oso 276 205 a15 a foo oo Tao oo Tas T20 as e oso 0400 040 38 158 iss o 000 6000 6 100 2323 2362 2002 pe 3200 3400 800 1200 1339 107 L oso oso 0750 197 236 205 De Py Le Toomlo 2 AMIC Technology Corp A25L40P Series
5. tCHHL gt tCHHH gt A25L40P Series SEE Cs EEE Cen SE Cae EEEN tHLQZ 4 gt tHHQX Q wise HOLD Figure 24 Output Timing 5 ee C PRELIMINARY EEE May 2007 Version 0 4 30 tCH AMIC Technology Corp A25L40P Series Part Numbering Scheme A25 X XX X X X XXX Package Material Blank normal F PB free Temperature Package M 209 mil SOP 8 N SOP 16 O 150 mil SOP 8 Q QFN 8 Boot Sector T Top type U Bottom type Device Version Device Function P Page Program amp Sector Erase Device Density 05 512 Kbit 40 4 Mbit 80 8 Mbit 16 16 Mbit Device Voltage L 2 7 3 6V Device Type A25 AMIC Serial Flash Optional PRELIMINARY May 2007 Version 0 4 31 AMIC Technology Corp AMIC Ordering Information Speed MHz 2 7V 3 6V 3 0V 3 6V A25L40PT F A25L40PT UF A25L40PTO F A25L40PTO UF A25L40PTM F A25L40PTM UF A25L40PTN F A25L40PTN UF A25L40PTQ F A25L40PT Q UF Active Read Current Typ mA Program Erase Current Typ mA Standby Current Typ uA A25L40PU F A25L40PU UF A25L40PUO F A25L40PUO UF A25L40PUM F A25L40PUM UF A25L40PUN F A25L40PUN UF A25L40PUQ F A25L40PUQ UF U is for industrial operating temperature range 40 C 85 C PRELIMINARY May 2007 Version 0 4 A25L40P Series Package 8 Pin Pb Free DIP 300 mil 8 Pin Pb Free DIP 300
6. A25L40P Series Table 10 DC Characteristics Tu fme S S BIETE BIT e fomen 1 1 e Im a ae a a SM G opon 18 na ee eos Operating Curent rs m ees Operating men Save le m Cie open Curent Sv le fm C A A E v va Jowa m af vn omanonvoes ooa Mom Note 1 This is preliminary data at 85 C Table 11 Instruction Times smo am OO rae f E Tresen cyeotine Pe senoressecysetine x _ormersecyaetine Sid Note 1 At 85 C 2 This is preliminary data Table 12 AC Measurement Conditions DER Input Pulse Voltages 0 2Vcc to 0 8Vcc BEE Da Input Timing Reference Voltages 0 3Vcc to 0 7Vcc a Note Output Hi Z is defined as the point where data out is no longer driven PRELIMINARY May 2007 Version 0 4 26 AMIC Technology Corp i AMIC A25L40P Series Figure 20 AC Measurement I O Waveform Input Levels Input and Output Timing Reference Levels PRELIMINARY May 2007 Version 0 4 27 AMIC Technology Corp AMIC Table 13 AC Characteristics Symbol a Parameter Min Clock Frequency for the following instructions FAST_READ D C PP SE BE DP RES RDID WREN WRDI RDSR WRSR or Clock Frequency for READ instructions D C Clock High Time 6 Clock Low Time 5 tan Clock Rise Time peak to peak 0 1 toc Clock Fall Time peak to peak 0 1 S Active Setup Time relative to C j tow S Not Active Hold Time relative to C torox Data In Hold T
7. Each page is 256 bytes wide Thus the whole memory m Deep Power down Mode 1pA typical can be viewed as consisting of 2048 pages or 524 288 bytes m Top or Bottom boot block configuration available The whole memory can be erased using the Bulk Erase m Electronic Signatures instruction or a sector at a time using the Sector Erase JEDEC Standard two Byte Signature 2013h instruction RES Instruction One Byte Signature 12h for backward compatibility m Package options 8 pin SOP 150mil or 209mil 16 pin SOP 8 pin DIP 300mil or 8 pin QFN All Pb free Lead free products are RoHS compliant Pin Configurations E SO8 Connections E SO16 Connections A25L40P A25L40P Note DU Do not Use E DIP8 Connections E OFN8 Connections A25L40P A25L40P PRELIMINARY May 2007 Version 0 4 1 AMIC Technology Corp AMIC Block Diagram Control Logic I 5 wo So O Op U Address register and Counter A25L40P Series High Voltage Generator O Shift Register zl Byte Status Data Buffer Register i B Y Decoder Pin Descriptions Description Serial Clock Serial Data Input Serial Data Output c Chip Select S A25L40P Write Protect w HOLD 7FFFFh Size of the read only memory area 00000h OOOFFh lt 256 Byte Page Size X Decoder Logic Symbol cc D Q Supply Voltage yv SS Ground PRELIMIN
8. WEL bit The Write Enable Latch WEL bit indicates the status of the internal Write Enable Latch BP2 BP1 and BPO bits The Block Protect BP2 BP1 BPO bits are non volatile They define the size of the area to be software protected against Program and Erase instructions SRWD bit The Status Register Write Disable SRWD bit is operated in conjunction with the Write Protect W signal The Status Register Write Disable SRWD bit and Write Protect W signal allow the device to be put in the Hardware Protected mode In this mode the non volatile bits of the Status Register SRWD BP2 BP1 BPO become read only bits Protection Modes The environments where non volatile memory devices are used can be very noisy No SPI device can operate correctly in the presence of excessive noise To help combat this the A25L40P boasts the following data protection mechanisms m Power On Reset and an internal timer tpuw can provide protection against inadvertant changes while the power supply is outside the operating specification m Program Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight before they are accepted for execution m All instructions that modify data must be preceded by a Write Enable WREN instruction to set the Write Enable Latch WEL bit This bit is returned to its reset state by the following events Power up Write Disable WRDI in
9. mil 8 Pin Pb Free SOP 150 mil 8 Pin Pb Free SOP 150 mil 8 Pb Free Pin SOP 209mil 8 Pb Free Pin SOP 209mil 16 Pin Pb Free SOP 16 Pin Pb Free SOP 8 Pin Pb Free QFP 8 Pin Pb Free QFP 8 Pin Pb Free DIP 300 mil 8 Pin Pb Free DIP 300 mil 8 Pin Pb Free SOP 150 mil 8 Pin Pb Free SOP 150 mil 8 Pb Free Pin SOP 209mil 8 Pb Free Pin SOP 209mil 16 Pin Pb Free SOP 16 Pin Pb Free SOP 8 Pin Pb Free QFP 8 Pin Pb Free QFP 32 AMIC Technology Corp i AMIC A25L40P Series Package Information P DIP 8L Outline Dimensions unit inches mm E1 BOTTOM E PIN INDENT 0 116 Seating Plane Dimensions in mm a fowl _ pm foot ose B 0014 oos 0022 036 e 0050 0 060 o ozo 1 27 Ba 0 082 0 039 0 046 0 81 o fosso fosso osr ss ps e i ee ave pe oss oss e7 Notes 1 Dimension D and E1 do not include mold flash or protrusions 2 Dimension B does not include dambar protrusion 3 Tolerance 0 010 0 25mm unless otherwise specified PRELIMINARY May 2007 Version 0 4 33 AMIC Technology Corp AMIC A25L40P Series Package Information SOP 8L 150mil Outline Dimensions unit mm Notes Maximum allowable mold flash is 0 15mm Complies with JEDEC publication 95 MS 012 AA All linear dimensions are in millimeters max min Coplanarity Max 0 4mm
10. 0P is 12h PRELIMINARY May 2007 Version 0 4 21 AMIC Technology Corp AMIC A25L40P Series Figure 18 Release from Deep Power down RES Instruction Sequence Instruction D ucti High Impedance gt Deep Power down Mode Stand by Mode Driving Chip Select S High after the 8 bit instruction byte has been received by the device but before the whole of the 8 bit Electronic Signature has been transmitted for the first time as shown in Figure 18 still insures that the device is put into Stand by Power mode If the device was not pre viously in the Deep Power down mode the transition to the Stand by Power mode is immediate If the device was PRELIMINARY May 2007 Version 0 4 previously in the Deep Power down mode though the transition to the Stand by Power mode is delayed by tres and Chip Select S must remain High for at least tres max as specified in AC Characteristics Table Once in the Stand by Power mode the device waits to be selected so that it can receive decode and execute instructions 22 AMIC Technology Corp AMIC POWER UP AND POWER DOWN At Power up and Power down the device must not be selected that is Chip Select S must follow the voltage applied on Vcc until Vcc reaches the correct value Vcc min at Power up and then for a further delay of tvs Vss at Power down Usually a simple pull up resistor on Chip Select S can be used to in
11. 1 BPO are 0 2 The sector 0 include sector 0 0 sector 0 1 sector 0 2 sector 0 3 and sector 0 4 PRELIMINARY May 2007 Version 0 4 6 AMIC Technology Corp AMIC i A25L40P Series Hold Condition The Hold HOLD signal is used to pause any serial communications with the device without resetting the clocking sequence However taking this signal Low does not terminate any Write Status Register Program or Erase cycle that is currently in progress To enter the Hold condition the device must be selected with Chip Select S Low The Hold condition starts on the falling edge of the Hold HOLD signal provided that this coincides with Serial Clock C being Low as shown in Figure 3 The Hold condition ends on the rising edge of the Hold HOLD signal provided that this coincides with Serial Clock C being Low If the falling edge does not coincide with Serial Clock C being Low the Hold condition starts after Serial Clock C next goes Low Similarly if the rising edge does not coincide with Serial Clock C being Low the Hold condition ends after Figure 3 Hold Condition Activation Serial Clock C next goes Low This is shown in Figure 3 During the Hold condition the Serial Data Output Q is high impedance and Serial Data Input D and Serial Clock C are Don t Care Normally the device is kept selected with Chip Select S driven Low for the whole duration of the Hold condition This is to e
12. 5L40P Series The Deep Power down mode automatically stops at Power down and the device always Powers up in the Standby mode The Deep Power down DP instruction is entered by driving Chip Select S Low followed by the instruction code on Serial Data Input D Chip Select S must be driven Low for the entire duration of the sequence The instruction sequence is shown in Figure 15 Chip Select S must be driven High after the eighth bit of the instruction code has been latched in otherwise the Deep Power down DP instruction is not executed As soon as Chip Select S is driven High it requires a delay of tpp before the supply current is reduced to Icc2 and the Deep Power down mode is entered Any Deep Power down DP instruction while an Erase Program or Write cycle is in progress is rejected without having any effects on the cycle that is in progress Me VE a 123 45 6 7 6 Tn Ls Instruction D a PRELIMINARY May 2007 Version 0 4 Stand by Mode Deep Power down Mode 19 AMIC Technology Corp AMIC Read Device Identification RDID The Read Identification RDID instruction allows the 8 bit manufacturer identification code to be read followed by two bytes of device identification The manufacturer identification is assigned by JEDEC and has the value 37h plus the continuation identification for AMIC Technology The device identification is assigned by the device ma
13. A25L40P Series 4 Mbit Low Voltage Serial Flash Memory Preliminary With 85MHz SPI Bus Interface Document Title 4 Mbit Low Voltage Serial Flash Memory With 85MHz SPI Bus Interface Revision History Rev No History Issue Date Remark 0 0 Initial issue August 29 2006 Preliminary 0 1 Add the Fast Read Dual Operation Instruction April 4 2006 Add QFN 8L 5 x 6mm package type 0 2 Add QFN 8L 5 x 6mm package outline dimensions April 20 2006 0 3 Modify the Part No for Top Bottom boot sector type September 5 2006 Add DIP 8 300mil package type Modify the maximum clock rate to 75MHz 0 4 Add transient voltage lt 20ns on any pin to ground potential spec May 25 2007 Add the maximum clock rate of 3 0V 3 6V 85MHz PRELIMINARY May 2007 Version 0 4 AMIC Technology Corp A25L40P Series AMIC 4 Mbit Low Voltage Serial Flash Memory Preliminary With 85MHz SPI Bus Interface FEATURES GENERAL DESCRIPTION m 4 Mbit of Flash Memory The A25L40P is a 4 Mbit 512K x 8 Serial Flash Memory with m Flexible Sector Architecture 4 4 8 16 32 KB 64x7 KB advanced write protection mechanisms accessed by a high ae ae 4 Hee el speed SPI compatible bus m up to a as typical The memory can be programmed 1 to 256 bytes at a time using m 2 7 to 3 6V Single Supply Voltage the Page Program instruction oo m SPI Bus Compatible Serial Interface The memory is organized as 8 sectors each containing 256 m 85MHz Clock Rate maximum pages
14. ARY May 2007 Version 0 4 2 AMIC Technology Corp AMIC SIGNAL DESCRIPTION Serial Data Output Q This output signal is used to transfer data serially out of the device Data is shifted out on the falling edge of Serial Clock C Serial Data Input D This input signal is used to transfer data serially into the device It receives instructions addresses and the data to be programmed Values are latched on the rising edge of Serial Clock C Serial Clock C This input signal provides the timing of the serial interface Instructions addresses or data present at Serial Data Input D are latched on the rising edge of Serial Clock C Data on Serial Data Output Q changes after the falling edge of Serial Clock C Chip Select S When this input signal is High the device is deselected and Serial Data Output Q is at high impedance Unless an internal Program Erase or Write Status Register cycle is in progress the device will be in the Standby mode this is not the Deep Power down mode Driving Chip Select SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes CPOL 0 CPHA 0 CPOL 1 CPHA 1 For these two modes input data is latched in on the rising edge of Serial Clock C and output data is available from the PRELIMINARY May 2007 Version 0 4 A25L40P Series S Low enables the device placing it in the active power m
15. L40P Series Register cycle is in progress the Status Register may still be read to check the value of the Write In Progress WIP bit The Write In Progress WIP bit is 1 during the self timed Write Status Register cycle and is 0 when it is completed When the cycle is completed the Write Enable Latch WEL is reset The Write Status Register WRSR instruction allows the user to change the values of the Block Protect BP2 BP1 BPO bits to define the size of the area that is to be treated as read only as defined in Table 1 The Write Status Register WRSR instruction also allows the user to set or reset the Status Register Write Disable SRWD bit in accordance with the Write Protect W signal The Status Register Write Disable SRWD bit and Write Protect W signal allow the device to be put in the Hardware Protected Mode HPM The Write Status Register WRSR instruction is not executed once the Hardware Protected Mode HPM is entered Figure 7 Write Status Register WRSR Instruction Sequence 6 7 8 9 10 11 0123 4 5 UU UUUU UW 12 13 14 UU Instruction Q High Impedance PRELIMINARY May 2007 Version 0 4 12 Status Register In AMIC Technology Corp AMIC Table 5 Protection Modes Write Protection of the Status Register Status Register is Writable if the WREN instruction has set the WEL bit The values in the Software Protected SRWD BP2 BP1 and BPO bits can be
16. RELIMINARY May 2007 Version 0 4 M 17 24 Bit Address gt SB Address bits A23 to A19 are Don t Care AMIC Technology Corp AMIC Bulk Erase BE The Bulk Erase BE instruction sets all bits to 1 FFh Before it can be accepted a Write Enable WREN instruction must previously have been executed After the Write Enable WREN instruction has been decoded the device sets the Write Enable Latch WEL The Bulk Erase BE instruction is entered by driving Chip Select S Low followed by the instruction code on Serial Data Input D Chip Select S must be driven Low for the entire duration of the sequence The instruction sequence is shown in Figure 14 Chip Select S must be driven High after the eighth bit of the instruction code has been latched in otherwise the Bulk Erase instruction Figure 14 Bulk Erase BE Instruction Sequence S 0 1 Notes PRELIMINARY May 2007 Version 0 4 A25L40P Series is not executed As soon as Chip Select S is driven High the self timed Bulk Erase cycle whose duration is tse is initiated While the Bulk Erase cycle is in progress the Status Register may be read to check the value of the Write In Progress WIP bit The Write In Progress WIP bit is 1 during the self timed Bulk Erase cycle and is 0 when it is completed At some unspecified time before the cycle is completed the Write Enable Latch WEL bit is reset The Bulk Erase BE instructi
17. a Output Q each bit being shifted out during the falling edge of Serial Clock C The instruction sequence is shown in Figure 17 The Release from Deep Power down and Read Electronic Signature RES instruction is terminated by driving Chip Select S High after the Electronic Signature has been read at least once Sending additional clock cycles on Serial Clock C while Chip Select S is driven Low cause the Electronic Signature to be output repeatedly When Chip Select S is driven High the device is put in the Stand by Power mode If the device was not previously in the Deep Power down mode the transition to the Stand by Power mode is immediate If the device was previously in the Deep Power down mode though the transition to the Stand by Power mode is delayed by tres2 and Chip Select S must remain High for at least tres2 max as specified in AC Characteristics Table Once in the Stand by Power mode the device waits to be selected so that it can receive decode and execute instructions Figure 17 Release from Deep Power down and Read Electronic Signature RES Instruction Sequence and Data Out Sequence 23 4 5 6 7 8 9 10 28 29 30 31 3 c ULLI UUU N q w mo amp A ao o W 0O N W 10 High Impedance 2990900 O MSB gt Deep Power down Mode Stand by Mode Note The value of the 8 bit Electronic Signature for the A25L4
18. ata bytes are sent to device they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page Chip Select S must be driven High after the eighth bit of the last data byte has been latched in otherwise the Page Program PP instruction is not executed As soon as Chip Select S is driven High the self timed Page Program cycle whose duration is tpp is initiated While the Page Program cycle is in progress the Status Register may be read to check the value of the Write In Progress WIP bit The Write In Progress WIP bit is 1 during the self timed Page Program cycle and is 0 when it is completed At some unspecified time before the cycle is completed the Write Enable Latch WEL bit is reset A Page Program PP instruction applied to a page which is protected by the Block Protect BP2 BP1 BPO bits see Table 2 and Table 1 is not executed 28 29 30 31 32 33 34 35 36 37 38 39 MSB 2072 2073 2074 2075 2076 2077 2078 2079 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 UUUUUUUUI e AUN L lt Data Byte 2 DataByte3 gt Data Byte 256 D X7X6XSX4X3X2XIKOXTXEXEKAMSMEK IOP THEMSKIKSKZK AKO MSB MSB Note Address bits A23 to A19 are Don t Care PRELIMINARY May 2007 Version 0 4 16 MSB AMIC Technology Corp AMIC Sector Erase SE The Sector Erase SE instr
19. bits and the Write Status Register WRSR instruction is no longer accepted for execution Figure 6 Read Status Register RDSR Instruction Sequence and Data Out Sequence O 1 Instruction High Impedance Status Register Out 23 4 5 6 7 8 Q 10 11 12 13 14 15 Status Register Out TX BXEXANSKAKIKONTXEXEXANSKAKIKONT MSB PRELIMINARY May 2007 Version 0 4 11 MSB AMIC Technology Corp AMIC Write Status Register WRSR The Write Status Register WRSR instruction allows new values to be written to the Status Register Before it can be accepted a Write Enable WREN instruction must previously have been executed After the Write Enable WREN instruction has been decoded and executed the device sets the Write Enable Latch WEL The Write Status Register WRSR instruction is entered by driving Chip Select S Low followed by the instruction code and the data byte on Serial Data Input D The instruction sequence is shown in Figure 7 The Write Status Register WRSR instruction has no effect on b6 b5 b1 and bO of the Status Register b6 and b5 are always read as 0 Chip Select S must be driven High after the eighth bit of the data byte has been latched in If not the Write Status Register WRSR instruction is not executed As soon as Chip Select S is driven High the self timed Write Status Register cycle whose duration is tw is initiated While the Write Status A25
20. changed Hardware Protected protected The values in the SRWD BP2 BP1 and BPO bits cannot be changed Status Register is Hardware write A25L40P Series Memory Content Protected Area Unprotected Area Protected against Page Program Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Protected against Page Program Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Note 1 As defined by the values in the Block Protect BP2 BP1 BPO bits of the Status Register as shown in Table 1 The protection features of the device are summarized in Table 5 When the Status Register Write Disable SRWD bit of the Status Register is 0 its initial delivery state it is possible to write to the Status Register provided that the Write Enable Latch WEL bit has previously been set by a Write Enable WREN instruction regardless of the whether Write Protect W is driven High or Low When the Status Register Write Disable SRWD bit of the Status Register is set to 1 two cases need to be considered depending on the state of Write Protect W If Write Protect W is driven High it is possible to write to the Status Register provided that the Write Enable Latch WEL bit has previously been set by a Write Enable WREN instruction If Write Protect W is driven Low it is not possible to write to the Status Register even if
21. erial Clock C Then the memory contents at that address is shifted out on Serial Data Output Q each bit being shifted out at a maximum frequency fc during the falling edge of Serial Clock C The instruction sequence is shown in Figure 9 The first byte addressed can be at any location The address is automatically incremented to the next higher address after each byte of data is shifted out The whole memory can therefore be read with a single Read Data Bytes at Higher Speed FAST_READ instruction When the highest address is reached the address counter rolls over to 000000h allowing the read sequence to be continued indefinitely The Read Data Bytes at Higher Speed FAST_READ instruction is terminated by driving Chip Select S High Chip Select S can be driven High at any time during data output Any Read Data Bytes at Higher Speed FAST_READ instruction while an Erase Program or Write cycle is in progress is rejected without having any effects on the cycle that is in progress Figure 9 Read Data Bytes at Higher Speed FAST_READ Instruction Sequence and Data Out Sequence S 0 1 23 4 5 6 78910 24 Bit Address 28 29 30 31 Instruction D A 23K22K21 3 X21 XO MSB Q High Impedance ae 5 32 33 34 35 36 37 38 3940 41 42 43 44 45 46 47 c _ UUUUUUUUUUUUUUUUUUUUUUUUL_ Dummy Byte gt D 7X6X5X4K3K2X1 KOK Data Out 1 Data Out 2 G
22. fted out at a maximum frequency fr during the falling edge of Serial Clock C The instruction sequence is shown in Figure 8 The first byte addressed can be at any location The address is automatically incremented to the next higher address after each byte of data is shifted out The whole memory can A25L40P Series therefore be read with a single Read Data Bytes READ instruction When the highest address is reached the address counter rolls over to 000000h allowing the read sequence to be continued indefinitely The Read Data Bytes READ instruction is terminated by driving Chip Select S High Chip Select S can be driven High at any time during data output Any Read Data Bytes READ instruction while an Erase Program or Write cycle is in progress is rejected without having any effects on the cycle that is in progress Figure 8 Read Data Bytes READ Instruction Sequence and Data Out Sequence 23 4 5 6 7 8 9 10 High Impedance Note Address bits A23 to A19 are Don t Care PRELIMINARY May 2007 Version 0 4 28 29 30 31 32 33 34 35 36 37 38 39 14 AMIC Technology Corp AMIC i A25L40P Series Read Data Bytes at Higher Speed FAST_READ The device is first selected by driving Chip Select S Low The instruction code for the Read Data Bytes at Higher Speed FAST_READ instruction is followed by a 3 byte address A23 A0 and a dummy byte each bit being latched in during the rising edge of S
23. ice most significant bit first on Serial Data Input D each bit being latched on the rising edges of Serial Clock C The instruction set is listed in Table 3 A25L40P Series sequence is being shifted out Inthe case of a Page Program PP Sector Erase SE Bulk Erase BE Write Status Register WRSR Write Enable WREN Write Disable WRDI or Deep Power down DP instruction Chip Select S must be driven High exactly at a byte boundary otherwise the instruction is rejected and is not executed That is Chip Select S must driven High when the number of clock pulses after Chip Select S being driven Low Every instruction sequence starts with a one byte instruction code Depending on the instruction this might be followed by address bytes or by data bytes or by both or none In the case of a Read Data Bytes READ Read Data Bytes at Higher Speed Fast_Read Read Status Register RDSR or Release from Deep Power down Read Device Identification and Read Electronic Signature RES instruction the shifted in instruction sequence is followed by a data out sequence Chip Select S can be driven High after any bit of the data out is an exact multiple of eight All attempts to access the memory array during a Write Status Register cycle Program cycle or Erase cycle are ignored and the internal Write Status Register cycle Program cycle or Erase cycle continues unaffected Table 3 Instruction Set Describtion O
24. ime IchsH S Active Hold Time relative to C tsHcH S Not Active Setup Time relative to C 2 tss S Deselect Time en Output Disable Time Clock Low to Output Valid Output Hold Time 0 tHLcH HOLD Setup Time relative to C 5 otom HOLD Hold Time relative to C 5 tmon HOLD Setup Time relative to C 5 tom HOLD Hold Time relative to C 5 HOLD to Output Low Z HOLD to Output High Z Write Protect Setup Time 20 Write Protect Hold Time 100 to 2 4 2 P tres S S High to Standby Mode without Electronic Signature Read 2 p E E O tese S High to Standby Mode with Electronic Signature Read S High to Deep Power down Mode Write Status Register Cycle Time Page Program Cycle Time ts ts Note 1 tcn te must be greater than or equal to 1 fc 2 Value guaranteed by characterization not 100 tested in production 3 Expressed as a slew rate 4 Only applicable as a constraint for a WRSR instruction when SRWD is set at 1 5 Vcc range 3 0V 3 6V for 85MHz Sector Erase Cycle Time Bulk Erase Cycle Time A25L40P Series PRELIMINARY May 2007 Version 0 4 28 AMIC Technology Corp i AMIC A25L40P Series Figure 21 Serial Input Timing High Impedance Figure 22 Write Protect Setup and Hold Timing during WRSR when SRWD 1 WHSL tSHWL ol DN NK XK KK KKK High Impedance PRELIMINARY May 2007 Version 0 4 29 AMIC Technology Corp Figure 23 Hold Timing N
25. mpedance lt gt ab gt gt Continuation ID Manufacture ID Memory Type Memory Capacity PRELIMINARY May 2007 Version 0 4 20 AMIC Technology Corp AMIC Release Electronic Signature RES from Deep Power down and Read Once the device has entered the Deep Power down mode all instructions are ignored except the Release from Deep Power down and Read Electronic Signature RES instruction Executing this instruction takes the device out of the Deep Power down mode The instruction can also be used to read on Serial Data Output Q the 8 bit Electronic Signature whose value for the A25L40P is 12h Except while an Erase Program or Write Status Register cycle is in progress the Release from Deep Power down and Read Electronic Signature RES instruction always provides access to the 8 bit Electronic Signature of the device and can be applied even if the Deep Power down mode has not been entered Any Release from Deep Power down and Read Electronic Signature RES instruction while an Erase Program or Write Status Register cycle is in progress is not decoded and has no effect on the cycle that is in progress The device is first selected by driving Chip Select S Low The instruction code is followed by 3 dummy bytes each bit being latched in on Serial Data Input D during the rising A25L40P Series edge of Serial Clock C Then the 8 bit Electronic Signature stored in the memory is shifted out on Serial Dat
26. n Pb or Pb assembly 2 JEDEC Std JESD22 A114A C1 100 pF R1 1500 Q R2 500 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions and the DC and AC characteristics of the device The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Table 7 Operating Conditions Parameter A25L40P Series Comments Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Refer also to the AMIC SURE Program and other relevant quality docu ments Measurement Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters Ambient Operating Temperature Table 8 Data Retention and Endurance Erase Program Cycles At 85 C P 100 000 Cycles per sector Data Retention At 85 C Note 1 This is preliminary data Table 9 Capacitance Note Sampled only not 100 tested at Ta 25 C and a frequency of 33 MHz PRELIMINARY May 2007 Version 0 4 25 AMIC Technology Corp AMIC
27. ne byte Address Dummy Data p Instruction Code Bytes Bytes Bytes RDSR Read Status Register 0000 0101 FREE WRSR Write Status Register ooooooon oth o o a FAST_READ Read Data Bytes at Higher Speed 0000 1011 ee oe Fraser oomamo om a o tem se secors BEE fom a 0 ee Fame oom emo oo AB BEE DR RDID Read Device Identification Device Identification 10011111 1111 1to4 to 4 Release from Deep Power down and iito o RES Read Electronic Signature 1010 1011 Release from Deep Power down from Release from Deep Power down Power down PRELIMINARY May 2007 Version 0 4 9 AMIC Technology Corp AMIC i A25L40P Series Write Enable WREN The Write Enable WREN instruction Figure 4 sets the Write Enable Latch WEL bit The Write Enable Latch WEL bit must be set prior to every Page Program PP Sector Erase SE Bulk Erase BE and Write Status Register WRSR instruction Figure 4 Write Enable WREN Instruction Sequence ol The Write Enable WREN instruction is entered by driving Chip Select S Low sending the instruction code and then driving Chip Select S High Koo u 0123 45 6 7 Instruction _ High Impedance Write Disable WRDI The Write Disable WRDI instruction Figure 5 resets the Write Enable Latch WEL bit The Write Disable WRDI instruction is entered by driving Chip Select S Low sending the instruction code and then driving Chip The W
28. nsure that the state of the internal logic remains unchanged from the moment of entering the Hold condition If Chip Select S goes High while the device is in the Hold condition this has the effect of resetting the internal logic of the device To restart communication with the device it is necessary to drive Hold HOLD High and then to drive Chip Select S Low This prevents the device from going back to the Hold condition lt lt Hold gt Condition standard use PRELIMINARY Hold gt Condition non standard use AMIC Technology Corp May 2007 Version 0 4 AMIC A25L40P Series MEMORY ORGANIZATION The memory is organized as Each page can be individually programmed bits are m 524 288 bytes 8 bits each programmed from 1 to 0 The device is Sector or Bulk m 8 sectors one 4 4 8 16 32 Kbytes amp 64x7 Kbytes Erasable bits are erased from 0 to 1 but not Page Erasable m 2048 pages 256 bytes each Table 2 Memory Organization A25L40PT Top Boot Block Address Table 7FFFFh 7EFFFh A25L40PU Bottom Boot Block Address Table PRELIMINARY May 2007 Version 0 4 8 AMIC Technology Corp AMIC INSTRUCTIONS All instructions addresses and data are shifted in and out of the device most significant bit first Serial Data Input D is sampled on the first rising edge of Serial Clock C after Chip Select S is driven Low Then the one byte instruction code must be shifted in to the dev
29. nufacturer and indicates the memory in the first bytes 20h and the memory capacity of the device in the second byte 13h The Device Identification of memory capacity is 13h Any Read Identification RDID instruction while an Erase or Program cycle is in progress is not decoded and has no effect on the cycle that is in progress The device is first selected by driving Chip Select S Low A25L40P Series Then the 8 bit instruction code for the instruction is shifted in This is followed by the 32 bit device identification stored in the memory being shifted out on Serial Data Output Q each bit being shifted out during the falling edge of Serial Clock C The instruction sequence is shown in Figure 16 The Read Identification RDID instruction is terminated by driving Chip Select S High at any time during data output When Chip Select S is driven High the device is put in the Stand by Power mode Once in the Stand by Power mode the device waits to be selected so that it can receive decode and execute instructions Table 6 Read Identification READ_ID Data Out Sequence Device Identification Manufacture Identification Continuation ID Manufacture ID Memory Type Memory Capacity Figure 16 Read Identification RDID Data Out Sequence Se ee 012345678 910 131415 16 1718 21 22 23 24 25 26 2930 313233 34 3738 39 Instruction D Q I RKRKKIKIAKKKKIIIIIKII ZX IX OK C High I
30. ode After Power up a falling edge on Chip Select S is required prior to the start of any instruction Hold HOLD The Hold HOLD signal is used to pause any serial communications with the device without deselecting the device During the Hold condition the Serial Data Output Q is high impedance and Serial Data Input D and Serial Clock C are Don t Care To start the Hold condition the device must be selected with Chip Select S driven Low Write Protect W The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions as specified by the values in the BP2 BP1 and BPO bits of the Status Register falling edge of Serial Clock C The difference between the two modes as shown in Figure 2 is the clock polarity when the bus master is in Stand by mode and not transferring data C remains at 0 for CPOL 0 CPHA 0 C remains at 1 for CPOL 1 CPHA 1 AMIC Technology Corp i AMIC A25L40P Series Figure 1 Bus Master and Memory Devices on the SPI Bus SPI Interface with CPOL CPHA 0 0 or 1 1 Bus Master ST6 ST7 ST9 ST10 Other SPI Memory SPI Memory SPI Memory Device Device Device CS3 CS2 CS1 Note The Write Protect W and Hold HOLD signals should be driven High or Low as appropriate Figure 2 SPI Modes Supported CPOL CPHA 0 0 C 1 1 C
31. on is executed only if all Block Protect BP2 BP1 BPO bits are 0 The Bulk Erase BE instruction is ignored if one or more sectors are protected Sn zu 23 45 67 Co YUU UU Instruction 18 Address bits A23 to A19 are Don t Care AMIC Technology Corp AMIC Deep Power down DP Executing the Deep Power down DP instruction is the only way to put the device in the lowest consumption mode the Deep Power down mode It can also be used as an extra software protection mechanism while the device is not in active use since in this mode the device ignores all Write Program and Erase instructions Driving Chip Select S High deselects the device and puts the device in the Standby mode if there is no internal cycle currently in progress But this mode is not the Deep Power down mode The Deep Power down mode can only be entered by executing the Deep Power down DP instruction to reduce the standby current from Icc to Icc2 as specified in DC Characteristics Table Once the device has entered the Deep Power down mode all instructions are ignored except the Release from Deep Power down and Read Electronic Signature RES instruction This releases the device from this mode The Release from Deep Power down and Read Electronic Signature RES instruction also allows the Electronic Signature of the device to be output on Serial Data Output Q Figure 15 Deep Power down DP Instruction Sequence A2
32. rite Enable Latch WEL bit is reset under the following conditions Figure 5 Write Disable WRDI Instruction Sequence ol Power up Write Disable WRDI instruction completion Write Status Register WRSR instruction completion Page Program PP instruction completion Sector Erase SE instruction completion Bulk Erase BE instruction completion e S 23 45 6 7 hi O MUU U UU Instruction Oo __ wen High Impedance PRELIMINARY AMIC Technology Corp May 2007 Version 0 4 AMIC Read Status Register RDSR The Read Status Register RDSR instruction allows the Status Register to be read The Status Register may be read at any time even while a Program Erase or Write Status Register cycle is in progress When one of these cycles is in progress it is recommended to check the Write In Progress WIP bit before sending a new instruction to the device It is also possible to read the Status Register continuously as shown in Figure 6 Table 4 Status Register Format b7 SRWD 0 0 bO BP2 BP1 BPO WEL WIP Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit The status and control bits of the Status Register are as follows WIP bit The Write In Progress WIP bit indicates whether the memory is busy with a Write Status Register Program or Erase cycle When set to 1 such a cycle is in progress
33. struction completion Write Status Register WRSR instruction completion Page Program PP instruction completion Sector Erase SE instruction completion Bulk Erase BE instruction completion m The Block Protect BP2 BP1 BPO bits allow part of the memory to be configured as read only This is the Software Protected Mode SPM m The Write Protect W signal allows the Block Protect BP2 BP1 BPO bits and Status Register Write Disable SRWD bit to be protected This is the Hardware Protected Mode HPM m In addition to the low power consumption feature the Deep Power down mode offers extra software protection from inadvertant Write Program and Erase instructions as all instructions are ignored except one particular instruction the Release from Deep Power down instruction AMIC Technology Corp AMIC A25L40P Series Table 1 Protected Area Sizes A25L40PT Top Boot Block Status Register Content Memory Content BP2 Bit BP1 Bit BPO Bit Protected Area Unprotected Area Note 1 The device is ready to accept a Bulk Erase instruction if and only if all Block Protect BP2 BP1 BPO are 0 2 The sector 7 include sector 7 0 sector 7 1 sector 7 2 sector 7 3 and sector 7 4 A25L40PU Bottom Boot Block Status Register Content Memory Content BP2 Bit BP1 Bit BPO Bit Protected Area Unprotected Area Note 1 The device is ready to accept a Bulk Erase instruction if and only if all Block Protect BP2 BP
34. sure safe and proper Power up and Power down To avoid data corruption and inadvertent write operations during power up a Power On Reset POR circuit is included The logic inside the device is held reset while Vcc is less than the POR threshold value Vwi all operations are disabled and the device does not respond to any instruction Moreover the device ignores all Write Enable WREN Page Program PP Sector Erase SE Bulk Erase BE and Write Status Register WRSR instructions until a time delay of tpuw has elapsed after the moment that Vcc rises above the VWI threshold However the correct operation of the device is not guaranteed if by this time Vcc is still below Vcc min No Write Status Register Program or Erase instructions should be sent until the later of Figure 19 Power up Timing PRELIMINARY May 2007 Version 0 4 23 A25L40P Series tpuw after Vcc passed the VWI threshold tvst afterVcc passed the Vcc min level These values are specified in Table 7 If the delay tvst has elapsed after Vcc has risen above Vec min the device can be selected for READ instructions even if the tpuw delay is not yet fully elapsed At Power up the device is in the following state The device is in the Standby mode not the Deep Power down mode The Write Enable Latch WEL bit is reset Normal precautions must be taken for supply rail decoupling to stabilize the Vcc feed Each device in a system should ha
35. the Write Enable Latch WEL bit has previously been set by a Write Enable WREN instruction Attempts to write to the Status PRELIMINARY May 2007 Version 0 4 Register are rejected and are not accepted for execution As a consequence all the data bytes in the memory area that are software protected SPM by the Block Protect BP2 BP1 BPO bits of the Status Register are also hardware protected against data modification Regardless of the order of the two events the Hardware Protected Mode HPM can be entered by setting the Status Register Write Disable SRWD bit after driving Write Protect W Low or by driving Write Protect W Low after setting the Status Register Write Disable SRWD bit The only way to exit the Hardware Protected Mode HPM once entered is to pull Write Protect W High If Write Protect W is permanently tied High the Hardware Protected Mode HPM can never be activated and only the Software Protected Mode SPM using the Block Protect BP2 BP1 BPO bits of the Status Register can be used AMIC Technology Corp AMIC Read Data Bytes READ The device is first selected by driving Chip Select S Low The instruction code for the Read Data Bytes READ instruction is followed by a 3 byte address A23 A0 each bit being latched in during the rising edge of Serial Clock C Then the memory contents at that address is shifted out on Serial Data Output Q each bit being shi
36. tor its value polling it to establish when the previous Write cycle Program cycle or Erase cycle is complete Active Power Stand by Power and Deep Power Down Modes When Chip Select S is Low the device is enabled and in the Active Power mode When Chip Select S is High the device is disabled but could remain in the Active Power mode until all internal cycles have completed Program Erase Write Status Register The device then goes in to the Stand by Power mode The device consumption drops to Icc1 The Deep Power down mode is entered when the specific instruction the Enter Deep Power down Mode DP instruction is executed The device consumption drops further to Icc2 The device remains in this mode until another specific instruction the Release from Deep Power down Mode and Read Electronic Signature RES instruction is executed All other instructions are ignored while the device is in the Deep Power down mode This can be used as an extra software protection mechanism when the device is not in active use to protect the device from inadvertent Write Program or Erase instructions PRELIMINARY May 2007 Version 0 4 A25L40P Series Status Register The Status Register contains a number of status and control bits that can be read or set as appropriate by specific instructions WIP bit The Write In Progress WIP bit indicates whether the memory is busy with a Write Status Register Program or Erase cycle
37. uction sets all bits to 1 FFh Before it can be accepted a Write Enable WREN instruction must previously have been executed After the Write Enable WREN instruction has been decoded the device sets the Write Enable Latch WEL The Sector Erase SE instruction is entered by driving Chip Select S Low followed by the instruction code on Serial Data Input D Chip Select S must be driven Low for the entire duration of the sequence The instruction sequence is shown in Figure 13 Chip Select S must be driven High after the eighth bit of the instruction code has been latched in otherwise the Sector Erase Figure 13 Sector Erase SE Instruction Sequence 5 A25L40P Series instruction is not executed As soon as Chip Select S is driven High the self timed Sector Erase cycle whose duration is tge is initiated While the Sector Erase cycle is in progress the Status Register may be read to check the value of the Write In Progress WIP bit The Write In Progress WIP bit is 1 during the self timed Sector Erase cycle and is 0 when it is completed At some unspecified time before the cycle is completed the Write Enable Latch WEL bit is reset The Sector Erase SE instruction is executed only if all Block Protect BP2 BP1 BPO bits are 0 The Sector Erase SE instruction is ignored if one or more sectors are protected ee 123 4 5 6 7 8 9 10 28 29 30 31 e 1UUUUUUUUU UT Instruction Notes P
38. ve the Vcc rail decoupled by a suitable capacitor close to the package pins Generally this capacitor is of the order of 0 1uF At Power down when Vcc drops from the operating voltage to below the POR threshold value Vwi all operations are disabled and the device does not respond to any instruction The designer needs to be aware that if a Power down occurs while a Write Program or Erase cycle is in progress some data corruption can result Full Device Access time AMIC Technology Corp i AMIC A25L40P Series Table 7 Power Up Timing Dem eem o f Note These parameters are characterized only INITIAL DELIVERY STATE The device is delivered with the memory array erased all bits are set to 1 each byte contains FFh The Status Register contains 00h all Status Register bits are 0 PRELIMINARY May 2007 Version 0 4 24 AMIC Technology Corp AMIC Absolute Maximum Ratings Storage Temperature TSTG 65 C to 150 C Lead Temperature during Soldering Note 1 D C Voltage on Any Pin to Ground Potential BREITER TRUE Pes es 0 6V to VCC 0 6V Transient Voltage lt 20ns on Any Pin to Ground Potential od Gana ae a Wood ak ov eaten es 2 0V to VCC 2 0V Supply Voltage VCO 22 222220 0 6V to 4 0V Electrostatic Discharge Voltage Human Body model VESD Note 2 2 22 22er ren 2000V to 2000V Notes 1 Compliant with JEDEC Std J STD 020B for small body S
39. when reset to 0 no such cycle is in progress A25L40P Series WEL bit The Write Enable Latch WEL bit indicates the status of the internal Write Enable Latch When set to 1 the internal Write Enable Latch is set when set to 0 the internal Write Enable Latch is reset and no Write Status Register Program or Erase instruction is accepted BP2 BP1 BPO bits The Block Protect BP2 BP1 BPO bits are non volatile They define the size of the area to be software protected against Program and Erase instructions These bits are written with the Write Status Register WRSR instruction When one or both of the Block Protect BP2 BP1 BPO bits is set to 1 the relevant memory area as defined in Table 1 becomes protected against Page Program PP and Sector Erase SE instructions The Block Protect BP2 BP1 BPO bits can be written provided that the Hardware Protected mode has not been set The Bulk Erase BE instruction is executed if and only if both Block Protect BP2 BP1 BPO bits are 0 SRWD bit The Status Register Write Disable SRWD bit is operated in conjunction with the Write Protect W signal The Status Register Write Disable SRWD bit and Write Protect W signal allow the device to be put in the Hardware Protected mode when the Status Register Write Disable SRWD bit is set to 1 and Write Protect W is driven Low In this mode the non volatile bits of the Status Register SRWD BP2 BP1 BPO become read only
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AMIC A25L40P Series handbook