Lattice MACH 5 CPLD Family Fifth Generation MACH Architecture
Contents
1. 91 0 49019 91 0 49018 91 0 91 0 49018 91 91 91 91 91 91 91 91 5190 5190 5199 1 30142 30142 80 182 30192 91 2 2 91 2 91 2 Jojejeue L JojeJeuec L Jojjeue L L gt H 1 j 1 1 184 14 c 144 1499 1842. M5 256 22 92 QNT M5 256 MBLV 256 55555555 88888888 8888 8888 88888888 55555555 MBLV 256 O CO QN 0 CO QN oobBnbonhono Db3Xy3x3XoYX3 Y oo 9999999995988 69999090052009000000500900025 2090905 00000900 25000000005 0858850558955 555905995555559558 89595589 95 TDI mcum
3. 91 0 51 0 sijeooi2ew g 401g 91 0 901g 91 0 sijo20128W g 51 0 9 51 0 sijeooi2ew g 49019 9 9 9100 5190 1 30142 amp m 30 142 5 y 5 1 20219090 iE 2 e lonuoo gt sje Ky lonuoo gt aa 51990 jonuoo sieooiew mt ouo pm 1 1 1 1 144 14 142 1 1479 14 144 1499 26 144 14 25 192 1479 2 601 pue 91507 pue 91607 pue 91607 pue 21607 pue 91607 pue 2601 2601 2601 ANY 9 601 2601 ANY 2601
4. 91 0 49019 91 0 401g 91 0 49019 91 0 49019 91 0 49019 51 0 9 9 9 5160 soon 5100 5169 5 90 142 30142 30142 1 30142 1 30142 1 30192 1 2 2 2 2 z 9 2 jojeieueo 701019090 20219090 01219090 10113039 gt ouo i uoo muog sjoen 1904900 11 1 144 1479 E 142 1459 z 192 14 144 1819 26 144 1479 C 144 1479 91607 pue 2 pue 91607 pue 21507 pue pue 91
5. Top View 100 68 1 0 M5LV 128 MBLV 128 M5 192 9222 lt M5 192 CN CV CV 5 256 5 256 MBLV 256 55555555 55555555 MBLV 256 10 LO st CN XO D co 9 L0 10 O 10 lO 00000000 622 860000000 8885885855 8 98 8 59 5 GND 1 80 GND GND 2 79 GND TDI 3 78 TDO 14 0A12 12 100 4 77 51 3A12 2A12 0014 0B13 0B13 0B13 1 5 76 050 3813 2813 0C13 0B12 0B12 OB12 1 02 6 75 1 049 3B12 2B12 0 12 OB11 0811 103 7 74 048 3B11 2811 OB8 088 04 8 73 047 388 288 0 8 7 087 087 5 9 72 046 3B7 287 0 7 0B4 084 084 1 06 10 71 1 045 384 284 0 4 0B3 1 07 11 70 1 044 3B3 283 0C3 0B2 0B2 0B2 108 12 69 043 3B2 282 0 2 I0 CLKO 13 68 I3 CLK3 Vcc 14 67 GND Vcc 15 66 GND GND 16 65 Vec GND 17 64 Vcc H CLK1 18 63 12721 2 182 1B2 182 109 19 62 V042 2B2 2 2
6. LN3IND3S 0 LN3IANO3S 91 0 9019 91 0 12018 9 9 9 91 5199 199 30 18 2 8018 2 91 9 1 Jonuo Jonuo 1 1 144 1499 aE 144 id 21601 pue 21601 pue keny 21601 ANY 21601 LX v9 64 9 1 1 c H 12018 H 55 c Y Y Jojeool v 21601 pue 91607 pue 01507 21607 9 LXv9 132 14 9 1424 14 9 ze L L Joje1euec 7 5 D siieoo ew 9r 2 1 91 2 30192 Y 199 5199 91 9 91 91 91 0 49018 91 0 49018 1 1 1 tey 0 20 91 0 401g 91 0 91 0 91 0 SII 49018 91 94 9 91 94 9 9 91 5199 5199 199 5199
7. CLKO CLK1 2 SEGMENT INTERCONNECT CLK3 Block A Macrocells 0 15 Block D Macrocells 0 15 16 Me Cells 2PTOE 2PTOE EN 16 Control 16 Control Macrocells 77 Generator 4 Macrocells Generator 32 64 7PT 64 PT 64 73 64 73 AND Logic Array AND Logic Array and Logic Allocator and Logic Allocator 1 32 32 P s 2 3 Block Interconnect 2 64 73 AND Logic Array and Logic Allocator 64 x 73 AND Logic Array and Logic Allocator 32 64 PT 7PT 64 PT Macrocells Control Control 7 Generator Generator 2PTOE B Cells 16 Cells Block B Macrocells 0 15 Block C Macrocells 0 15 SEGMENT 1 20446G 007 14 MACH 5 Family Ci 65 I BLOCK DIAGRAM M5 192 XXX L 935
8. cell Es Control Generator 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 4 204466 015 MACH 5 Family 13 Lattice Semiconductor Corporation BLOCK DIAGRAM M5 LV 128 XXX SEGMENT 0 Block A Macrocells 0 15 Block D Macrocells 0 15 ocells Macrocells Control Generator 64x 73 AND Logic Array and Logic Allocator pE 7 32 J f Y 64x 73 AND Logic Array and Logic Allocator Control Generator 64 x 73 AND Logic Array and Logic Allocator 64 x 73 AND Logic Array and Logic Allocator 64 PT Control Generator Macrocells Control Macrocells Generator 2 PT OE Cells Cells 16 16 16 Block B Macrocells 0 15 Block C Macrocells 0 15
9. SSSSSSSSS Ser Nes vetees seen 29298299299 98 182522930000 204895 899 5 5250888888528 9586856255552 9555555555555558 556556588 gt 65 awe yeu rU 5 512 ML Veo EPIS SEEEESES 555555 889458808 25525552 MeL V 512 Fa wedrdqex Ms Bus 585552 QESRER 88555558 35588888 M5 320 ogoorun M5 320 MSLV 320 5555 D LL55 44455554 MSLV 320 Package obsolete contact factory Pin Designations CIK Clock GND Ground I Input YO Input Output NC No Connect 20446G 025 Supply Voltage 7 D 15 Test Data In Test Clock Macrocell 0 15 Test Mode Select PAL Block A D Test Data Out Segment 0 7 MACH 5 Family 37 Semiconductor Corporation 256 BALL BGA CONNECTION DIAGRAM M5 320 M5LV 320 M5 384 M5LV 384 M5 512 M5LV 512 Bottom View 1 0 Pin outs 256 Ball BGA lt M OA 2 gt En I c v S 9 L 8 6 OL St 9
10. te eg ie vc 0A8 1 00 2 155 1 0119 3A8 0A9 1 01 3 154 1 0118 3A9 0A10 1 02 4 153 1 0117 3A10 0A11 1 03 5 152 1 0116 3A11 0A12 1 04 6 151 1 0115 2A12 0A13 1 05 7 150 1 0114 3A13 0A14 1 06 8 149 1 0113 3A14 0A15 1 07 9 148 1 0112 3A15 Vcc 10 147 Vcc GND 11 146 GND 0B13 1 08 12 145 1 0111 3B13 0B12 1 09 13 144 1 0110 3B12 0B11 1 010 14 143 1 0109 3B11 0B10 1 011 15 142 1 0108 3B10 0B9 1 012 16 141 1 0107 3B9 0B8 1 013 17 140 1 0106 3B8 0B7 1 014 18 139 1 0105 3B7 086 1 015 19 138 1 0104 3B6 GND 20 137 GND 0B5 1 016 21 136 1 0103 3B5 0B4 1 017 22 135 1 0102 3B4 0B3 1 018 23 134 1 0101 3B3 0B2 1 019 24 t33 1 0100 3B2 10 CLKO 25 132 13 CLK3 Vcc 26 131 GND GND 27 130 Voc M CLK1 28 129 I2 CLK2 1B2 020 29 128 1 099 2B2 1B3 1 021 30 127 1 098 2B3 1B4 1 022 31 126 1 097 2B4 1B5 1 023 32 125 1 096 2B5 GND 33 124 GND 1B6 1 024 34 123 1 095 2B6 1B7 1 025 35 122 1 094 2B7 1B8 1 026 36 121 1 093 2B8 1B9 1 027 37 120 1 092 2B9 1B10 1 028 38 119 1 091 2B10 1B11 1 029 39 118 1 090 2B11 1B12 1 030 40 117 1 089 2B12 1B13 1 031 41 116 1 088 2B13 GND 42 145 GND Vcc 43 114 Vcc 1A15 1 032 44 113 1 087 2A15 1A14 1 033 45 112 1 086 2A14 1A13 1 034 46 111 1 085 2A13 1412 1 035 47 110 1 084 2A12 1A11 1 036 48 109 1 083 2A11 1A10 1 037 49 108 1 082 2A10 1 9 1 038 50 107 1 081 2A9 1A8 1 039 51 106 1 080 2A8 TCK 52 105 TMS o3995989959902995890c00ECCLPPSELSDS59599959932958895292 Nc x 10 00
11. 1 1 142 18 79 182 1419 21601 pue Jojeoojv 21607 pue 21601 21601 2Xv9 54 99 1 1 42018 c 7 1 21607 pue 21601 pue 21601 21601 4 X Y9 54 79 142 1459 25 147 i 1479 ze L L Y p 5 iou p 91 2 91 18 2 18 2 5199 9 199 91 9 9r 61 0 91 0 49019 61 0 49019 ay 91 91 5199 T 18 2 30 18 2 9r 2 9 Jonuo p gt 1 1 144 1479 B 142 1419 E 91607 pue 91607 pue 21607 ONY 21601 LX v9 LXY9 1 1 1oeuuooJeju 42018 c c 1 91607 pue 91607 pue 21601 ANY 91607 LXv9 LXYv9 142 1 14 9 ze 142 14
12. pue 21601 91601 pue 21601 ONY 21601 21601 ONY 01607 ONY LXYv9 LXY9 LX v9 142 i 1479 ER 142 i 1479 ze 142 i 1479 ze 144 ld v9 i ze L Y 4 Y L Y 4 jojjeue 6 p m sijeocuoeyy joejeueo 4 h 9r 2 1 9r 2 1 9r 2 1 9r 2 30 18 2 30 18 2 80182 30192 Y 199 94 _ 5190 9L RN 199 9L _ 5190 9 9 9 9r 9 91 0 49018 91 0 5 49018 91 0 12019 91 0 49018 945 51 0 Sije20428y 2 49019 51 0 49018 ay 91 9 9 5199 5199 18 2 182 9 9 2 lonu0g p 1 1 id 1479 ey 144 1479 2 21601 21601 21601 21601 2Xv9 54 9 1 k 55 c Hi 3oeuuoo1eju 4201
13. x 10 I QOO 000 O AD 2552224282 2404 M5 256 Oram M5 256 lt lt lt lt lt lt lt lt e lt lt lt lt lt lt lt lt MBLV 256 555 8000 6 A A MBLV 256 20446G 023 Pin Designations CIK Clock Supply Voltage 3 D 15 GND Ground TDI TestData In I Input TCK Test Clock Macrocell 0 15 Input Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 3 MACH 5 Family 35 Lattice Semiconductor au u a a a Corporation 208 PIN PQFP WITH INTERNAL HEAT SPREADER CONNECTION DIAGRAM Top View 208 Pin PQFP 320 384 512 Macrocells M5 320 wreare var M5 320 PZN unan ZNT ongoa M5LV 320 SSSSSSSS 233333323 5555 999 929292929 8988885898 MBLV 320 MBLV 384 wosan MBLV 384 88880808 55555555 5555 90000000 S9999999 5 512 Sz9222985 Baas 5 512 MBLV
14. P TDI 1 1 0A2 0A2 0A2 o0 179 1 0139 5A2 4A2 2 3 178 0138 5A3 4 0 4 0A4 0 4 o2 4 4 177 1 0137 5A4 4A4 4 0 7 0 7 7 5 176 10136 5A7 4A7 7 0A8 0A8 0A8 104 6 175 10135 5A8 4A8 0 11 0 11 0 11 105 7 174 1 0134 5A11 4A11 3A11 0A12 0A12 0A12 vos 8 173 1 0133 12 4A12 12 0 13 1 0 13 7 9 172 0132 5A13 4A13 3A13 10 171 Voc GND 4 11 170 GND 0D15 0D15 0D15 vos 12 169 1 0131 5015 4015 3015 0014 0014 0014 09 13 168 1 0130 5014 4014 3014 0013 0013 0013 Co 14 167 1 0129 5013 4013 3013 0012 0012 0012 L 15 166 1 0128 5012 4012 3012 0011 0011 0011 012 16 165 0127 5011 4011 3011 0010 0010 0010 17 164 1 0126 5D10 4D10 3D10 009 009 009 1014 18 163 10125 509 409 309 008 008 008 1015 19 162 1 0124 508 408 308 GND 20 161 C GND 0D7 0D7 0D7 01 21 160 vo123 507 407 307 006 006 006 0017 Co 22 159 10122 5D6 4D6 306 005 005 005 vo18 23 158 00121 505 405 305 004 004 004 FOIS 24 157 0120 504 404 304 003 003 003 25 156 1 0119 503 403 303 002 002 002 0021 26 155 10118 502 402 302 001 001 001 1022 27 154 1 0117 501 401 301 000 000 000 1023 28 153 1 0116 500 400 300 29 152 I3 CLK3 30 151 GND GND L 31 150
15. 084 1 06 8 68 046 387 287 0 7 0B3 0B3 1 07 9 67 045 284 004 0B2 OB2 082 1 08 10 66 044 283 10 CLKO 11 65 043 382 282 002 Vcc 12 64 I3 CLK3 GND 18 63 GND GND 14 62 Vcc H CLK1 15 61 I2 CLK2 1B2 1B2 1B2 1 09 16 60 042 282 2 2 1C2 183 1B3 1B3 1010 17 59 1VO41 283 2c3 103 1B4 1B4 1B4 1011 18 58 040 284 2 4 1 4 187 187 1B7 1012 19 57 039 287 2C7 1C7 188 188 1B8 1 013 20 56 288 2 8 1C8 1811 1811 1811 1014 21 55 037 2811 2011 1014 1812 1812 1812 1015 22 54 036 2B12 2 12 1C12 1813 1813 1813 016 23 53 035 2813 2013 1C13 1 14 1412 1 12 1 017 24 52 O34 2412 2012 1014 TCK 25 51 TMS OQ Q LO sb s SE SB ob OL VLORARWOrAMAA 6699999999778 6299999999868 M5 256 9 lt 22991295 5 256 M5LV 256 Wil Sate EN ee M5LV 256 82 9 aaadda aa 5 192 lt lt lt lt lt 5 192 5 128 2 2222 5 M5 128 M5LV 128 monum ATUM MET M5LV 128 Package obsolete contact factory 20446G 017 Pin Designations CLK Clock Vcc Supply Voltage 3 D 15 GND Ground TDI Test Data In I nput TCK Test Clock Macrocell 0 15 YO Input
16. 4 2 gt gt I c v S 9 L 8 6 ZI eive QNO zye 282 282 az eve evr oge pge sae 68 2182 9182 2182 682 saz 98 082 99A eve 282 0182 198 0182 982 282 eve Live 29A erar 99A 99A eve eae eae erae 2 82 saz ege 99A eve 99A evi Stal OLAY SAL MOL yL 99 SS GND 5 9 s 5 uc E amp B 5 oar oo lenoe 105 oa ee es tao Jono eas sas 905 55255 8 x 900 0 200 48555524
17. owe 99A N 9v viv GND 9107 99A OLWL 91 StAL QNO 99A N N 210 22 99 olak in ext ln L sar gt a 4 107 o m o gt 1 amp oar ono 994 8 B 8 5 oat B 38 N oas eas 5 gt E ES E 994 N gt 2 S Dx 8 a JA vas sas c SB uuu i 700 zao 100 o S OQ Qu ZUGE T et 9as eas eas 900 2 g d a vias 99A DG 2100 1100 0400 tras eias eivs rvs dz vrao erao Stas 01 6 99A 1 0 SLVO SLOO D vi VS 99 OLWO ZLVO 190 21 6 evs evs vyo 6v0 QO a svs vvs ovs ovo svo svo ON lt v N LA Bottom View 1 0 Pin outs z135 Semiconductor 122222
18. ON 4901 ON MOL 990 990 790 99A 90 99A 290 9 090 99A 6SO 8S0 490 99A 9SO 99A SSO vSO 09 6 8 470 9 vO 1701 079 01 OvO 6EO 820 ZEO 9EO SEO vEO 220 Sc ON ON ON 020 620 820 2001 920 220 020 610 810 410 910 910 t LO I 10 Sc 9c ON ON ON ON 010 1 60 80 40 90 O H LO ON 9c dom UO ee Wood A BA m e o8 m MACH 5 Family 42 43 e I v 9 L 8 6 OT VL SI Li SI 6I 0 Ic 9 9c 6355 ON cIVE Sve OVE GND 98 Olde GND vide 0182 982 QNO 182 GND ON ON 55 EVE EWE 098 982 68 9182 682 cde OVE OVE GND ON QNO SAL SIVE LIVE BVE PVE IVE 198 786 882 2182 9182 clade 882 v
19. 1 SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3 3 V and 5 V Vcc MACH 5 devices are safe for mixed supply voltage system designs The 5 V devices will not overdrive 3 3 V devices above the output voltage of 3 3 V while they accept inputs from other 3 3 V devices The 3 3 V devices will accept inputs up to 5 5 V Both the 3 3 V and 5 V versions have the same high speed performance and provide easy to use mixed voltage design capability Note 1 Excludes original M5 128 M5 192 and M5 256 while M5 128 1 M3 192 1 and M5 256 1 are supported Please refer to Application Note titled Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices BUS FRIENDLY INPUTS AND 1 05 All MACH 5 devices have inputs and I Os which feature the Bus Friendly circuitry incorporating two inverters in series which loop back to the input This double inversion weakly holds the input at its last driven logic state While itis a good design practice to tie unused pins to a known state the Bus Friendly input structure pulls pins away from the input threshold voltage where noise can cause high frequency switching At power up the Bus Friendly latches are reset to a logic level 1 For the circuit diagram please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD ROM or Lattice web site POWER MANAGEMENT There are 4 power speed options in each MACH 5 PAL block Table 5 The speed and power trade
20. C7 Co Cy Cy Cs Cg C Cg Cry Cys Co 6 Cs Cs Cy Cy Co 15 Cy C5 Co Ciy Gs C3 Cy MACH 5 Family 5 Lattice EEEE Semiconductor uuum Corporation 54 Macrocells The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial registered or latched operation Figure 3 The D type flip flops can be configured as T type J K or S R operation through the use of the XOR gate associated with each macrocell Each PAL block has the capability to provide two input registers by using macrocells 0 and 15 In order to use this option these macrocells must be accessed via the I O pins associated with macrocells 3 and 12 respectively Once the macrocell is used as an input register it cannot be used for logic so its clusters can be re directed through the logic allocator to another macrocell The pins associated with macrocells 0 and 15 can still be used as input pins Although the I O pins for macrocells 3 and 12 are used to connect to the input registers these macrocells can still be used as buried macrocells to drive devic
21. x 08 0 GND GND LZLOA SLLO I GND 290 GND 6 59 ZZ LO I OZ LO I tooto LOLO I 68 28 690 1 290 95 ZZO 6 8210 99A leron Le 92 6 90 LO 1 00 6 88 18 EZO 890 90 1 99A 920 OBLONIZZEONIZ9LON 99A 99A fazion 99A ZLLO ISOLO 660 6 99A 4290 1 99A 99A lt 20 68 9 191 SNL MOL 2 SZLO I 09LO I FP LO I 9810 I 6 99A 994 220 20 6710 8610 L8LON ZZLONIZSLON Zr ZSO ZEON 9 onoz 98LO l Le LO 5 3 LS0 l broni 8 98 LO I SS LO I OT LOI E S 8 8 0 lt SEO onoo GND o a O S8 LO I LZLO IFSLO I 6 5 d 6 6 2 lozronlesronlsero S OO amp ERSZOHBBEBE 810 1 gt y ng n m wg m 810 6910 290 99A 9 e _ e e
22. Package obsolete contact factory Contact Factory for availability Device Marking Actual device marking differs from the ordering part number OPN All MACH devices are dual marked with both Commercial and Industrial grades The Industrial grade is EE slower i e M5IV 512 256 7AC 10AI Valid Combinations list configurations planned to be supported in volume for this device Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations Valid Combinations MACH 5 Family 45 Semiconductor Corporation 46 MACH 5 Family 3 3 V Ind Semiconductor Corporation 2 MACH 5 Family 3 3 V Ind 47
23. 8vcO LvcO 9vcO ON ON 0 20 6 20 8 20 26001 9620 SEZO 6220 8220 20001 9220 5660 ON ON ON SWL 22c0 220 0220 6120 8120 21201 9120 9120 e192 vicO 2120 2120 0120 6020 8020 40 0 9020 020 2020 2080 99A 1020 0020 99A 6610 99A 8610 2610 9610 99A 9610 v6LO 610 99A 2610 99A L6LO 0610 6810 8810 1 S e e Toe roe eee p oozosazsazassa cnc fy nc ofc prp fe oro rer 9 n at BeBe 85298 2 SEPRE ETRE gt y nm o 85855 FS PRR 810 1 9210 6910 1 E9LO I ZS 0S L O I EV LO I 95 S L LO I 20 c0 LO I S6O I ano 29 01198 LO I ano fenton 82 LO I ano n on 1010 1 ano E E A 880 1 180 1 E E E 080 1 E E vLO 60 1 210 99A 20446G 030
24. 91607 fei ANY 91607 0601 ANY 9501 54 9 v9 LX v9 LX v9 121 14994 1321 tae 1411 date 26 1421 14 HE 1499 26 1424 za L 1 4 1 4 4 opu owu 511900102 oup 4 p opu 4l iosu 10u09 2 10u00 2 101005 9r 2 10u00 9r 2 10u09 9i 2 142 142 h 30142 30192 30142 30142 gt oL 5160 5190 5 90 90 519501 9L 9 91 0 49018 9 0 49018 91 0 91 0 49018 91 0 49018 91 0 49018 1 1 1 1 n5 LOANNOOYSALNI 9 45 7 idc 1 0x10 91 0 49018 91 0 49018 91 0 91 0 49018 91 91 5189 gt 5190 519501 142 1 80 142 182 30192 1 9 2 9 2 z 2 10119090 109099 nuo siewen 4p nuo 1 1 1 144 1 14 144 14 26 142 1479
25. LXv9 2x99 54 ELX LXv9 ry ry 1 ry 1 1 5 ze amp ze ze ze 49019 H 92018 E Y Y Y Y Y Y pue 2607 pue 2 601 pue 91007 pue 3 601 pue 91007 pue 91607 ANY fei 21607 ANY fei 91607 ANY fei 21807 ANY ANY 2 x49 L x49 141 1 ze 4 1419 141 26 1421 1839 141 9 ze 4 2 L L L e iojeiouen p m sioen L tosu CEET 9 1 orug sileoiem L silssomew p 10 000 Sr z ouo En A nuog z 01u00 Si 2 Sr 2 Sr 142 30192 30192 30192 142 30192 gt 9 9i gt 51 0 91 0 12018 510 49019 51 0 49019 91 0 49019 91 0 49019 LOANNOOYSFILNI 945
26. 182 282 11 28 evz eve ogz vaz saz 682 2182 9182 918 218 68 sat 091 evi evi siaz 9 sve 982 0182 7191 0181 991 Swi 99A eraz eive eve 99A 99 egz 882 erar 99A 99A 99A evi oraz 91 SNL MOL OLYL 2142 2 LIVE Zaz viaz 99A iG 994 viat 0141 9 8 zaz saz saz 9az a 5 gat val E QNO Laz Sue BS ea oar bnon 106 v 582 o 0 eO O A rae sas 5 5 i 900 sao 5 o trae B QUO UD iS 1100 vao gt y wy n n n wg m a viae 994 9 994 00 c Z oo DIO 2 0 2190 2180 148 e
27. GND o lt 5 N E ME 0181 GND gt 8 6 5 8 m tq o m T a ouis Sa 3 E OGL 5 a pm m 8 gt E E oao GND 5 o 00228 a 5 SO m 20222 zao 2333 8 lt _ H IP m 2 H H Ii Ao 3 vido zao a c SAORA d gt BEBE 21 0 2100 GND o a LVO 0100 X sor e a mas a s ens 9 99 oo S 5 var 2189 eas sas iae ive svs evs 2180 rao 280 99A evo 6 9 8185 1186 0186 gas eas ovs eve ovs 0196 SIVS 1180 880 evo GND SE nes ano ee ves avo avo ms ws ono rns ereo ono one go 5 I v 9 L 8 6 OL ZI St OL 25 gt 555 20446G 028 lt DHMH 5 gt gt MACH 5 Family Package obsolete contact factory 40 Semiconductor Corporation 256 BALL BGA CONNECTION DIAGRAM M5 512 M5LV 512 Bottom View Macrocell Association 256 Ball BGA
28. Semiconductor Corporation 100 TQFP CONNECTION DIAGRAM 68 1 0 Top View 100 Pin TQFP 68 1 0 M5 128 Oo Ot Soe ESO HEU eic x hor eS M5 128 MBLV 128 55555555 88888888 MBLV 128 5 192 72272772 5 192 NN N N N NNN M5 256 5 256 MBLV 256 55555555 55555555 MBLV 256 58859958 2 2 2 2 2 556900000000 290000000098 8885989588588 959939 8 5590 ffe TDI 1 75 GND 0 14 12 12 100 2 74 TDO 0B13 0B13 0B13 01 3 73 VO51 12 2A12 0014 0812 0812 0812 1 02 4 72 O50 3B13 2813 0 13 0B11 OB11 0811 103 5 71 O49 3812 2B12 0012 OB8 1 04 6 70 048 3B11 2811 0B7 7 0B7 105 7 69 1047 288 0 8
29. Synchronous clock hold time Asynchronous clock hold time Synchronous clock to internal output Synchronous clock to output Asynchronous clock to internal output Asynchronous clock to output Latched Delays Latch setup time Latch hold time Transparent latch internal Propagation delay through transparent latch Gate to internal output Gate to output Input Register Delays nput register setup time using a synchronous clock nput register setup time using an asynchronous clock nput register hold time using a synchronous clock nput register hold time using an asynchronous clock put Latch Delays Input latch setup time Input latch hold time Transparent input latch Output Delays tg Output buffer delay tgw Slow slew rate delay tga Output enable time Output disable time MACH 5 Family 23 Semiconductor 122222 Corporation M5 LV TIMING PARAM ETERS OVER OPERATING RANGES CONTINUED Power Delays jj Power level 1 delay Note 2 12 Power level 2 delay Note 2 Power level 3 delay Note 2 Additional Cluster Delay PT Product term cluster delay Interconnect Delays pix Block interconnect delay Segment interconnect delay Reset and Preset Delays Asynchronous reset or
30. 91 0 49018 91 0 91 0 51 0 91 0 49018 91 0 49018 91 91 5189 160 5190 30142 30192 30192 80 182 30142 80 182 9t 2 91 9 2 91 91 2 9r 2 10219090 10 e10U99 jonuoo gt jonuoo Jonuoo 245 1 m 1 1 141 1479 2 142 1 14 1 144 1479 142 1459 144 1499 141 1 v9 Jojeoo y 91607 pue 91607 pue 91607 pue Jojeoo v 91607 pue 91607 pue JOjeoo v 21601 keny 91607 ONY 91507 21607 2601 2601 2 601 ELX v9 eX v9 L X v9 ELX v9 L X v9 1 1 1 1 1 1 ze ze ze ze 109uuooieju 32019 H 10911001910 49018 1090000791 49018 ze E Y Y Y Y Y Y 21607 pue 91607 pue 21601 pue 91609 pue pue 91609 pue 91607
31. 99 10400 f 5 1 1 gt 194 1499 142 1499 144 14 142 1499 91607 pue 21607 pue 21607 pue 91607 pue 21601 ONY 91607 21601 91607 gLX v9 L X49 1 1 1 1 gt ze ze ze ze H 1oeuuoaielul 2018 1 E 9 ze e Y Y Y Y 31607 pue Jojeoo 21601 pue 91607 pue 21601 pue Aeuy 01607 91607 ONY 91607 91607 ONY X 99 X 49 L X v9 X v9 uzg 19 192 129 ze 141 199 ze 182 1496 2 4 4 4 10 7 19208 1 2 1 2 1 91 2 1 OL 2 5 30192 30 192 JO ldz Y Y Y 5 5199 9i 5190 91 9 o c s E 5 e 91 91 91 91 D t 9 91 0 49018 61 0 49019 91 0 49018 91 0 49019 0 9 5 0 IN3IND3S MACH 5 Family 16 du
32. L LS 2 22 LEO 9LO I 810 1 9L0 1 08LO OGL 28 0 99 LO I 99A 99A fezeron 99A 860 260 980 6204 99A 990 99A LOM L8LO I S9 ron 99A 9610 0610 6210 8110 0110 010 6 160 220 590 090 99A LO I ez L LO 160LO I to 9 8 220 11 BSO 820 ZLO 10 210 GND 9110 80 0 GND GND 9 0 86 GND I v S 9 7 8 6 St 9 20446G 026 lt 2 gt gt Package obsolete contact factory MACH 5 Family 38 Semiconductor Corporation 256 BALL BGA CONNECTION DIAGRAM M5 320 M5LV 320 Bottom View Macrocell Association 256 Ball BGA lt HO DTHMH gt 2 gt Ss gt I c v S 9 L 8 6 OL St Of x
33. 142 1379 1 2 10jeoo 91607 91607 pue 91609 pue pue keny 91607 91607 ANY 9501 keny 9501 LX v9 LX v9 L X v9 X v9 1 1 1 1 M amp H 10 uu00124U1 32019 15euuoo1a u 39019 0 ze ze e Y 1 1 Y pue 91607 pue pue 91609 pue 91607 Keay 91607 ANY Keny 91607 keny 91607 X v9 LX v9 LX v9 LX v9 142 1 1419 142 14 9 ze 142 i 18 79 ze 142 1 1479 ze L Y L Y L Y L Y sie omew 1 74 gt p piou 9 jonuoo jonuoo 2 jonuoo 2 30192 30142 30192 182 m SIRO 9 5190 9 519501 9L 91 91 0 49018 91 0 49018 91 0 49018 91 0 49018 935 0 LN3IND3S MACH 5 Family e S 5 es of 55 0 H BLOCK DIAGRAM M5 LV 384 XXX IN3W93S LN3IN93S 1 9
34. and Igzg C Not more than one output should be shorted time Duration of the short circuit should not exceed one second MACH 5 Family 21 Semiconductor 122222 Corporation ABSOLUTE MAXIMUM RATINGS M5LV Storage Temperature 65 C to 150 C Device Junction Temperature 130 C Supply Voltage with Respect to Ground 0 5 V to 4 5 V DC Input Voltage 0 5 V to 5 5 V Static Discharge Voltage 2000 V Latchup Current 40 C to 85 C 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure Functionality at or above these limits is not implied Exposure to Absolute Maximum Ratings for extended periods may affect device reliability OPERATING RANGES Commercial C Devices Ambient Temperature TA Operating in Free Supply Voltage with Respect to Ground Industrial I Devices Ambient Temperature T4 Operating in Free 40 to 85 C Supply Voltage Vcc with Respect to Ground 43 0 V to 43 6 V Operating ranges define those limits between which the functionality of the device is guaranteed 3 3 V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Von Output HIGH Voltage VoL Output LOW Voltage Voc Min Vin Vigor Vi Input HIGH Voltage Test Description Vour
35. 009 vo14 18 139 E d1 votos 509 409 008 008 008 vois 19 138 2 0104 508 408 GND 20 137 2 GND 0D7 007 007 voie 21 136 E 0103 507 407 307 004 004 004 17 22 135 E d 0102 404 304 003 003 003 018 23 134 0101 403 303 002 002 002 1019 24 133 0100 502 402 302 25 132 26 131 2 GND 27 130 28 129 102 102 102 29 128 voee 402 302 202 103 103 103 127 EL 098 403 303 203 1 4 1D4 1022 31 126 097 404 304 204 107 107 107 32 125 2 10 307 207 GND 124 GND 108 108 108 024 34 123 2 1095 408 308 208 109 109 109 1025 35 122 E 094 409 309 209 1010 1010 1010 026 36 121 E 093 4010 3010 2010 1011 1011 1011 027 37 120 E 4011 3011 2011 1012 1012 1012 1028 38 119 091 4012 3012 2012 1013 1013 1013 1029 118 E 090 4013 3013 2013 1014 1014 1014 40 117 EL 089 4014 3014 2014 1015 1015 1015 vost 41 116 4015 3015 2015 42 115 43 114 E 1A15 1A13 1 13 032 4 113 1 087 4 13
36. 0014 0812 0812 02 4 72 053 3813 0 13 0811 0B11 O3 5 71 052 3 12 0 12 088 088 6 70 051 3811 0 11 0B7 087 O5 7 69 O50 388 084 084 O6 8 68 049 387 0 7 0B3 O7 9 67 048 384 0 4 0B2 O8 10 66 047 383 I0 CLKO 11 65 046 3B2 0 2 Voc 12 64 I3 CLK3 GND 13 63 GND GND 14 62 Voc H CLK1 15 61 I2 CLK2 1B2 1B2 09 16 60 045 282 1C2 183 1B3 1010 17 59 1 044 283 1 3 184 1B4 011 18 58 43 284 1C4 187 1B7 1012 19 57 042 287 1C7 1B8 1 8 1 013 20 56 041 288 1 8 1B11 1811 1014 21 55 040 2811 1211 1812 1812 1015 22 54 039 2812 1212 1813 1813 1016 23 53 1038 2B13 1213 1 14 1412 1017 24 52 037 2 12 1014 TCK 25 51 TMS OQ X xt 10 st 10 CO SE SE SE SE SE SE SE O00 st 10 st LO Z X OQ OQ OQ OQ 2 00104 7 6959889959999766799999555658 M5LV 256 9 9 5 256 64 A M5LV 12 ONT eee Sees ABA DS M5LV 12 22125515555 88909885555 ER 20446G 018 Pin Designations CIK Clock Vcc Supply Voltage 3 D 15 GND Ground TDI Test Data In I Input TCK Test Clock Macrocell 0 15 I
37. MULTIPLE I O AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of I O options This allows designers to choose a device close to their logic density and I O requirements thus minimizing costs For the same package type every density has the same pin out With proper design considerations a design can be moved to a higher or lower density part as required IEEE 1149 1 COMPLIANT BOUNDARY SCAN TESTABILITY Most MACH 5 devices have boundary scan registers and are compliant to the IEFE 1149 1 standard This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes Internal registers are linked internally allowing test data to be shifted in and loaded directly onto test nodes or test node data to be captured and shifted out for verification In addition these devices can be linked into a board level serial scan path for more complete board level testing IEEE 1149 1 COMPLIANT IN SYSTEM PROGRAMMING Programming devices in system provides a number of significant benefits including rapid prototyping lower inventory levels higher quality and the ability to make in field modifications All MACH 5 devices provide in system programming ISP capability through their IEEE 1149 1 compliant Boundary Scan Test Access Port By using the IEEE 1149 1 compliant Boundary Scan Test Access Port as the communication interface through which I
38. t 10 00 t 10 Oo MEME ME Mb Wb 10 10 0 0 0000 LO KO KO CO CO CO 0 POP 00 8882995999 824 9919 920 82 3 22205 828 885 88588 82 5 gt 999909090996 gt 0990909099 gt 665 gt 9999909 gt 699099909099 gt 6 5 512 5 512 MBLV 512 GA e eoo 9999955 lt lt MBLV 512 M5 384 CLI2I2 cc 85dm8 M5 384 MS5LV 384 1m om o MBLV 384 Z22Q122xz 28558 2 952 M5 320 55555555 i QA 5 320 5 320 y SUR MBLV 320 Package obsolete contact factory 20446G 022 Pin Designations CIK Clock Supply Voltage 7 D 15 GND Ground TDI Test Data In I Input TCK Test Clock Macrocell 0 15 Input Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 7 34 MACH 5 Family Lattice Semiconductor Corporation 208 PIN PQFP CONNECTION DIAGRAM Top View 208 Pin PQFP 192 256 acrocells
39. y Y 1 1018201 21607 pue 21601 pue 1018201 21601 pue 40jeooJ v 21601 pue 21601 21601 21601 21607 ELX v9 54 79 EL X v9 2Xv9 142 i ld v9 ze 147 1 1479 ze 142 1479 ze 144 1479 ze L Y 4 Y 4 Y 4 Y Joyesauay D p 749 1 9r 2 1 91 2 1 91 2 91 2 30 18 2 30192 30192 JO ldz 5199 9 199 91 5199 9L 199 9L 91 91 9 91 0 5 49018 91 0 49018 91 0 52018 91 0 49018 204466 013 i I I93NNOOHHBLNI Semiconductor Corporation Lattice BLOCK DIAGRAM M5 LV 512 XXX 91 0 49019 51 0 49019 91 0 49019 9 9 9 9 199 30192 30192 91 2 91 Joyesausy
40. 10 10 CO CO OQ 2 61 9 gt 69 0 OFF ONTIYYYFYYITITTHN oz 6799999990 0550557 670959952 599599078 lt QI xt QN CN CO CO x 10 M5 256 SSSSEEE 559999 M5 256 MSLV 256 xx E M5LV 256 9 228925 2388885 Br 88 B8825882r M5 192 LIENERT 000wq AL 3 5 192 5 128 429958 8582 272 M5 128 lt lt lt 6668 128 Package obsolete contact factory 20446G 019 Pin Designations CIK Clock Supply Voltage 3 D 15 GND Ground TDI Test Data In I nput TCK Test Clock Macrocell 0 15 Input Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 3 MACH 5 Family 31 Lattice Semiconductor Corporation 144 PIN TQFP CONNECTION DIAGRAM Top View 144 Pin TQFP MBLV 128 orozr27 MBLV 128 lt lt lt lt lt lt lt lt lt lt lt lt gt MSLV 256 etnors M5LV 256 lt lt lt lt lt lt
41. 1C2 183 1B3 183 1 010 20 61 041 283 2 3 1C3 184 1B4 1B4 1011 21 60 040 284 2C4 184 187 1B7 187 1012 22 59 039 287 2C7 1C7 1B8 1B8 1B8 1 013 23 58 038 288 2 8 1C8 1B11 1B11 1B11 014 24 57 V037 2811 2211 1812 1812 1812 1015 25 56 V036 2812 2212 1212 1813 1813 1813 016 26 55 O35 2 13 2213 1213 1A14 1412 1412 017 27 54 O34 2 12 2012 1014 TCK 28 53 TMS GND 29 52 GND GND 30 51 GND xt LO 00 lt 10 CO CO sb SE SE SE SE SE SE SB 00 ON gt 90990090900 gt 66 gt 099909099009 M5 256 M5 256 MBLV 256 885858834 MBLV 256 5 192 72272773 88888888 5 192 Wet eot qim e NNN CV CN st 00 5 128 lt lt lt lt lt gt 5 128 MSLV 128 piu bi crema 51 128 Package obsolete contact factory 20446G 016 Pin Designations CIK Clock Supply Voltage 3 D 15 GND Ground TDI Test Data In I nput TCK Test Clock Macrocell 0 15 Input Output TMS Test Mode Select PAL Block A D nn TD Test D NC No Connect O est Data Out Segment 0 3 28 MACH 5 Family Lattice
42. 2 Min or Vour lt Note 2 100 log 3 2 100 pA Io 16 mA Note 1 0 2 2 4 gt BO Input LOW Voltage Vour 2 Min or Vour lt Vo Max Note 2 Vin 3 6 Voc emm tolo Ex E Note 3 Im Input HIGH Leakage Current Input LOW Leakage Current lozg Off State Output Leakage Current HIGH Vin 0 Voc Max Note 3 Vour 3 6 Voc i Max Vin or Vi Note 3 Off State Output Leakage Current LOW Notes 1 Total between ground pins should not exceed 64 mA 2 3 4 Vour 0 Voc Max Vin or Note 3 Isc Output Short Circuit Current Vour 0 5 Voc Max Viy Vigor Note 4 EE gt These are absolute values with respect to device ground and all overshoots due to system and or tester noise are included pin leakage is the worst case of I and 10 or and Igzg Not more than one output should be shorted at one time Duration of the short circuit should not exceed one second 22 MACH 5 Family Semiconductor Corporation M5 LV TIMING PARAM ETERS OVER OPERATING RANGES Combinatorial Delay Internal combinatorial propagation toni delay tpp Combinatorial propagation delay Registered Delays Synchronous clock setup time Asynchronous clock setup time
43. 30192 18 2 30 18 2 30142 1 91 2 91 2 9 2 91 Jojejeueo Jojejeueo Jojejeueo lonuog sijeooioew sljeoojoew 1 1 1 1d 1479 E du 1499 144 1499 141 14 91607 pue Aojeoo y 21601 pue 21601 pue 21001 pue Keay 21601 21601 ANY keny 91601 91607 ANY LXYv9 4 9 ELX v9 64 9 1 1 1 1 7 e 26 26 26 26 2 49014 EE Hi 0 55 55 1 1 1 21601 pue Jojeoojlv 21601 91607 pue Jojeoojlv 91607 pue 21601 21601 91607 91607 LXv9 LX v9 LXv9 79 144 i ld 79 ze 14 4 ld v9 ze 147 i 1459 ze 147 i 25 2 Y L Y 4 Y Jojejeuet 9 002 9 2 10 9r 2 101009 2 30 18 2 30 18 2 30 18 2 Y 30 18 2 91 9L 5190 9L 9L 91 9 91 91 91 0 91 0 91 0 52018 51 0 49019 20446G 008 eo 0019 15 MACH 5 Family LN3IN93S LNAINDAS 20446G 009
44. 3A13 2415 1 14 1 12 1A12 45 112 E 086 4ai2 3A12 2A14 1 13 1011 46 111 EL 1085 4 11 3A11 2A13 1 12 1A8 1A8 1035 47 110 4A8 2412 1 11 1 7 147 48 109 1 083 4A7 1A10 1A4 144 7 49 4 2 10 1 143 50 107 vosi 4A3 2 9 1A2 1A2 51 106 080 4A2 2 2 8 1 52 105 Ts cx oroooc aoxoortooo aosoorooo odozoorooo qdozoorooS59988 Q50959090090399509 E EREREEREERREREOLODSLSS5S95599025090887c 7 7 29499i9 950099 0509550090550 800585880288 5 SORKRRLKLRG 656859565585 gt 595988888565568856 gt 755 gt 78895585585555 gt 5555555555 5 512 ONONE SraAMTHOR ROHTMAKTS 5 512 MBLV 512 hoa DOORS 96860809090 555555155 MBLV 512 aaa aaa 89 555 i 2398 885 M5 384 lt lt lt lt lt ANNAN 2228598989 5 384 MBLV 384 222 NNN MBLV 384 5 320 z22123z 2 BESS 55334355 5 320 M5LV 320 PARA Ona Seb A A MBLV 320 20446G 024 Pin Designations CLK Clock Supply Voltage 7 D 15 GND I Tes
45. 91 0 20I8 4 IN3AN93S 0 IN3AN93S 20446G 012 19 MACH 5 Family LN3IN53S 51 0 12018 LN3IN93S 91 0 91 0 91 0 x oig 194 9 9 9 Iy 5199 199 5199 30 18 2 30 18 30192 14 2 91 9L 2 91 91 Jojeeue 2101219099 1 99 Jonu00 lonuog 1 1 1 1 144 1 1479 144 14 144 1d 9 144 149 B 21801 pue Jojeoo lv 21601 pue 10jeoojy 21601 pue Jojeoojlv 21601 pue 91801 21601 ANY 91607 21601 ANY 54 79 54 X 79 54 79 54 X 79 ry 1 1 1 2 ge c 55 c H 3oeuuoo1eju 401g H 32019 c ze ze E
46. Corporation BLOCK DIAGRAM M5 LV 512 XXX Continued c LN3IN93S L LN3IN93S 51 0 5 49018 51 0 5 42018 91 0 49019 91 0 2018 9 91 9 9 91 91 91 91 5199 5199 5199 30 18 30142 30 19 30 18 2 9 2 91 2 9r 2 9 2 Jojjeueo 101210099 1011999 jonuog jonuog 1 74 1 1 192 1d v9 9s 142 1479 144 1419 141 14 9 2 Jojeoo y 21601 pue 21601 pue Jojeoojy 21601 pue Jojeoojy 21601 pue 91501 21601 21601 91607 LXY9 51 9 L X v9 ELX 9 1 1 1 1 I al 26 c 3oeuuoo1eju 42018 Hi 12018 c c ze e 1 1 Y Y Joje2o 21607 pue
47. GND 10 111 7 GND 088 0 11 0B13 11 110 1 083 3813 2811 0C8 0B7 0812 09 12 109 d4 082 3812 288 0C7 0B6 085 0B11 4 13 108 1 081 3811 285 006 085 0B4 0B8 11 14 107 1 080 3B8 284 0605 084 083 085 7012 15 106 1079 385 283 004 0B3 0B2 084 7013 16 105 1 078 384 282 0C3 0B2 0B1 0B3 014 4 104 1 077 3B3 2B1 0c2 0 1 082 15 4 18 103 L 4 1 076 382 280 0C1 I0 CLKO 19 102 L 4 L 4 20 101 GND GND 21 100 E Voc 22 99 I2 CLK2 1B1 1 0 1 2 016 23 98 7 1 075 2 2 2C0 1C1 1B2 1B1 1B3 017 24 97 L 4 1 074 2B3 2C1 1C2 183 182 184 018 25 96 1 073 284 2C2 163 1 4 1B3 1B5 019 26 95 1 072 2 5 2C3 1C4 1B5 1B4 1B8 020 27 94 071 288 2C4 105 1B6 1B5 1B11 02 28 93 1 070 2B11 2C5 1 6 187 188 1812 22 29 92 5 1069 2812 2C8 1C7 1B8 1B11 1B13 023 30 91 1 068 2813 2C11 1C8 GND 31 90 7 GND 1B9 1B12 1A15 024 32 89 7 1 067 2415 2012 1C9 1B10 1B13 1A14 25 33 88 1 066 2A14 2C13 1010 1B11 1B14 1A13 26 4 34 87 065 2A13 2C14 1C11 1B12 1B15 1A12 027 35 86 1 064 2A12 2C15 1C12 1B13 1A15 1A11 028 36 85 1 063 2 11 2015 1C13 1 14 1 14 1A10 029 37 84 1 062 2A10 2014 1C14 1A15 1A13 1A9 030 38 83 1 061 2A9 2D13 1D15 1A14 1A12 1A8 1031 3
48. Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 3 MACH 5 Family 29 100 TQFP CONNECTION DIAGRAM 74 1 0 Lattice Semiconductor Corporation 100 Pin 74 1 0 MBLV 128 SSE 2 MBLV 128 lt lt lt lt lt lt lt M5LV 256 MSLV 256 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt CO ORRERSSS3 S9200009909555050 5999999999925629999999996 888560505550986885905 TDI 1 75 GND 14 OA12 O0 2 74 TDO 0813 0813 O1 3 73 054 12
49. Voc M CLK1 32 149 4 I2 CLK2 100 100 100 24 33 148 0115 400 300 200 101 101 101 025 34 147 1 0114 401 301 201 102 102 102 1026 35 146 C 1 0113 402 302 202 103 103 103 0027 36 145 1 0112 403 303 203 104 104 104 1028 37 144 10111 404 304 204 105 105 105 1029 38 143 1 0110 405 305 205 106 106 106 39 142 1 0109 406 306 206 107 107 107 031 40 141 10108 407 307 207 GND L 41 140 GND 1D8 1D8 1D8 032 42 139 110107 408 308 208 109 109 109 1033 43 138 0106 409 309 209 1010 1010 1010 1034 44 137 10105 4010 3010 2010 1011 1011 1011 1035 45 136 1 0104 4011 3011 2011 1012 1012 1012 036 46 135 10103 4012 3012 2012 1013 1013 1013 037 47 134 1 0102 4013 3013 2013 1014 1014 1014 038 48 133 0101 4014 3014 2014 1015 1015 1015 1039 49 132 1 0100 4015 3015 2015 GND 50 131 GND 51 130 2 1 15 1 13 1A13 1040 52 129 voe9 4A13 13 2 15 1 14 1 12 1 12 041 53 128 098 4A12 12 2A14 1A13 1A11 1A11 104 54 127 1 097 4 11 11 2 13 1A12 1A8 1A8 1043 55 126 1096 4A8 2A12 1A11 1A7 1A7 1044 56 125 1095 4 7 7 2A11 1A10 1A4 1A4 1045 57 124 094 4A4 4 2 10 1 9 1A3 1A3 1046 58 123 1 093 4A3 2A9 1A8 1A2 1A2 1047 4 122 1092 4A2 2 2 8 60 121 TMS
50. i _ 5 CPLD Family 222233 Semiconductor Fifth Generation MACH Architecture au u u a a Corporation FEATURES High logic densities and I Os for increased logic integration 128 to 512 macrocell densities 68 to 256 I Os Wide selection of density and I O combinations to support most application needs 6 macrocell density options 71 0 options Up to 41 0 options per macrocell density Up to 5 density amp options for each package Performance features to fit system needs 5 5 ns tpp Commercial 7 5 ns tpp Industrial 182 MHz font Four programmable power speed settings per block Flexible architecture facilitates logic design Multiple levels of switch matrices allow for performance based routing 100 routability and pin out retention Synchronous and asynchronous clocking including dual edge clocking Asynchronous product or sum term set or reset 16 to 64 output enables Functions of up to 32 product terms Advanced capabilities for easy system integration 3 3 V amp 5 JEDEC compliant operations EEE 1149 1 compliant for boundary scan testing 3 3 V amp 5 V in system programmable via IEEE 1149 1 Boundary Scan Test Access Port PCI compliant 5 6 7 10 12 speed grades Safe for mixed supply voltage system design Bus Friendly Inputs amp I Os Individual output slew rate control Hot socketing Programmable security
51. lt 0 0 lt lt lt lt lt lt lt 28 2 822 8 2 82 55955096029909969522 2009099299909999 35 XO LO t CO 10 69 090 6069 Go Eo Kc n Ea 1 108 TDO 0A14 0A8 0 2 107 1 077 3A8 0014 0813 9 01 4 3 106 1 076 3A9 0013 0812 0 10 2 4 4 105 L 3 1 075 10 0C12 0 11 0 11 5 104 1 074 11 0 11 0 10 0 12 4 6 103 1 073 12 0C10 GND 7 102 GND 0 8 0813 5 8 101 1 072 3B13 0C8 0B7 0B12 6 9 100 071 3B12 0C7 0 6 0 11 VO7 10 99 1 070 3B11 0C6 085 088 8 14 98 1 069 3B8 0C5 GND 12 97 GND 084 085 VOS 18 96 L a3 1 068 385 0C4 083 084 10 C 14 95 7 1067 384 0C3 082 083 O11 15 94 L a3 066 3B3 0C2 081 082 1012 4 16 93 65 3B2 0C1 I0 CLKO 17 92 L 4 13 CLK3 18 91 GND GND 19 90 M CLK1 20 89 I2 CLK2 1B1 1B2 O13 21 88 64 282 101 182 183 O14 4 22 87 1 063 283 102 1B3 1B4 O15 23 86 2 1 062 2B4 103 1B4 1B5 O16 24 85 1 1 061 2B5 104 G
52. preset to internal register output Asynchronous reset or preset to register output Reset and set register recovery time Asynchronous reset or preset width Clock Enable Delays Clock enable setup time Clock enable hold time Global clock width low Note 3 Global clock width high Note 3 Product term clock width low Product term clock width high Gate width low for low transparent or high for high transparent Input register clock width low or high 24 MACH 5 Family Semiconductor Corporation M5 LV TIMING PARAM ETERS OVER OPERATING RANGES CONTINUED External feedback PAL block level Min Internal feedback PAL block level Min of twas or No feedback PAL block level Min of tus t or 106 External feedback PAL block level Min of 1 twra or tooa Internal feedback PAL block level Min of t or No feedback PAL block level Min of 1 twa or 1 Maximum input register frequency 1 or 1 2 X tow Notes 1 See MACH Switching Test Circuits documentation on the Lattice Data Book CD ROM or Lattice web site 2 Numbers in parentheses are for M5 128 M5 192 M5 256
53. reset then that macrocell will RESET on power up To guarantee MACH 5 Family 11 Lattice Semiconductor Corporation initialization values the rise must be monotonic and the clock must be inactive until the reset delay time has elapsed SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns Once programmed this bit defeats readback of the programmed pattern by a device programmer securing proprietary designs from competitors Programming and verification are also defeated by the security bit The bit can only be reset by erasing the entire device 12 MACH 5 Family Semiconductor Corporation MACH 5 PAL BLOCK 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 Output Enable Output Enable UU Macro vo a d Macro Macro 1 cell Macro cell vo Le 4 o Macro cell n Switch Matrix Logic Allocator
54. 1 M5 xxx is for 5 V devices M5LV xxx is 3 3 V devices 2 Preliminary specifications for new 6 515 speed grade 7 5ns speed grade in production now GENERAL DESCRIPTION The MACH 5 family consists of a broad range of high density and high I O Complex Programmable Logic Devices CPLDs The fifth generation MACH architecture yields fast speeds at high CPLD densities low power and supports additional features such as in system programmability Boundary Scan testability and advanced clocking options Table 1 The MACH 5 family offers 5 V M5 xxx and 3 3 V operation Manufactured in state of the art ISO 9000 qualified fabrication facilities on E CMOS process technologies MACH 5 devices are available with pin to pin delays as fast as 5 5 ns Table 2 The 5 9 6 5 7 5 10 and 12 ns devices are compliant with the PCI Local Bus Specification 2 MACH 5 Family Semiconductor Corporation Table 2 MACH 5 Speed Grades Speed Grade Note 1 Commercial grade 1 Industrial grade 2 11 version recommended for new designs 3 Preliminary specificatons With Lattice s unique hierarchical architecture the MACH 5 family provides densities up to 512 macrocells to support full system logic integration Extensive routing resources ensure pinout retention as well as high utilization It is ideal for PAL block device integ
55. 10 99 1070 3B11 2B5 0 6 085 084 0B8 O8 C 3 11 98 1 069 3B8 2B4 0 5 GND L 4 12 97 GND 084 OB3 0B5 O9 13 96 1 1068 5 2B3 0 4 0B2 084 O10 14 95 1067 384 282 0C3 0B2 0 1 0B3 O11 15 94 1 066 383 281 0C2 0 1 0 0 0B2 O12 4 16 93 2 1065 3B2 280 0C1 I0 CLKO 17 92 cc 18 91 GND GND 19 90 M CLK1 20 89 2 I2 CLK2 1B1 1B0 1B2 O18 21 88 1 064 2B2 2C0 1C1 1B2 1B1 1B3 O14 22 87 1 063 283 201 1C2 1B3 1B2 184 O15 23 86 1 062 284 2C2 1C3 1B4 1B3 1B5 O16 24 85 1 061 285 2C3 104 GND 25 84 GND 1B5 1B4 1B8 O17 L 26 83 1 060 2B8 204 105 1B6 1B5 1B11 O18 L 3 27 82 1 059 2B11 2C5 106 187 188 1812 19 28 81 1 058 2812 2C8 1 7 1B8 1B11 1B13 O20 29 80 1 057 2813 2211 1C8 GND 30 79 1 GND 1810 1812 1A12 O21 L 3 31 78 2 056 2 12 2012 1010 1B11 1B13 1A11 22 32 77 W055 2A11 2013 1C11 1812 1A14 1A10 23 33 76 m 1 054 2A10 2D14 1C12 1813 1413 1A9 24 34 75 1 053 2A9 2D13 1C13 1A14 1412 1A8 25 35 74 1 052 2A8 2D12 1D14 36 73 TMS CO xr LO CO CO CO xb xr xb wb xb xb 10 10 10 10 10 0 10
56. 199 2 142 1819 21601 pue 21601 pue 21601 pue 21501 pue 2 601 ANY 21607 ONY 21601 ONY 21601 ONY v9 L X v9 L X v9 v9 1 1 1 1 26 ze 19euuo2Je1u 12018 19euuooJeju 32019 H ze ze ze ze we Y Y Y Y 21601 916507 pue 21601 pue 21601 91607 ONY 31607 ANY 91607 ANY 91607 ANY ELX v9 ELX v9 ELX v9 L X v9 1421 1491 1324 1979 25 1421 1479 ze 142 2439 25 2 2 2 aoup oup 2 D sijeo ojoew p 91990196 1 91 2 9 9r 2 91 2 30 142 30 142 142 301d2 5120 9 91 91 5120 91 91 91 91 61 0 91 0 xolg 61 0 49019 91 0 49018 1 ono LOIOANNOOYSALNI LN3N 93S lt Be 1 gt 1 0 42018 91 0 49019 61 0 4901g 91 0 2018 91 91 94 91 91 91 91 12 5190 5190 5100 1 30142 80 182 1 30142 1 30192 1 9 2 2 91 2 Jojejeuap
57. 3 Ifa signal is used as both a clock and a logic array input then the maximum input frequency applies 2 MACH 5 Family 25 Lattice Semiconductor Corporation CAPACITANCE pin 3 3 Vor 5 V 25 C 1 MHz T O pin 3 3 Vor 5 V 25 C 1 MHz 1 These parameters are not 100 tested but are calculated initial characterization and atany time the design is modified where these parameters may be affected Icc 5 FREQUENCY These curves represent the typical power consumption for a particular device at system frequency The selected typical pattern is a 16 bit up down counter This pattern fills the device and exercises every macrocell Maximum frequency shown uses internal feedback and a D type register Power Speed are optimized to obtain the highest counter frequency and the lowest power The highest frequency LSBs is placed in common PAL blocks which are set to high power The lowest frequency signals MSBs are placed in a common PAL block and set to lowest power For a more detailed discussion about MACH 5 power consumption refer to the application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book CD ROM or Lattice web site Icc CURVES AT HIGH LOW POWER MODES Vcc 25V or 3 3 V Ta 25 700 M5 LV 512 high power 600 M5 LV 384 high power 500 Z M5 LV 320 high power 5 256 1 and 400 M5LV 25 high pow
58. 5 078 504 404 304 003 1014 17 104 077 503 403 303 002 002 002 1015 18 103 076 502 402 302 lo CLKO 19 102 I3 CLK3 20 101 GND GND 21 100 Vcc M CLK1 4 22 99 I2 CLK2 102 102 1D2 016 23 98 075 402 302 202 103 1D3 103 1017 24 97 074 403 303 203 104 104 1D4 1018 25 96 E gt 073 404 304 204 107 107 107 1019 26 95 E gt 072 407 307 207 108 108 108 1020 27 94 2 1071 408 308 208 1011 1011 1011 021 28 93 4011 2011 1012 1012 1012 1022 29 92 069 4012 3012 2D12 1013 1013 1013 1023 91 068 4013 3013 2013 GND 31 90 GND 1 15 1A13 1A13 024 32 89 067 4413 3A13 2A15 14 1 12 1 12 1025 33 88 66 4 12 12 2A14 13 1A11 1 11 1026 34 87 VO65 4 11 2A13 1 12 1 8 1A8 0027 35 86 064 448 2 12 1 11 1A7 1 7 0028 36 85 063 447 7 2 11 4 1 4 1029 37 84 1062 444 4 2 10 1 9 1A3 1 030 38 83 1 061 2 9 1A2 1 2 1031 39 82 oso 442 3A2 2 8 40 81 7 TMS CO t LO KO xt LO CO Q CO
59. 512 EKERERRER RERRERRRR 888 88585888 555555855 MBLV 512 2959935998 z9995993 Oe eee 09090 ot eer Oe eee eens 999999995 2999999995099090 256 29999 99999999 050005650006 OSS85 288588985993299599959929959R REeEERRERSSDOSSO00oSODSS5 eoe eee ge e e eire ue sue ge ea poesie e e e 10 0 2 2 0 2 voo 2 155 0119 2 4A2 voi 154 7 00118 4 4 4 4 102 4 153 017 4 4 4 OA7 vos 5 152 00116 5A7 4A7 104 6 151 E d vots 4 8 0 11 0 11 OA11 vos 7 150 114 5 11 4 11 0A12 12 0 12 vos 8 149 5A12 4A12 3A12 0A13 0A13 0A13 vo7 9 148 0112 5A13 4413 3A13 10 147 C Voc GND 11 146 GND 0015 0015 0015 vos 12 145 7 0111 5015 4015 3015 0014 0014 0014 vos 13 144 00110 5014 4014 3014 0D13 0013 0013 voio 14 143 0109 5013 4013 3013 0D12 0012 0012 voit E 15 142 votos 5012 4012 3012 0011 0011 0011 012 16 141 00107 5011 4011 3011 0010 0010 0010 013 L 17 140 votos 5010 4010 3010 009
60. 5586588 999990999 MSLV 384 5 512 M5 512 MBLV 512 RRRRRR 885888 885585852 MSLV 512 00 CO QN gr REP PEE ES OF EEE Ee 0009022727227 0089892288 6 2990990900996 20909009 566 20000900 2699090909099 95 KO LO t XO LO 4 LO t QI 10 E OS8859555828050999 9 3992 895595989588 AS NN TDI 1 120 5 TDO 0 2 0 2 2 voo 2 119 091 2 4A2 2 3 118 4A3 4 OA4 0 4 102 4 117 089 5 4 4A4 7 OA7 7 5 116 088 5A7 4 7 7 OA8 6 115 087 548 4 8 0 11 11 OA11 7 114 ose 5 11 4 3A11 0 12 0A12 0 12 vos m 8 113 5 085 12 4 12 3A12 0A13 0A13 13 7 9 112 1084 5A13 4A13 3A13 GND 10 111 GND 0D13 0D13 0D13 vos 11 110 1083 5013 4013 3013 0012 0D12 0012 09 12 109 082 5012 4012 3012 0011 0011 0011 13 108 1 081 5011 4011 3011 008 008 008 14 107 080 508 408 308 007 007 007 1012 15 106 1079 507 407 307 004 004 004 1013 16 105
61. 56 Macrocells M5 128 5 128 MBLV 128 959958 858858 60880000 MBLV 128 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt NANANA Nr M5 256 00 1 M5 256 MBLV 256 55555555 888888 999999 855555555 MBLV 256 xt CO QN or PEPE EEO or rero 000727272227 0099899222900 z z 5 3000000005 3000000 3555505050 5265650555555 KO xt 00 KO LO LO 00 F 10 QN 333 333 9 959 9 5 9 6 8 TDI 1 120 TDO 0A14 0A12 0A8 2 119 1 091 3A8 2A12 0D14 0A15 0A13 0A9 01 3 118 L 4 1 090 3A9 2A13 0015 0814 0A14 0A10 02 4 117 1 089 10 2A14 0014 0813 0A15 11 5 116 L 24 1 088 11 2A15 0013 0 12 0 15 0 12 1 04 6 115 1 087 12 2815 0 12 0811 0814 0A13 VOS 7 114 1 086 3A13 2814 0 11 0810 0813 0 14 06 8 113 1 085 14 2813 0 10 0B9 0B12 0A15 1 07 9 112 1 084 15 2812 0C9
62. 609 pue 9501 ANY ANY 2601 fei 91607 fei ONY fel 2 001 ANY LXv9 57 v9 9 L L v9 1 1 1 1 1 1 E ze ze ze ze ze pore 9 Hi 12910001911 2019 ze E ze ze E E 3 X E fe Y Y Y Y Y 2 601 pue 9601 pue 3 601 pue pue dojeooliy 21507 pue 9601 pue 21607 1607 ONY 21607 ONY 21607 ONY ELX LXv9 61 ELX v9 142 1 1459 1 25 142 1479 ze ze 182 i 14 9 i E3 142 14 9 1499 1 z 2 2 2 L L sioen p gt sioen orsu bm p jonuoo z 10u09 2 2 jonuoo 2 2 212 Sr 2 142 h 30192 y 30492 30142 30142 31180 9L 3180 9 5190 9i 5190 oi 5190 m 91 0 5 9018 91 0 401g 91 0 y2olg 91 0 2018 1 0 42019 91 0 9018 9 LNAINDAS S IN3IN93S 0 1 9 5 20446G 011 MACH 5 Family 18 Semiconductor au u u n a
63. 6666 oras 5 1100 vao D Hn m H H H ued a 99 99 eas eias 99A s eee 5180 10 elas zIVS OOH gt gt ZVO 2100 2109 5196 OGL OLGO evs 99 OA ego 889 6199 2182 282 99A evo evs 99A 21 9 evo 289 989 0189 199 0182 982 99A 8vo 65100 179 V9 089 99 S89 689 2189 6189 9182 2182 682 082 evo 9 189 289 1189 187 I c v 9 L 8 6 ZI Ot 20446G 027 5 gt FS gt Package obsolete contact factory 41 MACH 5 Family ice Semiconductor Corporation 352 BALL BGA CONNECTION DIAGRAM 5 512 M5LV 512 Bottom View 1 0 Pin outs 352 Ball BGA LE Oe Ba 2 gt gt gt ON ON 9920 1 ON vScO ScO 2920 920 0ScO 6
64. 79 25 L Y L Y owu 1 9r 2 10 9r 2 18 30 18 si 91 _ 5190 9 9 91 0 49019 91 0 49019 5 9 LNAINDAS Continued MACH 5 Family 20 Semiconductor Corporation ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M5 Commercial C Devices Storage Temperature 65 C to 150 C Ambient Temperature TA Device Junction Operating in Free 0 to 70 C Temperature Note 1 130 C or 150 C Supply Voltage Vcc Supply Voltage with Respect to Ground 44 75 V to 45 25 V with Respect to Ground 0 5 V to 47 0 V Industrial I Devices DC Voltage 0 5 V to 5 5 V Ambient Temperature Static Discharge Voltage 2000 V Operating in Free 40 C to 485 C Latchup Current 40 C to 85 C NR RUE er res 200 mA Supply Voltage Vcc Stresses above those listed under Absolute Maximum with Respect to Ground 44 5 V to 45 5 V Ratings may cause permanent device failure Functionality at or above these limits is not implied Exposure to Absolute Maximum Ratings for extended periods may affect device reliability Operating ranges define those limits between which the functionality of the device is
65. 8 55 t Y 21601 pue 91607 pue 91607 21601 LXYv9 54 99 192 i 1419 14 4 1879 ze L Y L Y Ly owu E sevow owu jouog 2 10u09 2 18 2 18 2 5199 9L 199 91 91 9 91 0 4901g 91 0 2018 v 91 0 42018 91 0 2018 91 0 42018 91 91 9 9 5199 199 18 2 30 18 2 9 2 91 10239099 j Jonuo 7 savone 1 1 de iiy ee 144 1419 40jeoo 21601 pue JojeooJv 21601 pue Keay 21607 feu 21601 LX 79 54 X79 1 1 26 HI 4901g JJ 21601 pue Jojeoo v 21601 21601 ONY 21601 ANY LXYv9 54 99 147 i 1479 ze 147 1 1479 ze L Y L Y Jojejeuec L 9r 2 9r 2 18 2 30 18 2 199 91 199 9L 91 9r
66. 9 82 1 060 2 8 2012 1014 4 40 81 TMS CO t LO KO xt LO Q CO QN CO t se LO 10 10 10 L0 10 L0 XO CO CO C CO CO 0 00 3883885889 9922919 S95 9295 858858 2999999995299999972656299999925999999959785 5 256 9299 2 27272322T M5 256 M5LV 256 00 QANANA M5LV 256 M5 192 xoonooor M5 192 555555 lt PSBBBSN SSSSSSAB M5 128 59958 855848 BS85882z22 M5 128 MSLV 128 MBLV 128 20446G 021 Pin Designations Clock Vcc Supply Voltage 3 D 15 GND Ground TDI Test Data In I Input TCK Test Clock Macrocell 0 15 YO Input Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 3 MACH 5 Family 33 160 PIN PQFP WITH INTERNAL HEAT SPREADER CONNECTION DIAGRAM Top View 160 Pin PQFP 320 384 512 Macrocells MSLV 320 2352358 225252328 MSLV 320 3 Ooo0o0o0000 555555 e 320 M5 384 9 goy M5 384 MBLV 384 2855522898 5555565
67. Corporation 5V M5 ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of the elements below 512 FAMILY TYPE 5 MACH 5 5 V MACROCELL DENSITY 128 128 Macrocells 192 192 Macrocells 256 256 Macrocells 320 320 Macrocells 384 384 Macrocells 512 512 Macrocells 168 681 Os in 100 pin or TQFP 74 7AT Os in 100 pin TQFP 104 104 I Os in 144 pin PQFP or TQFP 120 120 I Os in 160 pin PQFP 160 160 I Os in 208 pin PQFP 192 192 I Os in 256 ball BGA 256 256 I Os in 352 ball BGA Note 1 See below for valid device package combinations 256 7 A PROGRAMMING DESIGNATOR Blank Initial Algorithm 1 First Revision OPERATING CONDITIONS C Commercial 0 C to 70 C I Industrial 40 C to 85 C PACKAGE TYPE Y Plastic Quad Flat Pack PQ FP V z Thin Quad Flat Pack TQFP Ball Grid Array BGA Plastic Quad Hat Pack with exposed heat sink SPEED 5 5 5ns tpp 6 6 5ns tpp 7 7 5ns tpp 10 10ns tpp 12 12 05 tpp 15 1505 tpp 20 20 ns tpp 2 M5 128 1 M5 192 1 and M5 256 1 recommended for new designs Valid Combinations YC VC YI VI M5 128 104 Commercial YC VC YI VI Valid Combinations HC HI HC HI HC HI AC AI 5 7 10 12 15 Indu
68. ND 25 84 GND 185 188 O17 26 83 1 060 288 105 186 1811 O18 L 3 27 82 59 2811 126 187 1812 O19 28 81 1 058 2B12 1C7 1B8 1B13 O20 29 80 2 1 057 2B13 1C8 GND 30 79 GND 1810 1412 O21 31 78 1 056 2A12 1010 1B11 1A11 O22 32 77 1 055 2A11 1011 1812 1A10 O23 L 3 33 76 1 054 2A10 1012 1813 1A9 O24 34 75 1 053 2A9 1013 1A14 1A8 25 35 74 1 052 2A8 1D14 36 73 TMS Q x LO QI x CO st 10 9 CO wb b wb b L0 L0 L0 00 10 CO CO CO CO CO SSNESSZSODISSESSOOSESGXSSQI099599895 62990999996 999990972667299999959999999785 xt QN xt 00 QN sx CO OW C2 xb 10 CO M5LV 256 5555554 8855554 MBLV 256 NN O t 00 Moby 128 lt lt lt 445555 8828898 CAASA 20446 020 Pin Designations CIK Clock Vcc Supply Voltage 3 D 15 GND Ground TDI Test Data In I Input TCK Test Clock Macrocell 0 15 YO Input Output TMS Test Mode Select PAL Block A D NC No Connect TDO TestData Out Segment 0 3 32 MACH 5 Family Semiconductor Corporation 160 PIN PQFP CONNECTION DIAGRAM Top View 160 Pin PQFP 128 192 2
69. SP is achieved customers get the benefit of a standard well defined interface MACH 5 devices can be programmed across the commercial temperature and voltage range The PC based LatticePRO software facilitates in system programming of MACH 5 devices LatticePRO software takes the file output produced by design implementation software along with information about the Boundary Scan chain and creates a set of vectors that are used to drive the Boundary Scan chain LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC Alternatively LatticePRO software can output files in formats understood by common automated test equipment This equipment can then be used to program MACH 5 devices during the testing of a circuit board PCI COMPLIANT MACH 5 devices in the 5 6 7 10 12 speed grades are compliant with the PCI Local Bus Specification version 2 1 published by the PCI Special Interest Group SIG The 5 V devices are fully PCI compliant The 3 3 V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above Vcc because of their 5 V input tolerant feature MACH 5 devices provide the speed drive density output enables and I Os for the most complex PCI designs 10 MACH 5 Family Lattice Semiconductor Corporation
70. at Pack PQ FP 256 256 Macrocells V Thin Quad Flat Pack TQFP 320 320 Macrocells A Grid Array BGA 384 384 Macrocells H Plastic Quad Flat Pack PQFP 512 512 Macrocells with exposed heat sink I Os 68 68 I Os in 100 pin or TQFP SPEED 174 741 Os in 100 pin TQFP 5 5 5 ns tpp 104 104 I Os in 144 pin PQFP or TQFP 6 6 5 ns tpp 120 120 I Os in 160 pin PQFP 7 57 5 ns tpp 160 160 I Os in 208 pin PQFP 10 10 ns tpp 192 192 I Os in 256 ball BGA 12 12 ns tpp 256 256 I Os in 352 ball BGA 15 15 ns tpp 20 20 ns tpp Note 1 See below for valid device package combinations Valid Combinations M51y 128 68 YC VC YI VI 128 74 VC VI M51y 128 104 Commercial YC VC YI VI M51V 128 120 5 7 10 12 YC YI 256 68 VC YI 256 74 Industrial VC VI 256 104 7 10 12 15 YC VC YI VI 256 120 YC YI 256 160 YC YI Valid Combinations M51y 320 120 HC YC HI M51y 320 160 HC HI 511 320 184 HC HI M51y 320 192 M51Y 384 120 Commercial HC YC HI M51y 304 160 6 7 10 12 15 M51y 304 184 HC HI Industrial M51y 304 192 10 12 15 20 M51 512 120 HC YC HI M51 512 160 HC YC HI M51 512 184 HC M51 512 192 M51V 512 256 AC AI
71. az Ode SWZ 8Vc 01 2 ON ON ON ON ovr 99A vive OLve 9ve eve 99 9 282 99A eve 99 MOL 1 MACH 5 Family GND vs OGL 99A sivo Liv9 zv9 evo 99A 699 289 1189 9 882 2 A pwz 9194 99 evo evo 940 ON ON ON ON 8179 0179 8V9 SV9 099 799 889 2189 9189 2182 684 982 287 EW 494 VIVZ GND ON ON 1 9 6V9 9V9 7 9 Ov9 289 489 689 12189 9182 2182 0182 982 082 ZVZ 9 8192 ON GND ON ON GND ON GND ON 199 189 989 0189 7189 GND 118 ON 287 184 OWZ SWZ ON GND ON dA hb Oe gt A M a ee eo M M 1 2 S 9 L 8 6 OL IL SI 91 OC cc ec vc GE 9 AV av OV SV ON 0 svt ON VV vvv evi ZVL e gt
72. bit Advanced E CMOS process provides high performance cost effective solutions Supported by ispDesignEXPERT software for rapid logic development Supports HDL design methodologies with results optimized for MACH 5 devices Flexibility to adapt to user requirements Software partnerships that ensure customer success Lattice and Third party hardware programming support LatticePRO software for in system programmability support on PCs and Automated Test Equipment Programming support on all major programmers including Data I O BP Microsystems Advin and System General Publication 20446 Rev I Amendment 0 Issue Date September 2000 Semiconductor 122222 Corporation Table 1 MACH 5 Device Features 5 128 1 5 192 1 5 256 1 5 320 5 384 5 512 Feature M51V 128 M5IV 256 M51V 320 M51V 384 M51V 512 Supply Voltage V 5 3 3 5 3 3 5 3 3 5 3 3 5 3 3 Macrocells 128 128 256 256 320 320 384 384 512 512 Maximum User I O Pins 120 120 160 160 192 192 160 192 256 256 55 5 5 55 55 652 65 65 652 652 6 52 3 0 3 0 3 0 30 30 30 3 02 3 02 30 3 02 45 45 45 45 50 5 02 502 50 5 02 5 02 182 182 182 182 1672 1672 1672 Typical Static Power mA 35 35 55 55 70 70 75 75 100 100 IEEE 1149 1 Boundary Scan Compliant Yes Yes Yes Yes Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes Note
73. ctor C e iconc ion Corporat 945 LNAWS3S L 1 9 8 20446G 010 17 BLOCK DIAGRAM M5 LV 320 XXX
74. e logic via the matrix Macrocell Logic Allocator Control Bus 5 8 Clusters 9 Prog Polarity Mod ode Selection 20446G 003 Figure 3 Macrocell Diagram Control Generator The control generator provides four configurable clock lines and three configurable set reset lines to each macrocell in a PAL block Any of the four clock lines and any of the three set reset lines can be independently selected by any flip flop within a block The clock lines can be configured to provide synchronous global pin clocks and asynchronous product term clocks sum term clocks and latch enables Figure 4 Three of the four global clocks as well as two product term clocks and one sum term clock are available per PAL block Positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking Complementary clocking provides two clock lines exactly 180 degrees out of phase and is useful in applications such as fast data paths A biphase clock line clocks flip flops on both the positive and negative edges of the clock The configuration options for the four clock lines per PAL block are as follows Clock Line 0 Options Global clock 0 1 2 3 with positive or negative edge clock enable Product term clock A B C Sum term clock 6 MACH 5 Family Lattice Semiconductor Corporati
75. er loc mA 300 x 5 LV 512 low power 5 128 1 and M5LV 128 high power M5 LV 384 low power uc coe M5 LV 320 low power M5 256 1 and M5LV 256 low power M5 192 1 high power 200 100 5 192 1 low power M5 128 1 and M5LV 128 low power e te N 0 Frequency MHz 20446G 048 Figure 8 Curves at High Low Power Modes 26 MACH 5 Family Lattice Semiconductor Corporation 5 V 25 C 700 M5 256 high power 600 500 M5 192 high power 400 300 M5 128 high power 200 5 256 low power M5 192 low power i p M5 128 low power tss qub JF NET N N T T Frequency MHz 20446G 049 Figure 9 Curves at High Low Power Modes MACH 5 Family 27 100 PIN PQFP CONNECTION DIAGRAM
76. er 5 m 5 9 Product term o A 9 C Nae 5 32 gt zi 8 m S Input Register 2 Path PAR Interconnect Feeder 20446G 002 Figure 2 PAL Block Structure Product Term Array and Logic Allocator The product term array uses the same sum of products architecture as PAL devices and consists of 32 inputs plus their complements and 64 product terms arranged in 16 clusters A cluster 15 a sum of products function with either 3 of 4 product terms Logic allocators assign the clusters to macrocells Fach macrocell can accept up to eight clusters of three or four product terms but a given cluster can only be steered to one macrocell Table 4 If only three product terms in a cluster are steered the fourth can be used as an input to an XOR gate for separate logic generation and or polarity control The widelogic allocator is comprised of all 16 ofthe individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change The logic allocation scheme in the MACH 5 device allows for the implementation of large equations up to 32 product terms with only one pass through the logic array Table 4 Product Term Steering Options for PT Clusters and Macrocells C3 C4 C5 Cg Co Cy Cy 6 Cg Co
77. guaranteed 5 V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Output HIGH Voltage H 3 2 mA Voc Min Vin or For M5 128 1 M5 192 1 M5 256 1 M5 320 M5 384 M5 512 Devices 0 mA Voc Max Output HIGH Voltage 3 2 mA Voc Min Vigor For M5 128 5 192 M5 256 Devices 2 5 mA Voc 5 25 V Vy Vigor Vy Output LOW Voltage Note 2 L 16 mA Voc Min Vin or Guaranteed Input Logical HIGH Voltage for all Inputs Note 3 Guaranteed Input Logical LOW Voltage for all Inputs Note 3 Input HIGH Leakage Current Vin 5 25 Voc Max Note 4 Input LOW Leakage Current Vin 0 Voc Max Note 4 Off State Output Leakage Current HIGH 5 25 Max Vin Vig or Note 4 Off State Output Leakage Current LOW 0 Viy Vig or Note 4 Output Short Circuit Current 0 5 Voc Max Vin Viq or Note 5 Input HIGH Voltage Input LOW Voltage Note 1 150 for M5 128 M5 192 and M5 256 devices 130 for M5 128 1 M5 192 1 M5 256 1 M5 320 M5 384 and M5 512 devices Total between ground pins should not exceed 64 mA These are absolute values with respect to device ground and all overshoots due to system and or tester noise are included pin leakage is the worst case of Ij and Iozj or
78. ive pve OGL ervo OLOO eve eve 99A 99A ege 99A 280 99A 99A zvo eve OA ege vae 2182 197 ivy SVP 2180 780 280 evo 5100 282 1186 ovr 9Vb OLVE LIVE SIVE 1180 880 evo sav el VP 2180 280 I v 9 L 8 6 OL x lt m gt gt 20446G 029 Package obsolete contact factory 39 MACH 5 Family 1 T S SI 6I 9 L 8 6 OL TI SI Ll ns ons ser os ovo ono e owe e s we os M 1182 0182 gaz ova eve ovz 01 1191 88 A sve eae vae zige 2182 saz iaz iva sve eve 218 91 cat 99A evi Livi L nee so L MOL
79. making a distinction between internal feedback and external feedback A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer The input register specifications are also reported as internal feedback When a signal is fed back into the switch matrix after having gone through the output buffer it is using external feedback The parameter tgyp is defined as the time it takes to go through the output buffer to the I O pad If a signal goes to the internal feedback rather than to the I O pad the parameter designator is followed by an i By adding to this internal parameter the external parameter is derived For example tpp tpp tgyp A diagram representing modularized MACH 5 timing model is shown in Figure 7 Refer to the Technical Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters External Feedback Internal Feedback COMB DFF IN ts S A tepi S A 5 4 Q tsaL t a tpi2 PT 560 ipia INPUT REG INPUT LATCH s a tco 5 Q s a tei tsni tces hd PIN CLK De Figure 7 MACH 5 Timing Model 20446G 014 MACH 5 Family 9 Lattice EEEE Semiconductor Corporation
80. nput Output TMS Test Mode Select PAL Block A D NC No Connect TDO Test Data Out Segment 0 3 30 MACH 5 Family Lattice Semiconductor Corporation 144 PIN PQFP CONNECTION DIAGRAM Top View 144 Pin PQFP M5 128 SX 5 128 MBLV 128 5555555 555555 888888 88688888 MBLV 128 M5 192 or 5 192 9 25 22388885 855599 29858 NNN 5 256 5 256 MSLV 256 5555555 oooooo 5555555 MSLV 256 o BBBESLOSBASSLL 690050090 909099 355 9909099 9099990 35 CO LO xt CO L0 xt X sf CO OZS8s8885595989558 88S 6 6 SEE ESE TDI 1 108 0A14 0A12 0A8 2 107 077 2412 0014 0813 0A13 0A9 O1 3 106 1 076 9 2 13 OC13 0B12 0A14 0A10 O2 4 105 075 10 2 14 0012 0811 0813 11 O3 5 104 7 1 074 11 2813 0C11 0 10 0812 0A12 O4 6 103 4 073 3A12 2812 0C10 GND 7 102 7 GND 0B8 0B11 0B13 O5 J 8 101 1 072 3813 2811 0C8 0 7 088 0812 O6 9 100 071 3812 288 0C7 086 085 0811 O7 4
81. number of segments Therefore once a designer is familiar with one device consistent performance can be expected across the entire family devices have four clock pins available which can also be used as logic inputs CLK Block 16 MCs 4 Segment 4 Blocks o o ks amp Segment Interconnect Figure 1 MACH 5 Block Diagram 20446G 001 The MACH 5 PAL blocks consist of the elements listed below Figure 2 While each PAL block resembles an independent PAL device it has superior control and logic generation capabilities T O cells Product term array and Logic Allocator Macrocells Register control generator Output enable generator Cells The I Os associated with each PAL block have a path directly back to that PAL block called local feedback If the I O is used in another PAL block the interconnect feeder assigns a block interconnect line to that signal The interconnect feeder acts as an input switch matrix The block and segment interconnects provide connections between any two signals in a device The block feeder assigns block interconnect lines and local feedback lines to the PAL block inputs 4 MACH 5 Family Lattice Semiconductor Corporation 2 OE Generator Control Generator 32 Block gt 16 Feed
82. off can be tailored for each design The signal speed paths in the lower power PAL blocks will be slower than those in the higher power PAL blocks This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower power mode In large designs there may be several different speed requirements for different portions of the design Table 5 Power Levels High Speed High Power 100 Power Medium High Speed Medium High Power 67 Power Medium Low Speed Medium Low Power 40 Power Low Speed Low Power 20 Power PROGRAM MABLE SLEW RATE Each MACH 5 device I O has an individually programmable output slew rate control bit Each output can be individually configured for the higher speed transition 3 V ns or for the lower noise transition 1 V ns For high speed designs with long unterminated traces the slow slew rate will introduce fewer reflections less noise and keep ground bounce to a minimum For designs with short traces or well terminated lines the fast slew rate can be used to achieve the highest speed The slew rate is adjusted independent of power POW ER UP RESET SET All flip flops power up to a known state for predictable system initialization If a macrocell is configured to SET on a signal from the control generator then that macrocell will be SET during device power up If a macrocell is configured to RESET on a signal from the control generator or is not configured for set
83. on Clock Line 1 Options Global clock 0 1 2 or 3 with positive edge clock enable Global clock 0 1 2 3 with negative edge clock enable Global clock 0 1 2 3 with positive and negative edge clock enable biphase Clock Line 2 Options Global clock 0 1 2 or 3 with clock enable Clock Line 3 Options Complement of clock line 2 same clock enable Product term clock if clock line 2 does not use clock enable PT 0 3 PINCLK 0 3 E MUX 4TO1 9 IN 0 MUX 2TOT IN 1 CLKIN N 2 OUT 0 Clock Enable OUT 9 IN 3 PTO m F0 FI PT 0 2 gt PTO SETO RSTO MUX 4TO1 0 4 0 MUX 2TOT 2 CLK QUT S m 3110 L2 SETI RST1 S in 3 D CLKEN1 F0 Fi PT2 BIPHASE gt CLKEN2 PT2 MUX 4TO1 SET2 RST2 LE 2 L 5 our cue 4 CLKIN Clock Enable Block Fo FI MUX cd 2TO1 PT3 24 MUX 2TO1 ICLK2 OU PTCLK 20446G 004 20446G 005 Figure 4 Clock Generator Figure 5 Set Reset Generator The set reset generation portion of the control generator Figure 5 creates three set reset lines for the PAL block Each macrocell can choose one of these three lines or choose reset at all All three lines can be configured for product term set reset and t
84. ration and wide range of other applications including high speed computing low power applications communications and embedded control At each macrocell density point Lattice offers several I O and package options to meet a wide range of design needs Table 3 Table 3 MACH 5 Package and I O Options M5 128 1 5 256 1 5 320 5 384 5 512 128 M5 192 1 M5IV 256 M51V 320 M51V 384 M51V 512 Supply Voltage 5 5 3 3 5 3 3 5 3 3 5 3 3 Note 1 The I O options indicated with a are obsolete please contact factory for more information MACH 5 Family 3 Lattice 222222 Semiconductor Corporation Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today s complex designs I O safety features allow for mixed voltage design and both the 3 3 V and the 5 V device versions are in system programmable through an IEEE 1149 1 Test Access Port TAP interface FUNCTIONAL DESCRIPTION The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect The block interconnect provides routing among 4 PAL blocks This grouping of PAL blocks joined by the block interconnect is called a segment The second level of interconnect the segment interconnect ties all of the segments together The only logic difference between any two MACH 5 devices is the
85. strial 7 10 12 15 20 Package obsolete contact factory Contact Factory for availability Device Marking YC VC YI VI YC YI 5 384 184 5 384 192 5 512 120 5 512 192 5 512 256 Commercial HC HI 6 7 10 12 15 HC HI HC HI Industrial AC AT 7 10 12 15 20 HC HI HC HI HC HI AC AT AC AI Actual device marking differs from the ordering part number OPN All MACH devices are dual marked with both Commercial and Industrial grades The Industrial grade is slower i e M5 512 256 7AC 10AT Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations 44 MACH 5 Family Semiconductor Corporation 3 3V M5LV ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of the elements below M5LV 512 256 7 A FAMILY TYPE ____ OPERATING CONDITIONS MACH 5 Low Voltage 3 3 V C Commercial 0 C to 70 C I Industrial 40 C to 85 C MACROCELL DENSITY PACKAGE TYPE 128 128 Macrocells Y Plastic Quad Fl
86. t Data In Test Clock Test Mode Select Test Data Out Ground Input Input Output No Connect Macrocell 0 15 PAL Block A D Segment 0 7 36 MACH 5 Family Lattice Semiconductor Corporation 240 PIN PQFP CONNECTION DIAGRAM Top View 240 Pin PQFP 5 320 eee ES HEREBY SESSSE 5 320 MBLV 320 885058800 333323323 333333 999999 99999929 55558858 MBLV 320 MS 384 LEZAN Zoo gog9z99i9 M5 384 M5LV 384 lt lt lt lt lt lt lt lt lt lt lt lt lt lt C0 CO M5LV 384 84444888 55555555 555555 888888 0000008 22299999 M5 512 9 roozou o M5 512 MBLV 512 BRREBRERS DARRER 0022090 00008000 722555556 MSLV 512 8 588299 5888885895899 59919929 855 9955555 588556 89988 588568 69 566588 88 898666 584 5 29 82800000006 5 20055555505555555 25555 20000055555055550555555555 55 6 X ID x t O t lt t MAT t x 0 Q
87. wo of the three lines can be configured as sum term set reset and one of the lines can be configured as product term or sum term latch enable While signals are generated in the control generator whether that signal sets or resets a flip flop is determined within the individual macrocell The same signal can set one flip flop and reset another PT2 or PT2 can also be used as a latch enable for macrocells configured as latches MACH 5 Family 7 Lattice Semiconductor Corporation OE Generator There is one output enable OE generator per PAL block that generates two product term driven output enables Each I O cell is simply an output buffer Fach I O cell within the PAL block can choose to be permanently enabled permanently disabled or choose one of the two product term output enables per PAL block Figure 6 Output Enable Generator Internal Feedback KA External Feedback 20446G 006 Figure 6 Output Enable Generator and I O Cell MACH 5 Family Lattice EEEE Semiconductor Corporation 1 MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device and at the same time be easy to understand This model accurately describes all combinatorial and registered paths through the device
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