ST M27C512 512 Kbit (64K x8) UV EPROM OTP EPROM handbook
Contents
1. Note 1 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp 2 Sampled only not 100 tested 3 Speed obtained with High Speed AC measurement conditions 2 11 22 M27C512 Table 9 Read Mode AC Characteristics Symbol Alt Parameter t t Address Valid to AVOV ACG Output Valid teLav Ice Output Valid eLav toE to Output Valid 2 teHaz DF to Output Hi Z Output Enable taxax toH Chip Enable Low to Output Enable Low Chip Enable High 2 tenaz tDF High to Output Hi Z Address Transition to Output Transition Test Condition 1 M27C512 12 15 20 25 n mex win ax in uo Note 1 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp 2 Sampled only not 100 tested Figure 9 Read Mode AC Waveforms mi Ol Q0 Q7 12 22 tAVQV gt A0 A15 VALID tAXQX VALID Al00735B Unit ns ns ns ns ns ns lt M27C512 Table 10 Programming Mode DC Characteristics Symbol Parameter Test Condition 12 Min Max Unit ll Input Leakage Current Vin lt Vin lt Vin 10 HA lec Supply Current mA Ipp Program Current mA VIL Input Low Voltage V VIH Input High Voltage V VoL Output Low Voltage loL 2 1mA V VoH Output High Voltage TTL lOH 1mA V Vip A9 Voltage 115 125 V2. Note 1 Compliant with the JEDEC Std J STD 020B for small body Sn Pb or Pb assermbly the ST ECOPACK 7191395 specification and the European directive on Restrictions on Hazardous Substances RoHS 2002 95 EU 2 Minimum DC voltage on Input or Output is 0 5V with possible undershoot to 2 0V for a period less than 20ns Maximum DC voltage on Output is Vcc 0 5V with possible overshoot to Vcc 2V for a period less than 20ns 3 Depends on range Y 9 22 M27C512 DC AND AC PARAMETERS This section summarizes the operating and mea surement conditions and the DC and AC charac teristics of the device The parameters in the DC and AC Characteristic tables that follow are de rived from tests performed under the Measure Table 5 AC Measurement Conditions ment Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame ters High Speed Standard Input Rise and Fall Times Input Pulse Voltages lt 10ns 0 to 3V lt 20ns 0 4V to 2 4V Input and Output Timing Ref Voltages 1 5V 0 8V and 2V Figure 7 Testing Input Output Waveform Figure 8 AC Testing Load Circuit High Speed 3V E Gua ov Standard 2 4V 0 4V A101822 1 3V 1N914 3 3kQ DEVICE UNDER O OUT TEST 1 CL 30pF for High Speed CL 100pF for Stand
3. control and should be used for device selection Output Enable G is the output control and should be used to gate data to the output pins indepen dent of device selection Assuming that the ad Table 2 Operating Modes dresses are stable the address access time tavav is equal to the delay from E to output teLav Data is available at the output after a delay of tgLav from the falling edge of G assuming that E has been low and the addresses have been sta ble for at least tavav teLav Standby Mode The M27C512 has a standby mode which reduces the active current from 30mA to 100A The M27C512 is placed in the standby mode by apply ing a CMOS high signal to the E input When in the standby mode the outputs are_in a high imped ance state independent of the GVpp input Mode E GVpp Q7 Q0 Read Vi VIL Data Out Output Disable VIL ViH Hi Z Program Vit Pulse Vpp Data In Program Inhibit ViH Vpp Hi Z Standby VIH X Hi Z Electronic Signature VIL VIL Vip Codes Note X VjH or VIL Vip 12V 0 5V Table 3 Electronic gorane Identifier Hex Data Manufacturers Code a e e e e e e a Device Code Two Line Output Control Because EPROMs are usually used in larger memory arrays the product features a 2 line con trol function which accommodates the use of mul tiple memory connection The two line control function allows a the lowest possible memory power dissipation b complete assurance t
4. M27C512 Figure 15 TSOP28 28 lead Plastic Thin Small Outline 8 x 13 4 mm Package Outline A2 m N 2 Note Drawing is not to scale Table 16 TSOP28 28 lead Plastic Thin Small Outline 8 x 13 4 mm Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A 1 250 0 0492 Al 0 200 0 0079 A2 0 950 1 150 0 0374 0 0453 0 170 0 270 0 0067 0 0106 C 0 100 0 210 0 0039 0 0083 CP 0 0039 D 13 200 13 600 0 5197 0 5354 D1 11 700 11 900 0 4606 0 4685 e 0 550 E 00217 z ES E 7 900 8 100 0 3110 0 3189 L 0 500 0 700 0 0197 0 0276 28 28 2 19 22 M27C512 PART NUMBERING Table 17 Ordering Information Scheme Example M27C512 70 X C 1 TR Device Type M27 Supply Voltage C 5V Device Function 512 512 Kbit 64Kb x8 Speed 45 1 45 ns 60 60 ns 70 70 ns 80 80 ns 90 90 ns 10 100 ns 12 120 ns 15 150 ns 20 200 ns 25 250 ns Vcc Tolerance blank 10 X 5 Package F FDIP28W B PDIP28 C PLCC32 N TSOP28 8 x 13 4 mm Temperature Range 1 0to 70 C 3 40 to 125 C 6 40 to 85 C Options Blank Standard Packing TR Tape and Reel Packing E Lead free and RoHS Package Standard Packing F Lead free and RoHS Package Tape and Reel Packing Note 1 High Speed see AC Characteristics section for further information F
5. are the property of their respective owners O 2004 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 22 22 TA
6. devic es The bulk capacitor should be located near the power supply connection point The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces Figure 6 Programming Flowchart Voc 6 25V Vpp 12 75V SET MARGIN MODE RESET MARGIN MODE CHECK ALL BYTES 1st Voc 6V 2nd Vcc 4 2V Al00738B Programming When delivered and after each erasure for UV EPROM all bits of the M27C512 are in the 1 state Data is introduced by selectively program ming 0 s into the desired bit locations Although only 0 s will be programmed both 1 s and 0 s can be present in the data word The only way to change a 0 to a 1 is by die exposure to ultraviolet light UV EPROM The M27C512 is in the pro gramming mode when Vpp input is at 12 75V and E is pulsed to Vi_ The data to be programmed is applied to 8 bits in parallel to the data output pins The levels required for the address and data in puts are TTL Vcc is specified to be 6 25V 0 25V The M27C512 can use PRESTO IIB Pro gramming Algorithm that drastically reduces the programming time typically less than 6 seconds 577 M27C512 Nevertheless to achieve compatibility with all pro gramming equipments PRESTO Programming Algorithm can be used as well PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin in a typical ti
7. 2518 M 27C 51 24H pv a 571 o M27C512 512 Kbit 64K x8 UV EPROM and OTP EPROM FEATURES SUMMARY m 5V 10 SUPPLY VOLTAGE in READ Figure 1 Packages OPERATION m ACCESS TIME 45ns m LOW POWER CMOS CONSUMPTION Active Current 30mA Standby Current 100u4A PROGRAMMING VOLTAGE 12 75V 0 25V PROGRAMMING TIMES of AROUND 6sec m ELECTRONIC SIGNATURE FDIP28W F Manufacturer Code 20h Device Code 3Dh m PACKAGES Lead Free Versions a mii qe pd E W l 1 PDIP28 B November 2004 1 22 M27C512 TABLE OF CONTENTS FEATURES SUMMARY sieni co A ae ee ed di 1 Figure Packages A e i aha BE o SR Rt cg A Ie 1 SUMMARY DESCRIPTION 2 00 ee ke hee ated ei ads 4 Figure 2 Logic Diagram e yiee ea Meee Peed ee Edw ieee a dai eee Peay 4 Table 1 Signal Names 0 0000 etna 4 Figure 3 DIP Connections saaana aae 5 Figure 4 ECC Connections 240 rata cada biela taa bad 5 Figure 5 TSOP Connections ooooocccoc 000 ect t tee eeeeeee 5 DEVICE OPERATION cosain oe oe ett 2 a oO ee eee ee eee ee ee 6 Read Modem ee a tere ee hee ee eee Ah 6 Standby Mode Sowa et aR EO eB tl he ies Se ctl E A Od ad idas 6 Table 2 Operating Modes 0 0 0 cece teeta 6 Table 3 Electronic Signature 0 0 6 Two Line Output Control ii ees 6 System Considerations 0 0 cece eee 6 POG ramming iit tet ta el A de OE A wna eat ah nt ae 7 Figure
8. 6 Programming Flowchart 0 000 c eee eee eee 7 PRESTO IIB Programming Algorithm o coococcccon eee 7 Program INDIE eens see acre oct a ye ea een ee EN ee NA 7 Program Verily ici eee da aaa 7 Electronic Signature o io ie 8 a ete ee Oe we ee OE Lk eee ooo ld eee Pee es 7 ERASURE OPERATION APPLIES FOR UV EPROM 000 c eee eee eee eee 8 MAXIMUM RATING ieoi rae a ek cao Sere aS tae PO wie PE ee ee eee 9 Table 4 Absolute Maximum RatingS 0 0 00 eee eee 9 DC and AC PARAMETERS 2 2 wesc ead tae a eed 10 Table 5 AC Measurement Conditions 0 000 00 cece tee 10 Figure 7 Testing Input Output Waveform sss sa sssaaa aaaea eaea 10 Figure 8 AC Testing Load Circuit o an auauua aaae 10 Table 6 Capacitance ausus o 10 Table 7 Read Mode DC Characteristics 0 0 0 0 cece tee 11 Table 8 Read Mode AC Characteristics 00 0000 cece tte 11 Table 9 Read Mode AC Characteristics 00 0000 ccc tte 12 Figure 9 Read Mode AC WaveformS 00 cece ete eee 12 Table 10 Programming Mode DC Characteristics o ooooooooooooranooo noo 13 Table 11 Margin Mode AC Characteristics 000 0c 14 Figure 10 Margin Mode AC Waveforms ooooccoccco eee 14 Table 12 Programming Mode AC Characteristics 0 0 eee eee 15 Figure 11 Programming and Verify Modes AC Waveforms 00000 cece eee eens 15 2 22 TA M27C512 PACKAGE MEC
9. HANICAL hir ec A ee A a 16 Figure 12 FDIP28W 28 pin Ceramic Frit seal DIP with window Package Outline 16 Table 13 FDIP28W 28 pin Ceramic Frit seal DIP with window Package Mechanical Data 16 Figure 13 PDIP28 28 pin Plastic DIP 600 mils width Package Outline 17 Table 14 PDIP28 28 pin Plastic DIP 600 mils width Package Mechanical Data 17 Figure 14 PLCC32 32 lead Plastic Leaded Chip Carrier Package Outline 18 Table 15 PLCC32 32 lead Plastic Leaded Chip Carrier Package Mechanical Data 18 Figure 15 TSOP28 28 lead Plastic Thin Small Outline 8 x 13 4 mm Package Outline 19 Table 16 TSOP28 28 lead Plastic Thin Small Outline 8 x 13 4 mm Package Mechanical Data 19 PART NUMBERING 0020 eae oe ee he eves Lee OSE eek Pee eee eae ee oe 20 Table 17 Ordering Information Scheme 0000 cece eee eee 20 REVISION HISTORY v asiaa Seg A ee eee nek See ial es 21 Table 18 Revision History 0 0 0 tees 21 2 3 22 M27C512 SUMMARY DESCRIPTION The M27C512 is a 512 Kbit EPROM offered in the two ranges UV ultra violet erase and OTP one time programmable It is ideally suited for applica tions where fast turn around and pattern experi mentation are important requirements and is organized as 65536 by 8 bits The FDIP28W window ceramic frit seal package has transparent lid which allows the user to ex pose the chip t
10. HQX Chip Enable High to Input Transition us teHvPx Chip Enable High to Vpp Transition us tvPLEL Vpp Low to Chip Enable Low us TEHAX ns Note 1 Ta 25 C Voc 6 25V 0 25V Vpp 12 75V 0 25V 2 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp 3 Sampled only not 100 tested Figure 11 Programming and Verify Modes AC Waveforms A0 A15 VALID Q0 Q7 DATA IN tEHQX Vcc GVpp E I tELEH e PROGRAM pi VERIFY gt Al00737 2 15 22 M27C512 PACKAGE MECHANICAL Figure 12 FDIP28W 28 pin Ceramic Frit seal DIP with window Package Outline FDIPW a Note Drawing is not to scale Table 13 FDIP28W 28 pin Ceramic Frit seal DIP with window Package Mechanical Data Symbol millimeters inches Typ Min Max Typ Min Max A 5 72 0 225 Al 0 51 1 40 0 020 0 055 A2 3 91 0 154 0 180 A3 3 89 4 50 0 153 0 177 B 0 41 0 016 0 022 B1 1 45 0 057 C 0 23 0 009 0 012 D 36 50 37 34 1 437 1 470 D2 33 02 1 300 E 15 24 0 600 E1 13 06 0 514 0 526 e 2 54 0 100 eB 16 18 18 03 0 637 0 710 L 3 18 0 125 0 161 S 1 52 2 49 0 060 0 098 a 4 11 4 11 N 28 28 16 22 TA M27C512 Figure 13 PDIP28 28 pin Plastic DIP 600 mils width Package Outline B1 PDIP Note Drawing is not to scale Table 14 PDI
11. Note 1 Ta 25 C Voc 6 25V 0 25V Vpp 12 75V 0 25V 2 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp 2 13 22 M27C512 Table 11 Margin Mode AC Characteristics Symbol Alt Parameter Test Condition 1 2 Min Max Unit tagHVPH tasa Vag High to Vpp High 2 us tvPHEL Vpp High to Chip Enable Low us tA10HEH Vaio High to Chip Enable High Set us TA10LEH Vaio Low to Chip Enable High Reset us TEXA10X Chip Enable Transition to Vaio Transition us texvPx Chip Enable Transition to Vpp Transition us TVPXA9X Vpp Transition to Vag Transition us Note 1 Ta 25 C Voc 6 25V 0 25V Vpp 12 75V 0 25V 2 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp Figure 10 Margin Mode AC Waveforms Voc A8 AQ tA9HVPH tVPXA9X GVpp tVPHEL tA10HEH gt A10 Set A10 Reset tA10LEH 4 gt tEXA10X Al00736B Note A8 High level 5V A9 High level 12V 14 22 2 Table 12 Programming Mode AC Characteristics M27C512 Symbol Alt Parameter Test Condition 49 Min Max Unit tAVEL tas Address Valid to Chip Enable Low 2 us taveL Input Valid to Chip Enable Low us tVCHEL Voc High to Chip Enable Low us tvPHEL Vpp High to Chip Enable Low us tvPLVPH Vpp Rise Time ns tELEH Chip Enable Program Pulse Width Initial 105 us tE
12. P28 28 pin Plastic DIP 600 mils width Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A 4 445 0 1750 A1 0 630 0 0248 A2 3 810 3 050 4 570 0 1500 0 1201 0 1799 B 0 450 EA 0 0177 B1 1 270 0 0500 0 230 0 310 0 0091 0 0122 D 36 830 36 580 37 080 1 4500 1 4402 1 4598 D2 33 020 z fF 1 3000 z E 15 240 A 0 6000 E1 13 720 12 700 14 480 0 5402 0 5000 0 5701 el 2 540 E 0 1000 eA 15 000 14 800 15 200 0 5906 0 5827 0 5984 eB 15 200 0 5984 0 6567 L 3 300 0 1299 S 1 78 2 08 0 070 0 082 a 0 10 0 10 N 28 28 TA 17 22 M27C512 Figure 14 PLCC32 32 lead Plastic Leaded Chip Carrier Package Outline TD gt F 0 51 020 i 020 i 1 14 045 Al gt A2 gt E2 E2 D CP dl 4 PLCC A Note Drawing is not to scale Table 15 PLCC32 32 lead Plastic Leaded Chip Carrier Package Mechanical Data Symbol millimeters inches Typ Min Typ Min Max A 3 18 0 125 0 140 Al 1 53 0 060 0 095 A2 0 38 0 015 B 0 33 0 013 0 021 B1 0 66 0 026 0 032 CP 0 004 D 12 32 0 485 0 495 D1 11 35 0 447 0 453 D2 4 78 0 188 0 223 D3 7 62 0 300 E 14 86 0 585 0 595 El 13 89 0 547 0 553 E2 6 05 0 238 0 273 ES 10 16 0 400 e 1 27 0 050 F 0 00 0 000 0 005 R 0 89 0 035 N 32 32 18 22 TA
13. ard CL includes JIG capacitance Al01823B Table 6 Capacitance Input Capacitance Output Capacitance Note 1 Ta 25 C f 1MHz 2 Sampled only not 100 tested 10 22 2 Table 7 Read Mode DC Characteristics M27C512 Symbol Parameter Test Condition 1 Min Max Unit ll Input Leakage Current OV lt Vin lt Voc 10 uA ILO Output Leakage Current OV lt Vout lt Vcc 10 uA E Vi G Vi lec Supply Current lout OMA f 5MHz mA Icc1 Supply Current Standby TTL E VH 1 mA lccz Supply Current Standby CMOS E gt Vcc 0 2V 100 uA Ipp Program Current Vpp Vcc yA VIL Input Low Voltage 0 3 0 8 V Vin 9 Input High Voltage 2 Vcc 1 v VoL Output Low Voltage loL 2 1mA 0 4 V Output High Voltage TTL loH 1mA 3 6 V VoH Output High Voltage CMOS loH 100A Vcc 0 7V V Note 1 Vcc must be applied simultaneously with or before Vpp and removed simultaneously or after Vpp 2 Maximum DC voltage on Output is Vcc 0 5V Table 8 Read Mode AC Characteristics M27C512 Symbol Alt Parameter Test Condition 1 45 3 60 70 80 Unit Min Max Min Max Min Max Min Max wor ue ero e wew o fe o Tel aCe SESE o fo co rem e e ol el 2 Chip Enable High GL tEHOZ tDF to Output Hi Z G VI 25 0 25 0 30 30 ns 2 Output Enable E_ tGHQZ tDF High to Output Hi Z E VIL 25 0 25 0 30 30 ns taxax toH o o E V G ViL 0 0 0 0 ns
14. d erasure procedure for the M27C512 is exposure to short wave ultraviolet light which has wavelength 2537 A The integrated dose i e UV intensity x exposure time for erasure should be a minimum of 15 W sec cm The erasure time with this dos age is approximately 15 to 20 minutes using an ul traviolet lamp with 12000 uW cm power rating The M27C512 should be placed within 2 5 cm 1 inch of the lamp tubes during the erasure Some lamps have a filter on their tubes which should be removed before erasure 2 MAXIMUM RATING Stressing the device outside the ratings listed in Table 4 may cause permanent damage to the de vice These are stress ratings only and operation of the device at these or any other conditions out side those indicated in the Operating sections of Table 4 Absolute Maximum Ratings M27C512 this specification is not implied Exposure to Ab solute Maximum Rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Symbol Parameter Value Unit Ta Ambient Operating Temperature 9 40 to 125 C TBIAS Temperature Under Bias 50 to 125 C TsTG Storage Temperature 65 to 150 C TLEAD Lead Temperature during Soldering note 1 C Vio Y Input or Output Voltage except A9 2 to 7 V Vcc Supply Voltage 2 to 7 V Vag Y A9 Voltage 2 to 13 5 V Vpp Program Supply Voltage 2 to 14 V
15. hat output bus contention will not occur For the most efficient use of these two control lines E should be decoded and used as the prima ry device selecting function while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus This ensures that all deselect ed memory devices are in their low power standby mode and that the output pins are only active 6 22 when data is required from a particular memory device System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices The supply current Icc has three seg ments that are of interest to the system designer the standby current level the active current level and transient current peaks that are produced by the falling and rising edges of E The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors It is recommended that a 0 1uF ceram ic capacitor be used on every device between Vcc and Vss This should be a high frequency capaci tor of low inherent inductance and should be placed as close to the device as possible In addi ky tion a 4 7uF bulk electrolytic capacitor should be used between Vcc and Vss for every eight
16. me of 6 5 seconds This can be achieved with STMicroelectronics M27C512 due to several design innovations described in the M27C512 datasheet to improve programming effi ciency and to provide adequate margin for reliabil ity Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin Then a sequence of 100us program pulses are ap plied to each byte until a correct verify occurs No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin Program Inhibit Programming of multiple M27C512s in parallel with different data is also easily accomplished Ex cept for E all like inputs including GVpp of the par allel M27C512 may be common A TTL low level pulse applied to a M27C512 s E input with Vpp at 12 75V will program that M27C512 A high level E input inhibits the other M27C51 2s from being pro grammed Program Verify A verify read should be performed on the pro grammed bits to determine that they were correct ly programmed The verify is accomplished with G at Vi_ Data should be verified with teLov after the falling edge of E Electronic Signature The Electronic Signature ES mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type This mode is intended for use by programming equipment to automatically match the device to be programmed with its correspondi
17. ng programming algorithm The ES mode is functional in the 25 C 5 C am bient temperature range that is required when pro gramming the M27C512 To activate the ES mode the programming equipment must force 11 5V to 12 5V on address line AQ of the M27C512 Two identifier bytes may then be se quenced from the device outputs by toggling ad dress line AO from Vi_ to Vi All other address lines must be held at V L during Electronic Signa ture mode Byte 0 AO Vi represents the man ufacturer code and byte 1 AO Vjy the device identifier code For the STMicroelectronics M27C512 these two identifier bytes are given in Table 3 and can be read out on outputs Q7 to QO 7 22 M27C512 ERASURE OPERATION APPLIES FOR UV EPROM The erasure characteristics of the M27C512 is such that erasure begins when the cells are ex posed to light with wavelengths shorter than ap proximately 4000 A It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000 4000 A range Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C512 in about 3 years while it would take ap proximately 1 week to cause erasure when ex posed to direct sunlight If the M27C512 is to be exposed to these types of lighting conditions for extended periods of time it is suggested that 8 22 opaque labels be put over the M27C512 window to prevent unintentional erasure The recommende
18. o ultraviolet light to erase the bit pat tern A new pattern can then be written to the device by following the programming procedure For applications where the content is programmed only one time and erasure is not required the M27C512 is offered in PDIP28 PLCC32 and TSOP28 8 x 13 4 mm packages In addition to the standard versions the packages are also available in Lead free versions in compli ance with JEDEC Std J STD 020B the ST ECO PACK 7191395 Specification and the RoHS Restriction of Hazardous Substances directive 4 22 Figure 2 Logic Diagram Vcc AO A15 E M27C512 GVpp Vss Al00761B Table 1 Signal Names A0 A15 Address Inputs Q0 Q7 Data Outputs E Chip Enable GVpp Output Enable Program Supply Vcc Supply Voltage Vss Ground NC Not Connected Internally DU Don t Use 2 Figure 3 DIP Connections M27C512 Figure 5 TSOP Connections M27C512 Al00762 Figure 4 LCC Connections Al00764B Al00763 2 5 22 M27C512 DEVICE OPERATION The modes of operations of the M27C512 are list ed in the Operating Modes table A single power supply is required in the read mode All inputs are TTL levels except for GVpp and 12V on AQ for Electronic Signature Read Mode The M27C512 has two control functions both of which must be logically active in order to obtain data at the outputs Chip Enable E is the power
19. or a list of available options speed package device please contact your nearest ST Sales Of etc or for further information on any aspect of this fice 20 22 TA M27C512 REVISION HISTORY Table 18 Revision History Date Version Revision Details November 1998 1 0 First Issue 25 Sep 2000 1 1 AN620 Reference removed 02 Apr 2001 1 2 FDIP28W mechanical dimensions changed Table 13 as Package mechanical data clarified for PDIP28 Table 14 29 Aug 2002 8 PLCC32 Table 15 Figure 14 and TSOP28 Table 16 Figure 15 Details of ECOPACK lead free package options added pe NOV 2004 2 0 Additional Burn in option removed Y 21 22 M27C512 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names
Download Pdf Manuals
Related Search
ST M27C512 512 Kbit (64K x8) UV EPROM OTP EPROM handbook