MICROCHIP -MCP6V06/7/8 300 A Auto-Zeroed Op Amps handbook
Contents
1. o 0 05 3 Lots 40 40 C o c S 0 00 9 30 25 C 5 5 85 C gt _ 0 05 o 20 125 C sz 5 it 0 10 ps 10 o 5 0 15 Lower Vcomp Vss E E 0 E 0 20 S 10 I o 125 C 87 0 25 20 Rene 2 25 C a 20 30 Upper Von Vcg E 0 40 C 0 35 T T T T T T 40 T T T T T T T T T T T T 50 25 0 25 50 75 100 125 soe tease E Ambient Temperature C Power Supply Voltage V FIGURE 2 18 Input Common Mode FIGURE 2 21 Output Short Circuit Current Voltage Headroom Range vs Ambient vs Power Supply Voltage Temperature 1000 E 9 5 Von 55 o P gt Vbo 1 8V cae 9 2 100 8 S C Voo Von amp 5 23 amp a o p 7 5 Vo Vss 10 LI 0 1 1 10 Output Current Magnitude mA FIGURE 2 19 Output Voltage Headroom FIGURE 2 22 Supply Current vs Power vs Output Current Supply Voltage 30 gt 10 5 25 77 25 C E 9 E E 8 3 20 7 i 8 E 5 15 o T 5 S 10 33 32 o 5 o Er 1 n 0 0 N e i M 50 25 0 25 50 75 100 125 c c c Ambient Temperature C POR Trip Voltage V FIGURE 2 20 Output Voltage Headroom FIGURE 2 23 Power2. 160 2 10 S 120 a Voo 5 5V SN 100 oS 80 o gt Vpp 1 8V ae OT vo 40 z 5 20 a E O a aaa i0 VN onon nn on 010 0o S SS NNO d 4 4 HHS Common Mode Input Voltage V FIGURE 2 36 Input Noise Voltage Density vs Input Common Mode Voltage 100 7 n IMD tone at DC Gom 1 V V H Vom tone 50 MVpx f 1 kHz H B 3 m residual E 1kHz Ua v gt tone DD E 10 Vpp 1 8V 2 o o N a 1 100 1k 10k 100k Frequency Hz FIGURE 2 37 Inter Modulation Distortion vs Frequency with Von Disturbance see Figure 1 7 100 aa E MD tone at DC Gom 1 VV x Vpp tone 50 mMVpx f 1 kHz gt es ATH Vo 5 5V H E Von 1 8V E 10 D 9 o o 7 a z 1 t 100 1k 10k 100k Frequency Hz FIGURE 2 38 Inter Modulation Distortion vs Frequency with Vpp Disturbance see Figure 1 7 Voo 1 8V n Input Noise Voltage e t 0 5 pV div NPBW 1 Hz 0 10 20 30 40 50 60 70 80 90 100 t s FIGURE 2 39 Input Noise vs Time with 1 Hz and 10 Hz Filters and Vpp 1 8V Von 5
3. 14 4 o 80 Samples Vom Veur L 8 12 Ta 25 C S 3 Representative Part 4 S Vbo 1 8V and 5 5V 3 E 10 Soldered on PCB o 2 5 o S as S 1 o 8 o 5 x 6 o 2 o 1 E 4 125 C o 5 2 85 C 9 2 4 2 25 C o c 3 A 40 C 0 4 eo b eo 9 2 9 eo 9 eo qi gt e e N 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 Input Offset Voltage uV Power Supply Voltage V FIGURE 2 1 Input Offset Voltage FIGURE 2 4 Input Offset Voltage vs Power Supply Voltage with Voy Vour L 25 4 r r r o 80 Samples Vom Vcun H 2 Vbo 1 8V and 5 5V gt 3 Representative Part 5 20 Soldered on PCB 3 E o2 2 o 2 0 SF 3 AAA 5 g z o 2 125 C 3 57 85 C 5 gs 25 C n 40 C 4 3 23 9 9 8 92 LR 8 8 10 7 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 Input Offset Voltage Drift TC nV C Power Supply Voltage V FIGURE 2 2 Input Offset Voltage Drift FIGURE 2 5 Input Offset Voltage vs Power Supply Voltage with Vey Voyr H n 30 4 z 80 Samples Representative Part 25 1 Von 1 8V and 5 5V S 3 2 Soldered on PCB 3 o 2 o S 1 o 20 2 S d 2 3 S N e N x o eo o eo 4 Input Offset Voltage s Quadratic Temp Co 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 TC nV C Output Voltage V FIGURE 2 3 Input Offset V
4. Vout MCP6V06 Vp 0 AAA AN o VREF R4 R3 FIGURE 4 10 PCB Layout and Schematic for Single Difference Amplifier Note Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages DS22093A page 24 2008 Microchip Technology Inc MCP6V06 7 8 4 3 8 4 Dual Non inverting Amplifier Layout for Thermo junctions The dual op amp amplifiers shown in Figure 4 14 and Figure 4 15 produce a non inverting difference gain greater than 1 and a common mode gain of 1 They can use the layout shown in Figure 4 11 The gain set ting resistors R2 between the two sides are not com bined so that the thermal voltages can be canceled The guard traces with ground vias at the ends help minimize the thermal gradients The resistor layout cancels the resistor thermal voltages assuming the temperature gradient is constant near the resistors EQUATION 4 4 Voa Vos Via Vig Gpw Voa Vos 2 Via Vig 2 Where Thermal voltages are approximately equal Gpm 1 R3 R differential mode gain Gem 1 common mode gain Vos is neglected Via Vig S Xt R1 i R2 ILE Vo vo R3 LO U4
5. 200 2 Ta 85 C S 150 Vbo 5 5V eee G 100 FE a l o ene B ga 50 of 0 8 a 50 los La a 100 4AA 150 O 1 WP o 1 o o SSC OF HK NN co HH GS Common Mode Input Voltage V FIGURE 2 14 Input Bias and Offset Currents vs Common Mode Input Voltage with Ta 85 C 1600 T 11250 4 Von 5 5V Input Bias Offset Currents pA o o oo oo 0 0 1o Sm eRe 9 be o eo o ox Ow GS Common Mode Input Voltage V FIGURE 2 15 Input Bias and Offset Currents vs Common Mode Input Voltage with TA 125 C FIGURE 2 16 Input Bias and Offset Currents vs Ambient Temperature with VDD 5 5V 10m 1m 100p SN 10u 1p 100n 10n 4n 125 C 85 C 100p 25 C 10p 40 C 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Input Voltage V Input Current Magnitude A FIGURE 2 17 Input Bias Current vs Input Voltage below Vss DS22093A page 8 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ty 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 2 2 Other DC Voltages and Currents
6. Vint Vin O E Vour Nul lt Amp _ CH P FIGURE 4 3 Auto zeroing Mode of Operation 5 Equivalent Diagram 4 1 3 INTERMODULATION DISTORTION IMD The MCP6V06 7 8 op amps will show intermodulation distortion IMD products when an AC signal is present The signal and clock can be decomposed into sine wave tones Fourier series components These tones interact with the auto zeroing circuitry s non linear response to produce IMD tones at sum and difference frequencies IMD distortion tones are generated about all of the square wave clock s harmonics See Figure 2 37 and Figure 2 38 DS22093A page 20 2008 Microchip Technology Inc MCP6V06 7 8 4 2 Other Functional Blocks 4 2 1 RAIL TO RAIL INPUTS The input stage of the MCP6V06 7 8 op amps uses two differential CMOS input stages in parallel One operates at low common mode input voltage Vcy which is approximately equal to Viy and Vyn in nor mal operation and the other at high Vom With this topology the input operates with Vcm up to 0 2V past either supply rail at 25 C see Figure 2 18 The input offset voltage Vos is measured at Vem Vss 0 2V and Vpp 0 2V to ensure proper operation The transition between the input stages occurs when Vom Vpp 0 9V see Figure 2 7 and Figure 2 8 For the best distortion and gain linearity with non inverting gains avoid this region of operati
7. 2 MCP6eV07 Vog Vig M IB Ry FIGURE 4 11 PCB Layout and Schematic for Dual Non inverting Amplifier Note Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages 4 3 8 5 Other PCB Thermal Design Tips In cases where an individual resistor needs to have its thermo junction voltage cancelled it can be split into two equal resistors as shown in Figure 4 12 To keep the thermal gradients near the resistors as small as possible the layouts are symmetrical with a ring of metal around the outside Make R44 R4g R4 2 and Roa Rab 2R2 Ria Rip Roa Roe E Ria z Rig SN O O O O ANN Rop FIGURE 4 12 PCB Layout for Individual Resistors Note Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages Minimize temperature gradients at critical components resistors op amps heat sources etc Minimize exposure to gradients Small components Tight spacing Shield from air currents Align with constant temperature contour lines Place on PCB center line Minimize magnitude of gradients Select parts with lower power dissipation Use same metal junctions on thermo junc tions that need to match
8. t MCP6V06 oN Simple Design FIGURE 4 13 Figure 4 14 shows a higher performance circuit for Wheatstone bridges This circuit is symmetric and has high CMRR Using a differential input to the ADC helps with the CMRR MCP6V07 ER PS e 200 Q gt VW 1 MCP6V07 2 FIGURE 4 14 High Performance Design DS22093A page 26 2008 Microchip Technology Inc MCP6V06 7 8 4 4 2 RTD SENSOR The ratiometric circuit in Figure 4 15 conditions a three wire RTD It corrects for the sensor s wiring resistance by subtracting the voltage across the middle Rw The top R1 does not change the output voltage it balances the op amp inputs Failure open of the RTD is detected by an out of range voltage 2 MCP6V07 ANNE 249kO Voo 100 nF Rr Hm Rw 20 kQ Ra faa e AAA 100 kA S3 ko Ry Ro Vpp R US ton Ri X 2 49kQ o e R3 3 kQ Rw Rp 100 KQ 20 kQ Rw 100 nF _ e 2 49 kQ gt MW MCP6V07 FIGURE 4 15 RTD Sensor The voltages at the input of the ADC can be calculated with the following Garp 1 2 Rj R Gy Ggpp RAR Vom Cgrp Vr Vg GyVy V Vrt Vet Garp t 1 Gy Vy CM 77 n3 Where VT Voltage at the top of Rrtp VB Voltage at the bottom of Rrtp Vw Voltage across top and middle
9. R 250 Vodo v t M T o C MCP9700A NAAA AAA AAN O V4 I R R 3 kQ FIGURE 4 17 Thermocouple Sensor The MCP9700A senses the temperature at its physical location It needs to be at the same temperature as the cold junction Tc and produces V3 Figure 4 14 2008 Microchip Technology Inc DS22093A page 27 MCP6V06 7 8 The MCP1541 produces a 4 10V output assuming Vpp is at 5 0V This voltage tied to a resistor ladder of 4 100R and 1 3224R would produce a Thevenin equiv alent of 1 00V and 250R The 1 3224R resistor is com bined in parallel with the top right R resistor in Figure 4 16 producing the 0 5696R resistor V4 should be converted to digital then corrected for the thermocouple s non linearity The ADC can use the MCP1541 as its voltage reference Alternately an absolute reference inside a PIC can be used instead of the MCP1541 4 4 4 OFFSET VOLTAGE CORRECTION Figure 4 18 shows a MCP6V06 correcting the input offset voltage of another op amp R and C integrate the offset error seen at the other op amp s input the integration needs to be slow enough to be stable with the feedback provided by R4 and R3 MCP6V06 Offset Correction Vpp 2 O FIGURE 4 18 4 4 5 PRECISION COMPARATOR Use high gain before a comparator to improve the latter s performance Do not use MCP6V06 7 8 as a comparator by itself the Vos correction circuitry does not operate properly withou
10. 2 5 kHz ni 52 nVANHz f 100 kHz Input Noise Current Density ini 06 fA VHz Amplifier Distortion Note 1 Intermodulation Distortion Not DC IMD 32 HVpk Von tone 50 mVpx at 1 kHz Gy 1 Vpp 5 5V IMD 25 HVpk Vc tone 50 mVpy at 1 kHz Gy 1 Vpp 5 5V Amplifier Step Response Start Up Time tsTR 500 us Vos Within 50 uV of its final value Offset Correction Settling Time tsTL 300 Hus G 1 Vin step of 2V Vos Within 50 HV of its final value Output Overdrive Recovery Time topR 100 us G 100 0 5V input overdrive to Vpp 2 Vin 50 point to Voyt 90 point Note 2 Note 1 These parameters were characterized using the circuit in Figure 1 7 Figure 2 37 and Figure 2 38 show both an IMD tone at DC and a residual tone ati kHz all other IMD and clock tones are spread by the randomization circuitry 2 tone includes some uncertainty due to clock edge timing 2008 Microchip Technology Inc DS22093A page 3 MCP6V06 7 8 TABLE 1 3 DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vow Vpp 3 Vout Vpp 2 Vi Vpp 2 RL 20 kQ to Vj C 60 pF and CS GND refer to Figure 1 5 and Figure 1 6 Parameters Sym Min Typ Max Units Conditions CS Pull Down Resistor MCP6V08 CS Pull D
11. 7 Bir MN ZAR 22 S 20 120 8 8 8 10 Ral NI 150 8 2 0 180 o o E o amp 10 i 210 amp 20 240 30 270 1k 10k 100k 1M 10M Frequency Hz FIGURE 2 26 Open Loop Gain vs Frequency with Vpp 1 8V 60 n 0 Vbo 5 5V 50 C 60 pF 30 z Q 40 60 t c 30 n 90 2 T ZA 20 In br 120 amp S 9 9 10 AT 150 8 z 0 180 o o E a o amp 10 210 amp 20 240 30 270 1k 10k 100k 1M 10M Frequency Hz FIGURE 2 27 Open Loop Gain vs Frequency with Vpp 5 5V 2008 Microchip Technology Inc 1 8 130 a Em GBWP Von 5 5 120 B 44 N 110 a 12 100 i o 810 90 5 3 z 08 80 9 S 0 6 xt 70 E z a m n PM Vbo jal o 0 2 50 0 0 ji T H T T T 40 50 25 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 28 Gain Bandwidth Product and Phase Margin vs Ambient Temperature 1 8 130 S 16 rid 120 o 5 9 14 X 110 e z a NES EE 100 5 1 0 em 90 E 205 7 80 S 06 E 70 8 t c s 04 7 3 60 6 02 i 50 0 0 40 D NN nn 10 nn SSSe lt a ei ei FFO S Common Mode Input Voltage V FIGURE 2 29 Gain Bandwidth Product and Phase Margin vs Common Mode Input Voltage 1 8 130 z GBWP S 16 Y 120 9 14 110 a 12 iie Z 100 ER S Von 5 5V p 2 1 0 Vos 21 8V D
12. Parameters Sym Min Max Units Conditions Input Offset Input Offset Voltage Vos 10 10 HV TA 25 C Note 1 Note 2 Input Offset Voltage Drift with Temperature TC4 nV C TA 40 to 125 C Note 3 linear Temp Co Power Supply Rejection PSRR 115 dB Note 1 Common Mode Common Mode Rejection CMRR 106 dB Vpp 1 8V Vcm 0 2V to 2 0V Note 1 CMRR 116 dB Vpp 5 5V Vom 0 2V to 5 7V Note 1 Open Loop Gain DC Open Loop Gain large signal Ao 114 dB Vpp 1 8V Vout 0 2V to 1 6V Note 1 AoL 122 dB Vpp 5 5V Vout 0 2V to 5 3V Note 1 Note 1 production 2 Vos s also sample screened at 125 C 3 TC is not measured in production Due to thermal junctions and other errors in the production environment these specifications are only screened in DS22093A page 36 2008 Microchip Technology Inc PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office MCP6V06 7 8 PART NO zX Device Temperature Range IXX Package MCP6V06 MCP6VO6T Device MCP6V07 MCP6V07T MCP6V08 MCP6VO8T Package Single Op Amp Single Op Amp Tape and Reel for SOIC Dual Op Amp Dual Op Amp Tape and Reel for 4x4 DFN and SOIC Single Op Amp with Chip Select Single Op Amp with Chip Select Tape and Reel for SOIC Temperature Range E 40 C
13. The guard traces with ground vias at the ends help minimize the thermal gradients The resistor layout cancels the resistor thermal voltages assuming the temperature gradient is constant near the resistors EQUATION 4 2 Vout VpGp Vu GND RI VMGM Vp GND Where Gy R3 R2 inverting gain magnitude Gp 1 Gy non inverting gain magnitude Vos is neglected O 1 Vout R3 U1 o R2 y V a d O Bi O Ro R3 Vm M VW Uy MCP6V06 Vout Vp Ry FIGURE 4 9 PCB Layout and Schematic for Single Non inverting and Inverting Amplifiers Note Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages 4 3 8 3 Difference Amplifier Layout for Thermo junctions Figure 4 10 shows the recommended difference ampli fier circuit Usually we choose R4 R3 and R3 R4 The guard traces with ground vias at the ends help minimize the thermal gradients The resistor layout cancels the resistor thermal voltages assuming the temperature gradient is constant near the resistors EQUATION 4 3 Vout Vrer Vp Vw Gpm Where Thermal voltages are approximately equal Gpm R3R4 7R4R5 difference gain Vos is neglected Vu Te PL O
14. Use metal junctions with low temperature to voltage coefficients Large distance from heat sources Ground plane underneath large area FR4 gaps no copper for thermal insulation Series resistors inserted into traces adds thermal and electrical resistance Use heat sinks Make the temperature gradient point in one direction Add guard traces Constant temperature curves follow the traces Connect to ground plane Shape any FRA gaps Constant temperature curves follow the edges 2008 Microchip Technology Inc DS22093A page 25 MCP6V06 7 8 4 3 8 6 Crosstalk DC crosstalk causes offsets that appear as a larger input offset voltage Common causes include Common mode noise remote sensors Ground loops current return paths Power supply coupling Interference from the mains usually 50 Hz or 60 Hz and other AC sources can also affect the DC perfor mance Non linear distortion can convert these signals to multiple tones included a DC shift in voltage When the signal is sampled by an ADC these AC signals can also be aliased to DC causing an apparent shift in offset To reduce interference Keep traces and wires as short as possible Use shielding e g encapsulant Use ground plane at least a star ground Place the input signal source near to the DUT Use good PCB layout techniques Use a separate power supply filter bypass capacitors for these auto zeroed
15. In order to achieve DC precision on the order of 1 HV many physical errors need to be minimized The design of the Printed Circuit Board PCB the wiring and the thermal environment has a strong impact on the precision achieved A poor PCB design can easily be more than 100 times worse than the MCP6V06 7 8 op amps minimum and maximum specifications 4 3 8 1 Thermo junctions Any time two dissimilar metals are joined together a temperature dependent voltage appears across the junction the Seebeck or thermo junction effect This effect is used in thermocouples to measure tempera ture The following are examples of thermo junctions on a PCB Components resistors op amps soldered to a copper pad Wires mechanically attached to the PCB Jumpers Solder joints PCB vias Typical thermo junctions have temperature to voltage conversion coefficients of 10 to 100 uV C sometimes higher There are three basic approaches to minimizing thermo junction effects Minimize thermal gradients Cancel thermo junction voltages Minimize difference in thermal potential between metals 2008 Microchip Technology Inc DS22093A page 23 MCP6V06 7 8 4 3 8 2 Non inverting and Inverting Amplifier Layout for Thermo junctions Figure 4 9 shows the recommended non inverting and inverting gain amplifier circuits on one schematic Usually to minimize the input bias current related off set R4 is chosen to be Rog R3
16. Microchip s Mindi Circuit Designer amp Simulator aids in the design of various circuits useful for active filter amplifier and power management applications It is a free online circuit designer amp simulator available from the Microchip web site at www microchip com mindi This interactive circuit designer amp simulator enables designers to quickly generate circuit diagrams and simulate circuits Circuits developed using the Mindi Circuit Designer amp Simulator can be downloaded to a personal computer or workstation 5 4 Microchip Advanced Part Selector MAPS MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design require ment Available at no cost from the Microchip website at www microchip com maps the MAPS is an overall selection tool for Microchip s product portfolio that includes Analog Memory MCUs and DSCs Using this tool a customer can define a filter to sort features for a parametric search of devices and export side by side technical comparison reports Helpful links are also provided for Data sheets Purchase and Sampling of Microchip parts 5 5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demon stration and Evaluation Boards that are designed to help customers achieve faster time to market For a complete listing of these boards and their correspond ing user s guides and technical information visit the Microc
17. Rws Vem ADC s common mode input Vom ADC s differential mode input 4 4 3 THERMOCOUPLE SENSOR Figure 4 16 shows a simplified diagram of an amplifier and temperature sensor used in a thermocouple application The type K thermocouple senses the temperature at the hot junction Tj and produces a voltage at V4 proportional to TH in C The amplifier s gain is is set so that V4 Tyy is 10 mV C V3 represents the output of a temperature sensor which produces a voltage proportional to the temperature in C at the cold junction Tc and with a 0 50V offset Vs is set so that V4 is 0 50V when Ty Tc is 0 C EQUATION 4 5 V4 Tyy 40 uV C V5 1 00V V5 Tey 10 mV C 0 50V V4 250V4 V2 Va 10 mV C Tu Toy 0 50V hot junction at Tu R R 40 pv C V2 o 8 Type K C R 250 4F Thermocouple MCP6V06 diu V 2 1 _ Mwe 0 V4 R 250 _ cold junction C at Toy V o AAN AAN R R FIGURE 4 16 Thermocouple Sensor Simplified Circuit Figure 4 17 shows a more complete implementation of this circuit The dashed red arrow indicates a thermally conductive connection between the thermocouple and the MCP9700A it needs to be very short and have low thermal resistance Voo T 4 100R 0 5696R MCP1541 ANN s NAAN s i E C Type K R 250 o MCP6V06 eeu iS AAA e
18. Inputs and Outputs Vss 0 3V to Vpp 0 3V ur iy ORARE indicated in the operational listings of this specification is not Difference Input voltage gt s srssss IVpp Vssl implied Exposure to maximum rating conditions for extended Output Short Circuit Current Continuous periods may affect device reliability Current at Output and Supply Pins 30 mA t See Section 4 2 1 Rail to Rail Inputs Storage Temperature 65 C to 150 C Max Junction Temperature 150 C ESD protection on all pins HBM MM gt 4 kV 300V 1 2 Specifications TABLE 1 1 DC ELECTRICAL SPECIFICATIONS Electrical Characteristics Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 Vi Vpp 2 RL 20 kQ to V and CS GND refer to Figure 1 5 and Figure 1 6 Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Vos 3 3 UV Ta 25 C Note 1 Input Offset Voltage Drift with Temperature TC 50 50 nVPC Ty 40 to 125 C linear Temp Co Note 1 Input Offset Voltage Quadratic Temp Co TC 0 15 nV C2 Ta 40 to 125 C Power Supply Rejection PSRR 125 142 dB Note 1 Input Bias Current and Impedance Input Bias Current
19. On Reset Trip vs Ambient Temperature Voltage 2008 Microchip Technology Inc DS22093A page 9 MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 50 25 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 24 Power On Reset Voltage vs Ambient Temperature DS22093A page 10 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ty 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 2 3 Frequency Response 110 100 NN 90 ath S 80 NS v 70 m CMRR te 60 h e Bow wz N 40 H 30 hd 20 PSRR 10 PSRR 0 10 100 1k 10k 100k 1M Frequency Hz FIGURE 2 25 CMRR and PSRR vs Frequency 60 mr 0 Vpp 1 8V 50 C 60 pF 30 Q 40 60 t vo
20. V FIGURE 2 58 Chip Select Hysteresis FIGURE 2 61 Quiescent Current in Shutdown vs Power Supply Voltage 16 o E 14 H c 12 o c 10 E28 6 o o 4 2 S 2 0 50 25 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 59 Chip Select Turn On Time vs Ambient Temperature 2008 Microchip Technology Inc DS22093A page 17 MCP6V06 7 8 3 0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3 1 TABLE 3 1 PIN FUNCTION TABLE MCP6V06 MCP6V07 MCP6V08 Symbol Description SOIC DFN SOIC SOIC 6 1 6 Vout Vouta Output op amp A 2 2 2 Vin VINA Inverting Input op amp A 3 3 3 Vint Vinat Non inverting Input op amp A 4 4 4 Vss Negative Power Supply 5 ViNB Non inverting Input op amp B 6 ViNB Inverting Input op amp B 7 VourB Output op amp B 7 8 7 Vpp Positive Power Supply m 8 CS Chip Select op amp A 1 5 8 1 5 NC No Internal Connection 3 1 Analog Outputs 3 3 Power Supply Pins The analog output pins Vour are low impedance voltage sources 3 2 The non inverting and inverting inputs Vint Vin are high impedance CMOS inputs with low bias currents Analog Inputs The positive power supply Vpp is 1 8V to 5 5V higher than the negative power supply Vss For normal operation the other pins are between Vss and Vpp Typically these parts are used in a sing
21. and CS GND refer to Figure 1 5 and Figure 1 6 Parameters Sym Min Typ Max Units Conditions Output Maximum Output Voltage Swing VoL Vox Vss 15 Vpp 15 mV G 2 0 5V input overdrive Output Short Circuit Current Isc 7 mA Vip 1 8V Isc 22 mA Vpp 5 5V Power Supply Supply Voltage Vpp 1 8 5 5 V Quiescent Current per amplifier lo 200 300 400 UA lo 0 POR Trip Voltage VPoR 1 15 1 65 V Note 1 Set by design and characterization Due to thermal junction and other effects in the production environment these parts can only be screened in production except TC4 see Appendix B Offset Related Test Screens 2 Figure 2 18 shows how Vcyg changed across temperature for the first three production lots TABLE 1 2 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics Unless otherwise indicated TA 25 C Vpp 1 8V to 5 5V Vss GND Vow Vpp 3 Vout Vpp 2 Vi Vpp 2 Rq 20 kQ to VL C 60 pF and CS GND refer to Figure 1 5 and Figure 1 6 Parameters Sym Min Typ Max Units Conditions Amplifier AC Response Gain Bandwidth Product GBWP 1 3 MHz Slew Rate SR 0 5 Vlus Phase Margin PM 65 z G 1 Amplifier Noise Response Input Noise Voltage Eni 0 54 uVp p f 0 01 Hz to 1 Hz Eni 1 7 UVpp f 0 1 Hz to 10 Hz Input Noise Voltage Density ni 82 nVhhHz f
22. input s dynamic behavior i e IMD tsrr tsr and topp The potentiometer balances the resistor network Vour should equal VREF at DC The op amp s common mode input voltage is Vey Vin 2 The error at the input Verr appears at Vour with a noise gain of 10 V V 20 0 KQ 20 0kQ 509 0 196 0 1 25 turn VREF LI Riso Vout O lt 2 49kQ 2 49 kQ WI 20 0 KQ 20 0 KQ 24 90 0 1 0 1 FIGURE 1 7 Input Behavior Test Circuit for Dynamic 2008 Microchip Technology Inc DS22093A page 5 MCP6V06 7 8 2 0 Note TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range e g outside specified power supply range and therefore outside the warranted range Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 2 1 DC Input Precision
23. lg 0 0 EN 0 5V Overdrive 0 5 10 15 20 25 30 35 40 45 50 1 0 1 Time us Time 50 us div FIGURE 2 47 Inverting Large Signal Step FIGURE 2 49 Output Overdrive Recovery Response vs Time with G 100 V V 0 9 1000 0 E0 5V Output Overdrive 0 8 E fo ising Edge 7 d g 7 eere E Vop 5 5V 2 DD 9 0 6 SS D 109 toor high 3 20 5 ma 8 N 04 caet X wo tov 3 j 0 3 Falling n4 o 10 o t Vop 1 8V 0 2 B tonr low 0 1 S o 0 0 1 50 25 0 25 50 75 100 125 1 10 100 1000 Ambient Temperature C Inverting Gain Magnitude V V FIGURE 2 48 Slew Rate vs Ambient FIGURE 2 50 Output Overdrive Recovery Temperature Time vs Inverting Gain 2008 Microchip Technology Inc DS22093A page 15 MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vip 1 8V to 5 5V Vss GND Voy Vpp 3 Vout Vpo 2 V Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 2 6 Chip Select Response MCP6V08 only 13 e 1 2 1 C8 Voo lt 1 1 I 1 0 c 0 9 E 0 8 3 0 7 be 0 6 0 5 804 20 3 0 2 9 94 0 0 T T T T T T T 15 20 25 30 3 5 40 45 50 55 Power Supply Voltage V FIGURE 2 51 Chip Select Current vs Power Supply Voltage Von 1 8V 350 G 1 Vin 0 9V 300 Op Amp Op Amp V 0V turns on turns off 250 here here 150 Hysteresis 100 50 0 0 02 04 06 08 10 1 2 14 1 6 1 8 Chip Select Voltage
24. m EN 2 N Q SS HK NN GB GO GDH dc Q Q e e gt Input Common Mode Voltage V 1 Ao HV V FIGURE 2 8 Input Offset Voltage vs FIGURE 2 11 DC Open Loop Gain Common Mode Voltage with Vpp 5 5V 35 160 FA 39 Samples i65 30 Ta 25 C 5 j Soldered on PCB PR Vp E 5 5V 5 25 E 150 Vpp 1 8V i z 8 20 Ez E 5 15 a P g 08 St 10 130 CMRR S 5 o PSRR e 125 0 M NN OH NN o6 120 qo Gy FF cO eS ee 50 25 0 25 50 75 100 125 1 CMRR V V Ambient Temperature C FIGURE 2 9 CMRR FIGURE 2 12 CMRR and PSRR vs Ambient Temperature 2008 Microchip Technology Inc DS22093A page 7 MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 V Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 160 155 150 145 140 135 130 125 120 DC Open Loop Gain dB 50 25 0 25 50 75 100 125 Ambient Temperature C 10 000 EVpp 5 5V 1 000 100 10 1 Input Bias Offset Currents pA o 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature C FIGURE 2 13 DC Open Loop Gain vs Ambient Temperature
25. to 125 C MD Plastic Dual Flat No Lead 4x4x0 9 8 lead MCP6V07 only SN Plastic SOIC 150mil Body 8 lead DS22093A page 37 2008 Microchip Technology Inc Examples MCP6VO6T E SN Extended temperature 8LD SOIC package MCP6V07 E MD Extended temperature 8LD 4x4 DFN MCP6V07T E SN Tape and Reel Extended temperature 8LD SOIC MCP6V08 E SN Extended temperature 8LD SOIC MCP6V06 7 8 NOTES DS22093A page 38 2008 Microchip Technology Inc Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge reguire using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the prod
26. voltage as low as 1 8V while drawing 300 pu A amplifier typical of quiescent current The Microchip Technology Inc MCP6V06 7 8 op amps are offered in single MCP6VO6 single with Chip Select CS MCP6V08 and dual MCP6V07 They are designed in an advanced CMOS process Package Types MCP6V06 MCP6V07 SOIC SOIC NC 14 8 NC Vourali 8 Vpp Vel 7 Vpp Vina L2 7 Vours Vint 3 6 Vour ViNA 13 6 Vine Vss 4 5 NC Vssl4 5 Vins Lr MCP6V08 MCP6V07 SOIC 4x4 DFN NCH 8 CS Voural1l 8 Vop Vine 2 7 Vpop Vna L2 7 VourB Vint 3 6 Vout Vinat 3 6 ViNB Vss 4 5 NC Vss 4 5 ViNB Typical Application Circuit R4 R3 ViNO AN ja AW OVOUT Ro C z MCP6XXX 3 KQ Ro 5 Vpp 2 WW MCcpevoe Offset Voltage Correction for Power Driver 2008 Microchip Technology Inc DS22093A page 1 MCP6V06 7 8 1 0 ELECTRICAL CHARACTERISTICS 1 1 Absolute Maximum Ratings t MDD Mg ii 6 5V T Notice Stresses above those listed under Absolute Current at Input Pins sse 2 mA Maximum Ratings may cause permanent damage to the Analog Inputs Vint and Viy tt Vss 1 0V to Vop 1 0V device This is a stress rating only and functional operation of the device at those or any other conditions above those All other
27. 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 39 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 01 02 08 DS22093A page 40 2008 Microchip Technology Inc
28. 5 40 45 50 Time 5 us div FIGURE 2 56 Chip Select Voltage Output Voltage vs Time with Vpp 5 5V DS22093A page 16 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 70 7 La 65 ai aS 9 Vinoo N SV g 6 22 60 T5 or A S 25 55 i S a 4 B 0 N Y o 25 40 g2 s3 34 7 n g 35 Vo N Voo 1 8V 30 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 Ambient Temperature C Ambient Temperature C FIGURE 2 57 Chip Select Relative Logic FIGURE 2 60 Chip Select s Pull down Thresholds vs Ambient Temperature Resistor Rpp vs Ambient Temperature 0 40 2 0 Tis C8 Voo 20 35 3 t6 Representative Part N 3 0 30 Von 5 5V 1 4 212550 A LA 0 25 5 12 ee O o Pd gt 0 20 gt 1 0 ES ELI 7 40 C N 8 015 Vos 1 8V 2 0 8 2 A 0 6 0 10 S B 9 0 4 50 05 302 LE 0 00 0 0 uo uo uo uo 50 25 0 25 50 75 100 125 Soc dada iii Ambient Temperature C Power Supply Voltage
29. 5V o lu Ai uad y o Sz 5 3 TT T TT T gt n NPBW 10 Hz C EZ z FE a NPBW 1 Hz 0 10 20 30 40 50 60 70 80 90 100 t s FIGURE 2 40 Input Noise vs Time with 1 Hz and 10 Hz Filters and Vpp 5 5V 2008 Microchip Technology Inc DS22093A page 13 MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 2 5 Time Response 7 r r 50 Von 5 5V 6 Temperature increased by 45 A G 1 E 5 using heat gun for 4 seconds 40 gt E o 3 4 35 s t 1 Pi e zi a7 g 14 p20 pi 0 15 2 S gat Vos 10 E 5 o 2 5 gt 3 0 5 a 4 5 El 5 10 o 6 15 5 0 20 40 60 80 100 120 140 160 180 200 0 2 4 6 8 10 12 14 16 18 20 Time s Time us FIGURE 2 41 Input Offset Voltage vs FIGURE 2 44 Non inverting Small Signal Time with Temperature Change Step Response 25 5 0 5 5 50 POR Trip 4s 5 0 ea i5 Point 40 4 5 D 9 4 0 S 10 35 3 o o o 3 5 5 3 0 gt S 30 3 2S g
30. 6VO6E XXXXY Y WW SN 630823 o SNNN o S256 Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code eo Pb free JEDEC designator for Matte Tin Sn gt This package is Pb free The Pb free JEDEC designator C3 can be found on the outer packaging for this package Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information DS22093A page 30 2008 Microchip Technology Inc MCP6V06 7 8 8 Lead Plastic Dual Flat No Lead Package MD 4x4x0 9 mm Body DFN Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging F 77 MERE E K E2 A YA P 7 PE A 2 NOTE 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW A3 A meen fo a Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0 80 BSC Overall Height A 0 80 0 90 1 00 Standoff A1 0 00 0 02 0 05 Contact Thickness A3 0 20 REF O
31. D 90 5 0 8 7 SP 80 5 S 0 6 70 m 7 c 04 7 60 A 02 55 50 0 0 E 4 3 40 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Output Voltage V FIGURE 2 30 Gain Bandwidth Product and Phase Margin vs Output Voltage DS22093A page 11 MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 10k 100 NNI a Voo 1 8V 90 RTI o 5 1k n c 8 s S 70 Vpp 5 5V E o 5 60 100 2 q 50 Vop 18V LH 5 2s 40 Oo G 1VN 5 9 39 o 10 G 10VN zo 8 G 100 VV O 20 z 10 amp 1 0 o 100k 1M 10M 100M 100k 1M 10M Frequency Hz Frequency Hz FIGURE 2 31 Closed Loop Output FIGURE 2 33 Channel to Channel Imp
32. Length D 4 90 BSC Chamfer optional h 0 25 0 50 Foot Length L 0 40 1 27 Footprint L1 1 04 REF Foot Angle 0 8 Lead Thickness c 0 17 0 25 Lead Width b 0 31 0 51 Mold Draft Angle Top a 5 15 Mold Draft Angle Bottom B 5 15 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 15 mm per side 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 057B HEEEENEEE ag DS22093A page 32 2008 Microchip Technology Inc MCP6V06 7 8 8 Lead Plastic Small Outline SN Narrow 3 90 mm Body SOIC Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging x1 E Y1 SILK SCREEN RECOMMENDED LAND PATTERN MILLIMETERS Contact Pitch 1 27 BSC Contact Pad Spaci
33. MICROCHIP MCP6V06 7 8 300 nA Auto Zeroed Op Amps Features High DC Precision Vos Drift 50 nV C maximum Vos 3 HV maximum Ag 125 dB minimum PSRR 125 dB minimum CMRR 120 dB minimum Ew 1 7 Vp p typical f 0 1 Hz to 10 Hz Epi 0 54 Vp p typical f 0 01 Hz to 1 Hz Low Power and Supply Voltages lg 300 uA amplifier typical Wide Supply Voltage Range 1 8V to 5 5V Easy to Use Rail to Rail Input Output Gain Bandwidth Product 1 3 MHz typical Unity Gain Stable Available in Single and Dual Single with Chip Select CS MCP6V08 Extended Temperature Range 40 C to 125 C Typical Applications Portable Instrumentation Sensor Conditioning Temperature Measurement DC Offset Correction Medical Instrumentation Design Aids SPICE Macro Models FilterLab Software Mindi Circuit Designer amp Simulator Microchip Advanced Part Selector MAPS Analog Demonstration and Evaluation Boards Application Notes Related Parts MCP6V01 2 3 Spread clock lower offset Description The Microchip Technology Inc MCP6V06 7 8 family of operational amplifiers has input offset voltage correction for very low offset and offset drift These devices have a wide gain bandwidth product 1 3 MHz typical and strongly reject switching noise They are unity gain stable have no 1 f noise and have good PSRR and CMRR These products operate with a single supply
34. V Power Supply Current pA N e FIGURE 2 52 Power Supply Current vs Chip Select Voltage with Vpp 1 8V 600 Von 5 5V X G 1 500 Vin 2 75V Op Amp v 0V 400 turns off Op Amp turns on here here I Hysteresis e e Power Supply Current uA e e e 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Chip Select Voltage V FIGURE 2 53 Power Supply Current vs Chip Select Voltage with Vpp 5 5V 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Chip Select Current pA 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Chip Select Voltage V FIGURE 2 54 Select Voltage Chip Select Current vs Chip 1 8 1 6 1 4 1 2 1 0 0 8 0 6 0 4 0 2 0 0 Output Voltage V Vour On Vpp 1 8V G 1 VV Vin Voo R 10 kQ tied to Vpp 2 Chip Select Voltage V Time 5 us div FIGURE 2 55 Chip Select Voltage Output Voltage vs Time with Vpp 1 8V gt o gt 8 8 o 4 S gt 2 0 Vbo 5 5V 5 45 G 1 VW gt 2 4 0 Vw Vo 9 E 05 R 10 KQ tied to Vpp 2 3 0 0 e csl3 0 5 10 15 20 25 30 3
35. edance vs Frequency with Vpp 1 8V Separation vs Frequency amp 10k 10 E Voo 5 5V ER H o o o o S 8 1k ci 2 2 E ES 100 So 1 3 es gt 10 G 1VN E 2 9 a G 10 VW 4 G 100 V V S NI p z amp 1 0 1 o 100k 1M 10M 100M 1k 10k 100k 1M Frequency Hz Frequency Hz FIGURE 2 32 Closed Loop Output FIGURE 2 34 Maximum Output Voltage Impedance vs Frequency with Vpp 5 5V Swing vs Frequency DS22093A page 12 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 V Vpp 2 R 20 KQ to V C 60 pF and CS GND 2 4 Input Noise and Distortion 10 000 cuuu r u Vaa e 1000 an DD Y 2 Von 1 8V s 3 a v q 1 000 SI gt 5 j 10 3 gt H o En 8 100 gu 2 5 z a 2 E 0 Hz tof 10 pou ati 1 10 10 100 1k 10k 100k Frequency Hz FIGURE 2 35 Input Noise Voltage Density vs Frequency
36. es crosstalk Minimizes parasitic capacitances and induc tances that interact with fast switching edges Good power supply design solation from other parts Filtering of interference on supply line s 4 3 7 SUPPLY BYPASSING AND FILTERING With this family of operational amplifiers the power supply pin Vpp for single supply should have a local bypass capacitor i e 0 01 UF to 0 1 pF within 2 mm of the pin for good high frequency performance These parts also need a bulk capacitor i e 1 uF or larger within 100 mm to provide large slow currents This bulk capacitor can be shared with other low noise analog parts Additional filtering of high frequency power supply noise e g switched mode power supplies can be achieved using resistors The resistors need to be small enough to prevent a large drop in Vpp for the op amp which would cause a reduced output range and possible load induced power supply noise The resis tors also need to be large enough to dissipate little power when Vpp is turned on and off quickly The cir cuit in Figure 4 8 gives good rejection out to 1 MHz for Switched mode power supplies Smaller resistors and capacitors are a better choice for designs where the power supply is reasonably quiet Vs ANA 1430 1430 1 4W 1 10W 9 6 ANN n ANN A 0 1 uF 100 uF 100 pF aa to other analog parts FIGURE 4 8 Additional Supply Filtering 4 3 8 PCB DESIGN FOR DC PRECISION
37. g CS low the amplifier is enabled If the CS pin is left floating the internal pull down resistor about 5 MO will keep the part on Figure 1 4 shows the output voltage and supply current response to a CS pulse 2008 Microchip Technology Inc DS22093A page 21 MCP6V06 7 8 4 3 Application Tips 4 3 1 INPUT OFFSET VOLTAGE OVER TEMPERATURE Table 1 1 gives both the linear and quadratic tempera ture coefficients TC and TC of input offset voltage The input offset voltage at any temperature in the specified range can be calculated as follows EQUATION 4 1 Vos T4 Vogt TOATE TOAT Where AT Ta 25 C Vos Ta input offset voltage at Ta Vos input offset voltage at 25 C TC linear temperature coefficient TCo quadratic temperature coefficient 4 3 2 DC GAIN PLOTS Figure 2 9 Figure 2 10 and Figure 2 11 are histograms of the reciprocals in units of uV V of CMRR PSRR and Ag respectively They represent the change in input offset voltage Vos with a change in common mode input voltage Vc power supply voltage Vpp and output voltage Vour The 1 Ao histogram is centered near 0 p V V because the measurements are dominated by the op amp s input noise The negative values shown represent noise not unstable behavior We validate the op amps stability by making multiple measurements of Vos instability would manifest itself as a greater unex plained variability in Vos or as
38. gdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Nanjing Tel 86 25 8473 2460 Fax 86 25 8473 2470 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xiamen Tel 86 592 2388138 Fax 86 592 2388130 China Xian Tel 86 29 8833 7252 Fax 86 29 8833 7256 China Zhuhai Tel 86 756 3210040 Fax 86 756 3210049 ASIA PACIFIC India Bangalore Tel 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 4160 8631 Fax 91 11 4160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 Japan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Daegu Tel 82 53 744 4301 Fax 82 53 744 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Kuala Lumpur Tel 60 3 6201 9857 Fax 60 3 6201 9859 Malaysia Penang Tel 60 4 227 8870 Fax 60 4 227 4068 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2
39. hip web site at www microchip com analog tools Some boards that are especially useful are MCP6V01 Thermocouple Auto Zeroed Reference Design MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit P N SOIC8EV 8 Pin SOIC MSOP TSSOP DIP Evaluation Board P N SOIC14EV 14 Pin SOIC TSSOP DIP Evaluation Board 5 6 Application Notes The following Microchip Application Notes are available on the Microchip web site at www microchip com appnotes and are recommended as supplemental reference resources ADNO03 Select the Right Operational Amplifier for your Filtering Circuits DS21821 AN722 Operational Amplifier Topologies and DC Specifications DS00722 AN723 Operational Amplifier AC Specifications and Applications DS00723 AN884 Driving Capacitive Loads With Op Amps DS00884 AN990 Analog Sensor Conditioning Circuits An Overview DS00990 These application notes and others are listed in the design guide Signal Chain Design Guide DS21825 2008 Microchip Technology Inc DS22093A page 29 MCP6V06 7 8 6 0 PACKAGING INFORMATION 6 1 Package Marking Information 8 Lead DFN 4x4 MCP6V07 Example XXXXXX 6V07 XXXXXX E MD 3 YYWW 0823 NNN 256 O O 8 Lead SOIC 150 mil Example NATT XXXXXXXX MCP
40. ification 150 C 2 Measured on a standard JC51 7 four layer printed circuit board with ground plane and vias DS22093A page 4 2008 Microchip Technology Inc MCP6V06 7 8 1 3 Timing Diagrams Vpp OV Vos 50 uV FIGURE 1 1 Amplifier Start Up Vos 50 uV Vos 50 uV FIGURE 1 2 Offset Correction Settling Time ViN Vout FIGURE 1 3 Output Overdrive Recovery cs ViL ViH ton torr Vout High Z High Z 1 HA 1 pA ls typical 300 pA typical typical 300 HA Iss 2 HA typical 2 pA typical typical 5 pA ICS Vop 5MQ N typical Vpp 5 MQ typical typical FIGURE 1 4 Chip Select MCP6V08 1 4 Test Circuits The circuits used for the DC and AC tests are shown in Figure 1 5 and Figure 1 6 Lay the bypass capacitors out as discussed in Section 4 3 7 Supply Bypassing and Filtering Ry is equal to the parallel combination of Re and Rg to minimize bias current effects VDD 4 uF VIN Rn ta Hr Riso Vout MCP6VOX Par ANN o TE L 100 nF Cia BE DD EN 6 NW AW 4 RG RF L FIGURE 1 5 AC and DC Test Circuit for Most Non Inverting Gain Conditions VOD 4 uF Vpp 3 Rn Hi Riso Vout MCP6VOX Por ANN Oo Vin toon TR oN AN lt Re Re L FIGURE 1 6 AC and DC Test Circuit for Most Inverting Gain Conditions The circuit in Figure 1 7 tests the op amp
41. le positive supply configuration In this case Vss is connected to ground and Vpp is connected to the supply Vpp will need bypass capacitors 34 Chip Select CS Digital Input This pin CS is a CMOS Schmitt triggered input that places the MCP6V08 op amps into a low power mode of operation DS22093A page 18 2008 Microchip Technology Inc MCP6V06 7 8 4 0 APPLICATIONS The MCP6V06 7 8 family of auto zeroed op amps is manufactured using Microchip s state of the art CMOS process It is designed for low cost low power and high precision applications Its low supply voltage low quiescent current and wide bandwidth makes the MCP6V06 7 8 ideal for battery powered applications 4 1 Overview of Auto zeroing Operation Figure 4 1 shows a simplified diagram of the MCP6V06 7 8 auto zeroed op amps This will be used to explain how the DC voltage errors are reduced in this architecture Vin 1 ViN Oo d Crew E O Vout 4 Null Null Input 4 Output Switches Switches Nul e Amp _ J POR Oscillator Null Correct Switches 61 lt Digital Clock 2 7 Control Randomization 2 I CS FIGURE 4 1 Simplified Auto zeroed Op Amp Functional Diagram 4 1 1 BUILDING BLOCKS The Null Amp and Main Amp are designed for high gai
42. lg 6 pA Input Bias Current across Temperature lg 140 pA TA 85 C lg 1500 5000 PA Ta 125 C Input Offset Current los 85 pA Input Offset Current across Temperature los 85 pA Ta 85 C los 1000 190 1000 PA Ta 125 C Common Mode Input Impedance ZcM 103116 Ol IpF Differential Input Impedance ZpiFF 103116 QllpF Common Mode Common Mode Input Voltage Range Vemr Vss 0 20 Vpp 0 20 V Note 2 Common Mode Rejection CMRR 120 136 dB Vpp 1 8V Vom 0 2V to 2 0V Note 1 Note 2 CMRR 130 147 dB Vpp 5 5V Vom 0 2V to 5 7V Note 1 Note 2 Open Loop Gain DC Open Loop Gain large signal AoL 125 147 dB Vpp 7 1 8V Vour 0 2V to 1 6V Note 1 AoL 135 158 dB Vpp 5 5V Vout 0 2V to 5 3V Note 1 Note 1 Set by design and characterization Due to thermal junction and other effects in the production environment these parts can only be screened in production except TC4 see Appendix B Offset Related Test Screens 2 Figure 2 18 shows how Vcyg changed across temperature for the first three production lots DS22093A page 2 2008 Microchip Technology Inc MCP6V06 7 8 TABLE 1 1 DC ELECTRICAL SPECIFICATIONS CONTINUED Electrical Characteristics Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vom Vpp 3 Vout Vpp 2 Vi Vpp 2 RL 20 kQ to V
43. n and accuracy using a differential topology They have an auxiliary input bottom left used for correcting the offset voltages Both inputs are added together internally The capacitors at the auxiliary inputs Cew and CH hold the corrected values during normal operation The Output Buffer is designed to drive external loads at the Vour pin It also produces a single ended output voltage VREF is an internal reference voltage All of these switches are make before break in order to minimize glitch induced errors They are driven by two clock phases 4 and 5 that select between normal mode and auto zeroing mode The clock is derived from an internal R C oscillator running at a rate of fosc 650 kHz The oscillator s output is divided down to the desired rate It is also randomized to minimize spread undesired clock tones in the output The internal POR ensures the part starts up in a known good state It also provides protection against power supply brown out events The Chip Select input places the op amp in a low power state when it is high When it goes low it powers the op amp at its normal level and starts operation properly The Digital Control circuitry takes care of all of the housekeeping details of the switching operation It also takes care of Chip Select and POR events 2008 Microchip Technology Inc DS22093A page 19 MCP6V06 7 8 4 1 2 AUTO ZEROING ACTION Figure 4 2 shows the connections bet
44. ng e 540 7 Contact Pad Width X x 1 060 Contact Pad Length X8 y 155 Notes 1 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing No C04 2057A 2008 Microchip Technology Inc DS22093A page 33 MCP6V06 7 8 NOTES DS22093A page 34 2008 Microchip Technology Inc MCP6V06 7 8 APPENDIX A REVISION HISTORY Revision A June 2008 Original Release of this Document 2008 Microchip Technology Inc DS22093A page 35 MCP6V06 7 8 APPENDIX B OFFSET RELATED TEST SCREENS Input offset voltage related specifications in the DC spec table Table 1 1 are based on bench measure ments see Section 2 1 DC Input Precision These measurements are much more accurate because More compact circuit Soldered parts on the PCB More time spent averaging reduces noise Better temperature control Reduced temperature gradients Greater accuracy We use production screens to ensure the quality of our outgoing products These screens are set at wider lim its to eliminate any fliers see Table B 1 TABLE B 1 OFFSET RELATED TEST SCREENS Electrical Characteristics Unless otherwise indicated Ty 25 C Vip 1 8V to 5 5V Vss GND Vom Vpp 3 Vout Vpp 2 Vi Vpp 2 RL 20 kQ to Vj and CS GND refer to Figure 1 5 and Figure 1 6
45. o the Microchip logo Accuron dsPIC KEELOQ KEELOQ logo MPLAB PIC PICmicro PICSTART PRO MATE rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FilterLab Linear Active Thermistor MKDEV MKLAB SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U S A Analog for the Digital Age Application Maestro CodeGuard dsPICDEM dsPICDEM net dsPICworks dsSPEAK ECAN ECONOMONITOR FanSense In Circuit Serial Programming ICSP ICEPIC Mindi MiWi MPASM MPLAB Certified logo MPLIB MPLINK mTouch PICkit PICDEM PICDEM net PICtail PIC logo PowerCal Powerlnfo PowerMate PowerTool REAL ICE rfLAB Select Mode Total Endurance UNI O WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2008 Microchip Technology Incorporated Printed in the U S A All Rights Reserved I Printed on recycled paper Microchip received ISO TS 16949 2002 certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Company s quality system processes and procedures a
46. oltage FIGURE 2 6 Input Offset Voltage vs Quadratic Temp Co Output Voltage DS22093A page 6 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 V Vpp 2 RL 20 KQ to Vj C 60 pF and CS GND 9 4 I Voo 1 8V n T 40 Samples S 3 Representative Part S 12 Ta 25 C 3 5 Soldered on PCB g 2 5 10 1 8 0 o o 8 gt 0 7 5 6 41 o o 40 C 1 4 o z 25 C 9 po 2 3 85 C 8 2764 125 C d 4 ti 0 7 N N N N 2 d 1 Q2 X oOocgcoccoocoo uudduc Q Q Q Q S e e e e Input Common Mode Voltage V 1 PSRR V V FIGURE 2 7 Input Offset Voltage vs FIGURE 2 10 PSRR Common Mode Voltage with Vpp 1 8V AT ws oe ge lan Samples DD 9 125 C gt 3 Representative Part 85 C 8 45 1 Ta 25 C 2 425 C S 40 Soldered on PCB g 40 C 5 35 14 i 9 30 o gt 0 5 25 8 AL o 20 5 S 15 3 2 10 3 5 5 4 4 a 0 N NN W n W oN w
47. on 4 2 1 1 Phase Reversal The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages Figure 2 43 shows an input voltage exceeding both supplies with no phase inversion 4 2 1 2 Input Voltage and Current Limits The ESD protection on the inputs can be depicted as shown in Figure 4 4 This structure was chosen to protect the input transistors and to minimize input bias current Ig The input ESD diodes clamp the inputs when they try to go more than one diode drop below Vas They also clamp any voltages that go too far above Vpp their breakdown voltage is high enough to allow normal operation and low enough to bypass quick ESD events within the specified limits Bond VoD pad Bond Input Bond _ Vint Pad Stage Pad Vin Bond V ss Pad FIGURE 4 4 Simplified Analog Input ESD Structures In order to prevent damage and or improper operation of these amplifiers the circuit must limit the currents and voltages at the input pins see Section 1 1 Absolute Maximum Ratings T Figure 4 5 shows the recommended approach to protecting these inputs The internal ESD diodes prevent the input pins Vin and Viy from going too far below ground and the resistors R4 and R3 limit the possible current drawn out of the input pins Diodes D4 and D prevent the input pins Viy and Viy from going too far above Vpp and dump any curren
48. op amps 4 3 8 7 Miscellaneous Effects Keep the resistances seen by the input pins as small and as near to equal as possible to minimize bias cur rent related offsets Make the trace capacitances seen by the input pins small and equal This is helpful in minimizing switching glitch induced offset voltages Bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center or the tribo electric effect Make sure the bending radius is large enough to keep the conductors and insulation in full contact Mechanical stresses can make some capacitor types such as ceramic to output small voltages Use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration Humidity can cause electro chemical potential voltages to appear in a circuit Proper PCB cleaning helps as does the use of encapsulants 4 4 Typical Applications 4 4 1 WHEATSTONE BRIDGE Many sensors are configured as Wheatstone bridges Strain gauges and pressure sensors are two common examples These signals can be small and the common mode noise large Amplifier designs with high differential gain are desirable Figure 4 13 shows how to interface to a Wheatstone bridge with a minimum of components Because the circuit is not symmetric the ADC input is single ended and there is a minimum of filtering the CMRR is good enough for moderate common mode noise Vbpp 0 00 3kQ Vpp
49. own Resistor Rep 3 5 MO CS Low Specifications MCP6V08 CS Logic Threshold Low Vi Vss 0 3Vpp V CS Input Current Low les ES 5 PA CS Vss cs High Specifications MCP6V08 CS Logic Threshold High Vin 9 7Vpp Vpp V CS Input Current High los Vpp Rpp pA CS Vpp CS Input High GND Current per las 0 7 WA CS Vop Von 1 8V amplifier mE Iss 2 3 HWA CS Vpp Vpp 5 5V Amplifier Output Leakage CS High lo LEAK 20 pA CS Vpp CS Dynamic Specifications MCP6V08 CS Low to Amplifier Output On ton 11 100 HS CS Low Vgg 0 3 V G 1 VIV Turn on Time Vout 09 Vpp 2 CS High to Amplifier Output High Z torr 10 us CS High Vpp 0 3 V G 1 VI Vout 0 1 Vpp 2 Internal Hysteresis Vuyst 0 25 V TABLE 1 4 TEMPERATURE SPECIFICATIONS Electrical Characteristics Unless otherwise indicated all limits are specified for Vpp 1 8V to 5 5V Vss GND Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range Ta 40 125 C Operating Temperature Range Ta 40 125 c Note1 AA Storage Temperature Range Ta 65 150 C Thermal Package Resistances Thermal Resistance 8L 4x4 DFN Ow 44 CW Note Thermal Resistance 8L SOIC OJA 150 C W Note 1 Operation must not cause T to exceed Maximum Junction Temperature spec
50. re for its PIC MCUs and dsPIC DSCs KEELOQ code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified 2008 Microchip Technology Inc DS22093A page 39 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Duluth GA Tel 678 957 9614 Fax 678 957 1455 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Harbour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chen
51. t 6 BE 0 4 25 25 gt 25 o 5 2 0 8 2 0 5 5 1 5 a 10 pt 6 1 0 415 1 0 05 mmm e 220 a 0 0 5 25 0 0 0 5 10 15 20 25 30 35 40 45 50 Time 200 us div Time us FIGURE 2 42 Input Offset Voltage vs FIGURE 2 45 Non inverting Large Signal Time at Power Up Step Response 7 Vbo 5 5V 5 G 1 gt 2 e 3 o 2 5 gt ya 1 z 5 amp E E 0 1 2 3 4 5 6 7 8 9 10 0 1 5 3 4 5 6 7 8 9 10 Time ms Time us FIGURE 2 43 The MCP6V06 7 8 family FIGURE 2 46 Inverting Small Signal Step shows no input phase reversal with overdrive Response DS22093A page 14 2008 Microchip Technology Inc MCP6V06 7 8 Note Unless otherwise indicated Ta 25 C Vpp 1 8V to 5 5V Vss GND Vem Vpp 3 Vout Vpp 2 VL Vpp 2 R 20 KQ to Vj C 60 pF and CS GND 5 5 r 6 0 6 50 Vop 5 5V 3 G 1 5 0 5 4 5 F GV Vout S 4 0 240 42 o 3 5 2 3 0 S 3 0 3 9 o gt 2 5 9 o 5 2 0 Z 2 0 2 8 e 3 a 15 10 15 E 1 0 o Vour G Vin Vpp 5 5V amp 0 5 0 0 G 100VV
52. t a feedback loop MCP6V06 VIN Ry t NN R R RE 3 T 1kQ 40 Vout m Vpp 20 MCP6541 FIGURE 4 19 Precision Comparator DS22093A page 28 2008 Microchip Technology Inc MCP6V06 7 8 5 0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6V06 7 8 family of op amps 5 1 SPICE Macro Model The latest SPICE macro model for the MCP6V06 7 8 op amps is available on the Microchip web site at www microchip com This model is intended to be an initial design tool that works well in the op amp s linear region of operation over the temperature range See the model file for information on its capabilities Bench testing is a very important part of any design and cannot be replaced with simulations Also simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves 5 2 FilterLab Software Microchip s FilterLab software is an innovative software tool that simplifies analog active filter using op amps design Available at no cost from the Micro chip web site at www microchip com filterlab the Fil ter Lab design tool provides full schematic diagrams of the filter circuit with component values It also outputs the filter circuit in SPICE format which can be used with the macro model to simulate actual filter perfor mance 5 3 Mindi Circuit Designer amp Simulator
53. the railing of the output 4 3 3 SOURCE RESISTANCES The input bias currents have two significant components switching glitches that dominate at room temperature and below and input ESD diode leakage currents that dominate at 85 C and above Make the resistances seen by the inputs small and equal This minimizes the output offset caused by the input bias currents The inputs should see a resistance on the order of 109 to 1 kO at high frequencies i e above 1 MHz This helps minimize the impact of switching glitches which are very fast on overall performance In some cases it may be necessary to add resistors in series with the inputs to achieve this improvement in performance 4 3 4 SOURCE CAPACITANCE The capacitances seen by the two inputs should be small and matched The internal switches connected to the inputs dump charges on these capacitors an offset can be created if the capacitances do not match 4 3 5 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps As the load capacitance increases the feedback loop s phase margin decreases and the closed loop bandwidth is reduced This produces gain peaking in the frequency response with overshoot and ringing in the step response These auto zeroed op amps have a different output impedance than most op amps due to their unique topology When driving a capacitive load with these op amps a series resistor at the ou
54. tput Riso in Figure 4 6 improves the feedback loop s phase margin stability by making the output load resistive at higher frequen cies The bandwidth will be generally lower than the bandwidth with no capacitive load Riso ANN ANN ANN 1 9 Vout C c FIGURE 4 6 Output Resistor Riso Stabilizes Capacitive Loads Figure 4 7 gives recommended Riso values for different capacitive loads and is independent of the gain 10k 8 Gy 2 1k T o o z E 100 S Gy 5 E Gy 10 E 10 TT 1p 10p 100p 1n 10n 100n C F FIGURE 4 7 Recommended Riso values for Capacitive Loads After selecting Rigo for your circuit double check the resulting frequency response peaking and step response overshoot Modify Riso s value until the response is reasonable Bench evaluation and simulations with the MCP6V06 SPICE macro model good for all of the MCP6V06 7 8 op amps are helpful DS22093A page 22 2008 Microchip Technology Inc MCP6V06 7 8 4 3 6 REDUCING UNDESIRED NOISE AND SIGNALS Reduce undesired noise and signals with Low bandwidth signal filters Minimizes random analog noise Reduces interfering signals Good PCB layout techniques Minimiz
55. ts onto Vpp When implemented as shown resistors R4 and R also limit the current through D and Do Vss minimum expected V4 Ape 2mA RoS Vss minimum expected V 2 2 mA FIGURE 4 5 Protecting the Analog Inputs It is also possible to connect the diodes to the left of the resistor R4 and Ro In this case the currents through the diodes D4 and D need to be limited by some other mechanism The resistors then serve as in rush current limiters the DC current into the input pins Viy and Vin should be very small A significant amount of current can flow out of the inputs through the ESD diodes when the common mode voltage Vcy is below ground Vas see Figure 2 17 Applications that are high impedance may need to limit the usable voltage range 4 2 2 RAIL TO RAIL OUTPUT The output voltage range of the MCP6V06 7 8 auto zeroed op amps is Vpp 15 mV minimum and Vas 15mV maximum when R 20kQ is connected to Vpp 2 and Vpp 5 5V Refer to Figure 2 19 and Figure 2 20 for more information These op amps are designed to drive light loads use another amplifier to buffer the output from heavy loads 4 2 3 CHIP SELECT CS The single MCP6V08 has a Chip Select CS pin When CS is pulled high the supply current for the corresponding op amp drops to about 1 pA typical and is pulled through the CS pin to Vss When this happens the amplifier is put into a high impedance state By pullin
56. uct as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ISO TS 16949 2002 Trademarks The Microchip name and log
57. verall Length D 4 00 BSC Exposed Pad Width E2 0 00 2 20 2 80 Overall Width E 4 00 BSC Exposed Pad Length D2 0 00 3 00 3 60 Contact Width b 0 25 0 30 0 35 Contact Length L 0 30 0 55 0 65 Contact to Exposed Pad K 0 20 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Package may have one or more exposed tie bars at ends 3 Package is saw singulated 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 131C 2008 Microchip Technology Inc DS22093A page 31 MCP6V06 7 8 8 Lead Plastic Small Outline SN Narrow 3 90 mm Body SOIC Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging YY yy Yj E1 7 YA YA T Le NOTE 1 1 2 3 b A J H A2 P Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1 27 BSC Overall Height A 1 75 Molded Package Thickness A2 1 25 Standoff A1 0 10 0 25 Overall Width E 6 00 BSC Molded Package Width E1 3 90 BSC Overall
58. ween amplifiers during the Normal Mode of operation b4 The hold capacitor CH corrects the Null Amplifier s input offset Since the Null Amplifier has very high gain it dominates the signal seen by the Main Amplifier This greatly reduces the impact of the Main Amplifier s input offset voltage on overall performance Essentially the Null Amplifier and Main Amplifier behave as a regular op amp with very high gain Ag and very low offset voltage Vos Vint t ViN O m NC Output Buffer Vout VREF CH FIGURE 4 2 Normal Mode of Operation 4 Equivalent Amplifier Diagram Figure 4 3 shows the connections between amplifiers during the Auto zeroing Mode of operation 2 The signal goes directly through the Main Amplifier and the flywheel capacitor Cry maintains a constant correc tion on the Main Amplifier s offset The Null Amplifier uses its own high open loop gain to drive the voltage across C to the point where its input offset voltage is almost zero Because the principal input is connected to Viy the auto zeroing action corrects the offset at the current common mode input voltage Vcy and supply voltage Vpp This makes the DC CMRR and PSRR very high also Since these corrections happen every 50 us or so we also minimize slow errors including offset drift with temperature AVos ATA 1 f noise and input offset aging
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MICROCHIP MCP6V06/7/8 300 A Auto Zeroed Op Amps handbook