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TEXAS INSTRUMENTS UCC2540 handbook

1. vs FREQUENCY 0 Gain 45 90 9 a Phase 135 180 10 100 1k 10k 100k 1M 10M100M f Frequency Hz Figure 34 33 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS G2 Lower Gate Drive 5V div Predictive Delay Adjustment SW Node 5V div gt G2 Lower Gate Drive 5V div SW 500 mV div Synchronous FET Body Diode Conduction t Time 20 ns div Figure 36 Predictive Gate Drive G2 Falling t Time 20 ns div Figure 37 Predictive Gate Drive G2 Falling e G2 Lower Gate Driv Predictive Delay Adjustment t Time 20 ns div Figure 38 Predictive Gate Drive G2 Fallin g Wy TEXAS INSTRUMENTS 34 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 RELATED PRODUCTS UCC28089 Primary Side Push Pull Oscillator e UCC27223 High Efficiency Predictive Synchronous Buck Driver with Enable e UCC3583 Switch Mode Secondary Side Post Regulator e UCC25701 Advanced Voltage Mode Pulse Width Modulator e UCC3808A Low Power Currrent Mode Push Pull PWM UCC38083 4 5 6 8 Pin Current Mode Push Pull PWM with Programmable Slope Compensation REFERENCES 1 Power Supply Seminar SEM 1300 Topic 1 Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications by L Ba
2. 0 PINS DIM A A MIN 4073225 F 10 98 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusions The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane This pad is electrically and thermally connected to the backside of the die and possibly selected leads Falls within JEDEC MO 153 The PowerPAD is not directly connected to any lead of the package It is electrically and thermally connected to the substrate of the device which acts as ground and should be connected to PGND on the PCB The exposed dimension is 1 3 mm x 1 7 mm However the tolerances can be 1 05 mm 0 05 mm 41 mils 2 mils due to position and mold flow variation Dogs Powe Wy TEXAS INSTRUMENTS 36 www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the ti
3. 295 3 30 g L 305 a lt 3 25 315 3 20 325 50 0 50 100 150 50 0 50 100 150 TJ Junction Temperature C Ty Junction Temperature C Figure 25 Figure 26 Ic2c InAMP AND Iss IRamp REGULATOR OUTPUT VOLTAGE vs VS TEMPERATURE 28 TEMPERATURE IG2C IRAMP FRSET 10k0 MOBET O S gt 1 0 gt 74 IG2C IRAMP RRSET 50 0 a 0 9 gt 5 0 8 5 72 5 gt 5 IsS IRAMP RRSET 10 e i amp 7 0 Iss IRAMP RRSET 50 0 6 gt 0 5 6 8 50 0 50 100 150 50 0 50 100 150 Ty Junction Temperature C TJ Junction Temperature C Figure 27 Figure 28 5 INSTRUMENTS www ti com 31 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS TRACKING TO VOLTAGE ERROR AMPLIFIER OFFSET CURRENT ERROR AMPLIFIER OFFSET vs vs TEMPERATURE TEMPERATURE 70 55 gt E 60 5 53 t 2 50 v o 2 5 5 40 5 51 E E lt 30 2 49 n 20 5 gt 8 47 10 4 gt 0 45 50 0 50 100 150 50 0 50 100 150 Ty Junction Temperature C Ty Junction Temperature C Figure 29 Figure 30 THRESHOLD VOLT
4. Figure 21 Seguencing a Multiple Output Post Regulated Power Supply vy TEXAS INSTRUMENTS www ti com 27 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 V Voltage V APPLICATION INFORMATION Regulation loss due to loss of primary line voltage 130 ms Wo 3 3 t Time Figure 22 UDG 04061 Using the TR pin the UCC2540 can be programmed to ratio metrically track another converter output voltagel5 Ratio metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one or more of the outputs lock into regulation The TR pin is easier to use for tracking than the SS pin because the external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery It should be understood that the voltage that is being tracked must lag the bias voltages VDD VDRV and REF on start up and lead the bias voltages during shutdown Furthermore the output that is being tracked must not reach its steady state DC level before the output that is tracking reaches its steady state DC level Figure 23 illustrates the concept of programming an output voltage Vc to ratio metrically track another output Main Power Supply Leader Trader UCC2540 m Tracking Ratio Core Power Supply VM Leader V Tracker VM Leader Tracker V Leader Figure 23 Ratio Metric Tracki
5. Program the G2 time out G2TO duration using equation 1 2 X Vaset G2 Timeout Duration Reset G2C Timer Threshold Farads where e VrRseT 1 5 V typ 1 5 T lt G2 Timeout Duration lt e G2C Timer Threshold 2 5 V typ Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION RAMP pin PWM Modulator and G1 Timer The RAMP pin serves two purposes 1 programming the gain of the PWM modulator and 2 programming the time out duration of G1 in case the main power stage has not caused a SYNC pulse to occur A diagram of the PWM modulator and G1 timer is shown in Figure 9 The UCC2540 has a leading edge modulator that compares the error output with the RAMP voltage The modulator freguency is externally driven through the SYNCIN pin The RAMP pin provides both a sawtooth wave for the PWM comparator and it functions as G1 time out protection that is programmed by Rsgy and the value of the RAMP capacitor A switching cycle begins with the falling edge of the SYNCIN signal which must be LOW for at least 50 nanoseconds The falling edge of SYNCIN generates a 100 ns discharge strobe CLK to the RAMP function and then allows the RAMP capacitor to charge from the 2 x current source PWM PWM 6 2xIRSET VER Comparator Latch RAMP s a 5 D PWM 250 mV Rp ENA e 25V gt G1 Timeout Comparator UDG 04048 Fi
6. which allows a simple resistive divider to scale the secondary transformer voltage in post regulator applications Situations where the line voltage varies more extensively or there is extensive ringing may call for clamping and or additional gain Ground Clamping In applications where a ring or a spike causes SYNCIN to fall below GND protect the pin with a Schottky diode cathode SYNCIN anode GND Overvoltage Clamping The SYNCIN signal may reguire overvoltage clamping in applications where the peak SYNCIN voltage is perilously close to the absolute maximum level of 8 V due to either ringing or voltage levels The REF or VDRV can be used as clamp voltages as in Figure 10 Make sure that REF or VDRV always sources current The reason is that both REF and VDRV are used to detect the mode of operation when they are back driven and they could latch into the wrong operating mode at start up Main Output UCC2540 Auxiliary Output UDG 04049 Figure 10 REF Clamp for SYNCIN Note the REF Load Resistor Ji TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Another overvoltage clamping option is to directly clamp the SYNCIN pin Unfortunately Zener diodes have excessive junction capacitance which causes too much delay in the signal However a base emitter clamp that achieves the desired clamping action can be employed with minimal delay to the SYNCI
7. 1 uF of capacitance if it is used as an input Mode 3 or if it has large or pulsating loads Pin to program timer currents for G2C RAMP SS charge and SS discharge This pin generates a current propor RSET 1 tional to the value of the external resistor connected from RSET pin to GND RSET range is 10 to 50 giv ing a programmable nominal ISET range of 30 uA to 150 respectively ss 11 Soft start shutdown pin Connect capacitor to GND to set the soft start time Add switch to GND for imme diate shutdown functionality SYNCIN Input pin for timing signal SW 17 G1 driver return connection SWS 20 Used by the predictive controller to sense SR body diode conduction Connect to SR MOSFET drain close to the MOSFET package TR 10 Tracking input to the voltage error amplifier Connect to REF when not used VDD 16 Power supply to the device and input to the internal VDRV drive regulator Normal Vpp range is from 4 5 V to 36 V Bypass the pin with at least 1 uF of capacitance VDRV 13 Output of the drive regulator and power supply pin for the G2 driver VDRV is also the supply voltage for the in ternal logic and control circuitry VEA 7 Inverting input of the voltage error amplifier used for output voltage regulation 1 REF is an input in Mode only Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION The UCC2540 is
8. 15V Modulator VEA 1 5V Inverting Amplifier COMP Current Error Amplifier UCC2540 ZFV i CFIR i ZIV i UDG 04052 Figure 6 Error Amplifier Configuration Component selection includes setting the voltage regulation threshold then the current limit threshold as described below Voltage vs Current Programming refer to Figure 6 E VLOAD reg 1 5 V typ R V 1 Determine the ratio LOAb reg vo VygA Threshold Voltage i 1V 1V 2 Sense resistor Rg 1 x where IS max is the current limit level V2 I max Vogayoffset 50 mV typ 3 Arbitrarily select either Ry4 or Ryo so that the smallest of the two resistors is between 6 5 and 20 Then calculate the value of the other resistor using the eguation in the first step If the converter is in a current limit condition and the output voltage falls below half of the regulated output voltage the UCC2540 enters into a hiccup restart retry mode Figure 7 shows typical signals during hiccup mode vy TEXAS INSTRUMENTS www ti com 13 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION swem TET TL B B B B B ETT 3 3V SS G2 UDG 04046 Figure 7 Typical Hiccup Mode waveforms COMP VEA and pins Volt
9. IOUT SINK G1 G2 Source current IOUT SOURCE G1 G2 3 5 Operating junction temperature range TJ 55 to 150 Storage temperature Tstg 65 to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltages are with respect to GND Currents are positive into and negative out of the specified terminal RECOMMENDED OPERATING CONDITIONS NT Reference bypass capacitor CREF VDRV bypass capacitor CyDRV BST SW bypass capacitor CBST SW Junction operating temperature TJ Wy TEXAS INSTRUMENTS 2 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 ORDERING INFORMATION HTSSOP 20 PWP 1 40 C to 105 C UCC2540PWP 1 The PWP package is also available at 70 devices per tube and taped and reeled at 2 000 devices per reel Add an R suffix to the device type i e UCC2540PWPR See the application section of the data sheet for PowerPAD drawing and layout information CONNECTION DIAGRAM PWP PACKAGE TOP VIEW RSET 10 SWS REF 2 BST G2
10. a high efficiency synchronous buck controller that can be used in many point of load applications It can be used as a local controller for cascaded techniques such as post processing converters for isolated integrated bus converters IBC and dc transformer architectures It can also be used as a general purpose secondary side post regulator for high accuracy multiple output power supplies Using UCC2540 as the Secondary Side PWM Controller in the Cascaded Push Pull Buck Two Stage Converter The two stage cascaded push pull buck topology converts higher input bus voltage such as 48 V telecom voltage to sub 2 V output voltages OUTI OUT2 UCC28089 CLOCK RESET Tm Figure 2 Secondary Side Controlled Cascaded Push Pull Buck Converter The primary side power stage is an open loop push pull converter that provides voltage step down and galvanic isolation This takes the high bus voltage and converts it into an intermediate voltage such as 7 V The primary side push pull gate drive signals can come from either off the shelf oscillators or a fully integrated 5096 duty dual output oscillator such as the UCC28089 The secondary side power stage is a buck converter that is optimized for low output voltage regulation The clock reset pulse signal from the primary side is transmitted using a signal transformer vy TEXAS INSTRUMENTS www ti com 3 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION There are many advan
11. ability to easily add independently regulated auxiliary outputs A multiple output implementation of the cascaded push pull buck power converter is shown in Figure 3 Q2 L2 Q4 CLOCK 1 1 RESET UCC28089 UDG 02142 Figure 3 Multiple Output Implementation of Push Pull Buck Cascaded Converter Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Using UCC2540 as the Secondary Side Post Regulator UCC2540 can also be used as a secondary side post regulator SSPR for precision regulation of the auxiliary voltages of multiple output power supplies as shown in Figure 4 The UCC2540 uses leading edge modulation so that it is compatible with either voltage mode or current mode primary side control converters using any topology such as forward half bridge or push pull Q2 H O MAIN OUTPUT a Q6 AUX OUT1 OUTI OUT2 FB UCC3808x UDG 02145 Figure 4 Multiple Output Converter with Primary Side Push Pull Converter 6 INSTRUMENTS www ti com 11 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION CEA and VEA pins Current Limit and Hiccup Mode Typical power supply load voltage versus load current is shown in Figure 5 This figure shows steady state operation for no load to overcurrent shutdown soft start retry is not depicted in the diagram During the voltage
12. apply to resistance values between the power supply output voltage and pin 7 it also does not apply to resistance values between ground and pin 7 The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA pin and the CEA pin during current limit conditions Select the current sense element and the voltage divider ratios for the VEA pin to ground and the CEA pin to ground to provide the desired current limit level Place the same configuration of components in the negative feedback path of the current error amplifier between pins 9 and 8 that are in the negative feedback path of the voltage error amplifier between pins 9 and 7 However use resistors with values that are 67 of the corresponding resistors that are between pins 9 and 7 and use capacitors that 150 of the corresponding capacitors that are between 9 and pin 7 Check the COMP signal If it is unstable place a capacitor or increase the capacitance between pins 9 and 8 in order to attenuate the current ripple Raise the value of the capacitor until the COMP pin voltage becomes stable Compare the COMP voltage with the RAMP voltage With stable operation the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin vy TEXAS INSTRUMENTS www ti com 15 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION RSET RAMP G2C SS pins Programming t
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14. regulation conditions the voltage error amplifier output is lower than the current error amplifier allowing the voltage error amplifier to control operation During the current limit conditions the current error amplifier output is lower than the voltage error amplifier allowing the current error amplifier to control operation The boundary between voltage and current control occurs when the difference between and VEA tries to exceed 50 mV Current limiting begins to occur when the difference between CEA and VEA exceeds 50 mV For currents that exceed this operating condition the UCC2540 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level Then the UCC2540 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft start voltage at 30 of its charging rate UCC2540 inhibits a retry until the soft start voltage falls below 0 5 V A functional diagram of the voltage and current error amplifiers is shown in Figure 6 VREG Limited Current VLOAD Load Voltage V Shutdown ot o mo ILOAD Load Current A UDG 04053 Figure 5 Typical Power Supply Load Voltage vs Current Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION From Power MOSFET Switch Node Rs c RLOAD TR Pus 1 25 R Ry1 rror 0 7V Amplifier H 55 4 VERR to
15. switching region where it is most needed peak output current rating is the combined current from the bipolar and MOSFET transistors The output resistance is the Rps on of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor The output drivers can switch from VDD to GND Each output stage also provides a very low impedance to overshoot and undershoot This means that in many cases external schottky clamp diodes are not reguired The outputs are also designed to withstand 500 mA reverse current without either damage to the device or logic upset For additional information on drive current requirements at MOSFET s Miller plateau region refer to the Power Supply Seminar SEM 1400 2 and the UCC37323 4 5 datasheetl3 Predictive Gate Drive Technology The Predictive Gate Drive technology maximizes efficiency by minimizing body diode conduction It utilizes a digital feedback system to detect body diode conduction and adjusts the deadtime delays to minimize the conduction time interval This closed loop system virtually eliminates body diode conduction while adjusting for different MOSFETs temperature and load dependent delays Since the power dissipation is minimized a higher switching frequency can be utilized allowing for a smaller component size Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET bod
16. 35 0 55 VREF Start threshold voltage MODE 3 Vypp VvDRV 2 7V 2 75 3 00 3 20 MODE 3 2 25 2 50 2 70 MODE 3 0 3 0 5 0 8 Ta 25 C 3 28 3 30 3 32 Total variation 3 2 3 3 3 4 Short circuit current VREF 0 V TA 25 C 10 13 20 Line regulation 5 25 V lt VREF lt 7 2 V 0 1 5 15 Load regulation OmA lt IREFS 5 3 2 5 VVDRV Start threshold voltage VVDRV Stop threshold voltage V VREF Stop threshold voltage VREF Hysteresis VOLTAGE REFERENCE REF VREF Reference output voltage A S PWM RAMP VRAMP Offset voltage 010 0 25 045 Timeout threshold voltage fSYNC 200 kHz 150 175 200 ns RRSET 10 kQ 325 300 275 uA tDEAD G1 deadtime at maximum duty cycle ratio a EN HA IRAMP Ramp charge current CURRENT ERROR AMPLIFIER VCEA Offset voltage Total variation 45 55 GBW Gain bandwidth 3 3 4 EB I N ICOMP 9A VCEA 3 3 V VVEA 2 0 V 50 3 4 0 1 v Low level output volt OL ow level output voltage ICOMP 200 uA VCEA lt 15V d 0 060 083 VEA 1V VOH High level output voltage N N OM 2 25 30 0 80 10 5 0 80 1 0 MV V Vcomp 1 0V VoEgA 1 5 V VVEA 0V 0 0 mA CMR Common mode input range 3 3 Ensured by design Not production tested AVOL Open loop 6 100 140 3 k N ISINK Sink current K Texas INSTRUMENTS 4 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS Vp
17. 39A JUNE 2004 REVISED AUGUST 2004 PIN ASSIGNMENTS TERMINAL yo DESCRIPTION NAME NO BST 19 Floating G1 driver supply VHI is fed by an external Schottky diode during the SR MOSFET on time Bypass BST to SW with an external capacitor CEA 8 Inverting input of the current error amplifier used for output current regulation COMP 9 Output of the voltage and current error amplifiers for compensation G1 18 O High side gate driver output that swings between SW and BST G2 14 O Low side gate driver output that swings between PGND and VDRV 3 Timer pin to turn off synchronous rectifier capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH Ges 12 Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate dead time GND 6 Ground for internal circuitry GND and PGND should be tied to the pc board ground plane with vias PGND 15 Ground return for the G2 driver Connect PGND to the pc board ground plane with several vias RAMP 5 Input pin to connect capacitor to GND to generate the PWM and serve as a maximum duty ratio timer 3 3 V reference pin All internal circuits are powered from this 3 3 V rail Bypass this pin with at least 0 1 uF of REF 1 2 I O capacitance for REF loads that are 0 mA to 1 mA Bypass this with at least
18. AGE SYNC 2 INVERTING AMPLIFIER GAIN AND PHASE TEMPERATURE NS 1 80 B FREQUENCY 0 gt 4145 o 5 5 gt 1 70 s 90 N c a o e 2 1 65 m 135 E E 180 2 1 60 I o 2 225 0 1 55 25 270 1 50 1k 10k 100 k 1M 10M 100M 50 0 50 100 150 f Frequency Hz Ty Junction Temperature C Figure 31 Figure 32 49 5 INSTRUMENTS 32 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS Gain dB lvpp Bias Current mA CURRRENT ERROR AMPLIFIER GAIN AND PHASE VOLTAGE ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY 120 0 120 100 100 Gain 80 45 80 60 60 5 40 90 9 1 40 amp N 20 20 Phase 0 135 0 20 20 40 180 40 10 100 1k 10k 100k 1M 10M 100M f Frequency Hz Figure 33 OPERATING CURRENT DC vs BIAS VOLTAGE 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 Vypp Bias Voltage V Figure 35 3 TEXAS INSTRUMENTS www ti com
19. BE HUCC2540 H MN j 35 TEXAS INSTRUMENTS UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 HIGH EFFICIENCY SECONDARY SIDE SYNCHRONOUS BUCK PWM CONTROLLER FEATURES On Chip Predictive Gate Drive for High Efficiency Synchronous Buck Operation Dual 3 A TrueDrive Outputs 1 MHz High Frequency Operation with 70 ns Delay from SYNCIN to G1 Output Leading Edge Modulation Overcurrent Protection using a Parallel Average Current Mode Control Loop 3 Modes to Support 2 7 V to 35 V Bias Operation Reverse Current Protection for Output Stage User Programmable Shutdown 1 0 Initial Tolerance Bandgap Reference High Bandwidth Error Amplifiers Thermally Enhanced HTSSOP 20 Pin PowerPAD Package SIMPLIFIED APPLICATION DIAGRAM APPLICATIONS Secondary Side Post Regulation SSPR for Multiple Output Power Supplies Cascaded Buck Converters Post Processing Converters for Bus Converter and DC Transformer Architectures DESCRIPTION The UCC2540 is a secondary side synchronous buck PWM controller for high current and low output voltage applications It can be used either as the local secondary side controller for isolated dc to dc converters using two stage cascaded topologies or as a secondary side post regulator SSPR for multiple output power supplies The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi dc output of bus converters or dc transforme
20. C 3 p 4 G1 SYNCIN 4 SW RAMP 5 VDD GND 6 PGND VEA 7 G2 8 VDRV COMP 9 G2S TR 10 55 NOTE PowerPAD is not directly connected to any lead of the package It is electrically and thermally connected to the substrate of the device which acts as ground and should be connected to PGND on the PCB The exposed dimension is 1 3 mm x 1 7 mm However the tolerances can be 1 05 mm 0 05 mm 41 mils 2 mils due to position and mold flow variation THERMAL INFORMATION PACKAGE PACKAGE OJA C W C W C W MAXIMUM DIE FAMILY DESIGNATOR with PowerPAD without PowerPAD with PowerPAD TEMPERATURE PowerPAD 22 3 to 32 6 HTSSOP 20 PWP 500 to O LFM 19 9 14 125 C 49 Texas INSTRUMENTS www ti com 3 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS Vpp 12 V 1 uF capacitor from VDD to GND 1 uF capacitor from BST to SW 1 uF capacitor from REF to GND 0 1 uF 2 2 uF capacitors from VDRV to PGND fsyNciN 200 kHz Ta Ty 40 C to 105 C unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT OVERALL 8 11 13 IVDD Operating current CLOAD 22 nF 9 12 30 m UNDERVOLTAGE LOCKOUT VVDD Start threshold voltage MODE 1 8 0 8 5 9 0 MODE 1 7 5 8 0 8 5 MODE 1 0 3 0 5 0 8 0 4 3 6 Stop threshold voltage Hysteresis MODE 2 4 4 VVDRV Hysteresis MODE 2 0 15 0
21. IN MAX UNIT G1 MAIN OUTPUT Sink resistance Vsw 0Vv 6V Vai 0 5 0 3 0 7 1 3 Source resistance Vsw 0V VBsT 6 V VG1 5 7 V 10 25 45 ISINK Sink current 3 Vow 0 V Vest 6 V VG1 3 0V a Q 3 ISRCE Source current 3 Vsw 0 V Vest 6 V 3 0 3 tRISE Rise time CLOAD 2 2 nF from G1 to SW 12 25 tFALL Fall time CLOAD 2 2 nF from G1 to SW 12 25 G2 SYNCHRONOUS RECTIFIER OUTPUT RSINK Sink resistance VG2 0 3 V 5 15 80 ISINK Sink current 3 3 25 V 3 ISRC Source current 3 3 25 V tRISE Rise time CLOAD 2 2 nF from G2 to PGND tFALL Fall time CLOAD 2 2 nF from G2 to PGND High level output voltage G2 Vsw GND DEADTIME DELAY see Figure 1 tON G1 RAMP rising to G1 rising tOFF G1 SYNCIN falling to G1 falling lON G2 Delay control resolution tOFF G2 3 Ensured by design Not production tested tOFF G1 lt gt SYNCIN Oo VERR N RAMP 2 G1 a lt tON G2 G1 N lt gt 0FF G2 a Voi n 1 Figure 1 Predictive Gate Drive Timing Diagram Wy TEXAS INSTRUMENTS 6 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 FUNCTIONAL BLOCK DIAGRAM ERROR AMPLIFIERS AND FAULT LOGIC VREF VDRV VDD amp PWM LOGIC HIGH SIDE DRIVER PREDICTIVE LOW SIDE DRIVER UDG 04056 vy TEXAS INSTRUMENTS www ti com UCC2540 SLUS5
22. N signal See Figure 11 Simply select Reg and Rcg Reg to give the appropriate O V to 3 3 V signal at low line conditions Then select the ratio of Rcg to Rpg to cause the transistor to turn on when SYNCIN exceeds 4 V Main Output UCC2540 Auxiliary Output UDG 04050 Figure 11 VBE Clamp for SYNCIN SYNCIN Clamping for the Isolated Cascaded Buck Topology The UCC2540 is ideally suited as a secondary side controller for the cascaded buck topology when it is partnered with the UCC28089 primary side start up controller The primary side controller transmits a pulse edge during its dead time The UCC2540 uses the primary side pulse in order to provide zero voltage conditions for primary and secondary side switches The predictive delay feature tunes the secondary side transition to minimize reverse recovery losses in the synchronous rectifier The pulse edge information can vary with the primary side bias voltage and therefore it must be clamped The circuit shown in Figure 12 includes the appropriate pulse edge shaping circuit clamping and 1500 V isolation The recommended transformer COEV part MGBBT 00011 01 is smaller than many opto isolators Primary Ground Secondary Ground 1 1 1 1 1 1 1 1 Sree T1 1 1 UCC28089 UCC2540 R1 Ci 6340 680 pF REF UDG 04051 Figure 12 Isolation and Clamping the SYNCIN Signal for Cascaded Buck Converters vy TEXAS I
23. NSTRUMENTS www ti com 19 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION VDD VDRV VREF and BST pins Modes of Operation Depending on the available bias voltage for the UCC2540 the startup shutdown and restart conditions are different There are three distinct configurations or modes of biasing the UCC2540 The mode is detected and latched into an internal register during power up when VREF crosses 2 V The register is cleared when VDD VDRV and VREF are simultaneously less than 1 V All modes are compatible with either cascaded buck or with secondary side post regulator SSPR topologies The main bias voltage of Modes 1 and 2 can be implemented with a diode and a capacitor from an ac voltage such as the secondary winding of the transformer A summary of the modes and their programming reguirements are listed in Table 1 Table 1 Modes and Programming Reguirements Mode Reguirement Mode VBIAS Bias Pin UVEO ON UVLO OFF at Power Up and Remarks Range V v v 2 1 8 5 to 36 VDD 16 Vvpp 8 5 Vvpp 8 0 Vyoo U and Widest line operation 2 4 75 to 8 5 VDRV 13 VuDRV 4 65 VvDRV 4 3 Vyprv gt Vner Needs regulated bias and low 3 3 0 to 3 6 VREF 2 VREF 3 0 25 Veer gt VTH DONE MOSFETs Mode 1 or normal operation requires the availability of a bias of 8 5 V or higher for the devi
24. Regulator Vin High Side Driver Low Side Driver mE UDG 04039 Figure 14 Mode 1 With Auxiliary Biasing for Bias Voltages Between 8 5 V and 35 V vy TEXAS INSTRUMENTS www ti com 21 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION UCC2540 D2 Rectified Bias 4 75 V lt Vypnv lt 80 V Drive 7 2 v VDD VREF 3 3 V 2 Vin Regulator UDG 04040 Figure 15 Mode 2 With Rectified Biasing for Input Voltages Between 4 75 V and 8 0 V UCC2540 AUX Bias Drive 7 2 V VDD D2 4 75 V lt VypRv lt 8 0 V EJ 0V lt VIN lt 35V Vin l wd U Driver Low Side Driver E UDG 04041 Figure 16 Mode 2 With Auxiliary Biasing for Bias Voltages Between 4 75 V and 8 0 V TEXAS INSTRUMENTS 22 www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION 4 75 V lt V lt 8 0 V Drive 7 2 V DD VDE 0V lt VIN lt 35V Regulator 2 Vin ov 1 LIPPE Q1 wx en ae Driver 5 _ LI Q2 Low Side er LH Low VrH Driver Figure 17 Mode 2 With Auxiliary Biasing for Bias Voltages Between 4 75 8 0 and Low Threshold Power MOSFET Transistors UDG 04042 Regulated 3 3 Vpc Bias Drive 7 2 v VDD 16 4 75 V lt VYDRV lt 8 0 VREF 3 3 V UCC2540 DC or Pulse Train 1 8 V lt o lt 5V Regu
25. acitor Capacitor Capacitor Capacitor 1 C1 gt 50 Ciss C322xC1 C2 gt 0 1 uF C4 gt 1 uF n a 2 C1 2 50 Ciss C322xCl C2 gt 0 1 uF C4 gt 1 uF 2 x C3 C5 gt 2 x C4 3 C1 gt 50 CISS pc gd C2 gt 1 0 uF C4 gt 1uF 2xC1 5 gt 2 04 For Modes 2 3 the VDD filter capacitor C4 in Table 2 must supply the lypp idle current to the UCC2540 approximately 11 mA plus the charge to drive the gates G1 and G2 Capacitor C4 must be large enough to sustain adequate operating voltages during start ups and other transients under the full operational lypp current Knowing the operating frequency and the MOSFET gate charges the average lypp current can be estimated as Ivon lvooride Qa Qaa fs 4 where fs is switching frequency In order to prevent noise problems C4 must be at least 1 uF Furthermore it needs to be large enough to pass charge along to the power MOSFET gates Thus C4 often needs to have at least twice the capacitance of the VDRV filter capacitor as shown in Table 2 24 Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Output Stage The UCC2540 includes dual gate drive outputs and each is capable of 3 A peak current The pull up pull down circuits of the driver are bipolar and MOSFET transistors in parallel High side and low side dual drivers provide a true 3 A high current capability at the MOSFET s Miller Plateau
26. age and Current Error Amplifiers From no load to full rated load operating conditions the UCC2540 operates as a voltage mode controller Above the programmed rated current there are two levels of over current protection constant current limit and overcurrent reset retry This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion Refer to the functional diagram of the voltage and current error amplifiers in Figure 6 The voltage error amplifier in the figure shows three non inverting inputs The lowest of the three non inverting inputs 1 5 V SS and TR is summed with the non inverting input to achieve the voltage error signal The lowest of the two outputs drives the inverting stage which in turn drives the modulator During steady state voltage control operation the feedback elements in the current loop have no effect on the loop stability When current limit occurs the voltage error amplifier effectively shuts OFF and the current error amplifier takes control During steady state current limit operation the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop In order for the current error amplifier to be stable the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier This means
27. ce Here the bias drives the VDD pin The low side drive bias VypRv 7 V is generated from an internal linear regulator and it directly draws current from the VDD pin The high side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin when G2 is HI via a diode between G2 and BST The UCC2540 operates in Mode 1 if Vypp gt Vypgy and Vyper when Vyper rises above 2 V Mode 1 permits the widest range of bias voltages operational from 8 5 V Vypp 35 V This mode is compatible with systems that have 12 Vpc bias supply already available Alternatively Mode 1 is particularly useful for applications where the input line voltage varies over a wide range and the bias is to be derived directly from the reflected line voltage such as in Fig 13 Mode 2 is suitable for applications where the bias is typically 5 V between 4 5 V and 8 0 V The bias voltage is applied to the VDRV terminal of the UCC2540 The high side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin when G2 is HI Bias voltage to the VDD pin is obtained through an external voltage doubler charge pump If the system uses low threshold voltage power MOSFETs VDD can be directly tied to the VDRV pin The bias voltage could be either a bus converter output or an auxiliary supply or the reflected converter input voltage that originates from a regulated source Mode 3 is for synchronous buck converter applicati
28. e In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits UCC2540 is available in the 20 pin HTSSOP PowerPAD package The PowerPADTM HTSSOP 20 PWP offers the most effective means of removing the heat from the semiconductor junction and therefore long term reliability improvement As illustrated in 5 the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package This pad is soldered to the copper on the PC board directly underneath the device package reducing the 6jc down to 2 C W Data is presented in 5 to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem as summarized in 6 to realize a significant improvement in heat sinking over standard non PowerPAD surface mount packages 30 Wy TEXAS INSTRUMENTS www ti com VvREF Reference Voltage V UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS OUTPUT REFERENCE VOLTAGE RAMP CURRENT vs vs TEMPERATURE TEMPERATURE 3 40 275 RRSET 10 285 3 35 lt
29. e selected when designing the voltage control loop 3 Test if necessary when Vy lt 1 5 V or ArGy gt 1 a is needed set GT2 so that both equations 8 and 9 apply R Gy 1 5 i Ree so that both of the following apply 1 5 V Gro v x and Grp gt A x Gy b If Gro is not needed set 1 4 Set _ Hr G Gro 5 Select Ryo so that RT2 Ry4 Rye to minimize offset differences Ai TEXAS INSTRUMENTS www ti com 10 11 29 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 R RFI R Gp 1 3 Re Main i Power i Use stage if ArGy gt 10Rif Supply M VMGT1 lt 1 5Vat Leader steady state TLV271 ES Rectified Secondary Voltage UCC2540 J TR G1 SN Dz RT2 3 3V ss eal Rye Ru Ry i Determined by voltage loop design D7 needed only if VyGT4GT2 gt 3V mas n S TS N UDG 04059 Figure 24 Programming the UCC2540 to Track Another Output More elaborate power supply seguencing and tracking can easily be implemented by extending the above technigues Consult reference 5 for further information THERMAL INFORMATION The useful temperature range of a controller that contains high current output drivers is greatly affected by the drive power reguirements of the load and the thermal characteristics of the device packag
30. ented with this configuration using a minimum number of external components During a power up transient the converter output tracks the lower of the SS voltage the TR voltage or a 1 5 V internal reference provided the system is not in current limit In other words the voltage control loop is closed during power up provided the system is not current limited Figure 20 shows the UCC2540 configured for soft start operation For applications that do not use the tracking feature connect the TR pin to either SS or REF as shown in the figure Remote shutdown and seguential power up can be easily implemented as a transistor switch across UCC2540 REF 3 3 V Voltage Error Amplifier 1 33x IRSET COMP To Positive Input of Current Error Amplifier UDG 04045 Figure 20 Using the Soft Start Feature 26 3 TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION The soft start interval begins when the UCC2540 recognizes that the appropriate voltage see Mode 1 2 or 3 is above the UVLO level The voltage of Css then linearly increases until it is clamped at the REF voltage of 3 3V Regulation should be reached when the soft start voltage reaches about 2 2 V 1 5 V plus a diode drop Select a Css capacitor value using equation 5 to program a desired soft start duration Atss V At Coc 1 33 x RSET y 155 _ 193 x 15V x Alss Farads m Rset Rge
31. gure 9 PWM Modulator and G1 Time Out Comparator Low line or brownout conditions can cause the primary side duty ratio to approach 100 where parasitic converter impedances may temporarily impair the guality of the SYNCIN pulse The RAMP timing function terminates the G1 pulse when the RAMP voltage exceeds 2 5 V The duration of the RAMP timing function should be set as follows V 2 TA RSET gt RAMP PWM papp timeout threshold voltage 2 where Ts switching period e Vaset 1 5 typ e PWM Ramp 2 5 V typ sampo qs Gain PWM modulator gt 0 4 m In order to use the G1 Timer feature the peak RAMP voltage at the end of a switch cycle should be as close to 2 5 V as the Cramp and Reset tolerances allow In other words the PWM modulator gain should be programmed to be equal to or slightly greater than 0 4 inverse V vB TEXAS INSTRUMENTS www ti com 17 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION SYNCIN pin A falling edge applied to the SYNCIN pin generates a narrow pulse that is the base timer for internal UCC2540 functions The SYNCIN pulse must be HI for at least 100 ns preceding the falling edge and LOW for at least 50 order to be registered as a valid pulse Due to the critical nature of the timing avoid filtering the falling edge of the SYNCIN signal in order to avoid signal delay The peak SYNCIN voltage can easily range from between 2 5 V and 6 6 V
32. he Timer Currents Set the base current to the timers with a resistor between RSET and GND The block diagram of the UCC2540 shows the interaction of the RSET pin and the dependent current sources for the RAMP G2C and SS features The RSET pin is a voltage source the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP gain 2 G2C gain 2 and SS charge gain 1 33 net discharge gain 0 4 The resistance applied to the RSET pin and GND should be in the range of 10 lt Raset lt 50 RAMP G2C and SS timers are programmed by the selection of capacitors tied between each of their respective pins and GND G2C pin G2 Timer G2 Timeout Comparator G1D G2TO G1 with delay but not blanked UDG 04047 Figure 8 Functional diagram of the G2 Timer The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation Flgure 8 shows the functional diagram This function is programmed by connecting a capacitor between the G2C pin and GND The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin For best results program the typical G2 time limit to be between 1 5 and 3 times the switching period T Notice that when the G2 timer reaches its limit both G1 and G2 are forced to a LOW output This feature prevents the current in the output inductor from excessive negative excursions during zero duty ratio conditions
33. lator J High Side Low VTH Driver Low Side Low VTH Driver UDG 04043 Figure 18 Mode 3 With Regulated 3 3 Vpc Bias 9 TEXAS INSTRUMENTS www ti com 23 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Charge Pump Capacitor Selection Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2540 to pass charge to the MOSFET gates of Q1 and 2 all reference designators in this section refer to the schematics in Figure 13 through Figure 18 This section gives guidelines on selecting the values of C1 through 5 so that the converter functions properly Specific capacitor values may need to be larger than the recommended value due to MOSFET characteristics diode D1 D4 characteristics and closed loop converter performance All three modes of operation require a charge pump capacitor and diode C1 and D1 in order to drive the high side power MOSFET Modes 2 and 3 reguire additional charge pump capacitors and diodes in order to supply voltage to VDD In general all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed The charge pump capacitors should be ceramic capacitors with low effective series resistance ESR such as or X7R capacitors The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance the voltage level of the Miller plateau threshold the forward dro
34. logh C Bridge and B Andreycak SLUP118 2 Power Supply Seminar SEM 1400 Topic 2 Design And Application Guide For High Speed MOSFET Gate Drive Circuits by L Balogh SLUP133 Datasheet UCC27223 High Efficiency Predictive Synchronous Buck Driver SLUS558 Datasheet UCC37323 4 5 Dual 4 A Peak High Speed Low Side Power MOSFET Drivers SLUS492A 5 Power Supply Seminar SEM1600 Topic 2 Seguencing Power Supplies in Multiple Voltage Rail Environments by D Daniels D Gehrke and M Segal SLUP224 6 Technical Brief PowerPAD Thermally Enhanced Package SLMA002 7 Application Brief PowerPAD Made Easy SLMA004 8 Datasheet TPS3103K33 Ultra Low Supply Current Supply Voltage Supervisory Circuits SLVS363 9 Application Note A Revolutionary Power Management Solution for Highly Efficient Multiple Output Applications by Bill Andreycak SLUA255 10 Application Note Predictive Gate Drive FAO by Steve Mappus SLUA285 vy TEXAS INSTRUMENTS www ti com 35 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 MECHANICAL DATA PWP R PDSO G PLASTIC SMALL OUTLINE 20 PINS SHOWN Thermal Pad See Notes D and F 0 15 NOM i Gage Plane v THEN i Seating Plane 1 20 MAX nas 7 zx 0 10 4
35. me of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government reguirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction
36. ng Tra ker simultaneous ratio metric UDG 04061 28 Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION The general circuit to program the UCC2540 to track the leader supply voltage by the tracking ratio is shown in Figure 24 To program the tracking profile gains Gr and Gro follow the ratio metric tracking design procedure that is listed below The special case of simultaneous sequencing for Vyp gt 1 5V is the simplest to design set Rr1 Ry4 and Ryo Gro is not needed In many other cases the circuit can be simplified with the removal of the operational amplifier for Gro and the Zener clamping diode If an operational amplifier is necessary it should be capable of rail to rail operation and usually low voltage bias the TLV271 is an inexpensive solution for both of those requirements Notice that the tracking circuit in Figure 24 also has a soft start capacitor Css The soft start capacitor is useful for limiting the time between short circuit retry attempts and it can prevent overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply Ratio Metric Tracking Design Procedure see Figures 21 and 22 1 Determine the tracking ratio Ar M C A T My where Mc and are the soft start slopes of Vc and Vy respectively 2 Determine Gy R G V2 Ry Ry where Ryo and Ry4ar
37. ons where the bias voltage is a regulated 3 3 V source This is a common main output voltage in multiple output power converters The bias voltage is applied to the VREF pin of the UCC2540 The UCC2540 operates in Mode if it detects gt VvprRv and VDD when Vyggr rises above 2 V Assorted combinations of modes and biasing schemes are shown in Figure 13 through Figure 18 In Mode 1 and Mode 2 the bias voltage can either be an independent auxiliary supply or it can be generated by rectifying and filtering the reflected line voltage as shown in Figure 13 through Figure 16 A regulated auxiliary supply must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2540 In Mode 3 the regulated auxiliary supply can be independent of the power supply input voltage as shown in Figure 18 or the regulated auxiliary supply can be the same source as the power supply input voltage 20 Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Rectified Bias 8 5 V lt Vypp lt 35 V lt ov JU 8 5 V lt VIN lt 35 V UCC2540 D2 Drive 7 2 v VDD Regulator Regulator High Side Driver Low Side Driver UDG 04038 Figure 13 Mode 1 With Rectified Biasing for Input Voltages Between 8 5 V and 35 V AUX Bias UCC2540 Drive 7 2 v VDD 8 5 lt Vypp lt 35 V Regulator 16 VREF 3 3 V 2 0V lt VIN lt 35V
38. p 12 V 1 uF capacitor from VDD to GND 1 uF capacitor from BST to SW 1 uF capacitor from REF to GND 0 1 uF and 2 2 uF capacitors from VDRV to PGND fsyNciN 200 kHz TA Ty 40 C to 105 C unless otherwise noted VOLTAGE ERROR AMPLIFIER Threshold voltage VEA to COMP 0 C lt TA lt 105 C 1 485 1 500 1 515 PEN E ee Total variation 1 47 150 153 47 1 147 150 153 1 53 GEW Hm ICOMP 0 VCEA 1 75 V VyEA 2 0 V ICOMP 200 VcEgA 0 V VvEA 1 V VTR 0V V 20V High level output voltage joh voe S s 0 Vi z 1 0 V 0 V i 4 COMP CEA P ISINK Sink current 4 VEA 1 5V 0 35 080 170 CURRENT SET IOUT Output current RRSET 10 158 150 142 VRSET RsET voltage RRSET 10 kQ 142 1 50 1 58 SYNCHRONIZATION AND SHUTDOWN TIMER SYNCIN G2C Timer threshold 23 25 27 ssa VoL Low level output voltage SOFT START SS DRIVE REGULATOR VDRV Sonome pue G2S GATE DRIVE SENSE SWS GATE DRIVE SENSE Pd as ai v 3 Ensured by design Not production tested 35 TEXAS INSTRUMENTS www ti com 5 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS Vpp 12 V 1 uF capacitor from VDD to GND 1 uF capacitor from BST to SW 1 uF capacitor from REF to GND 0 1 uF and 2 2 uF capacitors from VDRV to PGND fsyNciN 200 kHz Ta Ty 40 C to 105 C unless otherwise noted PARAMETER TEST CONDITIONS M
39. p of D1 and the closed loop response time The unloaded high side gate driver typically draws 2 nC of charge per rising edge plus 30 LA of direct current from C1 Usually the unloaded high side gate driver load is miniscule compared to the gate charge reguirements of the high side power MOSFET 1 Typical values for C1 are approximately 50 to 100 times the input capacitance of MOSFET Q1 This usually allows for transient operation at extremely large duty ratio where C1 does not have sufficient time to fully recharge If C1 is excessively large its ESR and ESL prevents it from recharging during transients including the start up transient Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of the UCC2540 Selection guidelines are shown in Table 2 Keep in mind that each converter design may require adjustments for larger capacitor ratios than those that are suggested in Table 2 The selection process begins at the left side of Table 2 and progresses towards the right side of the table which is the reverse order of the charge flow during the first few cycles of start up If iteration is reguired in the design process review the progression of the capacitors in the order from left to right that is shown in the table Table 2 Charge Pump and Bias Capacitor Selection Guidelines Mode High Side Drive VDRV Filter VREF Filter VDD Filter VDD Charging Capacitor gt 0 1 uF Cap
40. rs For higher efficiency it also incorporates the Predictive Gate Drive technology that virtually eliminates body diode conduction losses in synchronous rectifiers Main Output O UDG 04057 Predictive Gate Drive TrueDrive and are a trademarks of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include i testing of all parameters EXAS INSTRUMENTS www ti com Copyright O 2004 Texas Instruments Incorporated UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 A Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet DESCRIPTION CONT The UCC2540 is available in the extended temperature range of 40 C to 105 C and is offered in thermally enhanced PowerPAD 20 pin HTSSOP PWP package This space saving package with standard 20 pin TSSOP footprint has a drastically lower thermal resistance of 1 4 C W to accommodate the dual high current drivers on board ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 2 COMP G2C RAMP SS TR 0 3 to 3 6 V Sink current peak
41. t 22V 6 If a UVLO fault is encountered both outputs of the UCC2540 are disabled and the soft start pin SS is discharged to GND The UCC2540 does not retry until the UVLO fault is cleared Using the TR pin the UCC2540 can be programmed to track another converter output voltage If the voltage to be tracked is between 0 V and 3 3 V simply connect the TR pin to the voltage to be tracked with a resistor that is approximately equal to the DC impedance that is connected to the VEA terminal Ry Ryo in Figure 6 If the voltage is above that range use a voltage divider again with an equivalent resistance that approximately equals the DC impedance that is connected to the VEA terminal Other strategies can be used to achieve sequential ratiometric or simultaneous power supply trackingl 4 An implementation of sequential sequencing of a multiple output power 5 is shown in Figure 21 Applications where the loads include a processor with a core voltage of 1 5 V and I O ports that require 3 3 V can require sequential sequencing in order to resolve system level bus contention problems during start up In this circumstance the core must power up first then after an initialization period of 130 ms the ports are allowed to power up V From Transformer Secondary 0v UCC2540 TR j I O 33V 58 02 ai TPS3103K33 REsETVDD GND PFO B m 1 6 vH MR 10 Du Gi 95 4 1 UDG 04061
42. tages to this secondary side control circuit The simple isolated power stage does not reguire any feedback across the isolation boundary Since the primary side oscillator is free running there is no need for an isolated start up power supply This high freguency circuit provides soft switching operation for all sik MOSFET switches optimum transformer core utilization and minimizes filter reguirements because there are no additional high current inductors The push pull primary side permits simple direct drive control of the input stage MOSFETs In exchange it requires that the input MOSFETs are rated to at least twice the peak input line voltage This configuration works well for 36 V to 72 V input line applications because there are many suitable power MOSFETs available in the range of 150 V For applications with larger input voltages a half bridge or full bridge with alternating modulation might be more suitable for an input stage Thus the cascaded topology has a large degree of flexibility with input power stages The cascaded topology also has flexibility in the output stages as well For additional information on this topology refer to Power Supply Seminar SEM 1300 Topic 1 Unigue Cascaded Power Converter Topology for High Current Low Output Voltage Applications 1 The topic discusses the operating principles design trade offs and critical design procedure steps UCC2540 in Multiple Output Power Supplies One such flexibility is an
43. that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path Capacitance is really an admittance value rather than an impedance value This concept is illustrated in Figure 6 In order for the current loop to be stable in Figure 6 Z y must be less than Zry over all frequencies This can be achieved if Rrj lt Rey and Cr gt Cry Wy TEXAS INSTRUMENTS www ti com UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION Another issue that can occur during current limit operation is modulator stability In order for the modulator to be stable the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin This can be met either in the selection of the ratio of Zjy to IZryll or by the addition of a capacitor in parallel to Rg and such as in Figure 6 Stable Dynamic Current Loop Design refer to Figure 6 1 Using any favorite approach design the voltage error amplifier for stable voltage mode design Use at least 15 for any resistors in the negative feedback path of the voltage error amplifier between pins 9 and 7 This does not
44. y diode which reduces reverse recovery losses seen in the main high side MOSFET Finally the lower power dissipation results in increased reliability Predictive Logic UDG 02149 Figure 19 For additional information on Predictive Gate Drive control and efficiency comparisons to earlier adaptive delay and adaptive control techniques refer to the UCC27223 datasheet 3 6 INSTRUMENTS www ti com 25 UCC2540 SLUS539A JUNE 2004 REVISED AUGUST 2004 APPLICATION INFORMATION VDD and IDD Although guiescent VDD current is low total supply current is higher depending on output gate drive requirements and the programmed oscillator frequency Total VDD current lypp is the sum of quiescent VDD current and the average output currents of G1 and G2 as described in equation 3 Knowing the operating frequency and the MOSFET gate charge average driver output current per gate can be calculated from 5 where fgis switching freguency To prevent noise problems connect a 1 uF ceramic capacitor between the VDD and GND pins Place the 1 uF ceramic capacitor as close to the UCC2540 as possible This capacitor is in addition to any electrolytic energy storage capacitors that may be used in the bias supply design Soft Start and Tracking Features Separate pins are provided for the soft start feature and the tracking feature Soft start or tracking seguencing can be easily implem

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