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ANALOG DEVICES AD9806 Manual

1. Register Map SDATA IEEE NEN AN Nee Rr Re je ts e REGISTER LOADED ON SL RISING EDGE Figure 8 Serial WRITE Operation DUMMY BITS IGNORED A2 ns os ons X D8 X D9 X XX XX Figure 9 16 Bit Serial WRITE Operation REV 0 09806 REGISTER DESCRIPTION a A REGISTER Modes of Operation Power On Default Value 11 al a Modes 0 0 ADC MODE 0 1 AUX MODE 1 0 AUXMID MODE 1 1 CCD MODE f F REGISTER AUXMID Mode PGA Default 00 0 f9 f8 f7 f6 5 f4 f3 f2 1 f0 AUXMID Gain 312 1 0 0 000000 0 4dB Gain 1023 1 1 1 1 1 1 1 1 1 1 14dB Only the 9 LSBs of F REG are used to adjust gain f F REGISTER AUX Mode PGA Default 00 0 b B REGISTER Output Modes Default 00 bl b0 09 D8 D7 D5 D4 D2 0 0 Normal 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 High Impedance c C REGISTER Clock Modes Default 00 0 SHP SHD Clock Pulses Clamp Active Pulses 0 0 Active Low Active Low 0 Active Low Active High 1 10 Active High Active Low 1 l Active High Active High d D REGISTER Power Down Modes Default 00 Modes di d0 Description Normal 0 0 Normal Operation High Speed 0 1 High Speed AUX ADC MODE Power Downl 1 0 Reference Stand By Same Mode as STBY Pin 18 Power Down2 1 1 Total Shu
2. in this configuration SDATA O 0 1pF VOUT2 VOUTI 0 1pF V 0 1pF 0 1 1 0 0 1pF o esp ed ed BH e o noax 2u E 29872275 u Vpp 1 T 8 sH V En E 0 1pF 4 ACVDD s3 0 1pF 45 CLPBYP 32 ACVSS 31 liu AD9806 NC lin ae 0 1pF ae CLPREF 28 rj 0 1pF V a NC ET DIGITAL 11 D9 MSB DIN 26 l 9 SIGNAL 12 DRVDD CLPOUT 25 5 0 1HF INPUT A m z o lt gt 0 1pF Vov 20 21 22 23 24 3 V V OipF CLPDM v SHD DDO SHP CLPOB PBLK NC NO CONNECT ADCCLK Figure 10 CCD Mode Circuit Configuration Used in AD9803 Socket REV 0 11 09806 Vpp SCK O SL 0 1pF VOUT2 VOUTI 1 0pF V 1 0 0 1pF AD9806 DIGITAL 9 MSB OUTPUT DATA DRVDD x m z o 8 a JII JO 2 VppO V V CLPDM y SHD DD O SHP 0 1pF CLPOB NC CONNECT ADCCLK O Vpp 0 1 pF Figure 11 CCD Mode Circuit Configuration Using Minimum External Components OUTLINE DIMENSIONS Dimensions shown in inches and mm 48 Lead LQFP ST 48 0 063 1 60 MAX 0 030 0 75 0 018 0 45 TOP VIEW PINS DOWN COPLANARITY 0 003 0 08 S 0 FMN la 0 008 0 2 0 019 0 5 0 011 0 27 0 004 0 09 BSC 0 006 0 17 0 057 1 45 ry 1 0 053 1 35 on 3 0 006 0 15 SEAT
3. valid register contents All registers default to 0s on power up except for the A register which defaults to 11 Thus on power up the AD9806 defaults to CCD mode with the 8 bit DACs powered down Dur ing the power up phase it is recommended that SL be HIGH and SCK be LOW to prevent accidental register write operations SDATA may be unknown The RNW bit Read Not Write must be LOW for all write operations to the serial interface and HIGH when reading back from the serial interface registers REV 0 09806 Table I AD9806 AD9803 Pin Differences APPLICATION INFORMATION Grounding and Decoupling Recommendations As shown in Figure 10 a single ground plane is recommended for the AD9806 This ground plane should be as continuous as possible particularly around Pins 25 through 37 This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins All decoupling capacitors should be located as close as possible to the package pins A single clean power supply is recommended for the AD9806 but a separate digital driver supply may be used for DRVDD Pin 12 DRVDD should always be decoupled to DRVSS Pin 13 which should be connected to the analog ground plane The advantages of using a separate digital driver supply include using a lower volt age 2 7 V to match levels with a 2 7 V ASIC reducing digital power dissipation and reduc
4. 1 ACVSS P Analog Ground 32 CLPBYP AO CDS Bypass 0 1 to Ground 33 ACVDD P Analog Supply 3 V 34 AUXIN AI AUX MODE Input 35 AUXMID AI AUXMID MODE Input 36 ADCIN AI ADC MODE Input 37 CMLEVEL AO Common Mode Level 0 1 uF to Ground 39 DACI AO DACI Output 40 DAC2 AO DAC2 Output 41 SL DI Serial I F Load Signal 42 SCK DI Serial I F Clock 43 ADVDD P Analog Supply 3 V 44 SDATA DI Serial I F Input Data 45 ADVSS P Analog Ground 46 SUBST Analog Ground 47 VRB AO Bottom Reference 0 1 UF to Ground and 1 uF to 48 VRT AO Top Reference 0 1 uF to Ground NOTE Type AI Analog Input AO Analog Output DI Digital Input DO Digital Output P Power 6 REV 0 09806 TIMING SPECIFICATIONS CCD N N 1 N 2 N 3 N 4 SHP SHD lip ADCCLK top ADCCLK RISING EDGE PLACEMENT 1 2 ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP 3 RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP 4 OUTPUT LATENCY IS 9 CYCLES 5 ACTIVE LOW CLOCK PULSE MODE IS SHOWN Figure 1 CCD MODE Timing VIDEO INPUT ADCCLK je Do D9 _ Xs XK NOTE EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE Figure 2 AUX AUXMID ADC Mode Timing EFFECTIVE BLANKING EFFECTIVE PIXELS OPTICAL BLACK INTERVAL DUMMY BLACK PIXELS CLPDM o NOTES CLPOB P
5. 33 34 dB BLACK LEVEL CLAMP Clamp Level Selected through Serial Interface E Reg E Reg 00 32 LSB E Reg 01 48 LSB CLP2 E Reg 10 64 LSB CLP3 E Reg 11 16 LSB SIGNAL TO NOISE RATIO Low PGA Gain 74 dB TIMING SPECIFICATIONS Pipeline Delay 9 Cycles Internal Clock Delay typ 3 ns Inhibited Clock Period 10 ns Output Delay top 14 5 16 ns Output Hold Time 6 ns ADCCLK SHP SHD Clock Period 47 55 6 ns ADCCLK High Level Low Level 20 28 ns SHP SHD Minimum Pulsewidth 10 14 ns SHP Rising Edge to SHD Rising Edge 20 28 ns NOTES Input signal characteristics defined as follows 500 TRANSIENT 1V MAX 200mV MAX INPUT OPTICAL SIGNAL RANGE BLACK PIXEL Use equations on page 8 to calculate gain 5SNR 20 logy Full Scale Voltage RMS Output Noise 420 pF loading timing shown in Figure 1 Internal aperture delay for actual sampling edge Specifications subject to change without notice REV 0 AD9806 SPECIFICATIONS AUX MODE SPECIFICATIONS to ty AVDD DVDD 3 0 V 18 MHz unless otherwise noted Parameter Min Typ Max Unit POWER CONSUMPTION Normal D Reg 00 50 mW High Speed D Reg 01 95 mW MAXIMUM CLOCK RATE Normal D Reg 00 18 MHz High Speed D Reg 01 28 6 MHz PGA Gain Selected through Serial Interface F Reg Max Input Range 700 mV p p Max Output Range 1000 mV p p Gain Control Resolution 7 Bits Gai
6. 67 895 1023 PGA GAIN REGISTER CODE Figure 5a PGA Gain Curve for CCD Mode 0 4V 4 dB TO 14dB 512 to Code 1023 the curve follows a linear in dB shape In AUXMID Mode the PGA provides a gain range of 4 dB to 14 dB programmable with 9 bit resolution The exact PGA gain for either mode can be calculated for any Gain Register value by using the following equations AUXMID MODE Code Range Gain Equation dB 512 1023 Gain 20 logy 146 code 1170 code 4 14 11 8 S 1 z i5 lt amp 2 1 4 512 639 767 895 1023 PGA GAIN REGISTER CODE Figure 5b PGA Gain Curve for AUXMID Mode MIDSCALE PGA GAIN REGISTER Figure 6 AUXMID Mode Circuit Block Diagram REV 0 09806 SERIAL INTERFACE SPECIFICATIONS Pe a fe a a CLAMP POWER DOWN CLOCK OUTPUT OPERATION LEVEL MODES MODES MODES MODES PGA GAIN LEVEL SELECTION DAC1 INPUT Ew mj m m DAC2 INPUT DONT mo eke OPERATION AND POWER DOWN MODES A A 3 EST Ea a OPERATION MODES b OUTPUT MODES c CLOCK MODES d POWER DOWN MODES e CLAMP LEVEL f PGA GAIN g0 g7 h0 h7 j 9 DAC1 INPUT h DAC2 INPUT j EVEN ODD OFFSET m DAC1 AND DAC2 CORRECTION POWER DOWN NOTE MODES2 REGISTER BIT D1 MUST BE SET TO ZERO Figure 7 AD9806 Internal
7. ANALOG DEVICES Complete 10 Bit 18 MSPS CCD Signal Processor FEATURES Pin Compatible with Industry Standard AD9803 18 MSPS Correlated Double Sampler CDS Low Noise PGA with 0 dB to 34 dB Gain Range Low Noise Clamp Circuits Analog Preblanking Function 10 Bit 18 MSPS A D Converter AUX Input with Input Clamp and PGA Direct ADC Input with Input Clamp AUXMID Input with PGA 3 Wire Serial Interface for Digital Control Two Auxiliary 8 Bit DACs 3 V Single Supply Operation Low Power 65 mW 2 7 V Supply 48 Lead LOFP Package APPLICATIONS Camcorders 8 mm and DVC Digital Still Cameras PRODUCT DESCRIPTION The AD9806 is a complete analog signal processor for CCD applications It features an 18 MHz single channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays The AD9806 s signal chain consists of an input clamp correlated double sampler CDS digitally programmable gain amplifier PGA black level clamp and 10 bit A D converter Additional input modes are provided for processing analog video signals The internal registers are programmed through a 3 wire serial digital interface Programmable features include gain adjust ment black level adjustment input configuration and power down modes The AD9806 operates from a single 3 V power supply typically dissipating 75 mW Packaged in a space saving 48 lead LOFP the AD9806 is specified over an operat
8. ING 0 002 0 05 PLANE 12 REV 0 C02197 2 5 1 01 rev 0 PRINTED IN U S A
9. MHz A D CONVERTER Resolution 10 Bits Differential Nonlinearity DNL 0 5 1 0 LSB No Missing Codes GUARANTEED Full Scale Input Voltage 1 0 VOLTAGE REFERENCE Reference Top Voltage VRT 2 0 Reference Bottom Voltage VRB 1 0 Specifications subject to change without notice DIGITAL SPECIFICATIONS orvon 2 1 v 20 pr Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Vin 2 1 Low Level Input Voltage 0 6 High Level Input Current 10 Low Level Input Current I 10 uA Input Capacitance 10 LOGIC OUTPUTS High Level Output Voltage 2 mA 2 2 Low Level Output Voltage 2 mA Vor 0 5 V SERIAL INTERFACE TIMING Figure 7 Maximum SCLK Frequency 10 MHz SDATA to SCLK Setup tps 10 ns SCLK to SDATA Hold 10 ns SLOAD to SCLK Setup tris 10 ns SCLK to SLOAD Hold 10 ns Specifications subject to change without notice REV 0 09806 CCD MODE SPEC IFICATIONS to Tia AVDD DVDD 3 0 V fabccik fsup fsup 18 MHz unless otherwise noted Parameter Min Typ Max Unit POWER CONSUMPTION Vpp 2 7 65 mW 3 0 75 mW 3 3 85 mW MAXIMUM CLOCK RATE 18 MHz CDS Gain 0 dB Allowable CCD Reset Transient 500 mV Max Input Range before Saturation 1000 mV p p PGA Gain Control Resolution 10 Bits Gain Range See Figure 5a for Gain Curve Low Gain Code 95 1 0 1 dB Max Gain 1023 32
10. N Same as AUX MODE MAXIMUM CLOCK RATE Same as AUX MODE ACTIVE CLAMP Same as AUX MODE TIMING SPECIFICATIONS Same as AUX MODE Specifications subject to change without notice DAC SPECIFICATIONS DAC1 and DAC2 Parameter Min Typ Max Unit RESOLUTION 8 Bits MIN OUTPUT 0 1 MAX OUTPUT VDD 0 1 CURRENT LOAD 1 mA MAX CAPACITIVE LOAD 500 pF Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Parameter With Respect To Min Max Unit AVDD1 AVDD2 AVSS 0 3 3 9 DVDD1 DVDD2 DVSS 0 3 3 9 DRVDD DRVSS 0 3 3 9 Digital Outputs DRVSS 0 3 DRVDD 0 3 V SHP SHD DATACLK DVSS 0 3 DVDD 0 3 V CLPOB CLPDM PBLK DVSS 0 3 DVDD 0 3 SCK SL SDATA DVSS 0 3 DVDD 0 3 VRT VRB CMLEVEL AVSS 0 3 AVDD 0 3 CCDIN CLPOUT CLPREF CLPBYP AVSS 0 3 AVDD 0 3 Junction Temperature 150 Lead Temperature 10 sec 300 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9806KST 20 to 85 C Thin Plastic Quad Flatpack LQFP ST 48 THERMAL CHARACTERISTICS Thermal Resistance 48 Lead LQFP Package Oya 92 C CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD9806 features proprietary ESD protection circuitry permanent damage may occur on devices subject
11. ULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE 20 OB PIXELS ARE RECOMMENDED CLPDM PULSEWIDTH SHOULD BE AT LEAST ips WIDE PBLK IS NOT REQUIRED BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p p CLPDM OVERWRITES PBLK ACTIVE LOW CLAMP PULSE MODE IS SHOWN Figure 3 CCD MODE Clamp Timing REV 7 09806 TIMING SPECIFICATIONS Continued VIDEO SIGNAL INPUT H SYNC INTERNAL CLAMPING CLAMP INTERVAL OCCURS DURING SYNC AD9806 INTERNAL SIGNAL sae NOTE The AD9806 uses an automatic video clamp that senses the most negative in the input signal and uses this level to set the clamp voltage As shown in the video waveform above the SYNC level will be clamped to the black level specified in the E Register Figure 4 AUX MODE and ADC MODE Clamp Operation PGA GAIN CURVE DETAILS In CCD Mode the AD9806 PGA stage provides a gain range of 0 dB to 34 dB programmable with 10 bit resolution through the serial digital interface The PGA gain curve is divided into two separate regions When the PGA Gain Register code is between 0 and 511 the curve follows a 1 x 1 x shape which is similar to a linear in dB characteristic From Code CCD MODE Code Range Gain Equation dB 0 511 Gain 20 logy 658 code 658 code 2 4 512 1023 0 0354 code 2 4 34 28 22 z lt 16 9 a 10 4 2 0 127 255 383 511 639 7
12. ed to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality REV 0 WARNING SI ESD SENSITIVE DEVICE 09806 PIN CONFIGURATION al lt 850 B lt 40 gt gt lt lt 2 48 46 45 44 43 42 41 40 39 38 37 PIN 1 IDENTIFIER AD9806 TOP VIEW Not to Scale PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Type Description See Figures 10 and 11 for Circuit Configurations 1 15 24 NC No Connect Should be Left Floating or Tied to Ground 2 11 D0 D9 DO Digital Data Outputs 12 DRVDD P Digital Driver Supply 3 V 13 DRVSS P Digital Driver Ground 14 DVSS P Digital Ground 16 ADCCLK DI ADC Sample Clock Input 17 DVDD P Digital Supply 3 V 18 STBY DI Power Down Mode Active High Internal Pull Down Enables Reference Standby Mode 19 PBLK DI Pixel Blanking 20 CLPOB DI Black Level Restore Clamp 21 SHP DI CCD Reference Sample Clock Input 22 SHD DI CCD Data Sample Clock Input 23 CLPDM DI Input Clamp 25 CLPOUT AO CDS Bypass 0 1 uF to Ground 26 CCDIN AI CDS Input Pin Connect to CCD Input Signal through 0 1 uF Capacitor 27 NC No Connect Should Be Left Floating or May Be Shorted to Pin 26 28 CLPREF AO CDS Bypass 0 1 uF to Ground 29 30 38 NC No Connect Should Be Left Floating Tied to Ground or Decoupled to Ground 3
13. ing potential noise coupling Using the AD9806 in AD9803 Sockets The AD9806 may be easily used in existing AD9803 designs without any circuit modifications Most of the pin assignments are the same for both ICs Table I outlines the differences The circuit of Figure 10 shows the necessary connections for the AD9806 when used in an existing AD9803 socket If the two auxiliary DACs are not used then Pins 39 and 40 and DAC2 may be grounded If the AUX or ADC modes are needed then the input signal should be connected to either AUXIN or ADCIN through a 0 1 capacitor in the same way that CCDIN is used with the input signal Pin No AD9803 AD9806 Circuit Connection 1 NC NC Ground 15 ACLP NC Ground 24 NC NC Ground 25 CCDBYP2 CLPOUT Decoupled with 0 1 to Ground 27 PIN NC Shorted to Pin 26 28 CCDBYP2 CLPREF Decoupled with 0 1 uF to Ground 29 PGABYPI NC Decoupled with 0 1 uF to Ground 30 PGABYP2 NC Shorted to Pin 29 35 AUXCONT AUXMID Ground or decoupled with 0 1 uF to Ground 38 VTRBYP NC Decoupled with 0 1 uF to Ground Using the AD9806 in New Designs Figure 11 shows the recommended circuit for using the AD9806 in new designs Three external decoupling capacitors have been removed from the circuit shown in Figure 9 one from Pin 29 one from Pin 38 and one from between Pins 47 and 48 Note that the decoupling capacitors for Pins 47 VRB and 48 VRT must be increased to 1 0 UF when used
14. ing temperature range of 20 to 85 C FUNCTIONAL BLOCK DIAGRAM PBLK CLPDM Q N 3 W INTF ADCIN AUXIN AUXMID REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices CLPOB OdB 34dB CRM E p CLAMP OdB 15dB AD9806 DOUT 4 14dB SHP SHD ADCCLK One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2001 AD9806 SPECIFICATIONS GENERAL SPECIFICATIONS to AVDD DVDD 3 0 V 18 MHz unless otherwise noted Parameter Min Typ Max Unit TEMPERATURE RANGE Operating 20 85 Storage 65 150 POWER SUPPLY VOLTAGE For Functional Operation 2 7 3 6 Analog Digital Digital Driver POWER CONSUMPTION Selected through Serial Interface D Reg Normal Operation D Reg 00 Specified Under Each Mode of Operation High Speed AUX Mode D Reg 01 Specified Under AUX Mode Reference Standby D Reg 10 5 mW Total Shut Down Mode D Reg 11 1 mW MAXIMUM CLOCK RATE Specified Under Each Mode of Operation
15. n Range Min Gain Code 128 2 dB Max Gain Code 255 15 dB ACTIVE CLAMP Clamp Level Selected through Serial Interface E Reg E Reg 00 32 LSB E Reg 01 48 LSB CLP2 E Reg 10 64 LSB CLP3 E Reg 11 16 LSB TIMING SPECIFICATIONS Pipeline Delay 9 Cycles Internal Clock Delay typ Output Delay top 14 5 16 ns Output Hold Time tgo p 7 ns NOTES 120 pF loading timing shown in Figure 2 Specifications subject to change without notice AUXMID MODE SPECIFICATIONS to Tu AVDD DVDD 3 0 V fyoccux 18 MHz unless otherwise noted Parameter Min Typ Max Unit POWER CONSUMPTION 50 mW MAXIMUM CLOCK RATE 18 MHz PGA Gain Selected through Serial Interface F Reg Max Input Range 700 mV p p Max Output Range 1000 mV p p Gain Control Resolution 9 Bits Gain Range See Figure 5b for Gain Curve Min Gain Code 512 4 Gain Code 1023 14 MIDSCALE OFFSET LEVEL MAX PGA GAIN 462 512 562 LSB TIMING SPECIFICATIONS Pipeline Delay 9 Cycles Internal Clock Delay typ Output Delay top 14 5 16 ns Output Hold Time tuor 7 ns NOTES 120 pF loading timing shown in Figure 2 Specifications subject to change without notice 4 REV 0 09806 ADC MODE SPECIFICATIONS T to AVDD DVDD 3 0 V 18 MHz unless otherwise noted Parameter Min Typ Max Unit POWER CONSUMPTIO
16. t Down e E REGISTER Clamp Level Selection Default 00 el 0 Clamp Level CLP 0 0 0 32 LSBs CLP 1 0 1 48 LSBs CLP 2 1 0 64 LSBs CLP 3 1 1 16 LSBs f F REGISTER CCD Mode PGA Default 00 0 f9f8 f7f6f5f4 f3f2f1 f0 CCD Gain Gain 0 000000 000 0 Minimum 1023 1 1 11 11 1 1 1 1 Maximum 10 f9 f8 f7 f6 f5 f4 f3 f2 AUX Gain Gain 128 100 0 0 0 0 0 Minimum Gain 255 1 1 1 1 1 1 1 1 Maximum g G REGISTER DACI Input Default 00 0 g7 g6 g5 g4 23 22 gl 20 DACI1 Output Code 0 00000000 Code 255 1 1 1 1 1 1 1 1 Minimum Maximum h H REGISTER DAC Input Default 00 0 h7 h6 h5 h4 h3 h2 hi h0 DAC2 Output Code 0 00000000 Minimum Code 255 1 1 1 1 1 1 1 1 Maximum 0 J REGISTER Even Odd Offset Correction Default 0 jo Even Odd Offset Correction Offset Correction In Use 1 Offset Correction Not Used m M REGISTER DAC1 and DAC2 PDN Default 0 m0 Power Down of 8 Bit DACs 8 Bit DACs Powered Down 1 8 Bit DACs Operational NOTE With the exception of a write to the PGA register dur ing AUX mode all data writes must be 10 bits During an AUX mode write to the PGA register only 8 bits of data are required If more than 14 SCK rising edges are applied during a write operation additional SCK pulses will be ignored see Figure 9 All reads must be 10 bits to receive

ANALOG DEVICES AD9806 Manual

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