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National Semiconductor COP8SG Family 8-Bit CMOS ROM Based OTP Microcontrollers with 8k to 32k Memory Two Comparators USART handbook(1)

1. SK 10131733 FIGURE 29 MICROWIRE PLUS SPI Mode Interface Timing Normal SK Mode SK Idle Phase being Low www national com 44 12 0 MICROWIRE PLUS continued SK 10131734 FIGURE 30 MICROWIRE PLUS SPI Mode Interface Timing Alternate SK Mode SK Idle Phase being Low SK Bit 7 Out so 10131735 FIGURE 31 MICROWIRE PLUS SPI Mode Interface Timing Normal SK Mode SK Idle Phase being High SK so SI 10131731 FIGURE 32 MICROWIRE PLUS SPI Mode Interface Timing Alternate SK Mode SK Idle Phase being High A we4 968409 45 www national com COP8SG Family 13 0 Memory Map All RAM ports and registers except A and PC are mapped into data memory address space Address Contents S ADD REG 0000 to 006F On Chip RAM bytes 112 bytes 0070 to 007 Unused RAM Address Space Reads As All Ones xx80 to xx93 Unused RAM Address Space Reads Undefined Data xx94 Port F data register PORTFD xx95 Port F configuration register PORTFC xx96 Port F input pins read only PORTFP xx97 to xxAF Unused address space Reads Undefined Data xxBO Timer T3 Lower Byte xxB1 Timer T3 Upper Byte xxB2 Timer T3 Autoload Register T3RA Lower Byte xxB3 Timer T3 Autoload Register T3RA Upper Byte xxB4 Timer T3 Autoload Register T3RB Lower Byte xxB5 Timer T3 Autoload Register T3RB Upper Byte xxB6 Timer T3 Control Register xxB7 Comparator Select Regist
2. Hi Z Input Leakage Voc 5 5V 2 2 Input Pullup Current Voc 5 5V Vin OV 40 250 G and L Port Input Hysteresis Voc 5 5V 0 25 Voc V 7 www national com 958402 COP8SG Family DC Electrical Characteristics continued 40 lt T4 lt 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Output Current Levels D Outputs Source Voc 4 5 3 3V 0 4 mA Voc 27V 1 8V 0 2 mA Sink Voc 4 5V Vor 1 0V 10 mA Voc 2 7V VoL 0 4V 2 mA All Others Source Weak Pull Up Mode Voc 4 5V 2 7V 10 0 110 Voc 2 7V 1 8V 2 5 33 Source Push Pull Mode Voc 4 5 3 3V 0 4 mA Voc 27V 1 8 0 2 mA Sink Push Pull Mode Voc 4 5V Vor 0 4V 1 6 mA Voc 2 7V Vor 0 4V 0 7 mA TRI STATE Leakage Voc 5 5V 2 Allowable Sink Current Pin Note 9 D Outputs and LO to L3 15 mA All Others 3 mA Maximum Input Current without Latchup Room Temp 200 Note 7 RAM Retention Voltage Vr 2 0 V Voc Rise Time from a Voc gt 2 0V Note 10 12 Hs EPROM Data Retenton Note 8 Note 9 T 55 C gt 29 years Input Capacitance Note 9 pF Load Capacitance on D2 Note 9 pF AC Electrical Characteristics 40 C lt 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Instruction Cycle Time tc Crystal Resonator External 4 5V lt
3. T1 and MICROWIRE PLUS control register contains the following bits T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1CO Timer T1 Start Stop control in timer modes 1 and 2 T1 Underflow Interrupt Pending Flag in timer mode 3 MSEL Selects G5 and G4 as MICROWIRE PLUS signals SK and SO respectively IEDG External interrupt edge polarity select 0 Rising edge 1 Falling edge 511 amp SLO Select the MICROWIRE PLUS clock divide by 00 2 01 4 1x 8 PSW Register Address X 00EF TIPNDA TIENA EXPND BUSY EXEN GIE Bit 7 Bit 0 The PSW register contains the following select bits HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag Autoreload RA in mode 1 T1 Underflow in Mode 2 T1A capture edge in mode 3 T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable enables interrupts The Half Carry flag is also affected by all the instructions that affect the Carry flag The SC Set Carry and R C Reset Carry instructions will respectively set or clear both the carry flags In addition to the SC and R C instructions ADC SUBC RRC and RLC instructions affect the Carry and Half Carry flags ICNTRL Register Address X 00E8 Reserved LPEN TOPND TO
4. EXchange A with Memory X AAIX LD LoaD A with Memory A Meml LD LoaD with Memory X LD B Imm LoaD B with Immed B Imm LD Mem Imm LoaD Memory Immed Mem Imm LD Reg Imm LoaD Register Memory Immed Reg Imm A B A X A B A Xt B Imm EXchange A with Memory B EXchange A with Memory X LoaD A with Memory B LoaD A with Memory X LoaD Memory B Immed CLeaR A BC B 1 AO X X X 1 lt B amp B 1 1 B B 1 www national com 50 14 0 Instruction Set Continued VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP INCrement A DECrement A Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration A A 1 A A 1 A ROM A lt BCD correction of A follows ADC SUBC C gt A7 gt gt A0 gt C C A7 A0 C HC A0 7 4 lt gt 0 C 1 lt 1 lt 0 HC 0 IF C is true do next instruction If C is not true do next instruction SP lt SP 1 AC SP SP A
5. Lu 2 Other functions of the ENUR register include saving the ninth bit received in the data frame enabling or disabling the USART s attention mode of operation and providing addi tional receiver transmitter status information via RCVG and XMTG bits The determination of an internal or external clock source is done by the ENUI register as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts A control flag in this register can also select the USART mode of operation asynchronous or synchronous WAKE UP LOGIC PRESCALER REGISTER E BAUD REGISTER X INTERRUPT INTERRUPT X XMIT CLOCK CLOCK SELECT RECV CLOCK CK 10131739 FIGURE 21 USART Block Diagram 8 2 DESCRIPTION OF USART REGISTER BITS ENU USART Control and Status Register Address at OBA PEN 9 CHL1 CHLO ERR RBFL PSELO 8 1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers ENU ENUR and ENUI Bit 7 Bit 0 www national com 28 8 0 USART Continued PEN This bit enables disables Parity 7 and 8 bit modes only Read Write cleared on reset PEN 0 Parity disabled 1 Parity enabled PSEL1 PSELO Parity select bits Read Write cleared on reset PSEL1 0 PSELO 0 PSEL1 0 PSELO 1 Odd Parity if Parity enabled Even Parity if Parity enabled PSEL1 1 PSELO
6. 10131726 FIGURE 19 Wakeup from IDLE www national com 26 7 0 Power Saving Features continued 7 3 MULTI INPUT WAKEUP The Multi Input Wakeup feature is used to return wakeup the device from either the HALT or IDLE modes Alternately Multi Input Wakeup Interrupt feature may also be used to generate up to 8 edge selectable external interrupts Figure 20 shows the Multi Input Wakeup logic The Multi Input Wakeup feature utilizes the L Port The user selects which particular L port bit or combination of L Port bits will cause the device to exit the HALT or IDLE modes The selection is done through the register WKEN The reg ister WKEN is an 8 bit read write register which contains a control bit for every L port bit Setting a particular WKEN bit enables a Wakeup from the associated L port pin The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge low to high transition or a negative edge high to low transition This selection is made via the register WKEDG which is an 8 bit control register with a bit assigned to each L Port pin Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin Resetting the bit selects the trigger condition to be a positive edge Changing an edge select entails several steps in order to avoid a Wakeup condition as a result of the edge change First the associated WKEN bit
7. 5 5V 2 7V Voc lt 4 5V us R C Oscillator Internal 4 5V Vec lt 5 5V Hs Frequency Variation Note 9 4 5V Voc lt 5 5V 96 External Clock Duty Cycle Note 9 fr Max 55 Rise Time Note 9 fr 10 MHz Ext Clock 8 ns Fall Time Note 9 fr 10 MHz Ext Clock 5 ns MICROWIRE Setup Time tyws Note ns 11 MICROWIRE Hold Time Note ns 11 MICROWIRE Output Propagation Delay 220 ns tupp Note 11 Input Pulse Width Note 9 Interrupt Input High Time 1 tc Interrupt Input Low Time 1 tc Timer 1 2 3 Input High Time 1 tc Timer 1 2 3 Input Low Time 1 tc Reset Pulse Width 1 Hs Note 3 tc Instruction cycle time www national com AC Electrical Characteristics continued Note 4 Maximum rate of voltage change must be lt 0 5 V ms Note 5 Supply and IDLE currents are measured with CKI driven with a square wave Oscillator External Oscillator inputs connected to and outputs driven low but not connected to a load Note 6 The HALT mode will stop CKI from oscillating in the R C and the Crystal configurations In the R C configuration CKI is forced high internally In the crystal or external configuration is TRI STATE Measurement of Ipp HALT is done with device neither sourcing nor sinking current with L F C GO and G2 G5 programmed as low outputs and not driving a load all outputs programmed low and not driving a load all inputs tied to Vcc clock monitor disa
8. 10 2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable Each maskable interrupt has an associated enable bit and pending flag bit The pending bit is set to 1 when the interrupt condition occurs The state of the interrupt enable bit com bined with the GIE bit determines whether an active pending flag actually triggers an interrupt All of the maskable inter rupt pending and enable bits are contained in mapped con trol registers and thus can be controlled by the software A maskable interrupt condition triggers an interrupt under the following conditions 1 The enable bit associated with that interrupt is set 2 The GIE bit is set 3 The device is not processing a non maskable interrupt f a non maskable interrupt is being serviced a maskable interrupt must wait until that service routine is completed An interrupt is triggered only when all of these conditions are met at the beginning of an instruction If different maskable interrupts meet these conditions simultaneously the highest priority interrupt will be serviced first and the other pending interrupts must wait Upon Reset all pending bits individual enable bits and the GIE bit are reset to zero Thus a maskable interrupt condi tion cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit When enabling an interrupt the user should consider whether or not a previously activa
9. 16 BIT AUTO RELOAD REGISTER TIME 1 16 BIT TIMER COUNTER 16 BIT AUTO RELOAD REGISTER TIME 2 TIMER UNDERFLOW INTERRUPT nTepzam z gt gt 10131746 FIGURE 15 Timer in PWM Mode In this mode the input pin TxB can be used as an indepen dent positive edge sensitive interrupt input if the TxENB control flag is set The occurrence of a positive edge on the TxB input pin is latched into the flag Figure 16 shows a block diagram of the timer in External Event Counter mode Note The PWM output is not available in this mode since the TxA pin is being used as the counter input clock 16 BIT AUTO RELOAD REGISTER ON TIME 16 BIT TIMER COUNTER 16 BIT AUTO RELOAD REGISTER OFF TIME TxB DX To Interrupt Control FIGURE 16 Timer in External Event Counter Mode TIMER UNDERFLOW INTERRUPT EXT CLK TxA DK rrzwmmaz EDGE SELECTOR LOGIC gt gt o 10131747 6 2 3 Mode 3 Input Capture Mode Each device can precisely measure external frequencies or time external events by placing the timer block Tx in the input capture mode In this mode the reload registers serve as independent capture registers capturing the contents of the timer when an external event occurs transition on the timer input pin The capture registers can be read while maintaining count a feature that lets the user measure elapsed time and time between events By saving the timer valu
10. Nim Semiconductor COP8SG Family 8 Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory Two Comparators and USART General Description The COP8SG Family ROM and OTP based microcontrollers are highly integrated COP8 Feature core devices with 8k to 32k memory and advanced features including Analog comparators and zero external components These single chip CMOS devices are suited for more complex applica tions requiring a full featured controller with larger memory low EMI two comparators and a full duplex USART COP8SGx7 devices are 100 form fit function compatible OTP One Time Programmable versions for use in produc tion or development of the COP8SGx5 ROM October 2001 Erasable windowed versions Q3 are available for use with a range of COP8 software and hardware development tools Family features include an 8 bit memory mapped architec ture 15 MHz CKI with 0 67 us instruction cycle 14 inter rupts three multi function 16 bit timer counters with PWM full duplex USART MICROWIRE PLUS two analog com parators two power saving HALT IDLE modes MIWU idle timer on chip R C oscillator high current outputs user se lectable options WATCHDOG 4 clock oscillator modes power on reset 2 7V to 5 5V operation program code se curity and 28 40 44 pin packages Devices included in this datasheet are RAM i i Pack Ti Device Memory bytes bytes Pins ackages emperature 28 DIP SO
11. 1 usr 1 140 76 14001 8 449X 009X 449x 009x uv 9 usr 9 940 75 940 01 6 448 008 449 009 uv 6 usr S 940 2588 84001 Ol dr 00 00 al v v VH1O 730 25 40 006 00 v dr usr 40 25 64001 44 008 4 00 2 dnr usr 2 240 25 4001 El dr Jj4lX 001X 441X 001 e dn dnr usr 140 2588 140 vi dn 440X 000X 330X 000x iako 0 usr 0 25 040 75 040 2 88 9 2 196 uononauisu 0771 www national com 53 COP8SG Family www national com 54 15 0 Mask Options See Section 5 5 ECON CONFIGURATION REGISTER 16 0 COP8 Tools Overview National is engaged with an international community of in dependent 3rd party vendors who provide hardware and software development tool support Through National s inter action and guidance these tools cooperate to form a choice of tools that fits each developer s needs This section provides a summary of the tool and develop ment kits currently available Up to date information selec tion guides free tools demos updates and purchase
12. 45 8692 8500 National 2900 Semiconductor Dr www national com cop8 Europe Tel 49 0 180 530 8585 Fax 49 0 180 530 8586 Hong Kong Distributors Worldwide The following companies have approved COP8 programmers in a variety of configurations Contact your vendor s local office or distributor and request a COP8FLASH update You can link to their web sites and get the latest listing of approved programmers at www national com cop8 Advantech American Reliance BP Microsystems Data I O Dataman EE Tools Hi Lo Systems ICE Technology KANDA Lloyd Research Logical Devices Minato MQP Needhams Phyton SMS Data 1 Stag Programmers System General and Tribal Microsystems 17 0 REVISION HISTORY Date Section Summary of Changes October 2001 Electrical Characteristics Added spec for comparator enable time Changed comparator response time to 600 ns Comparators Added note regarding comparator enable time 57 www national com 958402 COP8SG Family Physical Dimensions inches millimeters unless otherwise noted e 44X 0 25 186 5 5 8 Tao 4 3 40X 0 5 0000000000 DIMENSIONS ARE IN MILLIMETERS 5 8 RECOMMENDED LAND PATTERN 1 1 RATION WITH PKG SOLDER PADS c 0 1 MAX PIN 1 INDEX AREA 020 pi ib pi MAX u D 2 D 0 D D 2 3 0 1 D D D D 1 44 0 25 0 0
13. If the VIS instruction is located between 01FF and 02DF Hex then the vector table is located between addresses 02 and 02 Hex and so on Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space Each vector occupies two bytes of the vector table with the higher order byte at the lower address The vectors are arranged in order of interrupt priority The vector of the maskable interrupt with the lowest rank is located to OyEO higher order byte and OyE1 lower order byte The next priority interrupt is located at OyE2 and OyE3 and so forth in increasing rank The Software Trap has the highest rank and its vector is always located at OyFE and OyFF The number of interrupts which can become active defines the size of the table Table 6 shows the types of interrupts the interrupt arbitration ranking and the locations of the corresponding vectors in the vector table The vector table should be filled by the user with the memory locations of the specific interrupt service routines For ex 35 www national com 958402 COP8SG Family 10 0 Interrupts Continued ample if the Software Trap routine is located at 0310 Hex then the vector location OyFE and OyFF should contain the data 03 and 10 Hex respectively When a Software Trap interrupt occurs and the VIS instruction is executed the program jumps to the address specified
14. SP SP 1 PU lt VU PL lt VL PC lt ii ii 15 bits 0 to 32k PC9 0 lt i i 12 bits lt r is 31 to 32 except 1 SP PL SP 1 PU SP 2 PC lt ii SP PL SP 1 PU SP 2 PC9 0 lt i PL lt ROM SP 2 PL lt SP PU SP 1 SP 2 PL lt SP PU lt SP 1 skip next instruction SP 2 PL lt SP PU lt SP 1 GIE1 SP lt PL SP 1 PU SP 2 PC lt OFF PC lt PC 1 51 www national com 958402 COP8SG Family 14 0 Instruction Set continued 14 7 INSTRUCTION EXECUTION TIME Most instructions are single byte with immediate addressing mode instructions taking two bytes Most single byte instructions take one cycle time to execute Skipped instructions require x number of cycles to be skipped where x equals the number of bytes in the skipped instruction opcode See the BYTES and CYCLES per INSTRUCTION table for details Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte cycle Arithmetic and Logic Instructions Instructions Using A amp C 3 4 2 3 1 3 3 5 2 5 1 3 1 5 1 5 1 5 1 5 RPND 1 1 1 7 1 1 Memory Transfer Instructions Register Direct Immed Register Indirect Indirect Auto Incr amp Decr B X B B X X X A Note 18 1 1 1 3 2 3 1 2 1 3 LD A Note 1
15. derfined data 5 5 ECON CONFIGURATION REGISTER For compatibility with COP8SGx7 devices mask options are defined by an ECON Configuration Register which is pro grammed at the same time as the program code Therefore the register is programmed at the same time as the program memory The format of the ECON register is as follows Bit7 x This is for factory test The polarity is Don t Care Bt6 1 Power on reset enabled 0 Power on reset disabled Bt5 1 Security enabled Bits 4 3 2 0 0 External CKI option selected G7 is avail able as a HALT restart and or general pur pose input CKI is clock input R C oscillator option selected G7 is avail able as a HALT restart and or general pur pose input CKI clock input Internal R C components are supplied for maximum R C frequency 1 0 Crystal oscillator with on chip crystal bias resistor disabled G7 CKO is the clock generator output to crystal resonator Crystal oscillator with on chip crystal bias resistor enabled G7 CKO is the clock gen erator output to crystal resonator WATCHDOG feature disabled G1 is a gen eral purpose 1 0 WATCHDOG feature enabled G1 pin is WATCHDOG output with weak pullup Force port compatibility Disable port F outputs and pull ups This is intended for compatibility with existing code and Mask ROMMed devices only This bit should be 17 www national com 958402 COP8SG Family 5 0 Functi
16. 0 Mark 1 if Parity enabled PSEL1 1 PSELO 1 Space 0 if Parity enabled XBIT9 PSELO Programs the ninth bit for transmission when the USART is operating with nine data bits per frame For seven or eight data bits per frame this bit in conjunction with PSEL1 selects parity Read Write cleared on reset CHL1 CHLO These bits select the character frame format Parity is not included and is generated verified by hardware Read Write cleared on reset CHL1 0 0 0 The frame contains eight data bits CHL1 0 CHLO 1 The contains seven data bits 1 1 CHLO 0 The frame contains nine data bits CHL1 1 CHLO 1 Loopback Mode selected Trans mitter output internally looped back to receiver input Nine bit framing format is used ERR This bit is a global USART error flag which gets set if any or a combination of the errors DOE FE PE occur Read only it cannot be written by software cleared on reset RBFL This bit is set when the USART has received a complete character and has copied it into the RBUF register It is automatically reset when software reads the character from RBUF Read only it cannot be written by software cleared on reset TBMT This bit is set when the USART transfers a byte of data from the TBUF register into the TSFT register for trans mission It is automatically reset when software writes into the TBUF register Read only bit is set to one on reset it cannot be written by sof
17. 10 4 5 F2 y o COMP1IN 9 11 11 5 6 F3 VO COMP10UT 10 12 12 6 7 F4 COMP2IN 13 13 7 8 F5 y o COMP2IN 14 14 8 9 F6 COMP2OUT 15 15 9 10 F7 VO 16 16 10 11 CO 39 43 37 38 40 44 38 39 C2 O 1 1 39 40 C3 VO 2 2 40 41 C4 VO 21 15 16 C5 22 16 17 C6 y o 23 17 18 C7 VO 24 18 19 Vec 6 8 8 2 3 GND 23 33 37 31 32 CKI 5 4 7 1 2 RESET 24 34 38 32 33 G1 operation as WDOUT is controlled by ECON bit 2 www national com 968409 COP8SG Family 2 1 Ordering Information COP8 XX B 7 20N 8 XXX 8 Bit Control Oriented Processor Feature Indicator Memory Size 1k G 16k B 2k H 20k C 4k K 24k E 8k R 32k F 12k Memory Type 5 ROM 6 Mask RAM 7 OTP EPROM 9 EEPROM FLASH 0 ROMless ROM Code Temp Range 3 Room Temp only for lab use 6 Extended 559 to 125 7 Automotive 40 to 125 8 Industrial 409 to 85 9 Commercial 0 to 70 Pin Count and Package Type D Ceramic DIP L Ceramic PLCC M SOIC N DIP Q Windowed Package DIP PLCC DIE Scribed Die DWF Die in Wafer Form VEJ 44 pin PQFP 10131708 FIGURE 2 Part Numbering Scheme www national com 3 0 Electrical Characteristics Total Current out of GND Pin Sink 110 mA Absolute Maximum Ratings note 2 Storage Temperat re If Military Aerospace specified devices are required Range 65 C to 140 C please contact the
18. 100 frame trace 32k s w breaks Enhanced User Interface Met aLink Debugger Includes COP8 NSDEV power supply DIP emulation cables COP8 DM xx Metalink COP8 Debug Module for OTP ROM COP8 Families Windows based development and real time in circuit emulation tool with 100 frame trace 32k s w breaks Basic User Interface MetaLink Debugger and COP8 OTP Programmer with sockets Includes COP8 NSDEV power supply DIP and or SMD emulation cables and adapters COP8 IM MetaLink iceMASTER for OTP ROM COP8 devices Windows based full featured real time in circuit emulator with 4k trace 32k s w breaks and MetaLink Windows Debugger Includes COP8 NSDEV and power supply Package specific probes and surface mount adaptors are ordered separately Add COP8 PM and adapters for OTP programming COP8 Development and OTP Programming Tools COP8 PM COP8 Development Programming Module Windows programming tool for COP8 OTP Flash Fami lies Includes 40 DIP programming socket control soft ware RS232 cable and power supply Programming adapters are extra Development Metalink s Debug Module includes devel opment device programming capability for COP8 de vices Many other third party programmers are approved for development and engineering use Production Third party programmers and automatic handling equipment cover needs from engineering proto type and pilot production to full production environments Factory Pro
19. 4 PACKAGING PIN EFFICIENCY Real estate and board configuration considerations demand maximum space and pin efficiency particularly given today s high integration and small product form factors Microcon troller users try to avoid using large packages to get the I O needed Large packages take valuable board space and increases device cost two trade offs that microcontroller designs can ill afford The COP8 family offers wide range of packages and do not waste pins up to 90 9 or 40 pins in the 44 pin package are devoted to useful 1 www national com 968409 COP8SG Family Connection Diagrams 10131704 Top View Order Number COP8SGXY28M8 See NS Package Number M28B Order Number COP8SGXY28N8 See NS Package Number N28B Order Number COP8SGR728Q3 See NS Package Number D28JQ o en _ x Oo Fr Sy RE IS SS gt gt oO 0 c 18 19 20 21 22 25 24 25 26 27 28 T NM x Gn Jou 46 6 9 OO 4 A gt Top View Order Number COP8SGXY44V8 See NS Package Number V44A Order Number COP8SGR744J3 See NS Package Number EL44C 66 51 G5 SK 64 50 13 14 15 16 17 18 19 20 21 22 Top View Order Number COPSSGR7HLQ8 See NS Package Number LQA44A GO INT RESET GND D7 06 05 4 D3 D2 D1 DO 10131706 G3 TIA 62 T1B G1 WD 41 40 39 GO INT RESET 10131753 10131705 Top View
20. BYTES ON CHIP RAM 128 BYTES Not Available for 50 7 Not Available for COPBSGE7 0200 0300 10131745 FIGURE 7 RAM Organization The instructions that utilize the stack pointer SP always reference the stack as part of the base segment Segment 0 regardless of the contents of the S register The S register is not changed by these instructions Consequently the stack used with subroutine linkage and interrupts is always located in the base segment The stack pointer will be initial ized to point at data memory location 006 as a result of reset The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00 0 to OOFF of the upper base segment No RAM is located at the upper sixteen addresses 0070 to 007F of the lower base segment Additional RAM beyond these initial 128 bytes however will always be memory mapped in groups of 128 bytes or less at the data segment address extensions XX00 to XX7F of the lower base segment The additional 384 bytes of RAM in this device are memory mapped at address locations 0100 to 017F 0200 to 027F and 0300 to 037F hex Memory address ranges 0200 to 027F and 0300 to 037F are unavailable on the COP8SGx5 and if read will return un
21. Design Low current drain typically lt 4 uA m Two power saving modes HALT and IDLE Temperature Range m 40 C to 85 C 40 C to 125 C Development Support m Windowed packages for DIP and PLCC m Real time emulation and debug tools available POWER CONTROL DESEE 1 0 PORTS COMPARATOR INPUTS 16 BIT TIMER T3 256 512 BYTES 10131744 FIGURE 1 COP8SGx Block Diagram www national com 1 0 Device Description 1 1 ARCHITECTURE The 8 family is based on a modified Harvard architec ture which allows data tables to be accessed directly from program memory This is very important with modern microcontroller based applications since program memory is usually ROM or EPROM while data memory is usually RAM Consequently data tables need to be contained in non volatile memory so they are not lost when the micro controller is powered down In a modified Harvard architec ture instruction fetch and memory data transfers can be overlapped with a two stage pipeline which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory This is not possible with a Von Neumann single address bus architecture The COP8 family supports a software stack scheme that allows the user to incorporate many subroutine calls This capability is important when using High Level Languages With a hardware stack the user is limited
22. Development package for Windows on CD A fully Integrated Develop ment Environment for COP8 Includes a fully licensed WCOP8 IDE COP8 NSASM Plus Manuals Applications Software and other COP8 technical information COPS8C ByteCraft C Cross Compiler and Code Devel opment System Includes BCLIDE Integrated Develop ment Environment for Win32 editor optimizing C Cross Compiler macro cross assembler BC Linker and MetaLinktools support DOS SUN versions available e EWCOPS8 EWCOP8 M EWCOP8 BL IAR ANSI C Compiler and Embedded Workbench M version in cludes MetaLink debugger support BL version 4k code limit no FP A fully integrated Win32 IDE ANSI C Compiler macro assembler editor linker librarian and C Spy high level simulator debugger COP8 Development Productivity Tools DriveWay COP8 Aisys Corporation COP8 Peripherals Code Generation tool Automatically generates tested and documented C or Assembly source code modules containing drivers and interrupt handlers for each on chip peripheral Application specific code can be in serted for customization using the integrated editor COP8 UTILS COP8 assembly code examples device drivers and utilities to speed up code development In cluded with COP8 NSDEV and COP8 NSEVAL COP8 Hardware Debug Tools COP8 EM xx Metalink COP8 Emulation Module for OTP ROM COP8 Families Windows based development and real time in circuit emulation tool with
23. RBIT EXPND PSW JP INT EXIT GO pin configured Hi Z Ext interrupt polarity falling edge Enable the external interrupt Set the GIE bit Wait for external interrupt The interrupt causes a branch to address OFF The VIS causes a branch to interrupt vector table Vector table within 256 byte of VIS inst containing the ext interrupt service routine Interrupt Service Routine Reset ext interrupt pend bit Return set the GIE bit 39 www national com 958402 COP8SG Family 10 0 Interrupts Continued 10 4 NON MASKABLE INTERRUPT 10 4 1 Pending Flag There is a pending flag bit associated with the non maskable interrupt called STPND This pending flag is not memory mapped and cannot be accessed directly by the software The pending flag is reset to zero when a device Reset occurs When the non maskable interrupt occurs the asso ciated pending bit is set to 1 The interrupt service routine should contain an RPND instruction to reset the pending flag to zero The RPND instruction always resets the STPND flag 10 4 2 Software Trap The Software Trap is a special kind of non maskable inter rupt which occurs when the INTR instruction used to ac knowledge interrupts is fetched from program memory and placed in the instruction register This can happen in a variety of ways usually because of an error condition Some examples of causes are listed below If the program counter incorrect
24. USART Continued As an example considering Asynchronous Mode and a clock of 4 608 MHz the prescaler factor selected is 4 608 1 8432 2 5 The 2 5 entry is available in Table 5 The 1 8432 MHz prescaler output is then used with proper Baud Rate Divisor Table 4 to obtain different baud rates For a baud rate of 19200 e g the entry in Table 4 is 5 N 1 25 N 1is the value from Table 4 N 6 N is the Baud Rate Divisor Baud Rate 1 8432 MHz 16 x 6 19200 The divide by 16 is performed because in the asynchronous mode the input frequency to the USART is 16 times the baud rate The equation to calculate baud rates is given below The actual Baud Rate may be found from BR 16 x N x P Where BR is the Baud Rate Fc is the frequency N is the Baud Rate Divisor Table 4 P is the Prescaler Divide Factor selected by the value in the Prescaler Select Register Table 5 Note In the Synchronous Mode the divisor 16 is replaced by two Example Asynchronous Mode Crystal Frequency 5 MHz Desired baud rate 9600 Using the above equation N x P can be calculated first N x P 5 x 109 16 x 9600 32 552 Now 32 552 is divided by each Prescaler Factor Table 5 to obtain a value closest to an integer This factor happens to be 6 5 P 6 5 N 32 552 6 5 5 008 N 5 The programmed value from Table 4 should be 4 N 1 Using the above values calculated for N and P BR 5 x 109 16 x 5 x 6 5 961
25. bit is generated and verified by hard ware The third format for transmission CHLO 0 CHL1 1 consists of one Start bit nine Data bits and 7 8 one or two Stop bits This format also supports the USART ATTEN TION feature When operating in this format all eight bits of TBUF and RBUF are used for data The ninth data bit is transmitted and received using two bits in the ENU and ENUR registers called XBIT9 and RBIT9 RBIT9 is a read only bit Parity is not generated or verified in this mode For any of the above framing formats the last Stop bit can be programmed to be 7 8th of a bit in length If two Stop bits are selected and the 7 8th bit is set selected the second Stop bit will be 7 8th of a bit in length The parity is enabled disabled by PEN bit located in the ENU register Parity is selected for 7 and 8 bit modes only If parity is enabled PEN 1 the parity selection is then performed by PSELO and PSEL1 bits located in the ENU register Note that the XBIT9 PSELO bit located in the ENU register serves two mutually exclusive functions This bit programs the ninth bit for transmission when the USART is operating with nine data bits per frame There is no parity selection in this framing format For other framing formats XBIT9 is not needed and the bit is PSELO used in conjunction with PSEL1 to select parity The frame formats for the receiver differ from the transmitter in the number of Stop bits required The r
26. cleared on reset RCVG This bit is set high whenever a framing error occurs and goes low when RDX goes high Read only cleared on reset ENUI USART Interrupt and Clock Source Register Address at OBC STP2 STP78 ETDX SSEL 1 ERI ETI Bit 7 Bit 0 STP2 This bit programs the number of Stop bits to be transmitted Read Write cleared on reset STP2 0 One Stop bit transmitted STP2 1 Two Stop bits transmitted STP78 This bit is set to program the last Stop bit to be 7 8th of a bit in length Read Write cleared on reset ETDX TDX USART Transmit Pin is the alternate function assigned to Port L pin L2 it is selected by setting ETDX bit To simulate line break generation software should reset ETDX bit and output logic zero to TDX pin through Port L data and configuration registers Read Write cleared on reset SSEL USART mode select Read Write cleared on reset SSEL 0 Asynchronous Mode SSEL 1 Synchronous Mode XRCLK This bit selects the clock source for the receiver section Read Write cleared on reset XRCLK 0 The clock source is selected through the PSR and BAUD registers XRCLK 21 Signal on CKX L1 pin is used as the clock XTCLK This bit selects the clock source for the transmitter section Read Write cleared on reset XTCLK 20 The clock source is selected through the PSR and BAUD registers XTCLK 21 Signal on CKX L1 pin is used as the clock ERI This bit enables disables int
27. electrical specifications are not ensured Total Curent into V when operating the device at absolute maximum ratings u Pin Source 100 mA Total Current out of GND Pin Sink 110 mA DC Electrical Characteristics 40 C lt T4 125 C unless otherwise specified Parameter Conditions Min Operating Voltage 4 5 Power Supply Rise Time 10 Vcc Start Voltage to Guarantee POR 0 Power Supply Ripple Note 4 Peak to Peak Supply Current Note 5 CKI 10 MHz Voc 5 5V te 1 us CKI 4 MHz Voc 4 5V to 2 5 us HALT Current Note 6 Voc 5 5V CKI 0 MHz IDLE Current Note 5 CKI 10 MHz Voc 5 5V te 1 us CKI 4 MHz Voc 4 5V 2 5 us Input Levels Vit RESET Logic High 0 8 Voc V Logic Low 0 2 Vo V CKI All Other Inputs Logic High 0 7 Va V Logic Low 0 2 V Internal Bias Resistor for the 0 5 1 2 MQ Crystal Resonator Oscillator Resistance to GND when R C Voc 5 5V 5 8 11 Oscillator is selected Hi Z Input Leakage Vec 5 5V 5 5 Input Pullup Current Voc 5 5V Vin OV 35 400 and L Port Input Hysteresis Voc 5 5V 0 25 V Output Current Levels D Outputs Source Voc 4 5V 3 3V 0 4 mA Sink Voc 4 5V Vor 1 0V 9 mA All Others Source Weak Pull Up Mode Voc 4 5V 2 7V 9 140 Source Push Pull Mode Voc 4 5 3 3 0 4 mA Sink Push Pull Mode Voc 4 5V 0 4V 1 4 mA TRI STATE L
28. floating For lower frequencies an external capacitor should be con nected between and either Voc or GND Immunity of the R C oscillator to external noise can be improved by connect ing one half the external capacitance to Vec and one half to GND PC board trace length on the CKI pin should be kept as short as possible Table 3 shows the oscillator frequency as a function of external capacitance on the CKI pin Figure 14 shows the R C oscillator configuration TABLE 3 R C Oscillator Configuration 40 C to 85 4 5V to 5 5V OSC Freq Variation of 35 R C OSC Freq External Capacitor pF Instr Cycle us 125 1 10 6100 32 kHz 312 5 Assumes 3 5 pF board capacitance Without On Chip Bias Resistor FIGURE 12 Crystal Oscillator www national com 5 0 Functional Description Continued z o 5 5 Ln INPUT or EXTERNAL HALT CLOCK Restart 10131719 FIGURE 13 External Oscillator LI LI LI I 4h x 27 ii Q N Optional to improve noise INPUT or immunity HALT Restart 10131720 For operation at lower than maximum R C oscillator frequency 5 5 i nm e Open rn INPUT or HALT Restart 10131721 For operation at maximum R C oscillator frequency FIGURE 14 R C Oscillator 5 11 CONTROL REGISTERS CNTRL Register Address X 00EE T1C3 T1C2 T1C1 1 0 MSEL IEDG SL1 SLO Bit 7 Bit 0 The
29. frequency has not reached a minimum specified value in cluding the case where the oscillator fails to start The WDSVR register can be written to only once after reset and the key data bits 5 through 1 of the WDSVR Register must match to be a valid write This write to the WDSVR register involves two irrevocable choices i the selection of the WATCHDOG service window ii enabling or disabling of the Clock Monitor Hence the first write to WDSVR Register involves selecting or deselecting the Clock Monitor select the WATCHDOG service window and match the WATCH DOG key data Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data bits 7 through 1 in the WDSVR Register Table 9 shows the se quence of events that can occur The user must service the WATCHDOG at least once before the upper limit of the service window expires The WATCH DOG may not be serviced more than once in every lower limit of the service window The WATCHDOG has an output pin associated with it This is the WDOUT pin on pin 1 of the port G WDOUT is active low and must be externally connected to the RESET pin or to some other external logic which handles WATCHDOG event The WDOUT pin has a weak pullup in the inactive state This pull up is sufficient to serve as the connection to Vec for systems which use the internal Power On Reset Upon triggering the WATCHDOG the logic will
30. in the vector table The interrupt sources in the vector table are listed in order of rank from highest to lowest priority If two or more enabled and pending interrupts are detected at the same time the one with the highest priority is serviced first Upon return from the interrupt service routine the next highest level pending interrupt is serviced If the VIS instruction is executed but no interrupts are en abled and pending the lowest priority interrupt vector is used and a jump is made to the corresponding address in the vector table This is an unusual occurrence and may be the result of an error It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction such as executing a single cycle instruc tion which clears an enable flag at the same time that the pending flag is set It can also result however from inad vertent execution of the VIS command outside of the context of an interrupt The default VIS interrupt vector can be useful for applica tions in which time critical interrupts can occur during the servicing of another interrupt Rather than restoring the pro gram context A B X etc and executing the RETI instruc tion an interrupt service routine can be terminated by return ing to the VIS instruction In this case interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started After testing the
31. pull the WDOUT G1 pin low for an additional 16 32 tc cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold After this delay the device will stop forcing the WDOUT output low The WATCHDOG service window will restart when the WDOUT pin goes high A WATCHDOG service while the WDOUT signal is active will be ignored The state of the WDOUT pin is not guaranteed on reset but if it powers up low then the WATCHDOG will time out and WDOUT will go high The Clock Monitor forces the G1 pin low upon detecting a clock frequency error The Clock Monitor error will continue until the clock frequency has reached the minimum specified value after which the G1 output will go high following 16 32 tc clock cycles The Clock Monitor generates a con tinual Clock Monitor error if the oscillator fails to start or fails to reach the minimum specified frequency The specification for the Clock Monitor is as follows 1 gt 10 kHz clock rejection 1 lt 10 Hz Guaranteed clock rejection 41 www national com 968409 COP8SG Family 11 0 WATCHDOG Clock Monitor Continued TABLE 9 WATCHDOG Service Actions 11 3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET Following RESET the WATCHDOG
32. serves as the dedicated output pin for the CKO clock output With the internal R C or the external oscillator option selected G7 serves as a gen eral purpose Hi Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7 Since G6 is an input only pin and G7 is the dedicated CKO clock output pin crystal clock option or general purpose input R C or external clock option the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below Reading the G6 and G7 data bits will return zeroes Each device will be placed in the HALT mode by writing a 1 to bit 7 of the Port G Data Register Similarly the device will be placed in the IDLE mode by writing a 1 to bit 6 of the Port G Data Register Writing a 1 to bit 6 of the Port G Configuration Register enables the MICROWIRE PLUS to operate with the alter nate phase of the SK clock The G7 configuration bit if set high enables the clock start up delay after HALT when the R C clock configuration is used Config Reg Data Reg CLKDLY HALT Alternate SK IDLE Port G has the following alternate features G7 CKO Oscillator dedicated output or general purpose input G6 SI MICROWIRE Serial Data Input G5 SK MICROWIRE Serial Clock G4 SO MICROWIRE Serial Data Output G3 T1A Timer T1 I O G2 T1B Timer T1 Capture Input G1 WDOUT WATCHDOG and or CLock Monitor if WATCH DO
33. specify the new contents of the Program Counter The upper three bits of the Program Counter re main unchanged restricting the new Program Counter ad dress to the same 4 kbyte address space as the current instruction This restriction is relevant only in devices using more than one 4 kbyte program memory space Example Jump Absolute JMP 0125 Reg Contents Contents Before After PCU 0C Hex 01 Hex PCL 77 Hex 25 Hex Jump Absolute Long In this 3 byte instruction 15 bits of the instruction opcode specify the new contents of the Pro gram Counter Example Jump Absolute Long JMP 03625 Reg Contents Contents Memory Before After PCU 42 Hex 36 Hex PCL 36 Hex 25 Hex Jump Indirect In this 1 byte instruction the lower byte of the jump address is obtained from a table stored in program memory with the Accumulator serving as the low order byte of a pointer into program memory For purposes of access ing program memory the contents of the Accumulator are written to PCL temporarily The data pointed to by the Program Counter PCH PCL is loaded into PCL while PCH remains unchanged Example Jump Indirect JID Reg Contents Contents Memory Before After PCU 01 Hex 01 Hex PCL C4 Hex 32 Hex Accumulator 26 Hex 26 Hex Memory www national com 48 14 0 Instruction Set Continued Reg Contents Contents Memory Before After Location 32 Hex 32 Hex 0126 Hex The VIS instruction is a special case of the Indirect Tr
34. tc instruction cycle clock The tc clock is derived by dividing the oscillator clock down by a factor of 9 The Schmitt trigger following the inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications This Schmitt trigger is not part of the oscillator closed loop The start up time out from the IDLE timer enables the clock signals to be routed to the rest of the chip If an R C clock option is being used the fixed delay is introduced optionally A control bit CLKDLY mapped as configuration bit G7 controls whether the delay is to be introduced or not The delay is included if CLKDLY is set and excluded if CLKDLY is reset The CLKDLY bit is cleared on reset Each device has two options associated with the HALT mode The first option enables the HALT mode feature while the second option disables the HALT mode selected through bit O of the ECON register With the HALT mode enable option the device will enter and exit the HALT mode as described above With the HALT disable option the device cannot be placed in the HALT mode writing a 1 to the HALT flag will have no effect the HALT flag will remain 0 The WATCHDOG detector circuit is inhibited during the HALT mode However the clock monitor circuit if enabled remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters t
35. the PWM parameters require updating This capability is provided by the fact that the timer has two separate 16 bit reload registers One of the reload registers contains the ON timer while the other holds the OFF time By contrast a microcontroller that has only a single reload register re quires an additional software to update the reload value alternate between the on time off time The timer can generate the PWM output with the width and duty cycle controlled by the values stored in the reload registers The reload registers control the countdown values and the reload values are automatically written into the timer when it counts down through 0 generating interrupt on each reload Under software control and with minimal overhead the PMW outputs are useful in controlling motors triacs the intensity of displays and in providing inputs for data acqui sition and sine wave generators In this mode the timer Tx counts down at a fixed rate of tc Upon every underflow the timer is alternately reloaded with the contents of supporting registers RxA and RxB The very first underflow of the timer causes the timer to reload from the register RxA Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB Figure 15 shows a block diagram of the timer in PWM mode The underflows can be programmed to toggle the TxA output pin The underflows can also be programmed to generate interr
36. to the PSW register and thus allow other maskable interrupts to interrupt the current service routine If nested interrupts are allowed caution must be exercised The user must write the program in such a way as to prevent stack overflow loss of saved context information and other unwanted conditions The interrupt service routine stored at location OOFF Hex should use the VIS instruction to determine the cause of the interrupt and jump to the interrupt handling routine corre sponding to the highest priority enabled and active interrupt Alternately the user may choose to poll all interrupt pending and enable bits to determine the source s of the interrupt If more than one interrupt is active the user s program must decide which interrupt to service Within a specific interrupt service routine the associated pending bit should be cleared This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event Thus if the same event occurs a second time even while the first occurrence is still being serviced the second occur rence will be serviced immediately upon return from the current interrupt routine An interrupt service routine typically ends with an RETI instruction This instruction sets the GIE bit back to 1 pops the address stored on the stack and restores that address to the program counter Program execution then proceeds with the next
37. 0 10 1 IDENT sy 0 489 1 14 39 F 0 02940 003 74 0 08 0 610 0 020 15 49 0 51 YP SEATING PLANE 29 9020 TYP 0 050 10 51 1 271 0 105 0 015 2 67 0 38 0 165 0 180 4 19 4 57 TYP s woes Molded Dual In Line Package N Order Number COP8SGx544Vx NS Package Number V44A T 0 690 0 005 17 53 0 13 REV 61 www national com 958402 Physical Dimensions inches millimeters unless otherwise noted Continued 11 13 TOP amp BOTTOM Comparators and USART 1 6 MAX 2 Ti 2X OPTIONAL i 4 500 1 0 05 0 15 0 3110 09 0 1 N 0 07 0 2 MIN V sEATING PLANE SEE DETAIL A DETAIL A 1 4 0 05 1 0 125 7 DIMENSIONS ARE IN MILLIMETERS VEJ44A Rev Plastic Quad Flat Package VEJ Order Number COP8SGx544VEJx NS Package Number VEJ44A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life Systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support o
38. 5 44 0 530 1 LQA44A Rev Chip Scale Package CSP Order Number COP8SGR7HLQ8 NS Package Number 44 0 420 10 65 0 393 10 00 0 030 0 75 co 0 009 0 25 9 0 713 18 10 0 696 17 70 0 013 0 32 M 0 009 0 23 0 105 2 65 0 092 2 35 tL 0 012 0 30 0 003 0 10 0 050 1 27 0 020 0 49 BSC 0 013 0 35 0 050 1 27 pauni 0 015 0 40 Molded SO Wide Body Package WM Order Number COP8SGx528Mx NS Package Number M28B www national com 58 Physical Dimensions inches millimeters unless otherwise noted Continued 1 575 0 510 0 005 12 95 0 127 PIN NO 1 IDENT 1 393 1 420 35 38 36 07 0 030 0 600 0 620 0 145 0 210 0 050 0 762 15 24 15 75 3 683 5 334 1 270 0 125 0 165 3 175 4 191 0 020 i 0 508 95 5 0 009 0 015 0 229 0 381 86 94 TYP 0 050 0 015 0 100 0 010 0 018 0 003 14 73 0 125 0 145 IT 0 025 1 270 0 381 2 540 0 254 0 457 0 076 3 175 3 683 lt 969 0 015 0 635 15 88 2 on N28B REV E Molded Dual In Line Package N Order Number COP8SGx728Nx NS Package Number N28B 2 043 2 070 51 89 52 58 eo e psp pp Bel ps Bel s s mV op Bel pe ert psp ps pep psp 22 8 0 062 1 55 AD 0 550 0 005 13 970 20 127 PIN NO 1 IDENT 0 5
39. 5 384 error 9615 385 9600 9600 x 100 0 16 8 8 Effect of HALT IDLE The USART logic is reinitialized when either the HALT or IDLE modes are entered This reinitialization sets the TBMT flag and resets all read only bits in the USART control and status registers Read Write bits remain unchanged The Transmit Buffer TBUF is not affected but the Transmit Shift register TSFT bits are set to one The receiver registers RBUF and RSFT are not affected The device will exit from the HALT IDLE modes when the Start bit of a character is detected at the RDX L3 pin This feature is obtained by using the Multi Input Wakeup scheme provided on the device Before entering the HALT or IDLE modes the user program must select the Wakeup source to be on the RDX pin This selection is done by setting bit 3 of WKEN Wakeup Enable register The Wakeup trigger condition is then selected to be high to low transition This is done via the WKEDG register Bit 3 is one If the device is halted and crystal oscillator is used the Wakeup signal will not start the chip running immediately because of the finite start up time requirement of the crystal oscillator The idle timer TO generates a fixed 256 1 delay to ensure that the oscillator has indeed stabilized before allowing the device to execute code The user has to con sider this delay when data transfer is expected immediately after exiting the HALT mode 8 9 Diagnostic Bits CHARLO
40. 8 1 1 1 3 2 3 2 2 1 2 1 3 LD B Imm 1 1 If B 16 LD B Imm 2 2 If B gt 15 LD Mem Imm 2 2 3 3 2 2 LD Reg Imm 2 3 IFEQ MD Imm 3 3 Note 18 gt Memory location addressed by B or X or directly www national com 52 COP8SG Family V l 8 1 40 epoodo eui osje si 09 epoodo epoodo pasnun ue pesseJppe y si 300940 87 334 004 444 004 0048 a 19 91 ze dn usr 30 ugs 4 4 330 zsua 440 9 443 003X 443 X 003 alo al o 340 3 91 16 usr 30 41 5 134 9 1 25 9500 J40X 000X J4ax ooax dnr usr MS134 PWY 198 G40 2 339 009 449 009 940 usr 90 ZsHd 1 04001 Jj4gx oogx ddgx oogx 840 usr 90 2588 840 J4VX 00VX ddvX 00vx dnr usr vo 3N8dl 75 v4o S df 336 006 446 006 2 6 dnr usr 6 3 84 640 25 640 01 9 5 448 008 448 008 8 usr 8 939 840 75 840 1 5 Jj44X 00 X 00
41. 80 1473 0 030 0 762 0 050 0 600 0 620 MAX foni 0 125 0 165 15 240 15 748 3 175 4 191 0 145 0 210 3 683 5 334 dee 0 009 0 015 MTS 0 229 0 381 0 625 0015 A 0075 0015 __ e 0 100 0 010 el Le 0 018 0 003 805 0 0 457 0 585 114 1 905 0 381 2 540 0 254 0 457 0 076 0 125 0 140 3 175 3 556 N40A REV E Molded Dual In Line Package N Order Number COP8SGx540Nx NS Package Number N40A 59 www national com 958402 COP8SG Family Physical Dimensions inches millimeters unless otherwise noted Continued 0 280 0 320 e 7 11 8 13 UV WINDOW 44 Lead EPROM Leaded Chip Carrier EL Order Number COP8SGR744J3 NS Package Number EL44C C30 006 0 15 C 0 146 0 168 3 71 4 27 DOT 21 0 030 r 0 030 fore TY 0 76 1 7 22 0 610 0 650 15 49 16 51 TYP N CONTACT POINT SF 0 006 0 010 ir 0 15 0 25 0 060 1 52 11 0 078 0 108 0 014 0 020 1 98 2 74 0 36 0 51 TYP 0 030 0 76 AOS 20 015 0 38 EL44C REV www national com 60 Physical Dimensions inches millimeters unless otherwise noted Continued 0 006 0 650 0 000 0 15 0 017 0 004 yp 16 51 0 0 43
42. 8432 MHz pres caler output is then used to drive the software programmable baud rate counter to create a 16x clock for the following baud rates 110 134 5 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 and 38400 Table 4 Other baud 31 www national com 958402 COP8SG Family 8 0 USART Continued rates may be created by using appropriate divisors The 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver UART TRANSMIT CLOCK PRESCALER CRYSTAL BAUD RATE SELECT 5 BITS 11 BITS 1 16 UART RECEIVE CLOCK 10131741 FIGURE 23 USART BAUD Clock Generation SELECT REGISTER PSR I BAUD REGISTER BAUD RATE 10131742 PRESCALER SELECT FIGURE 24 USART BAUD Clock Divisor Registers TABLE 4 Baud Rate Divisors Prescaler Prescaler 1 8432 MHz Prescaler Output Select Factor Baud Baud Rate Rate Divisor 1 N 1 110 110 03 1046 134 5 855 134 58 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 4800 23 7200 15 9600 11 19200 5 38400 2 Note The entries in Table 4 assume a prescaler output of 1 8432 MHz In the asynchronous mode the baud rate could be as high as 987 5k TABLE 5 Prescaler Factors Prescaler Prescaler Select Factor 00000 NO CLOCK 00001 1 00010 1 5 00011 2 www national com 32 8 0
43. ARTING remains unchanged The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration ranking This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitration ranking Figure 26 illustrates the different steps performed by the VIS instruction Figure 27 shows a flowchart for the VIS instruc tion The non maskable interrupt pending flag is cleared by the RPND Reset Non Maskable Pending Bit instruction under certain conditions and upon RESET Vector table is 256 byte page same as PC Interrupt Vector Table HIGH ADDRESS LOW INTERRUPT SERVICE ROUTINE PROGRAM MEMORY 10131729 FIGURE 26 VIS Operation 37 www national com 968409 COP8SG Family 10 0 Interrupts Continued JUMP TO VECTOR AT OyFE OyFF EXTERNAL INTERRUPT ACTIVE JUMP TO VECTOR AT OyFA OyFB PORT L WAKEUP INTERRUPT ACTIVE JUMP TO VECTOR AT OyE2 OyE3 JUMP TO VECTOR AT OyEO OyE1 10131730 FIGURE 27 VIS Flowchart www national com 38 10 0 Interrupts continued Programming Example External Interrupt PSW 00EF CNTRL 00EE RBIT 0 PORTGC RBIT 0 PORTGD SBIT IEDG CNTRL SBIT EXEN PSW SBIT GIE PSW WAIT JP WAIT 0FF VIS 01 ADDRW SERVICE INT EXIT RETI SERVICE
44. Byte xxE7 Timer T1 Autoload Register T1RB Upper Byte xxE8 ICNTRL Register xxE9 MICROWIRE PLUS Shift Register xxEA Timer T1 Lower Byte xxEB Timer T1 Upper Byte xxEC Timer T1 Autoload Register T1RA Lower Byte xxED Timer T1 Autoload Register T1RA Upper Byte xxEE CNTRL Control Register xxEF PSW Register xxFO to FB On Chip RAM Mapped as Registers xxFC X Register xxFD SP Register xxFE B Register xxFF S Register 0100 017 On Chip 128 RAM Bytes 0200 027F On Chip 128 RAM Bytes Reads as undefined data on COP8SGE 0300 037F On Chip 128 RAM Bytes Reads as undefined data on COP8SGE Note Reading memory locations 0070H 007FH Segment 0 will return all ones Reading unused memory locations 0080H 0093H Segment 0 will return undefined data Reading memory locations from other Seg ments i e Segment 4 Segment 5 etc will return undefined data www national com 46 14 0 Instruction Set 14 1 INTRODUCTION This section defines the instruction set of the COP8 Family members It contains information about the instruction set features addressing modes and types 14 2 INSTRUCTION FEATURES The strength of the instruction set is based on the following features e Mostly single byte opcode instructions minimize program size One instruction cycle for the majority of single byte in structions to minimize program execution time Many single byte multiple function instructions
45. CONDITIONS The device can detect various illegal conditions resulting from coding errors transient noise power supply voltage drops runaway programs etc Reading of undefined ROM gets zeroes The opcode for software interrupt is 00 If the program fetches instructions from undefined ROM this will force a software interrupt thus signaling that an illegal condition has occurred The subroutine stack grows down for each call jump to subroutine interrupt or PUSH and grows up for each return or POP The stack pointer is initialized to RAM location O6F Hex during reset Consequently if there are more re turns than calls the stack pointer will point to addresses 070 and 071 Hex which are undefined RAM Undefined RAM from addresses 070 to 07F Segment 0 and all other seg ments i e Segments 4 etc is read as all 1 s which in turn will cause the program to return to address 7FFF Hex It is recommended that the user either leave this location unprogrammed or place an INTR instruction all 0 s in this location to generate a software interrupt signaling an illegal condition Thus the chip can detect the following illegal conditions 1 Executing from undefined ROM 2 Over the stack by having more returns than calls When the software interrupt occurs the user can re initialize the stack pointer and do a recovery procedure before restart ing this recovery program is probably similar to that foll
46. EN IWPND uWEN TIENB Bit 7 Bit 0 The ICNTRL register contains the following bits Reserved This bit is reserved and must be zero LPEN L Port Interrupt X Enable X Multi Input Wakeup Interrupt TOPND Timer TO Interrupt pending TOEN Timer TO Interrupt Enable Bit 12 toggle WWPND MICROWIRE PLUS interrupt pending HWEN Enable MICROWIRE PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for cap ture edge Timer T1 Interrupt Enable for T1B Input capture edge T1ENB T2CNTRL Register Address X 00C6 Bit 7 Bit 0 The T2CNTRL control register contains the following bits T2C3 Timer T2 mode control bit T2C2 Timer T2 mode control bit T2C1 Timer T2 mode control bit T2C0 Timer T2 Start Stop control in timer modes 1 and 2 T2 Underflow Interrupt Pend ing Flag in timer mode 3 T2PNDA Timer T2 Interrupt Pending Flag Autoreload RA in mode 1 T2 Underflow in mode 2 T2A capture edge in mode 3 Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B cap ture edge Timer T2 Interrupt Enable for Timer Underflow or T2B Input capture edge T2ENA T2ENB www national com 958402 COP8SG Family 5 0 Functional Description Continued TSCNTRL Register Address X 00B6 T3C3 T3C2 T3C1 0 Bit 7 Bit 0 The TSCNTRL control regi
47. G enabled otherwise it is a general purpose I O GO INTR External Interrupt Input Port C is an 8 bit I O port The 40 pin device does not have a full complement of Port C pins The unavailable pins are not terminated A read operation on these unterminated pins will return unpredictable values The 28 pin device do not offer Port C On this device the associated Port C Data and Configuration registers should not be used Port is an 8 bit I O port The 28 pin device does not have a full complement of Port F pins The unavailable pins are not terminated A read operation on these unterminated pins will return unpredictable values Port F1 F3 are used for Comparator 1 Port F4 F6 are used for Comparator 2 The Port F has the following alternate features F6 COMP2OUT Comparator 2 Output F5 COMP2 IN Comparator 2 Positive Input F4 COMP2 IN Comparator 2 Negative Input COMP10OUT Comparator 1 Output F2 COMP1 IN Comparator 1 Positive Input F1 COMP1 IN Comparator 1 Negative Input www national com 4 0 Pin Descriptions continued Note For compatibility with existing software written for COP888xG devices and with existing Mask ROM devices a read of the Port I input pins address xxD7 will return the same data as reading the Port F input pins address xx96 It is recommended new applications which will go to production with the COP8SGx use the Port F addresses Note that compatible ROM devices contai
48. G should not be serviced for at least 2048 instruction cycles following HALT but must be serviced within the selected window to avoid a WATCH DOG error The IDLE timer TO is not initialized with external RESET The user can sync in to the IDLE counter cycle with an IDLE counter TO interrupt or by monitoring the TOPND flag The TOPND flag is set whenever the twelfth bit of the IDLE counter toggles every 4096 instruction cycles The user is responsible for resetting the TOPND flag A hardware WATCHDOG service occurs just as the de vice exits the IDLE mode Consequently the WATCH DOG should not be serviced for at least 2048 instruction cycles following IDLE but must be serviced within the selected window to avoid a WATCHDOG error Key Window Clock Action Data Data Monitor Match Match Match Valid Service Restart Service Window Don t Care Mismatch Don t Care Error Generate WATCHDOG Output Mismatch Don t Care Don t Care Error Generate WATCHDOG Output Don t Care Don t Care Mismatch Error Generate WATCHDOG Output Following RESET the initial WATCHDOG service where the service window and the CLOCK MONITOR enable disable must be selected may be programmed any where within the maximum service window 65 536 in struction cycles initialized by RESET Note that this initial WATCHDOG service may be programmed within the ini tial 2048 instruction cycles without causing a WATCH DOG error 11 4 DETECTION OF ILLEGAL
49. GIE bit to ensure that execution is not erroneous the routine should restore the program context and execute the RETI to return to the interrupted program This technique can save up to fifty instruction cycles t or more 50us at 10 MHz oscillator of latency for pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending To ensure reliable operation the user should always use the VIS instruction to determine the source of an interrupt Al though it is possible to poll the pending bits to detect the source of an interrupt this practice is not recommended The use of polling allows the standard arbitration ranking to be altered but the reliability of the interrupt system is compro mised The polling routine must individually test the enable and pending bits of each maskable interrupt If a Software Trap interrupt should occur it will be serviced last even though it should have the highest priority Under certain conditions a Software Trap could be triggered but not ser viced resulting in an inadvertent locking out of all maskable interrupts by the Software Trap pending flag Problems such as this can be avoided by using VIS instruction TABLE 6 Interrupt Vector Table Arbitration Ranking Source Description a 1 Highest Software INTR Instruction OyFE OyFF yFC OyFD External Go OyFA OyFB Timer TO Underflow OyF8 0yF9 5 Timer T1 T1A Unde
50. IC 40 DIP 40 to 85 C COP8SGE5 8k ROM 256 24 36 40 44 PLCC QFP CSP 40 to 125 C 28 DIP SOIC 40 DIP 40 to 85 C COP8SGG5 16k ROM 512 24 36 40 44 PLCC QFP CSP 40 to 125 C COP8SGH5 20k ROM 24 36 40 COP8SGK5 24k ROM 24 36 40 28 DIP SOIC 40 DIP 44 PLCC QFP CSP 28 DIP SOIC 40 DIP 44 PLCC QFP CSP 40 to 85 C 40 to 125 C 40 to 85 C 40 to 125 C COP8SGR5 32k ROM 24 36 40 28 DIP SOIC 40 DIP 44 PLCC QFP CSP 40 to 85 C 40 to 125 C COP8SGE7 8k OTP EPROM 24 36 40 28 DIP SOIC 40 DIP 44 PLCC QFP CSP 40 to 85 C 40 to 125 C COP8SGR7 COP8SGR7 Q3 32k EPROM 512 24 36 40 28 DIP 40 DIP 44 PLCC Room Temp 32k OTP EPROM 24 36 40 Key Features Low cost 8 bit microcontroller Quiet Design low radiated emissions Multi Input Wakeup pins with optional interrupts 8 pins Mask selectable clock options Crystal oscillator Crystal oscillator option with on chip bias resistor External oscillator Internal R C oscillator Internal Power On Reset user selectable WATCHDOG and Clock Monitor Logic user selectable Eight high current outputs 256 or 512 bytes on board RAM 8k to 32k ROM or OTP EPROM with security feature CPU Features m Versatile easy to use instruction set m 0 67 us instruction cycle time COP8 is a trademark of National Semiconductor Corporation 28 DIP SOIC 40 DIP 44 PLCC QFP CSP 40 to 85 40 to 125 C
51. Mode Clock Select o o 2x amp 0 Pot LL Where tc is the instruction cycle clock 12 1 MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE PLUS to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8 bits to shift If CHIP SELECT LINES 8 BIT A D CON EEPROM VERTER DO DI SK DO DI SK enabled an interrupt is generated when eight data bits have been shifted The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 28 shows how two microcontroller devices and several peripherals may be interconnected using the MICROWIRE PLUS arrangements WARNING The SIO register should only be loaded when the SK clock is in the idle phase Loading the SIO register while the SK clock is in the active phase will result in undefined data in the SIO register Setting the BUSY flag when the input SK clock is in the active phase while in the MICROWIRE PLUS is in the slave mode may cause the current SK clock for the SIO shift register to be narrow For safety the BUSY flag should only be set when the input SK clock is in the idle phase 12 1 1 MICROWIRE PLUS Master Mode Operation In the MICROWIRE PLUS Master mode of operation the shift clock SK is generated internally The MICROWIRE Master always initiates all data exchanges The MSEL bit in the CNTRL register must be set to
52. National Semiconductor Sales Office ESD Protection Level 2kV Human Body Distributors for availability and specifications Model Supply Voltage Vcc 7V Note 2 Absolute maximum ratings indicate limits beyond which damage to Voltage at Any Pin 0 3 to Voc 0 3V the device may occur DC and AC electrical specifications are not ensured Total Current into Voc when operating the device at absolute maximum ratings Pin Source 100 mA DC Electrical Characteristics 40 C lt lt 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Operating Voltage 2 7 5 5 V Power Supply Rise Time 10 50 x 106 ns Voc Start Voltage to Guarantee POR 0 0 25 V Power Supply Ripple Note 4 Peak to Peak 0 1 V Supply Current Note 5 CKI 15 MHz Voc 5 5V tc 0 67 us 9 0 mA CKI 10 MHz Voc 5 5V to 1 us 6 0 mA CKI 4 MHz Voc 4 5V 2 5 us 2 1 mA HALT Current Note 6 Voc 5 5V 0 MHz 4 10 IDLE Current Note 5 CKI 15 MHz Voc 5 5V tc 0 67 us 2 25 mA CKI 10 MHz Voc 5 5V to 1 us 1 5 mA CKI 4 MHz Voc 4 5V 2 5 us 0 8 mA Input Levels RESET Logic High 0 8 V Logic Low 0 2 Voc V All Other Inputs Logic High 0 7 Voc V Logic Low 0 2 Voc V Internal Bias Resistor for the 0 5 1 2 MQ Crystal Resonator Oscillator Resistance to or GND when R C Voc 5 5V Oscillator is selected 2
53. Order Number COP8SGXY40N8 See NS Package Number N40A Order Number COP8SGR5740Q3 See NS Package Number D40KQ o en _ x gt Oo Fr TUM gt SS i ED S 10 x OMAN 41 40 59 38 37 GO INT 2 RESET 5 GND F1 4 07 22 5 D6 6 D5 4 17 D4 F5 8 03 re 9 D2 F7 10 D1 10 41 00 12 13 14 15 16 17 18 19 20 21 22 3 8 SEBSGRASAHA 10131743 Top View Order Number COP8SGXYVEJ8 See NS Package Number VEJ44A Note 1 X E for 8k G for 16k H for 20k K for 24k R for 32k Y 5 for ROM 7 for OTP www national com Pinouts for 28 40 and 44 Pin Packages Port Type Alt Fun E 40 Pin DIP MOD 44 Pin PQFP 44 Pin CSP LO VO MIWU 11 17 17 11 12 L1 VO MIWU or CKX 12 18 18 12 13 L2 VO MIWU or TDX 13 19 19 13 14 L3 VO MIWU or RDX 14 20 20 14 15 L4 VO MIWU or T2A 15 21 25 19 20 L5 VO MIWU or T2B 16 22 26 20 21 L6 VO MIWU or T3A 17 23 27 21 22 L7 VO MIWU or T3B 18 24 28 22 23 GO 25 35 39 33 34 G1 y o WDOUT 26 36 40 34 35 G2 y o T1B 27 37 41 35 36 G3 T1A 28 38 42 36 37 G4 50 1 3 3 41 42 G5 SK 2 4 4 42 43 G6 51 3 5 5 43 44 G7 CKO 4 6 6 44 1 DO 19 25 29 23 24 D1 20 26 30 24 25 D2 O 21 27 31 25 26 D3 O 22 28 32 26 27 D4 O 29 33 27 28 D5 30 34 28 29 D6 31 35 29 30 D7 32 36 30 31 FO 7 9 9 3 4 F1 y o COMP 1IN 8 10
54. am memory ROM is separated from the data store memory RAM Both ROM and RAM have their own separate ad dressing space with separate address buses The architec ture though based on the Harvard architecture permits transfer of data from ROM to RAM 5 1 CPU REGISTERS The CPU can do an 8 bit addition subtraction logical or shift operation in one instruction tc cycle time There are six CPU registers A is the 8 bit Accumulator Register PC is the 15 bit Program Counter Register PU is the upper 7 bits of the program counter PC PL is the lower 8 bits of the program counter PC B is an 8 bit RAM address pointer which can be optionally post auto incremented or decremented X is an 8 bit alternate RAM address pointer which can be optionally post auto incremented or decremented S is the 8 bit Segment Address Register used to extend the lower half of the address range 00 to 7F into 256 data segments of 128 bytes each SP is the 8 bit stack pointer which points to the subroutine interrupt stack in RAM With reset the SP is initialized to RAM address 02F Hex devices with 64 bytes of RAM or initialized to RAM address 06 Hex devices with 128 bytes of RAM All the CPU registers are memory mapped with the excep tion of the Accumulator A and the Program Counter PC 5 2 PROGRAM MEMORY The program memory consists of varies sizes of ROM These bytes may hold program instructions or constant data data tables fo
55. and CHARL1 in the ENU register provide a loopback feature for diagnostic testing of the USART When these bits are set to one the following occur The receiver input pin RDX is internally connected to the transmitter output pin TDX the output of the Transmitter Shift Register is looped back into the Receive Shift Register input In this mode data that is transmitted is immediately received This feature allows the processor to verify the transmit and re ceive data paths of the USART Note that the framing format for this mode is the nine bit format one Start bit nine data bits and 7 8 one or two Stop bits Parity is not generated or verified in this mode 8 10 Attention Mode The USART Receiver section supports an alternate mode of operation referred to as ATTENTION Mode This mode of operation is selected by the ATTN bit in the ENUR register The data format for transmission must also be selected as having nine Data bits and either 7 8 one or two Stop bits The ATTENTION mode of operation is intended for use in networking the device with other processors Typically in such environments the messages consists of device ad dresses indicating which of several destinations should re ceive them and the actual data This Mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1 If the ninth bit is reset to a zero the byte is a Data byte While in ATTENTION mode the USART mon
56. and CLOCK MONI TOR are both enabled with the WATCHDOG having the maximum service window selected The WATCHDOG service window and CLOCK MONI TOR enable disable option can only be changed once during the initial WATCHDOG service following RESET The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid aWATCHDOG error Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors The correct key data value cannot be read from the WATCHDOG Service register WDSVR Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 05 The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes Consequently the de vice inadvertently entering the HALT mode will be de tected as a CLOCK MONITOR error provided that the CLOCK MONITOR enable option has been selected by the program With the single pin R C oscillator option selected and the CLKDLY bit reset the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode With the crystal oscillator option selected or with the single pin R C oscillator option selected and the CLKDLY bit set the WATCHDOG service window will be set to its selected value from WDSVR following HALT Conse quently the WATCHDO
57. and tested The accumu lator A bits can also be directly and individually tested Note RAM contents are undefined upon power up 5 4 DATA MEMORY SEGMENT RAM EXTENSION Data memory address OFF is used as a memory mapped location for the Data Segment Address Register S The data store memory is either addressed directly by a single byte address within the instruction or indirectly rela tive to the reference of the B X or SP pointers each contains a single byte address This single byte address allows an addressing range of 256 locations from 00 to FF hex The upper bit of this single byte address divides the data store memory into two separate sections as outlined previously With the exception of the RAM register memory from address locations 00 0 to OOFF all RAM memory is memory mapped with the upper bit of the single byte ad dress being equal to zero This allows the upper bit of the single byte address to determine whether or not the base address range from 0000 to OOFF is extended If this upper bit equals one representing address range 0080 to OOFF then address extension does not take place Alternatively if this upper bit equals zero then the data segment extension register S is used to extend the base address range from 0000 to 007F from XX00 to XX7F where XX represents the 8 bits from the S register Thus the 128 byte data segment extensions are located from addresses 0100 to 017F for data segment 1 0200 to 027F
58. ansfer of Control addressing mode where the double byte vector associated with the interrupt is transferred from adjacent addresses in program memory into the Program Counter in order to jump to the associated interrupt service routine 14 4 INSTRUCTION TYPES The instruction set contains a wide variety of instructions The available instructions are listed below organized into related groups Some instructions test a condition and skip the next instruc tion if the condition is not true Skipped instructions are executed as no operation NOP instructions 14 4 1 Arithmetic Instructions The arithmetic instructions perform binary arithmetic such as addition and subtraction with or without the Carry bit Add ADD Add with Carry ADC Subtract SUB Subtract with Carry SUBC Increment INC Decrement DEC Decimal Correct DCOR Clear Accumulator CLR Set Carry SC Reset Carry RC 14 4 2 Transfer of Control Instructions The transfer of control instructions change the usual se quential program flow by altering the contents of the Pro gram Counter The Jump to Subroutine instructions save the Program Counter contents on the stack before jumping the Return instructions pop the top of the stack back into the Program Counter Jump Relative JP Jump Absolute JMP Jump Absolute Long JMPL Jump Indirect JID Jump to Subroutine JSR Jump to Subroutine Long JSRL Return from Subroutine RET Return from Subr
59. be programmed to gen erate interrupts Underflows are latched into the timer TxCO pending flag the TxCO control bit serves as the timer under flow interrupt pending flag in the Input Capture mode Con sequently the TxCO control bit should be reset when enter ing the Input Capture mode The timer underflow interrupt is enabled with the control flag When a TxA interrupt occurs in the Input Capture mode the user must check both the TxPNDA and TxCO pending flags in order to determine whether a TxA input capture or a timer underflow or both caused the interrupt Figure 17 shows a block diagram of the timer T1 in Input Capture mode Timer T2 and T3 are identical to T1 nezam z EDGE SELECTOR LOGIC gt gt o EDGE SELECTOR INT B LOGIC INPUT CAPTURE REG RB Tx BEX 10131748 FIGURE 17 Timer in Input Capture Mode 23 www national com 958402 COP8SG Family 6 0 Timers Continued 6 3 TIMER CONTROL FLAGS The control bits and their functions are summarized below TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag 1 Timer Interrupt Enabled 0 Timer Interrupt Disabled De TxPNDB Timer Interrupt Pending Flag Tite eontral TxENB Timer Interrupt Enable Flag 1 Timer Interrupt Enabled large EWN ang External Event 0 Timer Interrupt Disabled Counter where 1 Start 0 Stop The timer mode con
60. ble combinations of lower and upper limits for the WATCHDOG service window This flex ibility in choosing the WATCHDOG service window prevents any undue burden on the user software Bits 5 4 3 2 and 1 of the WDSVR register represent the 5 bit Key Data field The key data is fixed at 01100 Bit 0 of the WDSVR Register is the Clock Monitor Select bit TABLE 8 WATCHDOG Service Window Select Clock Monitor Service Window Lower Upper Limits 2048 8k tc Cycles 2048 16k tc Cycles 2048 32 Cycles 2048 64k tc Cycles Clock Monitor Disabled Clock Monitor Enabled 11 1 CLOCK MONITOR The Clock Monitor aboard the device can be selected or deselected under program control The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock 1 is greater or equal to 10 kHz This equates to clock input rate on CKI of greater or equal to 100 kHz 11 2 WATCHDOG CLOCK MONITOR OPERATION The WATCHDOG is enabled by bit 2 of the ECON register When this ECON bit is 0 the WATCHDOG is enabled and pin G1 becomes the WATCHDOG output with a weak pullup The WATCHDOG and Clock Monitor are disabled during reset The device comes out of reset with the WATCHDOG armed the WATCHDOG Window Select bits bits 6 7 of the WDSVR Register set and the Clock Monitor bit bit O of the WDSVR Register enabled Thus a Clock Monitor error will occur after coming out of reset if the instruction cycle clock
61. bled Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Note 7 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages gt and the pins will have sink current to Voc when biased at voltages gt Voc the pins do not have source current when biased at a voltage below Vcc The effective resistance to Vcc is 7500 typical These two pins will not latch up The voltage at the pins must be limited to lt 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning excludes ESD transients Note 8 National Semiconductor uses the High Temperature Storage Life HTSL test to evaluate the data retention capabilities of the EPROM memory cells used in our OTP microcontrollers Qualification devices have been stressed at 150 C for 1000 hours Under these conditions our EPROM cells exhibit data retention capabilities in excess of 29 years This is based on an activation energy of 0 7eV derated to 55 C Note 9 Parameter characterized but not tested Note 10 Rise times faster than the minimum specification may trigger an internal power on reset Note 11 MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock See and the MICROWIRE operation description Comparators AC and DC Characteristics Vcc 5V 40 C lt T4 lt 85 C Parameter Conditions Min Units Input Offset Volta
62. by B Register X Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or B Meml Direct Addressed Memory or B or Immediate Data Imm 8 Bit Immediate Data Reg Register Memory Addresses FO to FF Includes B X and SP Bit Bit Number 0 to 7 Loaded with Exchanged with ADD ADC SUBC AND ANDSZ A lmm ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed Skip if Zero A lt A A lt A C C lt Carry HC lt Half Carry A lt A C C lt Carry HC lt Half Carry AA and Skip next if A and Imm 0 OR A Meml Logical OR A lt A or Meml XOR A Meml Logical EXclusive OR A lt A xor IFEQ MD Imm IF EQual Compare MD and Imm Do next if MD Imm IFEQ EQual Compare A and Meml Do next if A Meml IFNE IF Not Equal Compare A and Meml Do next if A Meml IFGT A Meml IF Greater Than Compare A and Meml Do next if gt IFBNE If B Not Equal Do next if lower 4 bits of B Imm DRSZ Reg Decrement Reg Skip if Zero 1 Skip if Reg 0 SBIT Mem Set BIT 1 to bit Mem bit 0 to 7 immediate RBIT Mem Reset BIT 0 to bit Mem IFBIT Mem IF BIT If bit or Mem is true do next instruction RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag X A Mem EXchange A with Memory A Mem x
63. ced the microcontroller in the HALT or IDLE modes In the other case the device will first execute the interrupt service routine and then revert to normal operation See HALT MODE for clock option wakeup information 10 6 INTERRUPT SUMMARY The device uses the following types of interrupts listed below in order of priority 1 The Software Trap non maskable interrupt triggered by the INTR 00 opcode instruction The Software Trap is acknowledged immediately This interrupt service rou tine can be interrupted only by another Software Trap The Software Trap should end with two RPND instruc tions followed by a restart procedure 2 Maskable interrupts triggered by an on chip peripheral block or an external device connected to the device Under ordinary conditions a maskable interrupt will not interrupt any other interrupt routine in progress A maskable interrupt routine in progress can be inter rupted by the non maskable interrupt request A maskable interrupt routine should end with an RETI instruction or prior to restoring context should return to execute the VIS instruction This is particularly useful when exiting long interrupt service routiness if the time between interrupts is short In this case the RETI instruc tion would only be executed when the default VIS rou tine is reached www national com 40 11 0 WATCHDOG Clock Monitor Each device contains a user selectable WATCHDOG and clock monitor The fol
64. ch etc sets the STPND flag without providing a way for it to be cleared all other interrupts will be locked out To alleviate this condition the user can use extra RPND instructions in the main program and in the WATCHDOG service routine if present There is no harm in executing extra RPND instructions in these parts of the program 10 5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select able edge sensitive interrupts which are all vectored into the same service subroutine The interrupt from Port L shares logic with the wake up circuitry The register WKEN allows interrupts from Port L to be individually enabled or disabled The register WKEDG specifies the trigger condition to be either a positive or a negative edge Finally the register WKPND latches in the pending trigger conditions The GIE Global Interrupt Enable bit enables the interrupt function A control flag LPEN functions as a global interrupt enable for Port L interrupts Setting the LPEN flag will enable inter rupts and vice versa A separate global pending flag is not needed since the register WKPND is adequate Since Port L is also used for waking the device out of the HALT or IDLE modes the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled If he elects to disable the interrupt then the device will restart execution from the instruction immediately following the in struction that pla
65. ct The memory address is specified by the contents of the B Register or X register pointer register In assembly language the notation B or X speci fies which register serves as the pointer Example Exchange Memory with Accumulator B Indirect X A B Reg Data Contents Contents Memory Before After Accumulator 01 Hex 87 Hex Memory Location 87 Hex 01 Hex 0005 Hex B Pointer 05 Hex 05 Hex Register B or X Indirect with Post Incrementing Decrementing The relevant memory address is specified by the contents of the B Register or X register pointer register The pointer register is automatically incremented or decremented after execution allowing easy manipulation of memory blocks with software loops In assembly lan guage the notation B B X or X specifies which register serves as the pointer and whether the pointer is to be incremented or decremented Example Exchange Memory with Accumulator B Indirect with Post Increment X A B Reg Data Contents Contents Memory Before After Accumulator 03 Hex 62 Hex Memory Location 62 Hex 03 Hex 0005 Hex B Pointer 05 Hex 06 Hex Intermediate The data for the operation follows the instruc tion opcode in program memory In assembly language the number sign character indicates an immediate operand 47 www national com 958402 COP8SG Family 14 0 Instruction Set continued Example Load Accumulator Immediate LD A 05 Reg Data Con
66. e phase SK clock to shift data in and out of the SIO register In both the modes the SK idle polarity can be either high or low The polarity is selected by bit 5 of Port G data register In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock In the alternate SK phase operation data is shifted in on the falling edge of the SK clock and shifted out on the G4 SO G5 SK G4 G5 Operation rising edge of the SK clock Bit 6 of Port G configuration Config Bit Config Bit Fun Fun register selects the SK edge 1 1 so Int MCROWIRE PLUS A control flag SKSEL allows either the normal SK clock or SK Master the alternate SK clock to be selected Resetting SKSEL he MICROWIRE PLUS logi clocked from the 2 1 selects the alter STATE SK Master nate SK clock The SKSEL is mapped into the G6 configu 1 0 SO Ext MICROWIRE PLUS ration bit The SKSEL flag will power up in the reset condi SK Slave tion selecting the normal SK signal 0 0 TRI Ext MICROWIRE PLUS STATE SK Slave TABLE 12 MICROWIRE PLUS Shift Clock Polarity and Sample Shift Phase SK Phase G6 SKSEL SO Clocked Out On SI Sampled On SK Idle Config Bit Phase Normal SK Falling Edge SK Rising Edge Low Alternate 1 0 SK Rising Edge SK Falling Edge Low Alternate 0 1 SK Rising Edge SK Falling Edge High Normal 1 1 SK Falling Edge SK Rising Edge High
67. e when the external event occurs the time of the exter nal event is recorded Most microcontrollers have a latency time because they cannot determine the timer value when the external event occurs The capture register eliminates the latency time thereby allowing the applications program to retrieve the timer value stored in the capture register In this mode the timer Tx is constantly running at the fixed te rate The two registers RxA and RxB act as capture regis ters Each register acts in conjunction with a pin The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin The timer value gets copied over into the register when a trigger event occurs on its corresponding pin Control bits TxC3 TxC2 and TxC1 allow the trigger events to be speci fied either as a positive or a negative edge The trigger condition for each input pin can be specified independently The trigger conditions can also be programmed to generate interrupts The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively latched into the pending flags TXPNDA and TxPNDB The control flag Tx ENA allows the interrupt on TxA to be either enabled or disabled Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin Similarly the flag controls the interrupts from the TxB pin Underflows from the timer can also
68. eakage Voc 5 5V 5 5 Allowable Sink Current per Pin Note 9 D Outputs and LO to L3 15 15 mA All Others 3 3 mA www national com 10 DC Electrical Characteristics Continued 40 C lt 125 C unless otherwise specified 968409 Parameter Conditions Min Typ Max Units Maximum Input Current without Latchup Room Temp 200 mA Note 7 RAM Retention Voltage Vr 2 0 V Vec Rise Time from a Vec 2 2 0V Note 10 12 Us EPROM Data Retenton Note 8 Note 9 T 55 C gt 29 years Input Capacitance Note 9 7 pF Load Capacitance on D2 Note 9 1000 pF www national com COP8SG Family AC Electrical Characteristics 40 C lt Ta 125 C unless otherwise specified Parameter Conditions Max Units Instruction Cycle Time tc Crystal Resonator External 4 5V Vec lt 5 5V us R C Oscillator Internal 4 5V Voc lt 5 5V Hs Frequency Variation Note 9 4 5V Voc lt 5 5V 96 External Clock Duty Cycle Note 9 fr Max 55 Rise Time Note 9 fr 10 MHz Ext Clock 12 ns Fall Time Note 9 fr 10 MHz Ext Clock 8 ns MICROWIRE Setup Time tyws Note ns 11 MICROWIRE Hold Time tuwn Note ns 11 MICROWIRE Output Propagation Delay 220 ns tupp Note 11 Input Pulse Width Note 9 Interrupt Input High Time tc Interrupt Input Low Time ic Timer 1 2 3 Input High Time tc Timer 1 2 3 Input Low Time tc Reset Pulse Width H
69. eceiver only re quires one Stop bit in a frame regardless of the setting of the Stop bit selection bits in the control register Note that an implicit assumption is made for full duplex USART operation that the framing formats are the same for the transmitter and receiver www national com 30 8 0 USART Continued START BIT 7 BIT DATA 1a START B 7 BIT DATA 1b START B 7 BIT DATA 1 START 1 7 BIT DATA 2 STAR B 8 BIT DA 2a STAR BIT 8 BIT DA 2b STAR BIT 8 BIT DA 2c STAR B 8 BIT DA 3 START B 98 3a START BIT T DATA T DATA gt 7 gt gt A 25 25 10131740 FIGURE 22 Framing Formats 8 6 USART INTERRUPTS The USART is capable of generating interrupts Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty Both interrupts have individual interrupt vectors Two bytes of program memory space are reserved for each in terrupt vector The two vectors are located at addresses OxEC to OxEF Hex in the program memory space The interrupts can be individually enabled or disabled using En able Transmit Interrupt ETI and Enable Receive Interrupt ERI bits in the ENUI register The interrupt from the Transmitter is set pending and re mains pending as long as both the TBMT and ETI bits are set To remove this interrupt software must either clear the ETI bit or write to the TBUF register thus clearing
70. enable the SO and SK functions onto the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register In the slave mode the shift clock stops after 8 clock pulses Table 11 summarizes the bit settings required for Master mode of operation LCD VF LED DISPLAY DISPLAY 1 0 DRIVER 10131732 FIGURE 28 MICROWIRE PLUS Application 43 www national com Awe 958402 COP8SG Family 12 0 MICROWIRE PLUS continued 12 1 2 MICROWIRE PLUS Slave Mode Operation In the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register Table 11 summarizes the settings required to enter the Slave mode of operation TABLE 11 MICROWIRE PLUS Mode Settings This table assumes that the control flag MSEL is set The user must set the BUSY flag immediately upon entering the Slave mode This ensures that all data bits sent by the Master is shifted properly After eight clock pulses the BUSY flag is clear the shift clock is stopped and the sequence may be repeated 12 1 3 Alternate SK Phase Operation and SK Idle P The device allows either the normal SK clock or an alternat
71. er Reg CMPSL xxB8 UART Transmit Buffer Reg TBUF xxB9 UART Receive Buffer Reg RBUF xxBA UART Control and Status Register Reg ENU xxBB UART Receive Control and Status Register Reg ENUR xxBC UART Interrupt and Clock Source Register Reg ENUI xxBD UART Baud Register Reg BAUD xxBE UART Prescale Select Register Reg PSR xxBF Reserved for UART 0 Timer T2 Lower Byte xxC1 Timer T2 Upper Byte xxC2 Timer T2 Autoload Register T2RA Lower Byte xxC3 Timer T2 Autoload Register T2RA Upper Byte xxC4 Timer T2 Autoload Register T2RB Lower Byte xxC5 Timer T2 Autoload Register T2RB Upper Byte xxC6 Timer T2 Control Register xxC7 WATCHDOG Service Register Reg WDSVR xxC8 MIWU Edge Select Register Reg WKEDG Address S ADD REG xxC9 xxCA xxCB to xxCF xxDO xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD to xxDF xxEO to xxE5 xxE6 Contents MIWU Enable Register Reg WKEN MIWU Pending Register Reg WKPND Reserved Port L Data Register Port L Configuration Register Port L Input Pins Read Only Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins Read Only Port Input Pins Read Only Actually reads Port F input pins Port C Data Register Port C Configuration Register Port C Input Pins Read Only Reserved for Port C Port D Reserved for Port D Reserved for EE Control Registers Timer T1 Autoload Register T1RB Lower
72. er There is also the RCVG bit which is set high when a framing error occurs and goes low once RDX goes high TBMT XMTG RBFL and RCVG are read only bits 8 4 2 SYNCHRONOUS MODE In this mode data is transferred synchronously with the clock Data is transmitted on the rising edge and received on the falling edge of the synchronous clock This mode is selected by setting SSEL bit in the ENUI register The input frequency to the USART is the same as the baud rate When an external clock input is selected at the CKX pin data transmit and receive are performed synchronously with this clock through TDX RDX pins If data transmit and receive are selected with the CKX pin as clock output the device generates the synchronous clock output at the CKX pin The internal baud rate generator is used to produce the synchronous clock Data transmit and receive are performed synchronously with this clock 8 5 FRAMING FORMATS The USART supports several serial framing formats Figure 22 The format is selected using control bits in the ENU ENUR and ENUI registers The first format 1 1a 1b 1c for data transmission CHLO 1 0 consists of Start bit seven Data bits excluding parity and 7 8 one or two Stop bits In applications using parity the parity bit is generated and verified by hardware The second format CHLO 0 CHL1 0 consists of one Start bit eight Data bits excluding parity and 7 8 one or two Stop bits Parity
73. er supply rise time or 15 us whichever is greater FIGURE 9 Reset Circuit Using External Reset 5 9 2 On Chip Power On Reset The on chip reset circuit is selected by a bit in the ECON register When enabled the device generates an internal reset as Vcc rises to a voltage level above 2 0V The on chip reset circuitry is able to detect both fast and slow rise times on Voc Voc rise time between 10 ns and 50 ms To guar antee an on chip power on reset Vc c must start at a voltage less than the start voltage specified in the DC characteris tics Also if Voc be lowered to the start voltage before powering back up to the operating range If this is not pos sible it is recommended that external reset be used Under no circumstances should the RESET pin be allowed to float If the on chip Power On Reset feature is being used RESET pin should be connected directly or through a pull up resistor to Voc The output of the power on reset detector will always preset the Idle timer to OFFF 4096 tc At this time the internal reset will be generated If the Power On Reset feature is enabled the internal reset will not be turned off until the Idle timer underflows The internal reset will perform the same functions as external reset The user is responsible for ensuring that Vec is at the minimum level for the operating frequency within the 4096 tc After the underflow the logic is designed such that no additional internal resets occur as
74. errupt from the receiver section Read Write cleared on reset ERI 20 Interrupt from the receiver is disabled ERI 1 Interrupt from the receiver is enabled ETI This bit enables disables interrupt from the transmitter section Read Write cleared on reset 20 Interrupt from the transmitter is disabled 21 Interrupt from the transmitter is enabled 29 www national com 958402 COP8SG Family 8 0 USART Continued 8 3 Associated I O Pins Data is transmitted on the TDX pin and received on the RDX pin TDX is the alternate function assigned to Port L pin L2 it is selected by setting ETDX in the ENUI register to one RDX is an inherent function of Port L pin L3 requiring no setup The baud rate clock for the USART can be generated on chip or can be taken from an external source Port L pin L1 CKX is the external clock I O pin The CKX pin can be either an input or an output as determined by Port L Con figuration and Data registers Bit 1 As an input it accepts a clock signal which may be selected to drive the transmitter and or receiver As an output it presents the internal Baud Rate Generator output 8 4 USART Operation The USART has two modes of operation asynchronous mode and synchronous mode 8 4 1 ASYNCHRONOUS MODE This mode is selected by resetting the SSEL in the ENUI register bit to zero The input frequency to the USART is 16 times the baud rate The TSFT a
75. ery Low power 8 bit microcontrollers supply the smarts to control battery operated consumer industrial and automotive appli cations Each device offers system designers a variety of low power consumption features that enable them to meet the demand ing requirements of today s increasing range of low power applications These features include low voltage operation low current drain and power saving features such as HALT IDLE and Multi Input wakeup MIWU Each device offers the user two power save modes of op eration HALT and IDLE In the HALT mode all microcontrol ler activities are stopped In the IDLE mode the on board oscillator circuitry and timer TO are active but all other micro controller activities are stopped In either mode all on board RAM registers I O states and timers with the exception of TO are unaltered Clock Monitor if enabled can be active in both modes 7 1 HALT MODE Each device can be placed in the HALT mode by writing a 1 to the HALT flag G7 data bit All microcontroller activities including the clock and timers are stopped The WATCH DOG logic on the devices are disabled during the HALT mode However the clock monitor circuitry if enabled re mains active and will cause the WATCHDOG output pin WDOUT to go low If the HALT mode is used and the user does not want to activate the WDOUT pin the Clock Monitor should be disabled after the devices come out of reset resetting the Cl
76. ety world wide www national com cop8 Cost Free VL lt 100 L 100 300 M 300 1k H 1k 3k VH 3k 5k www national com 56 16 0 COP8 Tools Overview Continued 16 3 WHERE TO GET TOOLS Tools can be ordered directly from National National s e store a National Distributor or from the tool vendor Go to the vendor s web site for current listings of distributors Vendor Home Office Electronic Sites Other Main Offices Byte Craft Limited IAR Systems AB 421 King Street North Waterloo Ontario Canada N2J 4E4 Tel 1 519 888 6911 Fax 519 746 6751 PO Box 23051 S 750 23 Uppsala Sweden Tel 46 18 16 78 00 Fax 46 18 16 78 38 www bytecraft com info bytecraft com www iar se info ar se info ar com info arsys co uk info iar de Distributors Worldwide USA San Francisco Tel 1 415 765 5500 Fax 1 415 765 5503 UK London Tel 44 171 924 33 34 Fax 44 171 924 53 41 Germany Munich Tel 49 89 470 6022 Fax 49 89 470 956 Semiconductor Santa Clara CA 95051 USA Tel 1 800 272 9959 Fax 1 800 737 7018 support nsc com europe support nsc com KANDA Systems Unit 17 18 www kanda com USA LTD Glanyrafon Enterprise Park support kanda com Tel 800 331 7766 Aberystwyth Ceredigion usasupport kanda com Fax 303 456 2404 SY23 3JQ UK KandK Kaergaardsvej 42 DK 8355 www kkd dk kkd kkd dk Development ApS Solbjerg Denmark Fax
77. for data segment 2 etc up to FFOO to FF7F for data segment 255 The base address range from 0000 to 007F represents data segment 0 Figure 7 illustrates how the S register data memory exten sion is used in extending the lower half of the base address range 00 to 7F hex into 256 data segments of 128 bytes each with a total addressing range of 32 kbytes from XX00 to XX7F This organization allows a total of 256 data seg ments of 128 bytes each with an additional upper base segment of 128 bytes Furthermore all addressing modes are available for all data segments The S register must be changed under program control to move from one data segment 128 bytes to another However the upper base segment containing the 16 memory registers registers control registers etc is always available regardless of the contents of the S register since the upper base segment address range 0080 to OOFF is independent of data seg ment extension www national com 5 0 Functional Description Continued XXFF REGISTERS 16 BYTES INCLUDES B X SP 5 XXEF TIMERS 1 0 MW CNTRL PSW A D ICNTRL MIMU AND UART REGISTERS Xx90 XX8F READS UNDEFINED DATA XX80 007F BASE ADDRESS RANGE SEGMENT 0 017F UNUSED 0070 006F l 0000 SP INITIALIZED TO 6F ON CHIP RAM 112 BYTES 0100 SEGMENT 1 ON CHIP RAM 128 BYTES 027F 037F SEGMENT 2 SEGMENT 3 ON CHIP RAM 128
78. ge Note 12 0 4V lt Vin lt 1 5V mV Input Common Mode Voltage Range 0 4 V Voltage Gain dB Low Level Output Current Vor 0 4V 1 6 mA High Level Output Current Vou 0 4V 1 6 mA DC Supply Current per Comparator 150 When Enabled Response Time Note 13 200 mV step input 100 mV Overdrive 600 ns 100 pF Load Comparator Enable Time Note 14 600 ns Note 12 The comparator inputs are high impedance port inputs and as such input current is limited to port input leakage current Note 13 Response time is measured from a step input to a valid logic level at the comparator output software response time is dependent of instruction execution Note 14 Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the output of the comparator either by hardware or by software Be upp so X 10131709 FIGURE 3 MICROWIRE PLUS Timing 9 www national com 968409 COP8SG Family Absolute Maximum Ratings Note 2 Storage Temperature If Military Aerospace specified devices are required Range 65 C to 140 C please contact the National Semiconductor Sales Office ESD Protection Level 2kV Human Body Distributors for availability and specifications Model Supply Voltage 7 Note 15 Absolute maximum ratings indicate limits beyond which damage to Voltage at Any Pin 0 3 to 0 3V the device may occur DC and AC
79. ggle is latched into the TOPND pending flag and will occur every 2 731 ms at the maximum clock frequency 0 67 us A control flag TOEN allows the interrupt from the twelfth bit of Timer TO to be enabled or disabled Setting TOEN will enable the interrupt while reset ting it will disable the interrupt 6 2 TIMER T1 TIMER T2 and TIMER T3 Each device have a set of three powerful timer counter blocks T1 T2 and Since T1 T2 and are identical all comments are equally applicable to any of the three timer blocks which will be referred to as Tx Each timer block consists of a 16 bit timer Tx and two supporting 16 bit autoreload capture registers RxA and RxB Each timer block has two pins associated with it TxA and TxB The pin TxA supports I O required by the timer block while the pin TxB is an input to the timer block The timer block has three operating modes Processor Indepen dent PWM mode External Event Counter mode and Input Capture mode The control bits TxC3 TxC2 and TxC1 allow selection of the different modes of operation 6 2 1 Mode 1 Processor Independent PWM Mode One of the timer s operating modes is the Processor Inde pendent PWM mode In this mode the timer generates a Processor Independent PWM signal because once the timer is setup no more action is required from the CPU which translates to less software overhead and greater throughput The user software services the timer block only when
80. gramming Factory programming available for high volume requirements www national com 958402 COP8SG Family 16 0 COP8 Tools Overview continued 16 2 TOOLS ORDERING NUMBERS FOR THE COP8SGx FAMILY DEVICES The COP8 IM 400 ICE can be used for emulation with the limitation of 10 MHz emulation speed maximum For full speed COP8SGx emulation use the 15 MHz COP8 DM SG or COP8 EM SG Note The following order numbers apply to the COP8 devices in this datasheet only Vendor Tools Order Number Cost Notes COP8 NSEVAL COP8 NSEVAL VL Order from web site COP8 REF COP8 REF SG VL Order from web site COP8 EVAL COP8 EVAL COB1 VL Order from web site COP8 NSDEV COP8 NSDEV VL Included in EM Order CD from web site COP8 EM COP8 EM SG M Included p s 28 40 pin DIP target cable manuals software EM Target Cables COP8 EMC 44P VL 44 PLCC Target Cable and Converters 8 28 5 28 CSP Target Cable COP8 EMA xxSO DIP to SOIC Cable Converter COP8 EMA 44QFP 44 pin PLCC to 44 QFP Cable Converter Development COP8SGR7 COP8SGE7 VL 32k or 8k Eraseable OTP devices Devices COP8 PM COP8 PM 00 L Included p s manuals software 16 20 28 40 DIP SO and 44 PLCC programming socket add OTP adapter or target adapter if needed OTP Programming Adapters MetaLink COP8 DM COP8 PGMA 44QFP L For programming 44 QFP on any programmer COP8 PGMA 28CSP For programming 28 CSP on any programmer COP8 PGMA 44CSP For programm
81. he HALT mode as a result of a runaway program or power glitch If the device is placed in the HALT mode with the R C oscillator selected the clock input pin CKI is forced to a logic high internally With the crystal or external oscillator the CKI pin is TRI STATE It is recommended that the user not halt the device by merely stopping the clock in external oscillator mode If this method is used there is a possibility of greater than specified HALT current If the user wishes to stop an external clock it is recom mended that the CPU be halted by setting the Halt flag first and the clock be stopped only after the CPU has halted 25 www national com 958402 COP8SG Family 7 0 Power Saving Features Continued eedem 256 te DEVICE ACTIVE DEVICE IN HALT MODE i DEVICE ACTIVE Unaltered Dee late e SBIT 7 PORTGD Function NOP Registers NOP Timers 57 Active Ports xi x PORT L RESET CKO G7 10131725 FIGURE 18 Wakeup from HALT 7 2 IDLE MODE The user can enter the IDLE mode with the Timer TO inter The device is placed in the IDLE mode by writing a 1 to the rupt enabled In this case when the TOPND bit gets set the IDLE flag G6 data bit In this mode all activities except the device will first execute the Timer TO interrupt service routine associated on board oscillator circuitry and the IDLE Timer and then return to the ins
82. infor mation can be obtained at our web site at www national com cop8 16 1 SUMMARY OF TOOLS COP8 Evaluation Software and Reference Designs COP8 NSEVAL Software Evaluation package for Win dows A fully integrated evaluation environment for COP8 Includes WCOPS8 IDE evaluation version Inte grated Development Environment COP8 NSASM Full COP8 Assembler COP8 MLSIM 8 Instruction Level Simulator COP8C Compiler Demo DriveWay COP8 Device Driver Builder Demo Manuals Applica tions Software and other COP8 technical information COP8 REF xx Reference Designs for COP8 Families Realtime hardware environment with a variety of func tions for demonstrating the various capabilities and fea tures of specific COP8 device families Run Win 95 demo reference software and exercise specific device capabili ties COP8 Starter Kits and Hardware Target Solutions e COP8 EVAL xxx A variety of Multifunction Evaluation Design Test and Target Boards for COP8 Families Re altime target design environments with a selection of peripherals and features including multi LCD display keyboard A D D A EEPROM USART LEDs and bread board area Quickly design test and implement a custom target system some target boards are stand alone and ready for mounting into a standard enclosure or just evaluate and test your code COP8 Software Development Languages and Integrated Environments COP8 NSDEV National s COP8 Software
83. ing 44 CSP on any programmer COP8 PGMA 28SO For programming 16 20 28 SOIC on any programmer DM5 KCOP8 SG M Included p s PS 10 target cables DIP and PLCC 16 20 28 40 DIP SO and 44 PLCC programming sockets Add OTP adapter if needed and target adapter if needed DM Target Adapters OTP Programming MHW CNVxx 33 34 L DM target converters for etc 16DIP 20S0 28SO 44QFP 28CSP i e MHW CNV38 for 20 pin DIP to SO package converter MHW COP8 PGMA DS L For programming 16 20 28 SOIC and 44 PLCC on the IM Probe Card IM Probe Target Adapters EPU MHW COP8 PGMA 44QFP L For programming 44 QFP on any programmer MHW COP8 PGMA 28CSP L For programming 28 CSP on any programmer COP8 IM IM COP8 AD 464 220 H Base unit 10 MHz 220 220V add probe card 10 MHz maximum required and target adapter if needed included software and manuals PC COP8SG44PW AD 10 10 MHz 44 PLCC probe card 2 5V to 6 0V PC COP8SG40DW AD 10 10 MHz 40 DIP probe card 2 5V to 6 0V MHW SOICxx xx 16 20 L 16 or 20 or 28 pin SOIC adapter for probe card OTP Programmers Adapters 28 MHW CONV33 L 44 pin QFP adapter for 44 PLCC probe card KKD WCOP8 IDE WCOP8 IDE VL Included in DM and EM IAR EWCOP8 xx See summary above L H Included all software and manuals Byte COP8C COP8C COP8CWIN M Included all software and manuals Craft Aisys DriveWay COP8 DriveWay COP8 Included all software and manuals Go to L H A wide vari
84. instruction that would have been executed had there been no interrupt If there are any valid interrupts pending the highest priority interrupt is serviced immedi ately upon return from the previous interrupt 10 3 VIS INSTRUCTION The general interrupt service routine which starts at address OOFF Hex must be capable of handling all types of inter rupts The VIS instruction together with an interrupt vector table directs the device to the specific interrupt handling routine based on the cause of the interrupt VIS is a single byte instruction typically used at the very beginning of the general interrupt service routine at address OOFF Hex or shortly after that point just after the code used for context switching The VIS instruction determines which enabled and pending interrupt has the highest priority and causes an indirect jump to the address corresponding to that interrupt source The jump addresses vectors for all pos sible interrupts sources are stored in a vector table The vector table may be as long as 32 bytes maximum of 16 vectors and resides at the top of the 256 byte block con taining the VIS instruction However if the VIS instruction is at the very top of a 256 byte block such as at OOFF Hex the vector table resides at the top of the next 256 byte block Thus if the VIS instruction is located somewhere between OOFF and 01DF Hex the usual case the vector table is located between addresses 01E0 and 01FF Hex
85. is a pending register for the occurrence of selected wakeup conditions the device will not enter the HALT mode if any Wakeup bit is both enabled and pending Consequently the user must clear the pending flags before attempting to enter the HALT mode WKEN and WKEDG are all read write registers and are cleared at reset WKPND register contains random value after reset INTERNAL DATA BUS LO L7 LPEN BIT IN ICNTRL REG Low going High High going Low 1 TO INTERRUPT LOGIC CHIP CLOCK 10131727 FIGURE 20 Multi Input Wake Up Logic 27 www national com 958402 COP8SG Family 8 0 USART Each device contains a full duplex software programmable USART The USART Figure 21 consists of a transmit shift register a receive shift register and seven addressable reg isters as follows a transmit buffer register TBUF a re ceiver buffer register RBUF a USART control and status register ENU a USART receive control and status register ENUR a USART interrupt and clock source register ENUI a prescaler select register PSR and baud BAUD register The ENU register contains flags for transmit and receive functions this register also determines the length of the data frame 7 8 or 9 bits the value of the ninth bit in transmission and parity selection bits The ENUR register flags framing data overrun and parity errors while the US ART is receiving o 2 a lt H lt a l lt 2
86. itors the com munication flow but ignores all characters until an address character is received Upon receiving an address character the USART signals that the character is ready by setting the RBFL flag which in turn interrupts the processor if USART Receiver interrupts are enabled The ATTN bit is also cleared automatically at this point so that data characters as well as address characters are recognized Software examines the contents of the RBUF and responds by deciding either to accept the subsequent data stream by leaving the ATTN bit reset or to wait until the next address character is seen by setting the ATTN bit again Operation of the USART Transmitter is not affected by se lection of this Mode The value of the ninth bit to be trans mitted is programmed by setting XBIT9 appropriately The value of the ninth bit received is obtained by reading RBIT9 Since this bit is located in ENUR register where the error flags reside a bit operation on it will reset the error flags 9 0 Comparators The device contains two differential comparators each with a pair of inputs positive and negative and an output Ports F1 F3 and F4 F6 are used for the comparators The follow ing is the Port F assignment F6 Comparator2 output F5 Comparator2 positive input F4 Comparator2 negative input F3 Comparatori output F2 Comparatori positive input 33 www national com 968409 COP8SG Family 9 0 Comparators Conti
87. long as Voc remains above 2 0V The contents of data registers and RAM are unknown fol lowing the on chip reset On Chip Reset NOT ACTIVE 9 lt gt 3 ACTIVE 1 1 1 1 RESET 1 I x is the minimum operating voltage for the 1 frequency of operation gt 50 ms 14 4096 t gt tun 10ns 10131715 FIGURE 10 Reset Timing Power On Reset Enabled with Vcc Tied to RESET 10131716 FIGURE 11 Reset Circuit Using Power On Reset 19 www national com 968409 COP8SG Family 5 0 Functional Description Continued 5 10 OSCILLATOR CIRCUITS There are four clock oscillator options available Crystal Oscillator with or without on chip bias resistor R C Oscillator with on chip resistor and capacitor and External Oscillator The oscillator feature is selected by programming the ECON register which is summarized in Table 1 TABLE 1 Oscillator Option 4 ECON3 0 0 Oscillator Option External Oscillator 1 0 Crystal Oscillator without Bias Resistor 0 1 R C Oscillator 1 1 Crystal Oscillator with Bias Resistor 5 10 1 Crystal Oscillator The crystal Oscillator mode can be selected by programming ECON Bit 4 to 1 CKI is the clock input while G7 CKO is the clock generator output to the crystal An on chip bias resistor connected between and CKO can be enabled by pro gra
88. lowing section is applicable only if WATCHDOG feature has been selected in the ECON regis ter WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or runaway programs The WATCHDOG logic contains two separate service win dows While the user programmable upper window selects the WATCHDOG service time the lower window provides protection against an infinite program loop that contains the WATCHDOG service instruction The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin The WATCHDOG consists of two independent logic blocks WD UPPER and WD LOWER WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM This value is com posed of three fields consisting of a 2 bit Window Select a 5 bit Key Data field and the 1 bit Clock Monitor Select field Table 7 shows the WDSVR register TABLE 7 WATCHDOG Service Register WDSVR Window Select Key Data Monitor xx 01111 01 1 v 7 6 5 4 3 2 1 lower limit of the service window is fixed at 2048 instruc tion cycles Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window Table 8 shows the four possi
89. ly points to a memory loca tion beyond the available program memory space the non existent or unused memory location returns zeroes which is interpreted as the INTR instruction If the stack is popped beyond the allowed limit address O6F Hex a 7FFF will be loaded into the PC if this last location in program memory is unprogrammed or unavailable a Soft ware Trap will be triggered A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch The Software Trap has the highest priority of all interrupts When a Software Trap occurs the STPND bit is set The GIE bit is not affected and the pending bit not accessible by the user is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction Nothing can interrupt a Software Trap service routine except for another Software Trap The STPND can be reset only by the RPND instruction or a chip Reset The Software Trap indicates an unusual or unknown error condition Generally returning to normal execution at the point where the Software Trap occurred cannot be done reliably Therefore the Software Trap service routine should reinitialize the stack pointer and perform a recovery proce dure that restarts the software at some known point similar to a device Reset but not necessarily performing all the same functions as a device Reset The routine must also execute the RPND instruction to rese
90. m Fourteen multi source vectored interrupts servicing External interrupt Timers TO T3 MICROWIRE PLUS Serial Interface Multi Input Wake Up Software Trap USART 2 1 receive and 1 transmit Default VIS default interrupt 8 bit Stack Pointer SP stack in RAM True bit manipulation BCD arithmetic instructions Peripheral Features m Multi Input Wakeup Logic Two 8 bit Register Indirect Data Memory Pointers m Three 16 bit timers T1 T3 each with two 16 bit registers supporting Processor Independent PWM mode External Event Counter mode Input Capture mode 2001 National Semiconductor Corporation DS101317 www national com LYVSN pue 5 5 JZE 0 48 410 pue peseg WOY SOND 18 8 AjueJ 968402 COP8SG Family Peripheral Features Continued m Idle Timer TO MICROWIRE PLUS Serial Interface SPI Compatible Full Duplex USART m Two Analog Comparators Features m Software selectable 1 options TRI STATE9 Output Push Pull Output Weak Pull Up Input and High Impedance Input m Schmitt trigger inputs on ports G and L m Eight high current outputs m Packages 28 SO with 24 I O pins 40 DIP with 36 I O pins 44 PLCC PQFP and CSP with 40 I O pins Block Diagram AC 8 BIT CORE MODIFIED HARVARD ARCHITECTURE ILLEGAL COND DETECT 16 BIT TIMER T2 Fully Static CMOS
91. mming ECON Bit 3 to 1 with the crystal oscillator option selection The value of the resistor is in the range of 0 5M to 2M typically 1 0M Table 2 shows the component values required for various standard crystal values Resistor R2 is only used when the on chip bias resistor is disabled Figure 12 shows the crystal oscillator connection diagram TABLE 2 Crystal Oscillator Configuration 25 C Voc 5V CKI Freq R1 R2 MO C1 pF C2 pP nu 0 18 18 15 0 0 5 6 100 156 5 10 2 External Oscillator The External Oscillator mode can be selected by program ming ECON Bit 3 to 0 and ECON Bit 4 to 0 CKI can be driven by an external clock signal provided it meets the With On Chip Bias Resistor specified duty cycle rise and fall times and input levels G7 CKO is available as a general purpose input G7 and or Halt control Figure 13 shows the external oscillator connec tion diagram 5 10 3 R C Oscillator The R C Oscillator mode can be selected by programming ECON Bit 3 to 1 and ECON Bit 4 to 0 In R C oscillation mode CKI is left floating while G7 CKO is available as a general purpose input G7 and or HALT control The R C controlled oscillator has on chip resistor and capacitor for maximum R C oscillator frequency operation The maximum frequency is 5 MHz 35 for between 4 5V to 5 5V and temperature range of 40 C to 85 C For max fre quency operation the CKI pin should be left
92. nd TBUF registers double buffer data for trans mission While TSFT is shifting out the current character on the TDX pin the TBUF register may be loaded by software with the next byte to be transmitted When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register and the Transmit Buffer Empty Flag TBMT in the ENU register is set The TBMT flag is automatically reset by the USART when software loads a new character into the TBUF register There is also the XMTG bit which is set to indicate that the USART is transmitting This bit gets reset at the end of the last frame end of last Stop bit TBUF is a read write register The RSFT and RBUF registers double buffer data being received The USART receiver continually monitors the sig nal on the RDX pin for a low level to detect the beginning of a Start bit Upon sensing this low level it waits for half a bit time and samples again If the RDX pin is still low the receiver considers this to be a valid Start bit and the remain ing bits in the character frame are each sampled a single time at the mid bit position Serial data input on the RDX pin is shifted into the RSFT register Upon receiving the com plete character the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag RBFL is set RBFL is automatically reset when software reads the character from the RBUF register RBUF is a read only regist
93. nd the Clock Monitor detector armed with the WATCHDOG service window bits set and the Clock Monitor bit set The WATCHDOG and Clock Monitor circuits are inhibited during reset The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tc clock cycles The Clock Monitor bit being initialized high will cause a Clock Monitor error follow ing reset if the clock has not reached the minimum specified frequency at the termination of reset A Clock Monitor error will cause an active low error output on pin G1 This error output will continue until 16 1 32 tc clock cycles following the clock frequency reaching the minimum specified value at which time the G1 output will go high 5 9 1 External Reset The RESET input when pulled low initializes the device The RESET pin must be held low for a minimum of one instruc tion cycle to guarantee a valid reset During Power Up ini tialization the user must ensure that the RESET pin is held low until the device is within the specified Voc voltage An R C circuit on the RESET pin with a delay 5 times 5x greater than the power supply rise time or 15 uis whichever is greater is recommended Reset should also be wide enough to ensure crystal start up upon Power Up RESET may also be used to cause an exit from the HALT mode A recommended reset circuit for this device is shown in Figure 9 omo lt rr 10131714 RC gt 5x pow
94. ns the input only Port I instead of the bi directional Port F Port D is an 8 bit output port that is preset high when RESET goes low The user can tie two or more D port outputs except D2 together in order to get a higher drive Note Care must be exercised with the D2 pin operation At RESET the external loads on this pin must ensure that the output voltages stay above 0 7 Vcc to prevent the chip from entering special modes Also keep the external loading on D2 to less than 1000 pF Vec Weak Pullup Software Selectable PORT 1 6 AND C F DATA REGISTER CONFIGURATION REGISTER mpzam zo Port read into a RAM location address 10131710 FIGURE 4 I O Port Configurations PORT L G AND C F DATA REGISTER 0 1 CONFIGURATION REGISTER gt Port read into RAM address location 10131712 FIGURE 5 1 Port Configurations Output Mode Weak Pullup Software Selectable PORT L G AND C F DATA REGISTER 0 1 Pullup Disabled Pullup Enabled CONFIGURATION REGISTER Port read into a RAM address location gt zuomaz 10131711 FIGURE 6 I O Port Configurations Input Mode 15 www national com 958402 COP8SG Family 5 0 Functional Description The architecture of the devices are a modified Harvard ar chitecture With the Harvard architecture the progr
95. nued F1 Comparator negative input A Comparator Select Register CMPSL is used to enable the comparators read the outputs of the comparators inter nally and enable the outputs of the comparators to the pins Two control bits enable and output enable and one result bit are associated with each comparator The comparator result bits CMP1RD and CMP2RD are read only bits which will read as zero if the associated comparator is not enabled The Comparator Select Register is cleared with reset result ing in the comparators being disabled The comparators should also be disabled before entering either the HALT or IDLE modes in order to save power The configuration of the CMPSL register is as follows CMPSL REGISTER ADDRESS X 00B7 CMP20E CMP2RD Reserved CMP2EN CMP10E CMP1RD CMP1EN Reserved Bit 7 Bit 0 The CMPSL register contains the following bits Reserved These bits are reserved and must be zero CMP20E Selects pin I6 as comparator 2 output provided that CMP2EN is set to enable the comparator CMP2RD Comparator 2 result this is a read only bit which will read as 0 if the comparator is not enabled Enable comparator 2 Selects pin I3 as comparator 1 output provided that CMPIEN is set to enable the comparator CMP1RD Comparator 1 result this is a read only bit which will read as 0 if the comparator is not enabled CMP1EN Enable comparator 1 Note that the two unused bits
96. ock Monitor control bit with the first write to the WDSVR register In the HALT mode the power require ments of the devices are minimal and the applied voltage may be decreased to V V 2 0V without altering the state of the machine Each device supports three different ways of exiting the HALT mode The first method of exiting the HALT mode is with the Multi Input Wakeup feature on Port L The second method is with a low to high transition on the CKO G7 pin This method precludes the use of the crystal clock configu ration since CKO becomes a dedicated output and so may only be used with an R C clock configuration The third method of exiting the HALT mode is by pulling the RESET pin low On wakeup from G7 or Port L the devices resume execution from the HALT point On wakeup from RESET execution will resume from location PC 0 and all RESET conditions apply If a crystal or ceramic resonator may be selected as the oscillator the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli tude and frequency stability The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid Wakeup signal only the oscillator circuitry is enabled The IDLE timer is loaded with a value of 256 and is clocked with the
97. of CMPSL may be used as software flags Note If the user attempts to use the comparator output immediately after enabling the comparator an incorrect value may be read At least one instruction cycle should pass between these operations The use of a direct addressing mode instruction for either of these two operations will guar antee this delay in the software CMP2EN CMP10E SOFTWARE TRAP TIMER T1 EXTERNAL MULTI INPUT WAKE UP MICROWIRE PLUS FUTURE PERIPHERAL IDLE TIMER INTERRUPT ENABLE Note For compatibility with existing code and with existing Mask ROMMed devices the bits of the CMPSL register will take precedence over the associated Port F configuration and data output bits 10 0 Interrupts 10 1 INTRODUCTION Each device supports thirteen vectored interrupts Interrupt sources include Timer 0 Timer 1 Timer 2 Timer 3 Port L Wakeup Software Trap MICROWIRE PLUS and External Input All interrupts force a branch to location OOFF Hex in program memory The VIS instruction may be used to vector to the appropriate service routine from location OOFF Hex The Software trap has the highest priority while the default VIS has the lowest priority Each of the 13 maskable inputs has a fixed arbitration rank ing and vector Figure 25 shows the Interrupt Block Diagram PENDING FLAG INTERRUPT 10131728 FIGURE 25 Interrupt Block Diagram www national com 34 10 0 Interrupts continued
98. of control ad dressing modes are available to specify jump addresses A change in program flow requires a non incremental change in the Program Counter contents The Program Counter consists of two bytes designated the upper byte PCU and lower byte PCL The most significant bit of PCU is not used leaving 15 bits to address the program memory Different addressing modes are used to specify the new address for the Program Counter The choice of addressing mode depends primarily on the distance of the jump Farther jumps sometimes require more instruction bytes in order to completely specify the new Program Counter contents The available transfer of control addressing modes are Jump Relative Jump Absolute Jump Absolute Long Jump Indirect The transfer of control addressing modes are described be low Each description includes an example of a Jump in struction using a particular addressing mode and the effect on the Program Counter bytes of executing that instruction Jump Relative In this 1 byte instruction six bits of the instruction opcode specify the distance of the jump from the current program memory location The distance of the jump can range from 31 to 32 A JP 1 instruction is not allowed The programmer should use a NOP instead Example Jump Relative JP 0A Reg Contents Contents Before After PCU 02 Hex 02 Hex PCL 05 Hex OF Hex Jump Absolute In this 2 byte instruction 12 bits of the instruction opcode
99. onal Description Continued programmed to 0 for all other applications 0 Enable full port F capability HALT mode disabled 0 HALT mode enabled 5 6 USER STORAGE SPACE IN EPROM The ECON register is outside of the normal address range of the ROM and can not be accessed by the executing soft ware The COP8 assembler defines a special ROM section type CONF into which the ECON may be coded Both ECON and User Data are programmed automatically by programmers that are certified by National The following examples illustrate the declaration of ECON and the User information Syntax label sect econ conf db value 1 byte configures options db lt user information gt endsect up to 8 bytes Example The following sets a value in the ECON register and User Identification for a COP8SGR728M7 The ECON bit values shown select options Power on enabled Security disabled Crystal oscillator with on chip bias disabled WATCHDOG enabled and HALT mode enabled sect econ conf db 0x55 por xtal wd halt sdb vl 00 user data declaration endsect 5 7 OTP SECURITY The device has a security feature that when enabled pre vents external reading of the OTP program memory The security bit in the ECON register determines whether secu rity is enabled or disabled If the security feature is disabled the contents of the internal EPROM may be read If the security feature is enabled then any attempt to externally
100. ons The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown be low CONFIGURATION Register DATA Register Port Set Up Hi Z Input TRI STATE Output Input with Weak Pull Up Push Pull One Output Port Lis an 8 bit I O port All L pins have Schmitt triggers on the inputs Port L supports the Multi Input Wake Up feature on all eight pins Port L has the following alternate pin functions L7 Multi input Wakeup or T3B Timer T3B Input L6 Multi input Wakeup or T3A Timer T3A Input L5 Multi input Wakeup or T2B Timer T2B Input L4 Multi input Wakeup or T2A Timer T2A Input L3 Multi input Wakeup and or RDX USART Receive L2 Multi input Wakeup or TDX USART Transmit L1 Multi input Wakeup and or CKX USART Clock LO Multi input Wakeup Port G is an 8 bit port Pin GO G2 G5 are bi directional I O ports Pin G6 is always a general purpose Hi Z input All pins have Schmitt Triggers on their inputs Pin G1 serves as the dedicated WATCHDOG output with weak pullup if WATCHDOG feature is selected by the Mask Option reg ister The pin is a general purpose 1 if WATCHDOG feature is not selected If WATCHDOG feature is selected bit 1 of the Port G configuration and data register does not have any effect on Pin G1 setup Pin G7 is either input or output depending on the oscillator option selected With the crystal oscillator option selected G7
101. outine and Skip RETSK Return from Interrupt RETI Software Trap Interrupt INTR Vector Interrupt Select VIS 14 4 3 Load and Exchange Instructions The load and exchange instructions write byte values in registers or memory The addressing mode determines the source of the data Load LD Load Accumulator Indirect LAID Exchange X 14 4 4 Logical Instructions The logical instructions perform the operations AND OR and XOR Exclusive OR Other logical operations can be performed by combining these basic operations For ex ample complementing is accomplished by exclusiveORing the Accumulator with FF Hex Logical AND AND Logical OR OR Exclusive OR XOR 14 4 5 Accumulator Bit Manipulation Instructions The Accumulator bit manipulation instructions allow the user to shift the Accumulator bits and to swap its two nibbles Rotate Right Through Carry RRC Rotate Left Through Carry RLC Swap Nibbles of Accumulator SWAP 14 4 6 Stack Control Instructions Push Data onto Stack PUSH Pop Data off of Stack POP 14 4 7 Memory Bit Manipulation Instructions The memory bit manipulation instructions allow the user to set and reset individual bits in memory Set Bit SBIT Reset Bit RBIT Reset Pending Bit RPND 14 4 8 Conditional Instructions The conditional instruction test a condition If the condition is true the next instruction is executed in the normal manner if the condition is false the next inst
102. ow ing reset but might not contain the same program initializa tion procedures The recovery program should reset the software interrupt pending bit using the RPND instruction 12 0 MICROWIRE PLUS MICROWIRE PLUS is a serial SPI compatible synchronous communications interface The MICROWIRE PLUS capabil ity enables the device to interface with MICROWIRE PLUS or SPI peripherals i e A D converters display drivers EE PROMS etc and with other microcontrollers which support the MICROWIRE PLUS or SPI interface It consists of an 8 bit serial shift register SIO with serial data input SI serial data output SO and serial shift clock SK Figure 28 shows a block diagram of the MICROWIRE PLUS logic The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS www national com 42 12 0 MICROWIRE PLUS arrangement with the internal clock source is called the Master mode of operation Similarly operating the MICROWIRE PLUS arrangement with an external shift clock is called the Slave mode of operation The CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one In the master mode the SK clock rate is selected by the two bits SLO and SL1 in the CNTRL register Table 10 details the different clock rates that may be selected Continued TABLE 10 MICROWIRE PLUS Master
103. r sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 449 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Email support nsc com Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Deutsch Tel 49 0 69 9508 6208 Fax 65 2504466 English Tel 44 0 870 24 0 2171 Email ap support nsc com www national com Frangais Tel 33 0 1 41 91 8790 COP8SG Family 8 Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory Two National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
104. r the LAID instruction jump vectors for the JID instruction and interrupt vectors for the VIS instruction The program memory is addressed by the 15 bit program counter PC All interrupts in the device vector to program memory location OFF Hex The contents of the program memory read 00 Hex in the erased state Program execution starts at location 0 after RESET 5 3 DATA MEMORY The data memory address space includes the on chip RAM and data registers the I O registers Configuration Data and Pin the control registers the MICROWIRE PLUS SIO shift register and the various registers and counters associated with the timers with the exception of the IDLE timer Data memory is addressed directly by the instruction or indirectly by the B X and SP pointers The data memory consists of 256 or 512 bytes of RAM Sixteen bytes of RAM are mapped as registers at ad dresses OFO to OFE Hex These registers can be loaded immediately and also decremented and tested with the DRSZ decrement register and skip if zero instruction The memory pointer registers X SP and B are memory mapped into this space at address locations OFC to OFE Hex respec tively with the other registers except OFF being available for general usage The instruction set permits any bit in memory to be set reset or tested All I O and registers except A and are memory mapped therefore I O bits and register bits can be directly and individually set reset
105. rand addressing modes are available allowing memory locations to be specified in a variety of ways An instruction can specify an address directly by supplying the specific address or indirectly by specifying a register pointer The contents of the register or in some cases two registers point to the desired memory location In the immediate mode the data byte to be used is contained in the instruction itself Each addressing mode has its own advantages and disad vantages with respect to flexibility execution speed and program compactness Not all modes are available with all instructions The Load LD instruction offers the largest number of addressing modes The available addressing modes are Direct Register B or X Indirect e Register B or X Indirect with Post Incrementing Decrementing Immediate mmediate Short Indirect from Program Memory The addressing modes are described below Each descrip tion includes an example of an assembly language instruc tion using the described addressing mode Direct The memory address is specified directly as a byte in the instruction In assembly language the direct address is written as a numerical value or a label that has been defined elsewhere in the program as a numerical value Example Load Accumulator Memory Direct LD A 05 Reg Data Contents Contents Memory Before After Accumulator XX Hex A6 Hex Memory Location A6 Hex A6 Hex 0005 Hex Register B or X Indire
106. re all open With a key closure the corresponding input line will read a logic zero since the weak pull up can easily be overdriven When the key is released the internal weak pull up will pull the input line back to logic high This eliminates the need for external pull up resistors The high current options are avail able for driving LEDs motors and speakers This flexibility helps to ensure a cleaner design with less external compo nents and lower costs Below is the general description of all available pins Vcc and GND are the power supply pins All and GND pins must be connected CKI is the clock input This can come from the Internal R C oscillator external or a crystal oscillator in conjunction with CKO See Oscillator Description section RESET is the master reset input See Reset description section Each device contains four bidirectional 8 bit I O ports C G L and F where each individual bit may be independently configured as an input Schmitt trigger inputs on ports L and G output or TRI STATE under program control Three data memory address locations are allocated for each of these ports Each port has two associated 8 bit memory mapped registers the CONFIGURATION register and the output DATA register A memory mapped address is also reserved for the input pins of each I O port See the memory map for the various addresses associated with the I O ports Figure 4 shows the 1 port configurati
107. read the contents of the EPROM will result in the value FF Hex being read from all program locations Under no circumstances can a secured part be read In addition with the security feature enabled the write opera tion to the EPROM program memory and ECON register is inhibited The ECON register is readable regardless of the state of the security bit The security bit when set cannot be erased even in windowed packages If the security bit is set in a device in a windowed package that device may be erased but will not be further programmable If security is being used it is recommended that all other bits in the ECON register be programmed first Then the security bit can be programmed 5 8 ERASURE CHARACTERISTICS The erasure characteristics of the device are such that era sure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 4000 range After programming opaque labels should be placed over the window of windowed devices to prevent unintentional era sure Covering the window will also prevent temporary func tional failure due to the generation of photo currents The recommended erasure procedure for windowed devices is exposure to short wave ultraviolet light which has a wave length of 2537 Angstroms The integrated dose i e UV intensity X exposure time for era
108. rflow OyF6 OyF7 6 Timer T1 T1B OyF4 OyF5 7 MICROWIRE PLUS BUSY Low OyF2 OyF3 8 Reserved OyFO OyF1 9 USART Receive OyEE OyEF USART Transmit OyEC OyED Timer T2 T2A Underflow OyEA OyEB 12 Timer T2 T2B 8 0 9 13 Timer T3 T2A Underflow OyE6 OyE7 14 Timer T3 T3B 0 4 0 5 15 Port L Wakeup Port L Edge OyE2 0yE3 16 Lowest Default VIS Reserved OyEO OyE1 Note 17 y is a variable which represents the VIS block VIS and the vector table must be located in the same 256 byte block except if VIS is located at the last address of a block In this case the table must be in the next block www national com 36 10 0 Interrupts continued 10 3 1 VIS Execution When the VIS instruction is executed it activates the arbitra tion logic The arbitration logic generates an even number between EO and FE E2 EA etc depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed For example if the software trap interrupt is active FE is generated If the external interrupt is active and the software trap interrupt is not then FA is generated and so forth If the only active interrupt is software trap than EO is generated This number replaces the lower byte of the PC The upper byte of the PC INTERRUPT after an interrupt ARBITRATION LOGIC generates an even number between EO and FE STARTING ADDRESS HIGH LOW ST
109. ruction is skipped If Equal IFEQ If Not Equal IFNE If Greater Than IFGT If Carry IFC If Not Carry IFNC If Bit IFBIT If B Pointer Not Equal IFBNE And Skip if Zero ANDSZ Decrement Register and Skip if Zero DRSZ 14 4 9 No Operation Instruction The no operation instruction does nothing except to occupy space in the program memory and time in execution No Operation NOP Note The VIS is a special case of the Indirect Transfer of Control addressing mode where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter PC in order to jump to the associated interrupt service routine 49 www national com 958402 COP8SG Family 14 0 Instruction Set continued 14 5 REGISTER AND SYMBOL DEFINITION The following abbreviations represent the nomenclature used in the cross assembler instruction description and the COP8 Enable 8 Bit Accumulator Register 8 Bit Address Register 8 Bit Address Register 8 Bit Stack Pointer Register 15 Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1 Bit of PSW Register for Carry 1 Bit of PSW Register for Half Carry 1 Bit of PSW Register for Global Interrupt Registers 14 6 INSTRUCTION SET SUMMARY VU Interrupt Vector Upper Byte VL Interrupt Vector Lower Byte Symbols B Memory Indirectly Addressed
110. s Comparators AC and DC Characteristics Voc 5V 40 C lt 125 Parameter Conditions Min Typ Max Units Input Offset Voltage Note 12 5 25 mV Input Common Mode Voltage Range Voc 1 5 V Voltage Gain dB Low Level Output Current Vor 0 4V mA High Level Output Current Vou Voc 0 4V mA DC Supply Current per Comparator 150 When Enabled Response Time Note 13 200 mV step input NENNEN 600 en 100 mV Overdrive Comparator Enable Time 11 11 600 ns www national com 12 Typical Performance Characteristics 25 C unless otherwise specified Idd HALT Idd Idle External Clock Option 3 3 25 3 3 5 4 4 5 5 5 5 6 2 5 3 3 5 4 4 5 5 5 5 6 Vec V Vec V 10131749 10131750 144 Dynamic External Clock Option Maximum Frequency E 8 E gt o 2 5 3 3 5 4 4 5 5 55 6 2 5 3 3 5 4 4 5 5 5 5 6 Vcc V Vcc V 10131751 10131752 13 www national com 958402 COP8SG Family 4 0 Pin Descriptions The COP8SGx structure enables designers to reconfig ure the microcontroller s I O functions with a single instruc tion Each individual I O pin can be independently configured as output pin low output high input with high impedance or input with weak pull up device A typical example is the use of I O pins as the keyboard matrix input lines The input lines can be programmed with internal weak pull ups so that the input lines read logic high when the keys a
111. should be reset followed by the edge select change in WKEDG Next the associated WKPND bit should be cleared followed by the associated WKEN bit being re enabled An example may serve to clarify this procedure Suppose we wish to change the edge select from positive low going high to negative high going low for L Port bit 5 where bit 5 has previously been enabled for an input interrupt The program would be as follows RBIT 5 WKEN Disable MIWU SBIT 5 WKEDG Change edge polarity RBIT 5 WKPND Reset pending flag SBIT 5 WKEN Enable MIWU If the L port bits have been used as outputs and then changed to inputs with Multi Input Wakeup Interrupt a safety procedure should also be followed to avoid wakeup condi tions After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled the associated edge select bits in WKEDG should be set or reset for the desired edge selects followed by the associated WKPND bits being cleared This same procedure should be used following reset since the L port inputs are left floating as a result of reset The occurrence of the selected trigger condition for Multi Input Wakeup is latched into a pending register called WK PND The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corre sponding Port L pin The user has the responsibility of clear ing these pending flags Since WKPND
112. ster contains the following bits T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control bit T3CO Timer Start Stop control in timer modes 1 and 2 T3 Underflow Interrupt Pend ing Flag in timer mode 3 T3PNDA Timer Interrupt Pending Flag Autoreload RA in mode 1 T3 Underflow in mode 2 T3A capture edge in mode 3 TSENA Timer Interrupt Enable for Timer Underflow or T3A Input capture edge Timer Interrupt Pending Flag for cap ture edge TSENB Timer T3 Interrupt Enable for Timer Underflow or T3B Input capture edge 6 0 Timers Each device contains a very versatile set of timers TO T1 T2 and T3 Timer T1 T2 and T3 and associated autoreload capture registers power up containing random data 6 1 TIMER TO IDLE TIMER Each device supports applications that require maintaining real time and low power with the IDLE mode This IDLE mode support is furnished by the IDLE timer TO The Timer TO runs continuously at the fixed rate of the instruction cycle clock The user cannot read or write to the IDLE Timer TO which is a count down timer The Timer TO supports the following functions Exit out of the Idle Mode See Idle Mode description WATCHDOG logic See WATCHDOG description Start up delay out of the HALT mode Timing the width of the internal power on reset The IDLE Timer TO can generate an interrupt when the twelfth bit toggles This to
113. such as DRSZ Three memory mapped pointers two for register indirect addressing and one for the software stack Sixteen memory mapped registers that allow an opti mized implementation of certain instructions Ability to set reset and test any individual bit in data memory address space including the memory mapped ports and registers Register Indirect LOAD and EXCHANGE instructions with optional automatic post incrementing or decrement ing of the register pointer This allows for greater effi ciency both in cycle time and program code in loading walking across and processing fields in data memory Unique instructions to optimize program size and throughput efficiency Some of these instructions are DRSZ IFBNE DCOR RETSK VIS and RRC 14 3 ADDRESSING MODES The instruction set offers a variety of methods for specifying memory addresses Each method is called an addressing mode These modes are classified into two categories op erand addressing modes and transfer of control addressing modes Operand addressing modes are the various meth ods of specifying an address for accessing reading or writ ing data Transfer of control addressing modes are used in conjunction with jump instructions to control the execution sequence of the software program 14 3 1 Operand Addressing Modes The operand of an instruction specifies what memory loca tion is to be affected by that instruction Several different ope
114. sure should be a minimum of 15W sec cm 5 9 RESET The devices are initialized when the RESET pin is pulled low or the On chip Power On Reset is enabled EXTERNAL INTERNAL RESET ON CHIP POWER ON RESET ECON Bit 6 10131713 FIGURE 8 Reset Logic The following occurs upon initialization Port L TRI STATE High Impedance Input Port C TRI STATE High Impedance Input Port G TRI STATE High Impedance Input Port F TRI STATE High Impedance Input Port D HIGH PC CLEARED to 0000 PSW CNTRL and ICNTRL registers CLEARED SIOR UNAFFECTED after RESET with power already applied RANDOM after RESET at power on T2CNTRL CLEARED TSCNTRL CLEARED Accumulator Timer 1 Timer 2 and Timer 3 RANDOM after RESET with crystal clock option power already applied UNAFFECTED after RESET with R C clock option power already applied RANDOM after RESET at power on WKEN WKEDG CLEARED WKPND RANDOM SP Stack Pointer Initialized to RAM address 06 Hex B and X Pointers UNAFFECTED after RESET with power already applied RANDOM after RESET at power on S Register CLEARED RAM UNAFFECTED after RESET with power already applied RANDOM after RESET at power on USART PSR ENU ENUR ENUI Cleared except the TBMT bit which is set to one COMPARATORS CMPSL CLEARED WATCHDOG if enabled www national com 5 0 Functional Description Continued The device comes out of reset with both the WATCH DOG logic a
115. t the STPND flag Otherwise all other interrupts will be locked out To the extent possible the interrupt routine should record or indi cate the context of the device so that the cause of the Software Trap can be determined If the user wishes to return to normal execution from the point at which the Software Trap was triggered the user must first execute RPND followed by RETSK rather than RETI or RET This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt The program must skip that instruction in order to proceed with the next one Otherwise an infinite loop of Software Traps and returns will occur Programming a return to normal execution requires careful consideration If the Software Trap routine is interrupted by another Software Trap the RPND instruction in the service routine for the second Software Trap will reset the STPND flag upon return to the first Software Trap routine the STPND flag will have the wrong state This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap To avoid problems such as this the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution Under normal conditions the STPND flag is reset by a RPND instruction in the Software Trap service routine If a programming error or hardware condition brownout power supply glit
116. ted set pending bit should be ac knowledged If at the time an interrupt is enabled any previous occurrences of the interrupt should be ignored the associated pending bit must be reset to zero prior to en abling the interrupt Otherwise the interrupt may be simply enabled if the pending bit is already set it will immediately trigger an interrupt A maskable interrupt is active if its asso ciated enable and pending bits are set An interrupt is an asychronous event which may occur be fore during or after an instruction cycle Any interrupt which occurs during the execution of an instruction is not acknowl edged until the start of the next normally executed instruction is to be skipped the skip is performed before the pending interrupt is acknowledged At the start of interrupt acknowledgment the following ac tions occur 1 The GIE bit is automatically reset to zero preventing any subsequent maskable interrupt from interrupting the cur rent service routine This feature prevents one maskable interrupt from interrupting another one being serviced 2 The address of the instruction about to be executed is pushed onto the stack 3 The program counter PC is loaded with OOFF Hex causing a jump to that program memory location The device requires seven instruction cycles to perform the actions listed above If the user wishes to allow nested interrupts the interrupts service routine may set the GIE bit to 1 by writing
117. tegrate additional features and functionality into the microcontroller program memory space Also the majority instructions executed by the device are single cycle result ing in minimum program execution time In fact 7796 of the instructions are single byte single cycle providing greater code and I O efficiency and faster code execution 1 2 2 Many Single Byte Multifunction Instructions The 8 instruction set utilizes many single byte multi function instructions This enables a single instruction to accomplish multiple functions such as DRSZ DCOR JID LD Load and X Exchange instructions with post incrementing and post decrementing to name just a few examples In many cases the instruction set can simulta neously execute as many as three functions with the same single byte instruction JID Jump Indirect Single byte instruction decodes exter nal events and jumps to corresponding service routines analogous to DO CASE statements in higher level lan guages LAID Load Accumulator Indirect Single byte look up table instruction provides efficient data path from the program memory to the CPU This instruction can be used for table lookup and to read the entire program memory for checksum calculations RETSK Return Skip Single byte instruction allows return from subroutine and skips next instruction Decision to branch can be made in the subroutine itself saving code AUTOINC DEC Auto Increment Au
118. tents Contents Memory Before After Accumulator XX Hex 05 Hex Immediate Short This is a special case of an immediate instruction In the Load B immediate instruction the 4 bit immediate value in the instruction is loaded into the lower nibble of the B register The upper nibble of the B register is reset to 0000 binary Example Load B Register Immediate Short LD B 7 Reg Data Contents Contents Memory Before After B Pointer 12 Hex 07 Hex Indirect from Program Memory This is a special case of an indirect instruction that allows access to data tables stored in program memory In the Load Accumulator Indi rect LAID instruction the upper and lower bytes of the Program Counter PCU and PCL are used temporarily as a pointer to program memory For purposes of accessing pro gram memory the contents of the Accumulator and PCL are exchanged The data pointed to by the Program Counter is loaded into the Accumulator and simultaneously the original contents of PCL are restored so that the program can re sume normal execution Example Load Accumulator Indirect LAID Reg Data Contents Contents Memory Before After PCU 04 Hex 04 Hex PCL 35 Hex 36 Hex Accumulator 1F Hex 25 Hex Memory Location 25 Hex 25 Hex 041F Hex 14 3 2 Tranfer of Control Addressing Modes Program instructions are usually executed in sequential or der However Jump instructions can be used to change the normal execution sequence Several transfer
119. the TBMT bit The interrupt from the receiver is set pending and remains pending as long as both the RBFL and ERI bits are set To remove this interrupt software must either clear the ERI bit or read from the RBUF register thus clearing the RBFL bit 8 7 Baud Clock Generation The clock inputs to the transmitter and receiver sections of the USART can be individually selected to come either from an external source at the CKX pin port L pin L1 or from a source selected in the PSR and BAUD registers Internally the basic baud clock is created from the oscillator frequency through a two stage divider chain consisting of a 1 16 in crements of 0 5 prescaler and an 11 bit binary counter Figure 23 The divide factors are specified through two read write registers shown in Figure 24 Note that the 11 bit Baud Rate Divisor spills over into the Prescaler Select Reg ister PSR PSR is cleared upon reset As shown in Table 5 a Prescaler Factor of 0 corresponds to NO CLOCK This condition is the USART power down mode where the USART clock is turned off for power saving pur pose The user must also turn the USART clock off when a different baud rate is chosen The correspondences between the 5 bit Prescaler Select and Prescaler factors are shown in Table 5 There are many ways to calculate the two divisor factors but one particularly effective method would be to achieve a 1 8432 MHz fre quency coming out of the first stage The 1
120. to Decrement These instructions use the two memory pointers B and X to effi ciently process a block of data analogous to FOR NEXT in higher level languages 1 2 3 Bit Level Control Bit level control over many of the microcontroller s 1 ports provides a flexible means to ease layout concerns and save board space All members of the COP8 family provide the ability to set reset and test any individual bit in the data memory address space including memory mapped ports and associated registers 1 2 4 Register Set Three memory mapped pointers handle register indirect ad dressing and software stack pointer functions The memory data pointers allow the option of post incrementing or post decrementing with the data movement instructions LOAD EXCHANGE And 15 memory maped registers allow de signers to optimize the precise implementation of certain specific instructions 1 3 EMI REDUCTION The COP8SGx5 family of devices incorporates circuitry that guards against electromagnetic interference an increasing problem in today s microcontroller board designs National s patented EMI reduction technology offers low EMI clock circuitry gradual turn on output drivers GTOs and internal smoothing filters to help circumvent many of the EMI issues influencing embedded control designs National has achieved 15 dB 20 dB reduction in EMI transmissions when designs have incorporated its patented EMI reducing cir cuitry 1
121. to a small fixed number of stack levels 1 2 INSTRUCTION SET In today s 8 bit microcontroller application arena cost performance flexibility and time to market are several of the key issues that system designers face in attempting to build well engineered products that compete in the marketplace Many of these issues can be addressed through the manner in which a microcontroller s instruction set handles process ing tasks And that s why COP8 family offers a unique and code efficient instruction set one that provides the flexibil ity functionality reduced costs and faster time to market that today s microcontroller based products require Code efficiency is important because it enables designers to pack more on chip functionality into less program memory space Selecting a microcontroller with less program memory size translates into lower system costs and the added security of knowing that more code can be packed into the available program memory space 1 2 1 Key Instruction Set Features The COP8 family incorporates a unique combination of in struction set features which provide designers with optimum code efficiency and program memory utilization Single Byte Single Cycle Code Execution The efficiency is due to the fact that the majority of instruc tions are of the single byte variety resulting in minimum program space Because compact code does not occupy a substantial amount of program memory space designers can in
122. trol bits TxC3 TxC2 and TxC1 are Timer Underflow Interrupt Pending Flag in Mode below 3 Input Capture Mode TxC3 TxC2 TxC1 Description interrupt A interrupt B Timer Source Source Counts On 1 0 1 PWM TxA Toggle Toggle 0 0 0 External Event Timer Underflow Pos TxB Edge Counter 0 0 1 External Event Timer Underflow Pos TxB Edge Counter 0 1 0 Captures Pos TxA Edge Pos TxB Edge TxA Pos Edge or Timer TxB Pos Edge Underflow 1 1 0 Captures Pos TxA TxA Pos Edge Edge or Timer TxB Neg Edge Underflow 5 0 1 1 Captures Neg TxA TxA Neg Edge Edge or Timer TxB Neg Edge Underflow 1 1 1 Captures Neg TxA TxA Neg Edge Edge or Timer TxB Neg Edge Underflow www national com 24 7 0 Power Saving Features Today the proliferation of battery operated based applica tions has placed new demands on designers to drive power consumption down Battery operated systems are not the only type of applications demanding low power The power budget constraints are also imposed on those consumer industrial applications where well regulated and expensive power supply costs cannot be tolerated Such applications rely on low cost and low power supply voltage derived di rectly from the mains by using voltage rectifier and passive components Low power is demanded even in automotive applications due to increased vehicle electronics content This is required to ease the burden from the car batt
123. truction following the Enter Idle TO are stopped Mode instruction As with the HALT mode the device can be returned to Alternatively the user can enter the IDLE mode with the normal operation with a reset or with a Multi Input Wakeup IDLE Timer TO interrupt disabled In this case the device will from the L Port Alternately the microcontroller resumes resume normal operation with the instruction immediately normal operation from the IDLE mode when the twelfth bit following the Enter IDLE Mode instruction representing 4 096 ms at internal clock frequency of Note It is necessary to program two NOP instructions following both the set 10 MHz tg 1 us of the IDLE Timer toggles HALT mode and set IDLE mode instructions These NOP instructions ns are necessary to allow clock resynchronization following the HALT or This toggle condition of the twelfth bit of the IDLE Timer TO is IDLE modes latched into the TOPND pending flag The user has the option of being interrupted with a transition on the twelfth bit of the IDLE Timer TO The interrupt can be enabled or disabled via the TOEN control bit Setting the TOEN flag enables the interrupt and vice versa IDLE TIMER CONTENTS DEVICE ACTIVE DEVICE IN IDLE MODE DEVICE ACTIVE out of IDLE Mode pee Unaltered 1 1 i 1 1 4 1 T bit 12 SBIT 6 PORTGD Function Idle NOP Registers Timer NOP Timers PORT L RESET
124. tware ENUR USART Receive Control and Status Register Address at OBB DOE FE PE Reserved RBIT9 ATTN XMTG RCVG Note 16 Bit 7 Bit 0 Note 16 Bit is reserved for future use User must set to zero DOE Flags a Data Overrun Error Read only cleared on read cleared on reset DOE 0 Indicates no Data Overrun Error has been de tected since the last time the ENUR register was read DOE 1 Indicates the occurrence of a Data Overrun Error FE Flags a Framing Error Read only cleared on read cleared on reset FE 0 Indicates no Framing Error has been detected since the last time the ENUR register was read 1 Indicates the occurrence of a Framing Error PE Flags a Parity Error Read only cleared on read cleared on reset PE 0 Indicates no Parity Error has been detected since the last time the ENUR register was read PE 1 Indicates the occurrence of a Parity Error SPARE Reserved for future use Read Write cleared on reset RBIT9 Contains the ninth data bit received when the US ART is operating with nine data bits per frame Read only cleared on reset ATTN ATTENTION Mode is enabled while this bit is set This bit is cleared automatically on receiving a character with data bit nine set Read Write cleared on reset XMTG This bit is set to indicate that the USART is transmit ting It gets reset at the end of the last frame end of last Stop bit Read only
125. upts Underflows from the timer are alternately latched into two pending flags TXPNDA and TxPNDB The user must reset these pending flags under software control Two control enable flags TXENA and TxENB allow the interrupts from the timer underflow to be enabled or disabled Setting the timer enable flag TXENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer Resetting the timer enable flags will disable the associated interrupts Either or both of the timer underflow interrupts may be enabled This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output Alternatively the user may choose to inter rupt on both edges of the PWM output 6 2 2 Mode 2 External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above The main difference is that the timer Tx is clocked by the input signal from the TxA pin The Tx timer control bits TxC3 TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin Underflows from the timer are latched into the TxPNDA pending flag Setting the TxENA control flag will cause an interrupt when the timer underflows www national com 22 6 0 Timers Continued

National Semiconductor COP8SG Family 8-Bit CMOS ROM Based OTP Microcontrollers with 8k to 32k Memory Two Comparators USART handbook(1)

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