Alliance Semiconductor AS7C252MFT18A 2.5V 2M × 18 Flow-through synchronous SRAM
Contents
1. CE0 CE2 ADSP ADSC ADV WRITE Address accessed CLK Operation DQ H X X X L X X X NA LtoH Deselect Hi Z L L X L X X X X NA LtoH Deselect Hi Z L L X H L X X X NA LtoH Deselect Hi Z L X H L X X X X NA LtoH Deselect Hi Z L X H H L X X X NA LtoH Deselect Hi Z L H L L X X X L External LtoH Begin read Q L H L L X X X H External LtoH Begin read Hi Z L H L H L X H L External LtoH Begin read Q L H L H L X H H External LtoH Begin read Hi Z X X X H H L H L Next LtoH Continue read Q X X X H H L H H Next LtoH Continue read Hi Z X X X H H H H L Current LtoH Suspend read Q X X X H H H H H Current LtoH Suspend read Hi Z H X X X H L H L Next LtoH Continue read Q H X X X H L H H Next LtoH Continue read Hi Z H X X X H H H L Current LtoH Suspend read Q H X X X H H H H Current LtoH Suspend read Hi Z L H L H L X L X External LtoH Begin write D X X X H H L L X Next LtoH Continue write D H X X X H L L X Next LtoH Continue write D X X X H H H L X Current LtoH Suspend write D H X X X H H L X Current LtoH Suspend write D 1 don t L low H high 2 For WRITE L means any one or more byte write enable signals BWa or BWb and BWE are LOW or GWE is LOW WRITE HIGH for all BWx BWE GWE HIGH See Write enable truth table per byte on page 6 for more information 3 For write operation following a READ OE must be high be 4 ZZ pin is always Low 1 17 05 v 1 2 Alliance Semiconductor f2. zEigAS C252M FT18A f S January 2005 AS7C252MFT18A A 2 5V 2M x 18 Flow through synchronous SRAM Features Organization 2 097152 words x 18 bits Fast clock to data access 7 5 8 5 10 ns Fast OE access time 3 5 4 0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100 pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 2 5V core power supply Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs Logic block diagram LBO E CLK ADSC cs Burst logic ADSP CLR 4 20 0 21 Q CLK D 2 Byte Write registers BWE 7 CLK D DQa Q Byte Write D registers CLK Ce Ese 9 4 Kc Enable register LJ CE 8 _ CLK CLK EE E U Input registers zz 4 Power dela lown regisfer CLK Selection guide 75 85 10 Units Minimum cycle time 8 5 10 12 Maximum clock access time 7 5 8 5 10 Maximum operating current 325 300 275 Maximum standby current 130 130 130 ABEDE Maximum CMOS standby current DC 90 90 90 1 17 05 v 1 2 Alliance Sem
3. Write D A 2Y01 2p a SEA tase a Suspend Read Suspend Write Q A2 Write D A1 D A2 Read Q A1 ADD when LBO low XOR when LBO high no connect Y Note Y AS7C252MFT18A te cycle ADSP Controlled ADSC High wri form of read iming wave T C 2 Address BWE BW a b CEI ADV Suspend Burst Read Q A 3Y11 Read ADV Burst Read 0 3 10 11 Read Suspend Read ADV Q A2 Write Q A3 Burst D A2 Read Q A 3YO1 Suspend Read Q A1 Read Q A1 high no connect Y low ADD when LBO XOR when LBO Note Y AS7C252MFT18A A Timing waveform of read write cycle ADSC controlled ADSP HIGH 9 5 tcyc tcu gt tcr tapscs tas ta ADDRESS 9 29 9 AS A6 AT B9 19 BWE BWL a b CEO CE2 CEI l l l Dout l 1 l l l 1 l 1 l 1 tDH l 1 1 l 1 Din peas READ READ READ READ WRITE WRITE WRITE WRITE READ READ QAD QAJ Q A3 Q A4 D AS
4. 0 5 0 5 ns 6 1 See Notes on page 16 Snooze Mode Electrical Characteristics Description Conditions Symbol Min Max Units Current during Snooze Mode ZZ gt Vin Ispo 80 mA ZZ active to input ignored tpps 2 cycle ZZ inactive to input sampled tpus 2 cycle ZZ active to SNOOZE current 1771 2 cycle ZZ inactive to exit SNOOZE current tRZZI 0 1 17 05 v 1 2 Alliance Semiconductor 10 of 19 AS7C252MFT18A Fs Key to switching waveforms Rising input N Falling input don t care ERES Undefined Timing waveform of read cycle gt teyc TU tcr CLK PPP PROPPED tADSPS hos ADSP wwwwwwwwwweAa T t AD wwwuawwuamw LOAD NEW ADDRESS Address GWE BWE wwwwwwwwwww CEI ADV OE V y Y avvio i gt 7 Read Suspend Read Burst Burst Suspend Burst Read Burst Burst Burst i Q A1 Read Q A2 Read Read Read Read Q A3 Read Read Read DSEL Q A1 Q A2Y01 Q A2Y10 Q A2Y10 Q A2Y11 Q A3Y01 Q A3Y10 Q A3Y11 Note Y XOR when LBO high no connect Y ADD when LBO low BW a d is don t care AS7C252MFT18A Timing waveform of write cycle lt gt tcr ADSC LOADS NEW AD Din gt 25 a SES tase a Burst Write D A 3Y01 22 25 c 3 oS lt 2 4 gt 25 tase a Suspend
5. Figure A Input waveform Figure B Output load A Figure C Output load B Notes 1 For test conditions see AC test conditions Figures A B and C 2 This parameter is measured with output load condition in Figure C 3 This parameter is sampled but not 100 tested 4 tgzog 15 less than tj zog and is less than tj at any given temperature and voltage 5 is measured as high if above VIH and is measured as low if below VIL 6 This is a synchronous device All addresses must meet the specified setup and hold times for all rising edges of CLK All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled 7 Write refers to GWE BWE and BW a b 8 Chip select refers to CE1 and CE2 1 17 05 v 1 2 Alliance Semiconductor 16 of 19 AS7C252MFT18A Package dimensions 100 pin quad flat pack TQFP TQFP Ha Min Max D Al 0 05 0 15 T EET b 0 22 0 38 s b c 0 09 0 20 H D 13 90 14 10 E E 1990 2010 E ES E e 0 65 nominal Exc EE Hd 15 85 16 15 H He 21 80 22 20 He E Es n 0 45 0 75 H L1 1 00 nominal a 0 7 E Dimensions in millimeters 0 1 17 05 v 1 2 Alliance Semiconductor 17 of 19 AS7C252MFT18A Ordering information Package amp Width 75 85 10 TOFP x 18 AS7C252MFT18A 75TQC AS7C252MFT18A 85TQC AS7C252MFT18A 10TQC
6. Vm Vpp Max 0 lt Vour lt Vppo 2 2 Address and control pins 1 7 0 3 Input high logic 1 voltage Vig I O pins 1 7 Vppg 0 3 V Address and control pins 0 3 0 7 Input low logic 0 voltage Vit I O pins 0 3 0 7 Output high voltage Vou 4 mA 2 375V 1 7 Output low voltage Vor 8 mA Vppo 2 625V 0 7 V and ZZ pins have an internal pull up or pull down and input leakage 10 uA Vig lt VDD 1 5V for pulse width less than 0 2 X Vi min 1 5 for pulse width less than 0 2 X Ipp operating conditions and maximum limits Parameter Sym Conditions 75 85 10 Unit lt CEI gt Vip CE2 f fy Operating power supply current Icc 4 a E 325 300 275 mA All lt 0 2V or gt Vpp 0 2V Deselected Isg 130 130 130 f fMax ZZ lt Vir Deselected f 0 ZZ 0 2V Standby power supply current gt gt gt mA T all V lt 0 2 or Vpp 0 2V 20 20 gt ios Deselected f fax ZZ gt Vpp 0 2V 80 80 80 all VIN lt Vit or Vin 1 Icc given with no output loading increases with faster cycle times and greater output loading 1 17 05 v 1 2 Alliance Semiconductor 9 of 19 AS7C252MFT18A Timing characteristics over operating ran
7. X AS7C252MFTI8A 75TQI AS7C252MFT18A 85TQI AS7C252MFT18A 10TQI Note Add suffix N to the above part number for Lead Free Parts Ex AS7C252MFT18A 85TQCN Part numbering guide AS7C 25 2M FT 18 A XX TQ C I X 1 2 3 4 5 6 7 8 9 10 1 Alliance Semiconductor SRAM prefix 2 Operating voltage 25 2 5V 3 Organization 2M 2M 4 Flow through mode 5 Organization 18 x 18 6 Production version A first production version 7 Clock access time 75 7 5 ns 85 8 5 ns 10 10 0 ns 8 Package type TQ TQFP 9 Operating temperature C commercial 0 C to 70 C I industrial 40 C to 85 C 10 N Lead free part 1 17 05 v 1 2 Alliance Semiconductor 18 of 19 AS7C252MFT18A FS Alliance Semiconductor Corporation Copyright Alliance Semiconductor 2575 Augustine Drive All Rights Reserved Santa Clara CA 95054 Part Number AS7C252MFT18A Tel 408 855 4900 Document Version v 1 2 Fax 408 855 4999 www alsc com Copyright 2003 Alliance Semiconductor Corporation All rights reserved Our three point logo our name and Intelliwatt are trademarks or registered trademarks of Alliance All other brand and product names may be the trademarks of their respective companies Alliance reserves the right to make changes to this document and its products at any time without notice Alliance assumes no responsibility for any errors that may appear in this do
8. 252MFT18A Functional description The AS7C252MFTI18A is a high performance CMOS 32 Mbit synchronous Static Random Access Memory SRAM device organized as 2 097152 words 18 bits Fast cycle times of 8 5 10 12 ns with clock access times tcp of 7 5 8 5 10 ns Three chip enable CE inputs permit easy memory expansion Burst operation is initiated in one of two ways the controller address strobe ADSC or the processor address strobe ADSP The burst advance pin ADV allows subsequent internally generated burst addresses Read cycles are initiated with ADSP regardless of WE and ADSC using the new external address clocked into the on chip address register when ADSP is sampled low the chip enables are sampled active and the output buffer is enabled with OE In a read operation the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data out buffer ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock edges Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high Burst mode is selectable with the LBO input With LBO unconnected or driven high burst operations use an interleaved count sequence With LBO driven low the device uses a linear count sequence Write cycles are performed by disabling the output buffers with OE and asserting a
9. 5 of 19 AS7C252MFT18A Write enable truth table per byte Function GWE BWE BWa BWb L X X X Write All Bytes H L L L Write Byte a H L L H Write Byte b H L H L H H X X Read H L H H Key X don t L low high n a b BWE BWn internal write signal Asynchronous Truth Table Operation ZL OE T O Status Snooze mode H X High Z L L Dout Read L H High Z Write L X Din High Z Deselected L X High Z Notes 1 X means Don t Care 2 ZZ pin is pulled down internally 3 For write cycles that follows read cycles the output buffers must be disabled with OE otherwise data bus contention will occur 4 Snooze mode means power down state of which stand by current does not depend on cycle times 5 Deselected means power down state of which stand by current depends on cycle times Burst sequence table Interleaved burst address LBO 1 Linear burst address LBO 0 A1 A0 A1 AO AL AO Al AO A1A0 A1 A0 Al AO AL AO 1 Address 00 01 10 11 1 Address 00 01 10 11 214 Address 01 00 11 10 214 Address 01 10 11 00 37 Address 10 11 00 01 34 Address 10 11 00 01 4 Address 11 10 01 00 4 Address 11 10 01 10 1 17 05 v 1 2 Alliance Semiconductor 6 of 19 Synchronous truth AS7C252MFT18A
10. D A6 D A7 D A8 Q A9 9 10 Note ADV is don t care here AS7C252MFT18A A Timing waveform of power down cycle gt gt tcr tADSPS m Y ww ADSC wy wy W ADDRESS A2 1 EE twsioetwu CENE Y BW a b CEO CE2 SE qucm e ADV 1 1 1 Din tHzOE 1 Dout t 4 FUS da QAXY0D ZZ Recovbry Cycle Normal Operation Mbde 1 ZZ ZZ Setup Cycle l 1771 1 RZZI supply 1562 1 gt l Sleep State READ READ READ READ Q AI IQ A1YODI 2 1Q A2Y01 AS7C252MFT18A AC test conditions Output load For tj zc zog tuzor 7 see Figure C For all others see Figure B Input pulse level GND to 2 5V Fi A S POSEE Thevenin equivalent Input rise and fall time measured at 0 25V and 2 25V 2 ns See Figure A Input and output timing reference levels 1 25V 2 5V Zo 502 500 Dou 3190 16670 Y 90 Pov 3530 15380 SpE 10 10 1 30 pF GND including sco e and jig capacitance GND
11. ce Semiconductor 2 of 19 AS7C252MFT18A Pin assignment 100 pin TQFP top view ii Ola 8 8 exe BB io O zimimio gt gt oioimiola i i lt lt OO XO LO CO CN OO O LO sr CO CN CO CO OO cO A cO cO 41 80 NC 2 79 3 78 NC Vppa 44 77 Vppa Vssq 5 76 Vssa 46 75 7 74 DQPa DQbO 8 73 7 DQb1 9 72 DQa6 Vssq 10 71 Vgsq DDQ 11 70 LL Vppa DQb2 12 69 5 DQb3 13 68 DQa4 NC 14 67 E3 Vss DD 15 66 NC NC 16 14 x 20mm 65 5 Vss 17 64 77 DQb4 18 63 DQa3 DQb5 19 62 DQa2 0 61 06 ssa 21 60 ssa DQb6 22 59 DQa1 DQb7 23 58 DQaO DQPb 24 57 25 56 Vssq c4 26 55 25 Vbpo 27 54 VDDQ NC 28 53 NC NC 29 52 NC NC 30 515 NC AEN EE 1 1 1 1 n ee l 1 17 05 v 1 2 Alliance Semiconductor 3 of 19 AS7C
12. cument The data contained herein represents Alliance s best data and or estimates at the time of issuance Alliance reserves the right to change or correct this data at any time without notice If the product described herein is under development significant changes to these specifications are possible The information in this product data sheet is intended to be general descriptive information for potential customers and users and is not intended to operate as or provide any guarantee or warrantee to any user or customer Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein and disclaims any express or implied warranties related to the sale and or use of Alliance products including liability or warranties related to fitness for a particular purpose merchantability or infringement of any intellectual property rights except as express agreed to in Alliance s Terms and Conditions of Sale which are available from Alliance All sales of Alliance products are made exclusively according to Alliance s Terms and Conditions of Sale The purchase of products from Alliance does not convey a license under any patent rights copyrights mask works rights trademarks or any other intellectual property rights of Alliance or third parties Alliance does not authorize its products for use as critical components in life supporting systems where a malfunction or failure may reasonably be expected to
13. ethods and 4 layer Ora 2 C W procedures for measuring thermal impedance Thermal resistance per EIA JESDS1 5 junction to top of case 3 CW 1 This parameter is sampled 1 17 05 v 1 2 Alliance Semiconductor 4 of 19 Signal descriptions AS7C252MFT18A Pin T O Properties Description CLK I CLOCK Clock All inputs except OE ZZ and LBO are synchronous to this clock A A0 A1 I SYNC Address Sampled when all chip enables are active and when ADSC or ADSP are asserted DQ a b IO SYNC Data Driven as output when the chip is enabled and when OE is active CEO I SYNC Master chip enable Sampled on clock edges when ADSP or ADSC is active When is inactive ADSP is blocked Refer to the Synchronous truth table for more information CE1 CE2 I SYNC ind a respectively Sampled on clock edges when ADSP I SYNC Address strobe processor Asserted low to load a new address or to enter standby mode ADSC I SYNC Address strobe controller Asserted low to load a new address or to enter standby mode ADV I SYNC Advance Asserted low to continue burst read write GWE I SYNC ein write enable Asserted low to write all 18 bits When high BWE and BW a b control write BWE I SYNC Byte write enable Asserted low with GWE high to enable effect of BW a b inputs Write enables Used to control write of individual bytes when GWE is high and BWE
14. ge 75 85 10 Parameter Sym Min Max Min Max Min Max Unit Notes Cycle time tcyc 8 5 10 12 ns Clock access time tcp 7 5 8 5 10 ns Output enable low to data valid tog 3 5 4 0 4 0 ns Clock high to output low Z tt zc 2 5 2 5 2 5 ns 2 3 4 Data output invalid from clock high tog 2 5 2 9 2 5 ns 2 Output enable low to output low Z tLZOE 0 0 0 ns 2 3 4 Output enable high to output high Z tHzOE 3 5 4 0 4 0 ns 2 3 4 Clock high to output high Z tuzc 4 0 5 0 5 0 ns 2 3 4 Output enable high to invalid output toHOE 0 0 z 0 ns Clock high pulse width tcu 2 5 3 0 3 0 ns 5 Clock low pulse width tcr 2 5 3 0 3 0 ns 5 Address setup to clock high tas 2 0 2 0 2 0 ns 6 Data setup to clock high tps 2 0 2 0 2 0 ns 6 Write setup to clock high tws 2 0 2 0 2 0 ns 6 7 Chip select setup to clock high tess 2 0 2 0 2 0 ns 6 8 Address hold from clock high tAH 0 5 0 5 0 5 ns 6 Data hold from clock high tou 0 5 0 5 0 5 ns 6 Write hold from clock high twH 0 5 0 5 0 5 ns 6 7 Chip select hold from clock high tcsH 0 5 0 5 0 5 ns 6 8 ADV setup to clock high tADVS 2 0 2 0 2 0 ns 6 ADSP setup to clock high tapsps 2 0 2 0 2 0 ns 6 ADSC setup to clock high tapscs 2 0 2 0 2 0 ns 6 ADV hold from clock high tADVH 0 5 0 5 0 5 ns 6 ADSP hold from clock high tapseH 5 0 5 0 5 ns 6 ADSC hold from clock high tapscH 0 5
15. iconductor 1 of 19 Copyright Alliance Semiconductor All rights reserved 2 5V 32 Mb Synchronous SRAM products list AS7C252MFT18A Org Part Number Mode Speed 2MX18 AS7C252MPFS18A PL SCD 200 166 133 MHz 1MX32 AS7C251MPFS32A PL SCD 200 166 133 MHz 1IMX36 AS7C251MPFS36A PL SCD 200 166 133 MHz 2MX18 AS7C252MPFD18A PL DCD 200 166 133 MHz 1MX32 AS7C251MPFD32A PL DCD 200 166 133 MHz 1MX36 AS7C251MPFD36A PL DCD 200 166 133 MHz 2MX18 AS7C252MFT18A FT 7 5 8 5 10 ns 1IMX32 AS7C251MFT32A FT 7 5 8 5 10 ns 1MX36 AS7C251MFT36A FT 7 5 8 5 10 ns 2MX18 AS7C252MNTD18A NTD PL 200 166 133 MHz 1MX32 AS7C251MNTD32A NTD PL 200 166 133 MHz 1MX36 AS7C251MNTD36A NTD PL 200 166 133 MHz 2MX18 AS7C252MNTF18A NTD FT 7 5 8 5 10 ns 1MX32 AS7C251MNTF32A NTD FT 7 5 8 5 10 ns 1MX36 AS7C251MNTF36A NTD FT 7 5 8 5 10 ns 1 Core Power Supply VDD 2 5V 0 125 2 Supply Voltage VDDQ 2 5V 0 125V PL SCD Pipelined Burst Synchronous SRAM Single Cycle Deselect PL DCD Pipelined Burst Synchronous SRAM Double Cycle Deselect FT Flow through Burst Synchronous SRAM NTDLPL Pipelined Burst Synchronous SRAM with NTD M NTD FT Flow through Burst Synchronous SRAM with NTD INTD No Turnaround Delay NTD is a trademark of Alliance Semiconductor Corporation All trademarks mentioned in this document are the property of their respective owners 1 17 05 v 1 2 Allian
16. is low If any of BW a b I SYNC BW a b is active with GWE high and BWE low the cycle is a write cycle If all BW a b are inactive the cycle is a read cycle OE I ASYNC Asynchronous output enable I O pins are driven when OE is active and chip is in read mode LBO I STATIC Selects Burst mode When tied to Vpp or left floating device follows interleaved Burst order When driven Low device follows linear Burst order This signal is internally pulled High 77 I ASYNC Snooze Places device in low power mode data is retained Connect to GND if unused NC No connect Snooze Mode SNOOZE MODE is a low current power down mode in which the device is deselected and current is reduced to The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state The ZZ pin is an asynchronous active high input that causes the device to enter SNOOZE MODE When the ZZ pin becomes a logic High Igp is guaranteed after the time t77 is met After entering SNOOZE MODE all inputs except ZZ is disabled and all outputs go to High Z Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete Therefore SNOOZE MODE READ or WRITE must not be initiated until valid pending operations are completed Similarly when exiting SNOOZE MODE during only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE 1 17 05 v 1 2 Alliance Semiconductor
17. ore the input data set up time and held high throughout the input hold time 7 of 19 AS7C252MFT18A Absolute maximum ratings Parameter Symbol Min Max Unit Power supply voltage relative to GND VDDQ 0 3 3 6 Input voltage relative to GND input pins VIN 0 3 Vpp 0 3 Input voltage relative to GND I O pins VIN 0 3 Vppo 0 3 Power dissipation Pa 1 8 W Short circuit output current lour 20 mA Storage temperature 65 150 C Temperature under bias Tbias 65 135 C Stresses greater than those listed under Absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied Exposure to abso lute maximum rating conditions may affect reliability Recommended operating conditions Parameter Symbol Min Nominal Max Unit Supply voltage for inputs 2 375 2 5 2 625 V Supply voltage for I O Vppo 2 375 25 2 625 V Ground supply Vss 0 0 0 V 1 17 05 v 1 2 Alliance Semiconductor 8 of 19 AS7C252MFT18A DC electrical characteristics Parameter Sym Conditions Min Max Unit Input leakage current Hl Vpp 0V lt Vin 2 uA Output leakage current 2
18. result in significant injury to the user and the inclusion of Alliance products in such life supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use
19. write command A global write enable GWE writes all 18 bits regardless of the state of individual BW a b inputs Alternately when GWE is high one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals BWn is ignored on the clock edge that samples ADSP low but it is sampled on all subsequent clock edges Output buffers are disabled when BWn is sampled LOW regardless of OE Data is clocked into the data input register when BWn is sampled low Address is incremented internally to the next burst address if BWn and ADV are sampled low Read or write cycles may also be initiated with ADSC instead of ADSP The differences between cycles initiated with ADSC and ADSP are as follows ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC e WE signals are sampled on the clock edge that samples ADSC low and ADSP high Master chip enable CEO blocks ADSP but not ADSC The AS7C252MFT18A family operates from a core 2 5V power supply These devices are available in 100 pin TQFP package TQFP capacitance Parameter Symbol Test conditions Min Max Unit Input capacitance Vin OV 3 pF I O capacitance Cro Vout 0V 1 pF Guaranteed not tested TQFP thermal resistance Description Conditions Symbol Typical Units Thermal resistance 2 1 layer 0 40 C W junction to ambient Test conditions follow standard test m
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