Home

AMD Am79C874 NetPHY -1LP Low Power 10/100-TX/FX Ethernet Transceiver service manual

1. 100 Mbps MII Receive Timing Symbol Parameter Description Min Max Unit MRJCRH100 CRS HIGH After First Bit of J 200 ns tMRJCOH100 COL HIGH After First Bit of J 80 150 ns tMRTCRL100 First Bit of T to CRS LOW 130 240 ns MRTCOL100 First Bit of T to COL LOW 130 240 ns tMRERL100 First Bit of T to RXD 3 0 DV De Asserting Going LOW 120 140 ns tMRJRA100 First Bit of J to RXD 3 0 DV and EN Active TBD TBD ns t RXD 3 0 DV RX ER valid prior to the Rising Edge of 10 MRRDC100 RX CLK twRCRD100 RXD 3 0 RX_DV RX ER valid after the Rising Edge of 10 ns X IJ K tMRJCRH100 e CRS tMRJCOH100 lt gt IMRJRA100 COL y RX_CLK tMRRDC100 tMRCRD100 RXD 3 0 COK RX_ER 222351 22 50 Figure 20 100 Mbps Receive Start of Packet Timing Am79C874 PRELIMINARY 100 Mbps Receive Timing Continued X T R tMRTCRL100 CRS tMRTCOL100 lt COL IMRERL100 RXD 3 0 RX DV X X 7 222351 23 Figure 21 100 Mbps MII Receive End of Packet Timing Am79C874 51 10 Mbps MII Transmit Timing PRELIMINAR Y Symbol Parameter Description Min Max Unit turs10 TX EN TXD10 3 0 Setup Time to TX CLK Rising Edge 12 ns
2. 4 Standard Products ba see DAP REN a t ad 4 RELATED AMD PRODUCTS 5 PIN DESIGNATIONS 321 3 xxr aw SESE xiu dues 9 PIN DESCRIPTIONS mm eee sexe mure mx EI 10 Media Connections uh ihe edie IIO RR EN DR We P AD 10 MII 7 Wire GPSI 10 Miscellaneous FUNCTIONS Hee ke nha Nel seve dc 11 BED 53 2 erat cesses an de oa ed 13 BIAS us esa sonent dee eodd qwe vi LAT Goal Dena Malad PUR anh RES 14 Power arid Grounds ica pe iie tette nam darte Moenia Me dA 14 FUNCTIONAL DESCRIPTION15 Mod s of Operations bk Pet ae tae be a 15 MIT MOGs u Su as ette ato ae ad iat apd aed tame ce oed s 15 7 Wire GPS Mod intei eee ed meae asun due ded ERR EUREN b RUE DR Ra 16 5B Symbol 2 4 16 TOOBASE X Cau La o eae es Peto aoe eae Ns Diu Sae erus 16 Transmib PIOCeSS ss deae Dole d eden CREE e da ded 17 Receive 88 xu a UR t USE b RE AERE ROO
3. 4 46 Figure 15 MLT 8 Test 1 46 Figure 16 Management Bus Transmit Timing 47 Figure 17 Management Bus Receive 0 47 Figure 18 100 Mbps MII Transmit Start of Packet Timing 48 Figure 19 100 Mbps Transmit End of Packet 0 49 Figure 20 100 Mbps MII Receive Start of Packet 0 50 Figure 21 100 Mbps MII Receive End of Packet Timing 51 Figure 22 10 Mbps MII Transmit Start of Packet Timing 52 Figure 23 10 Mbps MII Transmit End of Packet 0 53 Figure 24 10 Mbps MII Receive Start of Packet 0 54 Figure 25 10 Mbps MII Receive End of Packet Timing 55 Figure 26 GPSI Receive Timing Start of Reception 56 Figure 27 GPSI Receive Timing End of Reception Last Bit 0 56 Figure 28 GPSI Receive Timing End of Reception Last Bit 1 57 Figure 29 GPSI Collision 0 57 Figure 30 GPSI Transmit Timing Start of Transmission 58 F
4. Read Reg Bit Name Description Write Default 19 14 7 Reserved RW 00 Transmit transformer ratio selection 121 251 19 6 TP125 0 11 RW 0 The default value of this bit is controlled by reset read value of pin 20 1 Enable advanced power saving mode 0 Disable advanced power saving mode 19 5 LowPowerMode Note Under normal operating conditions this mode should never RW 1 be disabled Power dissipation will exceed data sheet values as circuitry for both 10 Mbps and 100 Mbps will be turned on 1 Enable test loopback Data will be transmitted from MII 19 4 Test Loopback interface to clock recovery and loopback to MII received data 9 1 Enable loopback 19 3 Digital loopback RW 0 0 Normal operation 1 Enable link pulse loopback 19 2 LP LPBK RW 0 0 Normal operation 1 In Auto Negotiation test mode send instead of FLP 19 1 Link Integrity order to test NLP receive integrity RW 0 es 0 Sending FLP in Auto Negotiation test mode 1 Reduce time constant for Auto Negotiation timer 19 0 Reduce Timer b RW 0 0 Normal operation 38 Am79C874 PRELIMINAR Y Mode Control Register Register 21 Table 23 Mode Control Register Register 21 Read Reg Bit Description Write Default 21 15 Reserved RO 0 1 Force link up without checking NLP Forced du
5. PRE ST OP PHYAD REGADD TA DATA IDLE READ 1 1 01 10 00000 RRRRR 20 2 WRITE 1 1 01 01 00000 RRRRR 10 XXXXXXXXXPPAAAAA 2 s U UU LLL tt PHY al z 10 1 1 0 1 0 1 1 0 0 0 0 0 1 01111 10 10 1 0 0 10 0 0 1 Jz Ide Start Opcode PHY Address Register Address TA Register Data Idle Read 16h Port 2 MII Status 1h Read Operation ile Start Opcode PHY Address Register Address TA Register Data Write 16h Port 2 Control Oh Write Operation 222351 9 Figure 7 PHY Management Read Write Operations 28 Am79C874 PRELIMINAR Y Bad Management Frame Handling The management block of the device can recognize management frames without preambles preamble suppression However if it receives a bad manage ment frame it will go into a Bad Management Frame state It will stay in this state and will not respond to any management frame without preambles until a frame with a full 32 bit preamble is received then it will return to normal operation A bad management frame is a frame that does not comply with the IEEE standard specification It can be one with less than 32 bit preamble with illegal OP field etc However a frame with more than 32 preamble bits is considered to be a good frame After a reset the NetPHY 1LP device requires a mini mum preamble of 32 bits before management data MDIO can be received Afte
6. 31 PHY Identifier 1 Register Register 2 31 PHY Identifier 2 Register Register 3 32 Auto Negotiation Advertisement Register Register 4 32 Auto Negotiation Link Partner Ability Register in Base Page Format Register 5 33 Auto Negotiation Link Partner Ability Register in Next Page Format Register 5 33 Auto Negotiation Expansion Register Register 6 34 Auto Negotiation Next Page Advertisement Register Register 7 35 Reserved Registers Registers 8 15 20 22 25 31 35 Miscellaneous Features Register Register 16 36 Interrupt Control Status Register Register 17 37 Diagnostic Register Register 18 37 Power Loopback Register Register 19 38 Mode Control Register Register 21 39 Disconnect Counter Register Register 23 40 Receive Error Counter Register Register 24 40 ABSOLUTE MAXIMUM RATINGS 41 OPERATING RANGES 5 uuu ctu xe Oe see ee thee NIE eis 41 Gommierclal G
7. TX EN TXD10 3 0 Hold time From TX Rising Edge 0 ns tMTEP10 Transmit Latency TX EN Sampled by TX CLK to Start of Packet 240 360 ns lMTECRH10 CRS Assert from TX EN Sampled HIGH 130 ns tMTECOH10 COL Assert from TX EN Sampled HIGH 300 ns tMTDCRL10 CRS De assert From TX EN Sampled LOW 130 ns tMTDCOL10 COL De assert From TX EN Sampled LOW 130 ns MTIDLE10 Required De assertion Time Between Packets 300 ns tMTP10 TX CLK Period 399 98 400 02 ns 10 TX HIGH 180 220 ns tMTWL10 TX CLK LOW 180 220 ns HK tMTWH10 lt gt gt tMTWL10 TX CLK tMTS10 TX_EN 100 TXD 3 0 CRS tMTECLH10 COL I amp TX 222351 24 Figure 22 10 Mbps MII Transmit Start of Packet Timing 52 Am79C874 PRELIMINARY TX CLK lt MTIDLE10 gt TX_EN 2 lt lwpcRH0 CRS N lt tutpcoL10 COL 220351 25 Figure 23 10 Mbps Transmit End of Packet Timing Am79C874 53 PRELIMINARY 10 Mbps MII Receive Timing Symbol Parameter Description Min Max Unit tMRPCRHI10 CRS HIGH After Start of Packet 80 150 ns tMRPCOH10 COL HIGH After Start of Packet 80 150 ns iMRCHR10 RXD 3 0 RX DV ER Valid after CRS HIGH 100 100 ns 1 10 RXD 3 0 RX DV ER Valid Prior to th
8. Description Controllers Am79C90 CMOS Local Area Network Controller for Ethernet C LANCE Integrated Controllers Am79C940 Media Access Controller for Ethernet MACETV Am79C961A PCnet ISA II Full Duplex Single Chip Ethernet Controller for ISA Bus Am79C965A PCnet 32 Single Chip 32 Bit Ethernet Controller for 486 and VL Buses Am79C970A Full Duplex Single Chip Ethernet Controller for PCI Local Bus ACE PCnet V FAST III Single Chip 10 100 Mbps PCI Ethernet Controller with Integrated PHY Am79C976 10 100 Mbps PCI Ethernet PCI Controller Am79C978 PCnet Home Single Chip 1 10 Mbps PCI Home Networking Controller Physical Layer Devices Single Port Am79C901 HomePHY Single Chip 1 10 Mbps Home Networking PHY Physical Layer Devices Multi Port Am79C875 NetPHYTM 4LP Low Power Quad10 100 TX FX Ethernet Transceiver Integrated Repeater Hub Devices Am79C984A Enhanced Integrated Multiport Repeater Am79C985 Enhanced Integrated Multiport Repeater Plus eIMR Am79C874 PRELIMINARY TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS 1 GENERAL DESCRIPTION 5I lel bl ye ER 1 BLOCK DIAGRAM niea a l ee 2 CONNECTION 3 ORDERING
9. Symbol Parameter Description Min Max Unit tMTS100 TX ER TX EN TXD 3 0 Setup Time to Rising Edge 12 ns TX ER TX TXD 3 0 Hold time From Rising Edge 0 ns lMTEJ100 Transmit Latency TX EN Sampled by TX CLK to First Bit of J 60 140 ns tMTECRH100 CRS Assert From TX EN Sampled HIGH 40 ns COL Assert From TX Sampled HIGH 200 ns tMTDCRL100 CRS De assert From TX EN Sampled LOW 2 160 ns COL De assert From TX EN Sampled LOW 13 240 ns tMTIDLE100 Required De assertion Time Between Packets 120 ns tMTP100 TX CLK Period 39 998 40 002 ns TX HIGH 18 22 ns MTWL1 00 TX_CLK LOW 18 22 ns lt 100 gt lt lt gt lMTWL100 TX CLK lurst00 lurECRH10077 CRS MTECOH100 COL tuts100 gt MTH100 TX ER X TXD 3 0 lt 7 J 222351 20 Figure 18 100 Mbps MII Transmit Start of Packet Timing 48 Am79C874 PRELIMINAR Y 100 Mbps MII Transmit Timing Continued TX CLK TX EN CRS COL TX MTIDLE100 lt wrbcRL100 lt wrpcoLt00 gt x Figure 19 100 Mbps Transmit End of Packet Timing Am79C874 222351 21 49 PRELIMINAR Y
10. DETAIL X Dwg 8 99 PACKAGE 8 JEDEC 136 B AM SYMBOL MIN NOM MAX NOTES A 120 1 ALL DIMENSIONS AND TOLERANCES CONFORM ANSI 14 5 1982 Al 2 DATUM PLANE IS LOCATED AT THE MOLD PARTING LINE AND IS 005 015 COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD m 095 100 105 EXITS THE PLASTIC BODY 3 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION D 1400 BSC ALLOWABLE PROTRUSION IS 0 254mm PER SIDE DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE Di 12 00 BSC DETERMINED AT DATUM PLANE H 4 DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION E 1400 BSC ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION El 12 00 BSC DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT L 045 060 075 5 CONTROLLING DIMENSIONS MILLIMETER x 6 DIMENSIONS D AND E ARE MEASURED FROM BOTH PQT80 80 NNERMOST AND OUTERMOST POINTS 7 DEVIATION FROM LEAD TIP TRUE POSITION SHALL BE WITHIN 050 BASIC 10 04 FOR PITCH 20 5 mm B 017 022 027 8 LEAD CORLANARITY SHALL BE WITHIN REFER TO 06 500 mm FOR DEVICES WITH LEAD PITCH OF 0 50 mm bl 016 020 0 23 COPLANARITY IS MEASURED PER SPECIFICATION 06 500 9 HALF SPAN CENTER OF PACKAGE TO LEAD TIP SHALL BE ccc m 008 15 305 165 mm 10 N IS THE TOTAL NUMBER OF TERMINALS 0 08 11 THE TOP OF PACKAGE IS SMALLER THAN THE BOTTOM OF T
11. Er ke oa e e 23 Far End Fault mt Lue ete ta a a Re er cad e eut us 24 SQE Lleartbeat a oma at Ws idee PRG FAS Rd 24 Loopback Operation 24 o ya ed ye diras on d dates scc MES c ode 25 EED Port Configuration eran DI RR 25 Power Savings Mechanisms 1 27 Selectable Transformer ze rue a dr Case RC CI dar e ed 27 PoWer DIONA dr di da e t M I DES 27 Unplugged cu e eee e e 27 Idle Wire A ARS E RU d 27 PHY CONTROL AND MANAGEMENT BLOCK PCM BLOCK 28 Register Administration for 1OOBASE X PHY Device 28 Description of the 4 28 Bad Management Frame 29 6 Am79C874 PRELIMINARY AMD REGISTER DESCRIPTIONS ull He et ee ed eee te x rei 29 Serial Management 29 Management Control Register Register 0 30 MII Management Status Register Register 1
12. Symbol Parameter Description Min Max Unit REFCLK Period 39 998 40 002 ns REFCLK Width HIGH 18 22 ns REFCLK Width LOW 18 22 ns REFCLK Rise Time 5 tcLF REFCLK Fall Time ns REFCLK 222351 16 Figure 14 Clock Signal MLT 3 Signals Symbol Parameter Description Min Max Unit trxR Rise Time of MLT 3 Signal 3 0 5 0 ns ttxF Fall Time of MLT 3 Signal 3 0 5 0 ns Rise Time Fall Time Symmetry of MLT 3 Signal 5 96 Duty Cycle Distortion Peak to Peak 0 5 ns Transmit Jitter Using Scrambled Idle Signals 5 1 4 ns 1 0 1 TX 222351 17 Figure 15 MLT 3 Test Waveform 46 Am79C874 PRELIMINAR Y MII Management Signals Symbol Parameter Description Min Max Unit MDC Period 40 ns tMMDWH MDC Pulse Width HIGH 16 ns tMDWL MDC Pulse Width LOW 16 ns MDIO Delay From Rising Edge MDC 20 ns tips MDIO Setup Time to Rising Edge of MDC 4 ns MDIO Hold Time From Rising Edge MDC 3 ns lt tMDWH gt tMDWL MDC lt lupPD gt MDIO mdio tx vsd 222351 18 Figure 16 Management Bus Transmit Timing MDC N tups gt gt MDIO 222351 19 Figure 17 Management Bus Receive Timing Am79C874 47 PRELIMINAR Y MII Signals 100 Mbps MII Transmit Timing
13. OK Int This bit is set when link status switches from OK status to Not OK RC 0 Fail or Ready 17 1 R Fault Int This bit is set when a remote fault is detected RC 17 0 A Neg Comp Int This bit is set when Auto Negotiation is complete RC Note See Interrupt Source Table for bit assignments Diagnostic Register Register 18 Table 21 Diagnostic Register Register 18 Read Reg Name Description Write Default 18 15 12 Reserved Ignore when read RO 0 1 The result of Auto Negotiation for Duplex is Full duplex 18 u DPEA 0 The result of Auto Negotiation for Duplex is Half duplex RO 0 1 The result of Auto Negotiation for data rate arbitration is 100 Mbps 18 TU Pata Rate 0 The result of Auto Negotiation for data rate arbitration is 10 RO 0 Mbps Operating in 100BASE X mode 1 valid signal has been received but the PLL has not necessarily locked 18 9 PASS 0 valid signal has not been received RO 0 Operating in 10BASE T mode 1 Manchester data has been detected 0 Manchester data has not been detected 1 Receive PLL has locked onto received signal for selected data rate 10 or 100BASE X 18 0 Receive PLL has locked onto received signal RORG 0 This bit remains set until it is read 18 7 0 Reserved Ignore when read RO 0 Am79C874 37 Power Loopback Register Register 19 PRELIMINAR Y Table 22 Power Loopback Register Register 19
14. 1 Message page RW 1 0 Un formatted page Acknowledge 2 7 12 ACK2 1 Will comply with message RW 0 0 Cannot comply with message Toggle 7 11 TOG TX 1 Previous value of transmitted link code word equals to 0 RW 0 0 Previous value of transmitted link code word equals to 1 17 10 0 CODE Message Un formatted Code Field RW 001 Reserved Registers Registers 8 15 20 22 25 31 The NetPHY 1LP device contains reserved registers at addresses 8 15 20 22 25 31 These registers should be ignored when read and should not be written at any time Am79C874 35 Miscellaneous Features Register Register 16 PRELIMINAR Y Table 19 Miscellaneous Features Register Register 16 Control A 0 indicates that runs continuously during LINK whether data is received or not In loopback and PCS bypass modes writing to this bit does not affect Receive clock will be constantly active Read Reg Bit Name Description Write Default 1 Repeater mode full duplex is inactive and CRS only responds Set by 1 193 to receive activity SQE test function is also disabled RW RPTR INTR will be active high if this register bit is set to 1 Pin requires an external pull down resistor 16 14 INTR LEVL HERAN RW 0 INTR will be active low if this register bit is set to 0 Pin requires an external pull up resistor 16 13 12 Reserv
15. Half uP RO TECH 2 0 Duplex 0 No 10BASE T ability pins 1 10 7 Reserved Ignore when read RO 0 Management The device accepts management frames that do not have a 1 6 Frame Preamble preamble after receiving a management frame with a 32 bit or RO 1 Suppression longer preamble ut 1 Auto Negotiation process completed Registers 4 5 and 6 1 5 oe are valid after this bit is set RO 0 p 0 Auto Negotiation process not completed 1 Remote fault condition detected 1 4 Remote Fautt 0 7 No remote fault RO LH 0 This bit will remain set until it is read via the management interface 1 Able to perform Auto Negotiation function value is 1 Auto Negoliation determined py ANEGA pin RO set Ability 2 0 Unable to perform Auto Negotiation function 1 Link is established however if the NetPHY 1LP device link fails this bit will be cleared and remain cleared until Register 1 1 2 Link Status is read via management interface RO LL 0 0 link is down 1 Jabber condition detected 1 1 Jabber Detect Y RO LH 0 0 No Jabber condition detected Extended 1 Extended register capable This bit is tied permanently to 1 0 RO 1 Capability one PHY Identifier 1 Register Register 2 Table 12 Identifier 1 Register Register 2 Read Reg Name Description Write Default 2 15 loul Composed of the 3rd through 18th bits of the Organizationally RO 0022 H Unique Identifier OUI respectively Am79C87
16. Transmit Data Input The MAC will source TXD 3 1 to the PHY The data will be synchronous with TX CLK when TX EN is as serted The PHY will clock in the data based on the ris ing edge of TX CLK TXD 0 1 OTXD Transmit Data 0 10 Mbps Transmit Data Input The MAC will source TXD 0 to the PHY The data will be synchronous with TX CLK when TX EN is as serted The PHY will clock in the data based on the ris ing edge TX CLK When 7 wire 10BASE T mode is enabled this pin will transmit serial data COL 10COL Collision Output High Impedance COL is asserted high when a collision is detected on the media COL is also used for the SQE test function in 10BASE T mode 10COL is asserted high when a collision is detected during 7 wire interface mode CRS 10CRS Carrier Sense Output High Impedance CRS is asserted high when twisted pair media is non idle This signal is used for both 10BASE T and 100BASE X In full duplex mode CRS responds only to RX activity In half duplex mode CRS responds to both RX and TX activity 10CRS is used as the carrier sense output for the 7 wire interface mode Miscellaneous Functions PCSBP PCS Bypass Input Pull Down The 100BASE TX PCS as well as scrambler descram bler will be bypassed when PCSBP is pulled high via a 10 resistor TX ER will become TXD 4 and ER will become RXD 4 In 10 Mbps PCS bypass mode the signals are not valid The signals that interf
17. 58 10 Mbps GPSI Transmit 0 58 PHYSICAL 5 59 PQT80 measured in millimeters 1 59 REVISION HISTORY A x RG 60 List of Figures Figure 1 FXT and FXR Termination for 100 5 17 Figure 2 MLT 3 20 Figure 3 TX RX Termination for 100BASE TX and 10 21 Figure 5 Standard LED Configuration 26 Figure 6 Advanced LED Configuration 27 Figure 7 PHY Management Read and Write 28 Figure 8 MLT 3 Receive Input 43 Figure 9 MLT 3 and 10BASE T Test Load with 1 1 Transformer Ratio 44 Figure 10 MLT 3 and 10BASE T Test Load with 1 25 1 Transformer 44 Figure 11 Near End 100BASE TX Waveform 45 Figure 12 10BASE T Waveform With 1 1 Transformer 45 Am79C874 PRELIMINARY Figure 13 PECL Test Loads cc sonei end ee Wa ee ee 45 Figure 14 Clock
18. The Far End Fault mechanism defaults to enable 100BASE FX mode and disable 100BASE TX and 10BASE T modes and may be controlled by software after reset SQE Heartbeat When the SQE test is enabled a COL signal with a 5 15 bit time pulse will be issued after each transmitting packet SQE is enabled and disabled via Register 16 bit 11 Loopback Operation A local loopback and remote loopback are provided for testing They can be enabled by writing to either MII 24 Register 0 bit 14 Loopback or MII Register 21 bit EN RPBK The local loopback routes transmitted data at the out put of NRZ to NRZI conversion module back to the receiving path s clock and data recovery module for connection to PCS in 5 bits symbol format This loop back is used to check all the connections at the 5 bit symbol bus side and the operation of analog phase locked loop In local loopback the SD output is forced to logic one and outputs are tristated During local loopback a 10 Mbps link is sent to the link partner In either 100BASE TX or 10BASE T loopback mode the link for 10 Mbps is forced Register 21 bit 14 and is seen externally If packets are transmitted from the Device Under Test DUT the link between the DUT and link partner is lost Ceasing transmission causes the link to go back up In remote loopback incoming data passes through the equalizer and clock recovery then loop back to NRZI MLT3 conversion module
19. A Dual Color LED LED 330 LEDTXB Link Note 2 LEDLNK JA 100BASE TX LED Indicator Notes 1 Use for non 7 wire interface configurations 2 Use for 7 wire interface configurations 222351 8 Figure 6 Advanced LED Configuration Power Savings Mechanisms The power consumption of the device is significantly re duced by its built in power down features Separate power supply lines are also used to power the 10BASE T circuitry and the 100BASE TX circuitry Therefore the two modes of operation can be turned on and turned off independently Whenever the Net PHY 1LP device is set to operate in a 100BASE TX mode the 10BASE T circuitry is powered down and when in 10BASE T mode the 100BASE TX circuitry is powered down The NetPHY 1LP device offers the following power management Selectable Transformer Power Down Unplugged and Idle Selectable Transformer The TX outputs can drive either a 1 1 transformer or a 1 25 1 transformer The latter can be used to reduce transmit power further The current at the TX pins for a 1 1 ratio transformer is 40 mA for MLT 3 and 100 mA for 10BASE T Using the 1 25 1 ratio reduces the cur rent to 30 mA for MLT 3 and 67 mA for 10BASE T The cost of using the 1 25 1 option is in impedance coupling The reflected capacitance is increased by the square of the ratio 1 25 1 56 Thus the reflected capacitance on the media side is roughly one and a half times the capacitanc
20. Exposure to absolute maximum ratings for extended periods may affect device reliability DC CHARACTERISTICS OPERATING RANGES Commercial C Operating Temperature TA 0 C to 70 Supply Voltage All 3 3 V 596 Supply Voltage 5 V tolerant pins 5 0 V 596 Industrial Operating Temperature TA 40 to 85 Supply Voltage 3 3 5 Supply Voltage 5 V tolerant pins 5 0 V 5 Operating ranges define those limits between which functionality of the device is guaranteed Note Parametric values are the same for Commercial and Industrial devices Symbol Parameter Description Test Conditions Minimum Maximum Units Input LOW Voltage 0 8 V Input HIGH Voltage 2 0 V VoL Output LOW Voltage 8 mA 0 4 V Output HIGH Voltage 4 mA 2 4 Output LOW Voltage LED lo LED 10 mA 0 4 V Output HIGH Voltage LED Io LED 10 mA Vpp 0 4 V Input Common Mode Voltage Vomp PECL Note 1 Vpop 1 5 Vpp 0 7 V Differential Input Voltage _ VipiFFP PECL Note 1 Vpp Maximum 400 1 100 mV Output HIGH Voltage PECL Vois Note 4 9 PECL Load Vpp 1 025 Vpp 0 60 V Output LOW Voltage PECL Voile Note 4 9 PECL Load Vpp 1 81 1 62 Signal Detect Assertion Vspa Threshold P P Note 2 MLT 3 10BASE T Test Load
21. LEDBTB 67 TEST1 FXR m LEDLNK 8 RST 28 DGND1 48 LED 10LNK 68 TEST2 LED PCSBP SD 9 PWRDN 29 DV 49 OVDD2 69 10 PLLVCC 30 RX CLKAORXCLK 50 OGND2 70 FXT 11 PLLGND 31 RX ER RXD 4 51 CRVGND 71 REFGND 12 OGND1 32 TX_ER TXD 4 52 CRVVCC 72 IBREF 13 OVDD1 33 4 53 SEL 2 73 14 PHYAD 4 10RXD 34 TX_EN 10TXEN 54 TECH_SEL 1 74 XTL 15 PHYAD 3 10RXD 35 DGND2 55 SEL 0 75 XTL 16 PHYAD 2 10TXD 36 VDD2 56 76 TGND2 17 PHYAD 1 10TXD 37 TXD OJ10TXD 57 usu 77 18 PHYAD O 1 OTXD 38 TXD 1 58 LEDDPX LEDTXB 78 TX 19 39 TXD 2 59 ADPVCC 79 20 GPIO 1 TP125 40 TXD 3 60 EQVCC 80 TVCC2 Am79C874 AMDA PIN DESCRIPTIONS The following table describes terms used in the pin de scriptions Term Description Input Digital input to the PHY Analog Input Analog input to the PHY Output Digital output from the PHY Analog Output Analog output from the PHY High Impedance Tri state capable output from the PHY PHY has internal pull up resistor Pull Up NC HIGH PHY has internal pull down resistor Pull Down NC LOW Media Connections Transmitter Outputs Analog Output The TX pins are the differential transmit output pair The pins transmit 10BASE T or MLT 3 signals de pending on the state of the link of the port Receiver Input Analog Input The RX pins are
22. LEDSEL description this pin serves as the duplex LED A logic low level indicates full duplex oper ation A logic high level indicates half duplex operation See Table 4 and Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED When the advanced LED configuration is enabled this pin works in conjunction with LEDSPD 1 LEDTXA CLK25EN pin 57 Refer to Table 5 and Figure 6 in the LED Port Configuration section to determine the cor rect polarity of the bi directional LED Bias IBREF Reference Bias Resistor Analog This pin must be tied to an external 10 0 196 resis tor which should be connected to ground The 1 re sistor provides the bandgap reference voltage Power and Ground PLLVCC OVDD1 OVDD2 VDD1 VDD2 CRVVCC ADPVCC EQVCC REFVCC TVCC1 TVCC2 Power Pins Power These pins are 3 3 V power for sections of the NetPHY 1LP device as follows PLLVCC is power for the PLL OVDD1 and OVDD2 are power for the VDD1 and VDD2 are power for the digital logic CRVVCC is power for clock recovery AD EQVCC are power for the equalizer REFVCO is power for the bandgap reference and TVCC1 and TVCC2 are power for the transmit driver PLLGND OGND1 OGND2 DGND1 DGND2 CRVGND EQGND REFGND TGND1 TGND2 Ground Pins Power These pins are ground for the power pins as follows PLLGND is ground for PLLVCC OGND is ground for OVDD DGND is ground for VDD CRVGN
23. Signals RXD 3 0 MII Receive Data Output High Impedance The data is synchronous with when DV is active When the 7 wire 10BASE T interface operation is enabled GPIO 0 HIGH RXD 0 will serve as the 10 MHz serial data output RX DV Receive Data Valid Output High Impedance RX DV is asserted when the NetPHY 1LP device is presenting recovered nibbles on RXD 3 0 This in cludes the preamble through the last nibble of the data stream on RXD 3 0 In 100BASE X mode the J K is considered part of the preamble thus RX DV is as serted when J K is detected In 10BASE T mode RX DV is asserted and data is presented on 01 when the device detects valid preamble bits DV is synchronized to RX CLKAORXCLK Receive Clock Output High Impedance A continuous clock which is active while LINK is estab lished provides the timing reference for RX DV RX ER and RXD 3 0 signals It is 25 MHz in 100BASE TX FX and 2 5 MHz in 10BASE T To further reduce power consumption of the overall system the device provides an optional mode enabled through MII Register 16 bit 0 in which RX CLK is held inactive low when data is received If is needed when LINK is not established the NetPHY 1LP must be placed into digital loopback or force the link via register 21 bits 13 or 14 When 7 wire 10BASE T mode is enabled this pin will provide a 10 MHz clock RX CLK is high impedance when t
24. TX Half Duplex 100BASE TX 4 7 Half Duplex 0 No 100BASE TX Half Duplex capability RW TECH 2 0 Default is set by Register 1 13 pins 1 10 Mbps Full Duplex 10BASE T 2 set by 4 6 Full Duplex 0 No 10 Mbps Full Duplex capability RW TECH 2 0 Default is set by Register 1 12 pins 1 10 Mbps Half Duplex 4 5 E 0 10 Mbps Half Duplex capabilit RW Half Duplex g p p y qu Default is set by Register 1 11 pins 4 4 0 Selector Field 00001 IEEE 802 3 RO 00001 32 Am79C874 PRELIMINAR Y Auto Negotiation Link Partner Ability Register in Base Page Format Register 5 Table 15 Auto Negotiation Link Partner Ability Register Base Page Format Register 5 Read Reg Bit Name Description Write Default 1 Next Page Requested by Link Partner 5 15 Next Page RO 0 0 Next Page Not Requested 1 Link Partner Acknowledgement 5 14 Acknowledge RO 0 0 No Link Partner Acknowledgement 1 Link Partner Remote Fault Request 5 13 Remote Fault RO 0 0 No Link Partner Remote Fault Request 5 12 11 Reserved Reserved for Future Technology RO 1 Link Partner supports Flow Control 5 10 Flow Control 4 0 0 Link Partner does support Flow Control 1 Remote Partner is 100BASE T4 Capable 5 9 100BASE T4 0 0 Remote Partner is not 100 4 Capable 1 Link Partner is capable of 100BASE TX Full Duplex 10
25. clock is also used to generate the 25 MHz RX CLK The APLL requires no external components for its operation and has high noise immunity and low jitter It provides fast phase align lock to data in one transition and its data clock acquisition time after power on is less than 60 transitions The APLL can maintain lock on run lengths of up to 60 data bits in the absence of signal transitions When no valid data is present i e when the SD is de asserted the switches back to lock with thus pro viding a continuously running The recovered data is converted from NRZI to NRZ and then to a 5 bit parallel format The 5 bit parallel data is not necessarily aligned to 4B 5B code group s symbol boundary The data is presented to PCS at re ceive data register output gated by the 25 MHz RX_CLK PLL Clock Synthesizer The NetPHY 1LP device includes an on chip PLL clock synthesizer that generates a 125 MHz and a 25 MHz clock for the 100BASE TX or a 100 MHz and 20 MHz clock for the 10BASE T and Auto Negotiation opera tions Only one external 25 MHz crystal or a signal source is required as a reference clock After power on or reset the PLL clock synthesizer is defaulted to generating the 20 MHz clock output and will stay active until the 100BASE X operation mode is selected Am79C874 21 AMDA 10BASE T Block The NetPHY 1LP transceiver incorporates the 10BASE T physical layer functions including cloc
26. it becomes an active LOW driver Proper configuration requires pull up or pull down re sistors As shown in the Pin Description sections each of the LED Configuration pins has internal pull up re sistors If the pin s LED functionality is not used the pin may still need to be terminated via an external pull down resistor according to the desired configuration The resistor value is not critical and can be in the range of 1 kO to 10 If the corresponding LED is used the terminating resistor must be placed in parallel with the LED Suggested LED connection diagrams simplifying the board design are shown in Figure 5 standard and Figure 6 advanced The value of the series resistor should be selected to ensure sufficient illumination of the LED It is depen dent on the rating of the LED Table 4 Standard LED Selections MODE LEDSDP 0 LEDSDP 1 LEDLNK LEDDPX LEDTX LEDRX LEDCOL No Link 0 0 0 0 0 0 0 10HD RX 0 1 1 0 0 T 0 10HD TX 0 1 1 0 T 0 0 10HD COL 0 1 1 0 T T T 10FD RX 0 1 1 1 0 T 0 10FD TX 0 1 1 1 T 0 0 10FD RX TX 0 1 1 1 T T 0 100HD RX 1 0 1 0 0 T 0 100HD TX 1 0 1 0 T 0 0 100HD COL 1 0 1 0 T T T 100FD RX 1 0 1 1 0 T 0 100FD TX 1 0 1 1 T 0 0 100FD RX TX 1 0 1 1 T T 0 Notes 1 1 means on logic level low since active low 2 0 means off logic level high since active low 3 T means toggles will end at logic level high Am
27. pin ISODEF 1 ISO bit will set to 1 amp ISODEF 0 ISO RW ISODEF bit will set to O pin 0 Normal operation 1 Restart Auto Negotiation process 0 9 Restart Auto estar 9 RW SC 0 Negotiation 0 Normal operation 1 Full duplex 0 Half duplex Set by 0 8 Duplex Mode T RW TECH 2 0 Refer to Table 3 to determine when this bit can be changed pins 1 Enable collision test which issues the COL signal in response 2 to the assertion of TX EN signal Collision test is disabled if PCSBP 0 7 Collision Test bin is high Collision test is enabled regardless of the duplex mode R 0 0 disable COL test 0 6 0 Reserved Write as 0 ignore when read RW 0 30 Am79C874 PRELIMINAR Y MII Management Status Register Register 1 Table 11 Management Status Register Register 1 Read Reg Bit Name Description Write Default 1 15 100 4 5 r RO 0 0 Not 100BASE T4 able 5 1 100BASE TX Full Duplex set by 1 14 100BASE TX Full p TECHI2 0 Duplex 0 No 100BASE TX Full Duplex ability pins 1 100BASE TX Half Duplex Set by 1 13 100BASE TX Half RO TECHI2 0 Duplex 0 No TX half duplex ability pins 1 10BASE T Full Duplex set by 1 48 RO TECH 2 0 Duplex 0 No 10BASE T Full Duplex ability pins 1 10BASE T Half Duplex Set by 11 10 5
28. the differential receive input pair The RX pins can receive 10BASE T or MLT 3 signals de pending on the state of the link of the port Transmit Analog Output These pins are not connected in 10 100BASE TX mode When FX SEL Pin 44 is pulled low these pins be come the ECL level transmit output for 100BASE FX TESTO FXR Test Output FX Receive Analog Output Input When BURN Pin 7 is pulled high this pin serves as a test mode output monitor pin When FX SEL Pin 44 is pulled low this pin becomes an ECL level negative receive input for 100BASE FX This pin can be left unconnected when the device is op erating in 100BASE TX or 10BASE T mode TEST1 FXR Test Output FX Receive Analog Output Input When Pin 7 is pulled high this pin serves as a test mode output monitor pin When FX_SEL Pin 44 is pulled low this pin becomes an ECL level positive receive input for 100BASE FX This pin can be left unconnected when the device is op erating in 100BASE TX or 10BASE T mode PRELIMINARY TEST3 SDI FX Transceiver Signal Detect Analog Output Input When BURN_IN Pin 7 is pulled high this pin serves as a test mode output monitor pin This pin is not connected in 10 100BASE TX mode When FX_SEL Pin 44 is pulled low this pin becomes the Signal Detect input from the Fiber Optic trans ceiver When the signal quality is good the SDI pin should be driven high MII 7 Wire GPSI
29. wire serial interface to connect a management entity and a managed PHY for the purpose of controlling the PHY and gathering status information The two lines are Management Data Input Output MDIO and Man PRELIMINAR Y agement Data Clock MDC A station management entity which is attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for each PHY entity Description of the Methodology The management interface physically transports man agement information across the MII The information is encapsulated in a frame format as specified in Clause 22 of IEEE 802 3u draft standard and is shown in Table 6 Table 6 Clause 22 Management Frame Format PRE ST OP PHYAD REGADD TA DATA IDLE READ 1 1 01 10 AAAAA RRRRR 20 Dus D Z WRITE 1 1 01 01 AAAAA RRRRR 10 2 The PHYAD field which is five bits wide allows 32 unique PHY addresses The managed PHY layer de vice that is connected to a station management entity via the MII interface has to respond to transactions addressed to the PHY address A station management entity attached to multiple PHYs such as in a managed 802 3 Repeater or Ethernet switch is required to have prior knowledge of the appropriate PHY address See Table 7 and Figure 7 Table 7 PHY Address Setting Frame Structure
30. 0BASE TX Full 5 9 Duplex 0 Link Partner is Not Capable of 100BASE TX Full RO 0 Duplex 1 Link Partner is Capable of 100BASE TX Half Duplex 100BASE TX Half 5 7 Duplex 0 Link Partner is Not Capable of 100BASE TX Half RO 0 Duplex 1 Link Partner is capable of 10BASE T Full Duplex 10BASE T Full 5 6 0 Link Partner is Not Capable of 10BASE T Full RO 0 Duplex 1 Link Partner is capable of 10BASE T Half Duplex 10BASE T Half 5 Duplex 0 Link Partner is Not Capable of 10BASE T Half RO 0 Duplex 5 4 0 Selector Field Link Partner Selector Field RO 00001 Auto Negotiation Link Partner Ability Register in Next Page Format Register 5 Table 16 Auto Negotiation Link Partner Ability Register in Next Page Format Register 5 Read Reg Bit Name Description Write Default 1 Next Page Requested by Link Partner 5 15 Next Page RO 0 0 Next Page Not Requested 1 Link Partner Acknowledgement 5 14 Acknowledge RO 0 0 No Link Partner Acknowledgement 1 Link Partner message Page Request 5 13 Message Page RO 0 0 No Link partner Message Page Request 1 Link Partner can Comply Next Page Request 5 12 Acknowledge 2 RO 0 0 Link Partner cannot Comply Next Page Request 5 11 Toggle Link Partner Toggle RO 0 5 10 0 Message Field Link Partner s Message Code RO 0 Am79C874 33 Auto Negotiation Expansion Register Register 6 PRELIMINAR Y Table
31. 1000 mV Signal Detect Deassertion Vspp Threshold P P Note 3 MLT 3 10BASE T Test Load 200 mV Vpp Maximum liL Input LOW Current Note 12 VIN 0 0 V 40 Vpp Maximum Input HIGH Current Note 12 VIN 227V 40 eremia Output Voltage ier gBASET Test Load 950 1050 mV Note 5 Nee Geer Output Overshoot MLT 3 10BASE T Test Load 005 Vrxour V Differential Output Voltage a Ratio Note5 amp Note 6 MLT 3 10BASE T Test Load 0 98 1 02 Am79C874 41 PRELIMINARY DC CHARACTERISTICS CONTINUED Symbol Parameter Description Test Conditions Minimum Maximum Units RX 10BASE T Squelch Threshold Sinusoid 5 MHz f 10 MHz 300 585 mV RX Post Squelch Differential VtHs Threshold 10BASE T Sinusoid 5 MHz lt f lt 10 MHz 150 293 mV 10BASE T RX Differential VnxpTH Switching Threshold Sinusoid 5 MHz f 10 MHz 60 60 mV 10BASE T Near End Peak _ Differential Voltage MLT 3 10BASE T Test Load 2 2 2 8 V Note 7 Output Leakage Current 0 4 V lt VOUT lt V 30 30 hA oz Note 10 BD Input Capacitance Cin Note 13 pr 10BASE T idle 30 10BASE T normal activity 105 10BASE T peak 130 loc Power Supply Current 100BASE TX 100 100BASE TX no cable 20 Power down 1 Notes 1 Applies to TEST1 FXR TESTO FXR SDI inputs only Valid only when PECL mode 2 Applies to R
32. 17 Auto Negotiation Expansion Register Register 6 Negotiation Able 0 Link partner is not auto negotiation able Read Reg Name Description Write Default 6 15 5 Reserved Ignore when read RO 0 1 Fault detected by parallel detection logic This fault is due to Parallel Detection more than one technology detecting concurrent link up 6 4 Fault conditions This bit is cleared upon reading this register RO LH 0 0 No fault detected by parallel detection logic 6 3 Link Partner Next 1 Link partner supports next page function RO 9 Page Able 0 Link partner does not support next page function 6 2 Next Page Able Next page is supported This bit is permanently tied to 1 RO 1 This bit is set when a new link code word has been received into 6 1 Page Received the Auto Negotiation Link Partner Ability Register This bit is RO LH 0 cleared upon reading this register i 1 Link partner is auto negotiation able 6 0 Link Partner Auto 9 RO 0 34 Am79C874 PRELIMINAR Y Auto Negotiation Next Page Advertisement Register Register 7 Table 18 Auto Negotiation Next Page Advertisement Register Register 7 Read Reg Name Description Write Default Next page indication 7 15 INP 1 Another Next Page desired RW 0 0 No other Next Page Transfer desired 7 14 Reserved Ignore when read RO 0 Message page 7 13
33. 2538 m79C 8744 Am79C874 NetPHY 1LP Low Power 10 100 TX FX Ethernet Transceiver DISTINCTIVE CHARACTERISTICS 10 100 Ethernet PHY device with 100BASE FX fiber optic support Typical power consumption of 0 3 W Sends receives data reliably over cable lengths greater than 130 meters MII mode supports 100BASE X and 10BASE T B 7 Wire General Purpose Serial Interface GPSI mode supports 10BASE T B Three PowerWise management modes from 300 mW typical Power down only management responds Typical power z 3 mW Unplugged no cable no receive clock Typical power 100 mW Idle wire no wire signal no receiver power Typical power 285 mW MAC saves over 100 mW GENERAL DESCRIPTION The Am79C874 NetPHY 1LP device provides the phys ical PHY layer and transceiver functions for one 10 100 Mbps Ethernet port It delivers the dual benefits of CMOS low power consumption and small package size Operating at 3 3 V it consumes only 0 3 W Three power management modes provide options for even lower power consumption levels The small 12x12 mm 80 pin PQL package conserves valuable board space on adapter cards switch uplinks and embedded Ether net applications The NetPHY 1LP 10 100 Mbps Ethernet PHY device is IEEE 802 3 compliant It can receive and transmit data reliably at over 130 meters It includes on chip input fil tering and output waveshaping for unshield
34. 4 31 Identifier 2 Register Register 3 PRELIMINAR Y Table 13 Identifier 2 Register Register 3 Read Reg Name Description Write Default 3 15 10 OUI Assigned to the 19th through 24th bits of the OUI RO 010101 9 4 Model Number Six bit manufacturer s model number RO 100001 3 0 Revision Number Four bit manufacturer s revision number RO 1011 Auto Negotiation Advertisement Register Register 4 Table 14 Auto Negotiation Advertisement Register Register 4 Read Reg Name Description Write Default 1 Next Page enabled 4 15 Next Page RW 0 0 Next Page disabled 4 14 Acknowledge This bit will be set internally after receiving three consecutive RO 0 and consistent FLP bursts 1 Remote fault supported 4 13 Remote Fault RW 0 0 No remote fault 4 12 11 Reserved For future technology RW 0 Full Duplex Flow Control 1 Advertise that the DTE MAC has implemented both the 4 10 FDFC optional MAC control sublayer and the pause function as RW 0 specified in clause 31 and annex 31 B of 802 3u 0 No MAC based full duplex flow control 4 9 100 5 4 NetPHY 1LP device does not support 100 4 function RO 0 i e this bit ties to zero 1 2 100BASE TX Full Duplex 100BASE TX set by 4 8 Full Duplex 0 No 100BASE TX Full Duplex ability RW TECH 2 0 Default is set by Register 1 14 pins 1 100BASE
35. 7 GPIO 0 Data If MII Register 16 bit 6 is set LOW GPIO 0 is an output The value of MII Register 16 bit 7 will be reflected on the GPIO 0 output pin GPIO 1 TP125 General Purpose I O 1 Input Output Pull Down If this pin is pulled high via 10 resistor on the ris ing edge of reset the device will be enabled for use with a 1 25 1 transmit ratio transformer If this pin is left unconnected during the rising edge of reset the device will be enabled for use with a 1 1 transmit ratio transformer After the reset operation has completed this pin can function as an input or an output dependent on the value of GPIO 1 DIR MII Register 16 bit 8 If MII Register 16 bit 8 is set HIGH GPIO 1 is an input The input value on the GPIO 1 pin will be reflected in MII Register 16 bit 9 GPIO 1 Data If MII Register 16 bit 8 is set LOW GPIO 1 is an output The value of MII Register 16 bit 9 will be reflected on the GPIO 1 output pin MDIO Management Data Input Output Pull Down This pin is a bidirectional data interface used by the MAC to access management registers within the Net PHY 1LP device This pin has an internal pull down therefore it requires a 1 5 pull up resistor as speci fied in IEEE 802 3 when interfaced with a MAC This pin can be left unconnected when management is not used 12 Am79C874 PRELIMINAR Y MDC Management Data Clock Input This clock is sourced by the MAC and is used
36. 79C874 25 PRELIMINAR Y LED VCC M 330 100Mbps LEDSPDI0 K LED VCC M 330 10Mbps LEDSP 1 lt LED VCC M 330 Collision LEDCOL lt LED VCC M 330 Duplex LEDDPX lt WW LED VCC M 330 Transmit LEDTX N LED VCC M 330 Receive LEDRX KI WW LED VCC M 330 Link Note 1 LEDLNK K LED ff 330 Link Note 2 LEDLNK N i 222351 7 Notes 1 Use for non 7 wire interface configurations 2 Use for 7 wire interface configurations Figure 5 Standard LED Configuration Table 5 Advanced LED Selections LEDBTX LEDBTA LEDTX LEDBTB LEDBT LEDTXA LEDFDX LEDTXB MODE Pin 44 Pin 47 Pin 57 Pin 58 No Link 0 0 0 0 10BT Half Duplex 1 0 0 0 10BT Half Activity Flash Note 1 0 0 0 10BT Full Duplex 0 1 0 0 10BT Full Activity 0 Flash Note 2 0 0 100BT Half Duplex 0 0 1 0 100BT Half Activity 0 0 Flash Note 1 0 100BT Full Duplex 0 0 0 1 100BT Full Activity 0 0 0 Flash Note 2 Notes 1 LED flashes for RX and TX activity 2 LED flashes for RX activity 26 3 0 means logic level low at the pin 4 1 means logic level high at the pin Am79C874 PRELIMINAR Y VCC 300 LED 330 LEDBTA AN Receive LEDRX K A 5K LED LEDBTB VCC LED 330 d 10BASE T LED Indicator Collision LEDCOL N VCC E a20 LEDTXA E Link Note 1 LEDLNK KI
37. D This pin toggles between high and low when data is received When the device is operating in the standard LED mode refer to Table 4 and Figure 5 in the LED Port Configuration section When the device is op erating in the advanced LED mode refer to Table 5 and Figure 6 in the LED Port Configuration section LEDCOL SCRAM EN Collision LED Scrambler Enable Input Output Pull Up When this pin is pulled low via a 1 resistor on the rising edge of reset the scrambler descrambler is dis abled If no pull down resistor is present on the rising edge of reset the scrambler descrambler is enabled After the rising edge of reset this pin controls the Colli sion LED This pin toggles between high and low when there is a collision in half duplex operation In full duplex operation this pin is inactive When the device is operating in the standard LED mode see LEDRX LED SEL pin description refer to Table 4 and Figure 5 in the LED Port Configuration section When the device is op erating in the advanced LED mode see LEDRX LED SEL pin description see Table 5 and Figure 6 LEDLNK LED 10LNK LED PCSBP SD Link LED 7 Wire Link LED PCSBP Signal Detect Output When link is established in 100BASE X or 10BASE T mode this pin will assume a logic low level When link is established in 7 Wire mode this pin will assume a logic high level When in PCS Bypass mode this pin assumes a logic high level indicating Signal Detec
38. D 11011 Data D 1110 E 11100 Data E 1111 11101 Data F Undefined 11111 IDLE used as inter Stream fill code 0101 J 11000 Start of Stream ot M of 2 always used 0101 K 10001 Start of Stream of 2 always used Undefined T 01101 End of Stream id RS always used in Undefined R 00111 End of Stream id 27 always used in Undefined H 00100 Transmit Error used to force signaling errors Undefined V 00000 Invalid Code Undefined V 00001 Invalid Code Undefined V 00010 Invalid Code Undefined V 0001 1 Invalid Code Undefined V 00101 Invalid Code Undefined V 00110 Invalid Code Undefined V 01000 Invalid Code Undefined V 01100 Invalid Code Undefined V 10000 Invalid Code Undefined V 11001 Invalid Code Am79C874 19 MLT 3 This block is responsible for converting the NRZI data stream from the PDX block to the MLT 3 encoded data stream The effect of MLT 3 is the reduction of energy on the copper media TX or FX cable in the critical fre quency range of 1 MHz to 100 MHz The receive sec tion of this block is responsible for equalizing and amplifying the received data stream and link detection The adaptive equalizer compensates for the amplitude and phase distortion due to the cable MLT 3 is a tri level signal All transitions are between 0 V and 1 V or 0 V and 1 V A transition has a logical value of 1 and a lack of a transition has a logical value of 0 The benefit of MLT 3 is that it reduces the maxi mum frequenc
39. D is ground for CRVVCC and ADPVCC EQGND is ground for EQVCC REFGND is ground for REFVCC and TGND is ground for TVCC Note Bypass capacitors of 0 1 uF between the power and ground pins are recommended The four areas where the capacitors must be very close to the pins within mm are the PLL pins 10 and 11 Clock Re covery pins 51 and 52 Equalizer pins 60 and 65 and Reference pins 71 and 73 areas The other bypass capacitors should be placed as close to the pins as possible 14 Am79C874 PRELIMINAR Y FUNCTIONAL DESCRIPTION The NetPHY 1LP device integrates the 100BASE X PCS PMA and PMD functions and the 10BASE T Manchester ENDEC and transceiver functions in a sin gle chip for Ethernet 10 Mbps and 100 Mbps opera tions It performs 4B 5B MLT3 NRZI and Manchester encoding and decoding clock and data recovery stream cipher scrambling descrambling adaptive equalization line transmission carrier sense and link integrity monitor Auto Negotiation and MII manage ment functions It provides an IEEE 802 3u compatible Media Independent Interface MII to communicate with an Ethernet Media Access Controller MAC Se lection of 10 Mbps or 100 Mbps operation is based on settings of internal Serial Management Interface regis ters or determined by the on chip Auto Negotiation logic The device can be set to operate either in full du plex mode or half duplex mode for either 10 Mbps or 100 Mbps The Ne
40. E Ra Red arte a d a deaur ge OR 17 4B 5B 18 RR RR e 18 Ein MORONS 5 ith MR ee qe Boe Radar A ace NAS 18 RECEPIT 20 Adaptive 20 Baseline Wander 1 20 Clock Data 21 PLL Clock Synthesizer 4 21 TOBASE T kiu aq Q ua Gb usa 22 Twisted Pair Transmit Process 22 Twisted Pair Receive 5 22 Twisted Pair Interface 22 Collision Detect F ricliorn y ss ERU ee e teat P eet ed ane e ecd 22 Jabber Eunctloris a d Te ade ac tp US De quls debes ues ho 22 Reverse Polarity Detection and 23 Auto Negotiation and Miscellaneous Functions 23 1 14 0 1 23 ParallelDet ctlOn vy
41. GPSI Transmit Timing Symbol Parameter Description Min Max Unit 10TXCLK to 10TXD or 10TXEN Hold Time 20 ns teptcs 10TXD or 10TXEN to 10TXCLK Setup Time 20 ns 10TXCLK Width HIGH 45 55 ns 10TXCLK Width LOW 45 55 ns 10TXCLK Period 99 995 100 005 ns 10TXCLK 10TXD tGTCDH 10TXEN 22235E 36 Figure 31 GPSI Transmit 10TXCLK and 10TXD Timing Q DUT E 50 pF 22235E 37 Figure 32 Test Load for 10RXD 10CRS 10RXCLK 10TXCLK and 10COL 58 Am79C874 PRELIMINAR Y PHYSICAL DIMENSIONS 80 measured in millimeters 80 Lead Thin Plastic Quad Flat Pack PQT 20 0 20 M H 4 B ODO 110 05 MM MM D 000 LEAD SIDES b DR D DETAIL X EVEN LEAD SIDES b WITH LEAD FINISH jt b T 0 09 016 0 09 0 20 1 5 SEE DETAIL A DETAIL Y BASE METAL SEE DETAIL A 0 05 SEATING PLANE E LL 2 C 119 139 c sd mr or dx rd 0
42. HE PACKAGE BY 0 15 MILLIMETERS aaa 0 20 12 THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MO 136 MS 026 Am79C874 59 PRELIMINARY REVISION SUMMARY Revisions to other versions this document are as follows Revision C to D 1 2 Corrected reversal of Figure 4 and Figure 5 in LED section Changed ECL to PECL Revision D to E 1 2 Added GPSI timing and diagrams Added Industrial Temperature support Revision E to F 1 Minor edits Revision F to G 1 Minor edits Revision G to H 1 PHYAD pins Specified using resistors in the range of 1 to 4 7 for setting PHYAD pins In GPSI mode PHYAD pins must be set to addresses other than OOh DC Characteristics added and Vout DC Characteristics added new values for loz Figure 6 Advanced LED Configuration changes to Re ceive LED component changes Revision H to I 1 Added clarification to throughout document which is active only while LINK is established See pin de scription for more information Added Flow Control descriptions to registers 4 and 5 Register 21 bit 9 was reversed 1 selects the standard LED configuration while 0 selects the advanced LED configuration Register 21 bit 2 was changed to indicate EN SCRM Scrambler Enable a 1 enables the scrambler This reg ister is set by the SCRAM EN pin Maximum input voltage is 5 5 V operating voltage for 5 V tolerant pins
43. LED This pin toggles between high and low when data is transmitted Refer to Table 4 and Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED When the advanced LED configuration is enabled this pin works in conjunction with LEDSPD O LEDBTA FX SEL pin 44 Refer to Table 5 and Figure 6 in the LED Port Configuration section to determine the cor rect polarity of the bi directional LED LEDSPD 1 LEDTXA CLK25EN 10 Mbps Speed LED Advanced LED 25 MHz Clock Enable Input Output Pull Up When this pin is pulled low via a 1 resistor on the rising edge of reset the device will output a 25 MHz clock on CLK25 pin 6 When no pull down resistor is present on the rising edge of reset CLK25 is inactive When the standard LED configuration is enabled see LEDRX LEDSEL pin description this pin serves as the 10 Mbps speed LED A logic low level indicates 10 Mbps operation logic high level indicates 100 Mbps operation Refer to Table 4 and Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED When the advanced LED configuration is enabled this pin works in conjunction with LEDDPX LEDTXB pin 58 Refer to Table 5 and Figure 6 in the LED Port Con PRELIMINAR Y figuration section to determine the correct polarity of the bi directional LED LEDDPX LEDTXB Duplex LED Advanced LED Output When the standard LED configuration is enabled see LEDRX
44. Mbps operation the MII signals are not used In stead the NetPHY 1LP device operates as a 10BASE T transceiver providing received data to the MAC over a serial differential pair see Pin Descrip tions PCSBP pin The MAC uses two serial differential pairs to provide transmit data to the NetPHY 1LP de vice where the two differential pairs are combined in the NetPHY 1LP device to compensate for inter symbol interference on the twisted pair medium 100BASE X Block The functions performed by the device include encod ing of MII 4 bit data 4B 5B decoding of received code groups 5B 4B generating carrier sense and collision detect indications serialization of code groups for transmission de serialization of serial data upon re ception mapping of transmit receive carrier sense and collision at the MII interface and recovery of clock from the incoming data stream It offers stream cipher scrambling and descrambling capability for 100BASE TX applications In the transmit data path for 100 Mbps the NetPHY 1LP transceiver receives 4 bit nibble wide data across the MII at 25 million nibbles per second For 100BASE TX applications it encodes and scram bles the data serializes it and transmits an MLT 3 data stream to the media via an isolation transformer For 100BASE FX applications it encodes and serializes the data and transmits a Pseudo ECL PECL data stream to the fiber optic transmitter See Figure 1 In the receive
45. Note 3 Yes Note 2 No Capabilities ANEG 1 0 0 1 Yes Note 3 Yes Note 3 Yes Note 2 10HD ANEG 1 0 1 0 Yes Note 3 Yes Note 3 Yes Note 2 100HD ANEG 1 0 1 1 Yes Note 3 Yes Note 3 Yes Note 2 100HD 10HD ANEG 1 1 0 0 Yes Note 3 Yes Note 3 Yes Note 2 No Capabilities ANEG 1 1 0 1 Yes Note 3 Yes Note 3 Yes Note 2 10FD HD ANEG 1 1 1 0 Yes Note 3 Yes Note 3 Yes Note 2 100FD HD ANEG 1 1 1 1 Yes Note 2 Yes Note 3 Yes Note 2 All Capabilities ANEG Notes 1 MII Register 0 speed and duplex bits must be set by the MAC to achieve a link 2 The advertised abilities in MII Register 4 cannot exceed the abilities of MII Register 1 Auto Negotiation should always remain enabled 3 When Auto Negotiation is enabled these bits can be written but will be ignored by the PHY Far End Fault Auto Negotiation provides a remote fault capability for detecting asymmetric link failure Since 100Base FX systems do not use Auto Negotiation an alternative in band signaling scheme Far End Fault is used to sig nal remote fault conditions Far End Fault is a stream of 63 consecutive 1 followed by one logic 0 This pattern is repeated three times A Far End Fault will be sig naled under three conditions 1 when no activity is re ceived from the link partner 2 when the clock recovery circuit detects signal error or PLL lock error and 3 when the management entity sets the transmit FEF bit MII Register 21 bit 7
46. O Su w met leet moder amne ce mrs 41 Industrial ly Rated epee PubMed ey 41 DC CHARACTERISTICS41 SWITCHING WAVEFORMS 43 Key to Switching 43 SWITCHING 5 5 46 System Clock 46 MEI auod stt ecd 46 Management Signals 1 47 M 48 100 Mbps Transmit Timing 2 48 100 Mbps Receive 0 2 1 50 10 Mbps Transmit Timing 4 4 52 10 Mbps Receive 0 1 1 54 GPSlSignals 2 ieu sete he Re etd seu tpa uL mier ADS EE UE 56 10 Mbps GPSI Receive 0 56 10 Mbps GPSI Receive 0 2 56 10 Mbps GPSI Collision 0 1 57 10 Mbps GPSI Transmit 0
47. TX CLK runs at 10 MHz When the cable is unplugged 10TXCLK ceases operation The MII pins that relate to 7 wire GPSI mode are shown in Table 1 The unused input pins in this mode should be tied to ground through a 1 resistor The RPTR pin must be connected to GND Table 1 MII Pins That Relate to 10 Mbps 7 Wire GPSI Mode PRELIMINAR Y MII Pin Name 7 Wire GPSI RX ER Not used CRS 10CRS Carrier Sense Detect Pin Name 7 Wire GPSI TX_CLK 10TXCLK Transmit Clock TXD O 1OTXD Transmit Serial Data Stream TXD 3 1 Not used TX_EN 10TXEN Transmit Enable TX_ER Not used RX_CLK 10RXCLK Receive Clock RXD 0 10RXD Receive Serial Data Stream RXD 3 1 Not used COL 10COL Collision Detect Note CRS ends one and one half bit times after the last data bit The effect is one or two dribbling bits on every packet All MACs truncate packets to eliminate the dribbling bits The only noticeable effect is that all CRC errors are recorded as framing errors Use the TECH SEL 2 0 to select the desired 10BASE T operation For example to auto negotiate between Full Duplex and Half Duplex at 10 Mbps set ANEG 1 and TECH 2 0 101 5B Symbol Mode The purpose of the 5B Symbol mode is to provide a way for the MAC to do the 4B 5B encoding decoding and scrambling descrambling in 100 Mbps operation This is useful in MAC similar to the Intel DEC 21143 MAC In 10
48. X ras x T TX_CLK 10TXCLK PCSBP_CLK Am79C874 EQVCC ADPVCC LEDDPX LEDTXB LEDSPD TJLEDTXA CLK25EN ANEGA TECH SEL O TECH SEL 1 TECH SEL 2 CRVVCC CRVGND OGND2 OVDD2 LEDLNK LED 10LNK LED PCSBP SD LEDTX LEDBTB LEDRX LEDSEL LEDCOL SCRAM EN LEDSPD OJ LEDBTA FX SEL INTR CRS 10CRS COL 10COL 222351 2 ORDERING INFORMATION Standard Products PRELIMINAR Y AMD standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of the elements below AM79C874 Valid Combinations AM79C874 VC AM79C874 ALTERNATE PACKAGING OPTION Not Applicable TEMPERATURE RANGE C Commercial 0 to 70 Industrial 40 to 85 PACKAGE TYPE V 80 Pin Thin Plastic Quad Flat Pack 80 SPEED OPTION Not Applicable DEVICE NUMBER DESCRIPTION Am79C874 NetPHY 1LP Low Power 10 100 TX FX Ethernet Transceiver Valid Combinations Valid Combinations list configurations planned to be sup ported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations Am79C874 PRELIMINAR Y RELATED AMD PRODUCTS
49. X inputs when in MLT 3 mode only The RX input is guaranteed to assert internal signal detect for any valid peak to peak input signal greater than MIN 3 Applies to RX inputs when MLT 8 mode only The RX input is guaranteed to de assert internal signal for any peak to peak signal less than Vspp MAX Applies to FXT and FXT outputs only Valid only when in PECL mode Applies to TX differential outputs only Valid only when in the MLT 3 mode is the ratio of the magnitude of TX in the positive direction to the magnitude of TX in the negative direction Only valid for TX output when in the 10BASE T mode An lg value applies to LED pins N A Applies to all output pins the MII port 10 loz applies to all high impedance output pins and all bi directional pins For COL and CRS parameters loz limits are up to 40 and IOZL up to 500 uA 11 7596 activity means 25 IPG and 75 data 100 activity means minimum IPG 12 Applies to digital inputs and all bidirectional pins These pins may have internal pull up or pull down resistors RX limits up to 1 0 mA max for I and 1 0 mA for lj XTL limits up to 6 0 mA for ly and 6 0 mA for lj External pull up pull down resistors affect this value 13 Parameter not measured 42 Am79C874 PRELIMINARY SWITCHING WAVEFORMS Key to Switching Waveforms WAVEFORM Ju etc INPUTS Must
50. ace to the MAC i e DECPC 21143 are located on pins 14 to 19 The sig nals are defined as follows 10RXDx are the differential receive outputs to the MAC 10TXD are the differential transmit inputs from the MAC 10TXD 10TXD are the differential pre emphasis transmit outputs from the MAC When left unconnected the device operates in MII or GPSI mode ISODEF Isolate Default Input Pull Down This pin is used when multiple PHYs are connected to a single MAC When it is pulled high via a 10 resis tor the interface will be high impedance The status of this pin will be latched into MII Register 0 bit 10 after reset When this pin is left unconnected the default condition of the MII output pins are in the high impedance state ISO Isolate Input Pull Down The output pins will become high impedance when ISO is pulled high via a 10 kO resistor However the MII input pins will still respond to data This allows multiple PHYs to be attached to the same interface The same isolate condition can also be achieved by assert ing MII Register 0 bit 10 In repeater mode ISO will not tri state the CRS pin When this pin is left unconnected the MII output pins are not in the high impedance state Am79C874 11 REFCLK Clock Input Input Pull Down This pin connects to a 25 MHz 50 ppm clock source with a 4096 to 60 duty cycle When a crystal input is used this pi
51. and out to the driver This loopback is used to check the device s connection on the media side and the operation of its internal adaptive equalizer phase locked loop and digital wave shape synthesizer During remote loopback signal detect SD output is forced to logic zero Note that remote loopback operates only in 100BASE TX mode Am79C874 PRELIMINAR Y External loopback can be accomplished using an ex ternal loopback cable with TX connected to RX Ex ternal loopback works for both 10 Mbps and 100 Mbps after setting Register O bit 8 to force full duplex and bit 13 to set the speed Reset The NetPHY 1LP device can be reset in the three fol lowing ways 1 During initial power on with internal power on reset circuit 2 At hardware reset A logic low signal of 10 ms pulse width applied to the RST pin 3 At software reset Write a 1 to MII Register 0 bit 15 LED Port Configuration The NetPHY 1LP device has several pins that are used for both device configuration and LED drivers These pins set the configuration of the device on the rising edge of RST and thereafter indicate the state of the re spective port See Table 4 for standard LED selections and Table 5 for advanced LED selections The polarity of the LED drivers Active LOW Active HIGH is set at the rising edge of RST If the pin is LOW at the rising edge of RST it becomes an active HIGH driver If itis HIGH at the rising edge of RST
52. as long as link is established Auto Negotiation and Miscellaneous Functions Auto Negotiation The NetPHY 1LP device has the ability to negotiate its mode of operation over the twisted pair using the Auto Negotiation mechanism defined in Clause 28 of the IEEE 802 3u specification Auto Negotiation may be enabled or disabled by hardware ANEGA 56 software MII Register 0 bit 12 control see Table 3 The NetPHY 1LP device will automatically choose its mode of operation by advertising its abilities and com paring them with those received from its link partner whenever Auto Negotiation is enabled The content of MII Register 4 is sent to the link partner during Auto Negotiation coded in Fast Link Pulses FLPs MII Register 4 bits 8 5 reflect the state of the TECH SEL 2 0 pins after reset After reset software can change any of these bits from 1 to 0 and back to 1 but not from 0 to 1 via the man agement interface Therefore hardware settings have priority over software A write to Register 4 does not cause the device to restart Auto Negotiation When Auto Negotiation is enabled the NetPHY 1LP device sends FLP during the one of the following con ditions a power on b link loss or c restart com mand At the same time the device monitors incoming data to determine its mode of operation When the de vice receives a burst of FLPs from its link partner with three identical link code words ignori
53. ation ratio and slicer thresholds are set by the on chip band gap reference In 100BASE FX mode signal will be received through a PECL receiver and directly passed to the clock re covery for data clock extraction In FX mode the scrambler descrambler cipher will be bypassed 4B 5B Encoder Decoder The 100 Mbps process in the NetPHY 1LP device uses the 4B 5B encoding scheme as defined in IEEE 802 3 Section 24 This scheme converts between raw data on the MII and encoded data on the media pins The en coder converts raw data to the 4B 5B code It also in serts the stream boundary delimiters J K and T R at the beginning and end of the data stream as appro priate The decoder converts between encoded data on the media pins and raw data on the It also de tects the stream boundary delimiters to help determine the start and end of packets The code group mapping is defined in Table 2 The 4B 5B encoding is bypassed when MII Register 21 bit 1 is set to 1 or the PCSBP pin pin 1 is strapped high Scrambler Descrambler The 4B 5B encoded data has repetitive patterns which result in peaks in the RF spectrum large enough to keep the system from meeting the standards set by regulatory agencies such as the FCC The peaks in the radiated signal are reduced significantly by scrambling the transmitted signal Scramblers add the output of a random generator to the data signal The resulting sig nal has fewer repetitive data p
54. atterns After reset the scrambler seed in each port will be set to the PHY address value to help improve the EMI per formance of the device The scrambled data stream is descrambled at the re ceiver by adding it to the output of another random gen erator The receiver s random generator uses the same function as the transmitter s random generator In 100BASE TX mode all 5 bit transmit data streams are scrambled as defined by the TP PMD Stream PRELIMINAR Y Cipher function in order to reduce radiated emissions on the twisted pair cable The scrambler encodes a plain text NRZ bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function X n X n 11 X n 9 modulo 2 The scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range thus eliminating peaks at a single fre quency When MII Register 21 bit 2 is set to 1 the data scrambling function is disabled and the 5 bit data stream is clocked directly to the device s PMA sublayer Link Monitor Signal levels are detected through a squelch detection circuit A signal detect SD circuit following the equal izer is asserted high whenever the peak detector senses a post equalized signal with a peak to ground voltage level larger than 400 mV This is approximately 40 percent of the normal signal voltage level In addi tion the energy level must be sustained longer than 2 ms in
55. be Steady May Change from H to L May Change from L to H Don t Care Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing State Unknown Center Line is High Impedance Off State KS000010 PAL a RX 9 9 Z m Um 222351 10 Figure 8 MLT 3 Receive Input Am79C874 43 PRELIMINARY 4990 4990 lt Isolation Transformer TX O 100 Q 2 Chassis Ground 222351 11 Figure 9 MLT 3 and 10BASE T Test Load with 1 1 Transformer Ratio TX Isolation Transformer TX O 100 Q 2 Chassis Ground 222351 12 Figure 10 MLT 3 10BASE T Test Load with 1 25 1 Transformer Ratio 44 Am79C874 PRELIMINARY NOUT 22235 13 Figure 11 100BASE TX Waveform VTX10NE TX 10BASE T 22235l 14 0 Figure 12 10BASE T Waveform With 1 1 Transformer Ratio Vpp 82 5 Q 69 Q Pin 1300 183 0 222351 15 Figure 13 PECL Test Loads Am79C874 45 SWITCHING CHARACTERISTICS Note Parametric values are the same for commercial devices and industrial devices System Clock Signal PRELIMINAR Y
56. d PRELIMINAR Y directly to a standard transformer External filtering modules are not needed Twisted Pair Receive Process In 10BASE T mode the signal first passes through a third order Elliptical filter which filters all the noise from the cable board and transformer This eliminates the need for a 10BASE T external filter A Manchester de coder and a Serial to Parallel converter then follow to generate the 4 bit nibble in MII mode RX ports are differential twisted pair receivers When properly terminated each RX port meets the electri cal requirements for 10BASE T receivers as specified in IEEE 802 3 Section 14 3 1 3 Each receiver has in ternal filtering and does not require external filter mod ules or common mode chokes Signals appearing at the RX differential input pair are routed to the internal decoder The receiver function meets the propagation delays and jitter requirements specified by the 10BASE T standard The receiver squelch level drops to half its threshold value after un squelch to allow reception of minimum amplitude sig nals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions Twisted Pair Interface Status The NetPHY 1LP transceiver will power up in the Link Fail state The Auto Negotiation algorithm will apply to allow it to enter the Link Pass state A link pulse detec tion circuit constantly monitors the RX pins for the presence of valid
57. d NetPHY are trademarks of Advanced Micro Devices Inc Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies 60 Am79C874
58. data path for 100 Mbps the NetPHY 1LP transceiver receives an MLT 3 data stream from the network For 100BASE TX it then recovers the clock from the data stream de serializes the data stream and descrambles decodes the data stream 5 4 be fore presenting it at the MII interface 16 Am79C874 PRELIMINAR Y 5903 3 3 V MT RJ 5 RD 3 3 Am79C874 1 NetPHY 1LP 690 2 2 690 1 lt ra TESTO FXR lt TE 4 RD TEST3 SDI 350 1830 2 2183 Q 3 3 V 2 130 27130 01130 60 2690 e 222351 3 Figure 1 FXT FXRz Termination for 100 5 For 100BASE FX operation the NetPHY 1LP device receives a PECL data stream from the fiber optic trans ceiver and decodes that data stream The 100BASE X block consists of the following sub blocks Transmit Process Receive Process 4B 5B Encoder and Decoder Scrambler Descrambler Link Monitor Far End Fault Generation and Detection amp Code Group Generator MLT 3 encoder decoder with Adaptive Equalization Baseline Restoration Clock Recovery Transmit Process The transmit process generates code groups based on the transmit control and data signals on the MII This process is also responsible for frame encapsulation into a Physical Layer Stream generating the collision signal based on whether a carrie
59. defined by TP PMD The amplitude and phase distortion from the cable will cause intersymbol interference ISI which makes clock and data recovery impossible The adaptive equalizer is made by closely matching the inverse transfer func tion of the twist pair cable This is a variable equalizer that changes its equalizer frequency response in ac cordance to cable length The cable length is estimated based on comparisons of incoming signal strength against some of the known cable characteristics The equalizer has a monotonical frequency response and tunes itself automatically for any cable length to com pensate for the amplitude and phase distortion incurred from the cable Baseline Wander Compensation The 100BASE TX data stream is not always DC bal anced The transformer blocks the DC component of the incoming signal thus the DC offset of the differen tial receive inputs can wander The shift in the signal levels coupled with non zero rise and fall times of the serial stream can cause pulse width distortion This creates jitter and a possible increase in error rates Therefore a DC restoration circuit is needed to com pensate for the attenuation of the DC component The NetPHY 1LP device implements a patent pending DC restoration circuit Unlike the traditional im plementation it does not need the feedback informa tion from the slicer and clock recovery circuit This not only simplifies the system circuit design but also eli
60. e Rising of CLK10 16 ns tMRCRD10 RXD 3 0 DV ER Valid After the Rising Edge of 12 ns tMRECRL10 End of Packet to CRS LOW 130 190 ns tMRECOL10 End of Packet to COL LOW 125 185 ns Packet to RXD 3 0 DV ER De Asserting Going 120 140 tMRPCRH10 gt CRS 7 0 gt COL RX tMRCHR10 tMRRC10 RXD 3 0 RX DV RX ER Figure 24 10 Mbps MII Receive Start of Packet Timing 22235l 26 54 Am79C874 PRELIMINARY 10 Mbps MII Receive Timing Continued lt tMRECRL10 gt CRS lt tMRECOL10 COL RX CLK M CR SM 2 22 2 I AMRERL10 gt RXD 3 0 E X X X Figure 25 10 Mbps MII Receive End of Packet Timing 222351 27 Am79C874 55 PRELIMINARY GPSI Signals 10 Mbps GPSI Receive Timing Symbol Parameter Description Min Max Unit tecp 10CRS HIGH To First Bit Of Data 750 850 ns Rising Edge to 10RXD 10CRS 45 55 ns Bit Cell 1 Bit Cell 2 Bit Cell 3 Bit Cell 4 Bit Cell 5 RX y 4 1 0 1 0 1 tGRCD 4 10CRS X 10RXCLK lt tGRCD 10RXD 222351 28 Figure 26 GPSI Recei
61. e on the board Extra care in the layout to control capacitance on the board is required Power Down Most of the NetPHY 1LP device can be disabled via the Power Down bit MII Register 0 bit 11 Setting this bit will power down the entire device with the exception of the MDIO MDC management circuitry Unplugged The TX output driver limits the drive capability if the re ceiver does not detect a link partner within 4 seconds This prevents wasted power If the receiver detects the absence of a link partner the transmitter is limited to transmitting normal link pulses Any energy detected by the receiver enables full transmit and receive capa bilities The power savings is most notable when the portis unconnected Typical power drops to one third of normal Idle Wire This can be achieved by writing to MII Register 16 bit 0 During this mode if there is no data other than idles coming in the receive clock will turn off to save power for the attached controller RX_CLK will re sume operation one clock period prior to the assertion of RX_DV The receive clock will again shut off 64 clock cycles after RX_DV gets deasserted Typical power savings of 100 mW can be realized in some MACs Am79C874 27 PHY CONTROL AND MANAGEMENT BLOCK PCM BLOCK Register Administration for 100BASE X PHY Device The management interface specified in Clause 22 of the IEEE 802 3u standard provides for a simple two
62. ed Write as 0 ignore when read RW 0 1 Disable 10BASE T SQE testing 16 11 SQE Test Inhibit 0 Enable 10BASE T SQE testing A COL pulse is generated RW 0 following the completion of a packet transmission 16 10 10BASE T 1 Enable normal loopback in 10BASE T mode RW 1 Loopback 0 Disable normal loopback in 10BASE T mode When GPIO 1 DIR bit is set to 1 this bit reflects the value of the 16 9 GPIO 1 Data GPIO 1 pin When GPIO 1 DIR bit is set to 0 the value of this bit RW 0 will be presented on the GPIO 1 pin 1 pin is an input 16 8 GPIO 1 DIR RW 1 0 GPIO 1 pin is an output When GPIO 0 DIR bit is set to 1 this bit reflects the value of the 16 7 GPIO 0 Data GPIO 0 pin When GPIO 0 DIR bit is set to 0 the value of this bit RW 0 will be presented on the GPIO 0 pin 1 GPIO 0 pin is an input 16 6 GPIO 0 DIR 2 RW 1 0 GPIO 0 pin is an output 16 5 Auto polarity 1 Disable auto polarity detection correction RW 0 Disable 0 Enable auto polarity detection correction When Register 16 5 is set to 0 this bit will be set to 1 if reverse polarity is detected on the media Otherwise it will be 0 16 4 Reverse Polarity When Register 16 5 is set to 1 writing a 1 to this bit will reverse RW 0 the polarity of the transmitter Note Reverse polarity is detected either through eight inverted NLPs or through a burst of an inverted FLP 16 3 1 Reserved Write as 0 ignore when read RO 0 Writing a 1 to thi
63. ed twisted pair operation without requiring external filters or chokes The NetPHY 1LP device can use 1 1 isolation transformers or 1 25 1 isolation transformers 1 25 1 isolation transformers provide 20 lower transmit power consumption A PECL interface is available for 100BASE FX applications Interface to the Media Access Controller MAC layer is established via the standard Media Independent Inter face MII a 5 bit symbol interface or a 7 wire GPSI B Supports 1 1 or 1 25 1 transmit transformer Using a 1 25 1 ratio saves 20 transmit power consumption No external filters or chokes required B Waveshaping no external filter required B Full and half duplex operation with full featured Auto Negotiation function B LED indicators Link TX activity RX activity Collision 10 Mbps 100 Mbps Full or Half Duplex MDIO MDC operates up to 25 MHz Automatic Polarity Detection Built in loopback and test modes Single 3 3 V power supply with 5 V I O tolerance 12 mm x 12 mm 80 pin TQFP package Support for industrial temperature 40 to 85 interface Auto Negotiation determines the network speed and full or half duplex operation Automatic po larity correction is performed during Auto Negotiation and during 10BASE T signal reception Multiple LED pins are provided for front panel status feedback One option is to use two bi color LEDs to show when the device is in 100BASE TX or 10BASE T mode by illuminat
64. gister 5 33 Table 16 Auto Negotiation LInk Partner Ability Register in Next Page Format Register 5 33 Table 17 Auto Negotiation Expansion Register Register 34 Table 18 Auto Negotiation Next Page Advertisement Register Register 7 35 Table 19 Miscellaneous Features Register Register 16 36 Table 20 Interrupt Control Status Register Register 17 37 Table 21 Diagnostic Register Register 18 37 Table 22 Power Loopback Register Register 19 38 Table 23 Mode Control Register Register 21 39 Table 24 Disconnect Counter Register 23 40 Table 25 Receive Error Counter Register Register 24 40 8 Am79C874 PIN DESIGNATIONS Listed by Pin Number PRELIMINAR Y Name 1 PCSBP 21 MDIO 41 COL 10COL 61 RPTR 2 ISODEF 22 MDC 42 CRS 10CRS 62 TEST3 SDI 3 ISO 23 RXD 3 43 INTR 63 RX 4 TGND1 24 RXD 2 44 SEL 64 RX 5 REFCLK 25 RXD 1 45 SCAM EH 65 EQGND 6 CLK25 26 RXD 0 40RXD 46 LEDRX LEDSEL 66 TESTO FXR 7 BURN 27 VDD1 47 LEDTX
65. he ISO pin is enabled RX ER RXD 4 Receive Error Output High Impedance When RX ER is active high it indicates an error has been detected during frame reception This pin becomes the highest order bit of the receive 5 bit code group in PCS bypass PCSBP HIGH mode This output is ignored in 10BASE T operation 10 Am79C874 PRELIMINAR Y TX ER TXD 4 Transmit Error Input When TX ER is asserted it will cause the 4B 5B en coding process to substitute the transmit error code group H for the encoded data word This pin becomes the higher order bit of the transmit 5 bit code group in PCS bypass PCSBP HIGH mode This input is ignored in the 10BASE T operation TX CLKAOTXCLK PCSBPCLK Transmit Clock Output High Impedance A free running clock which provides timing reference for TX EN TX ER and TXD S3 0 signals It is 25 MHz in 100BASE TX FX and 2 5 MHz in 10BASE T When 7 wire GPSI mode is enabled this pin will pro vide a 10 MHz transmit clock for 10BASE T operation When the cable is unplugged the 10TXCLK ceases operation When working in PCSBP mode this pin will provide a 25 MHz clock for 100BASE TX operation and 20 MHZ clock for 10BASE T operation TX CLK is high imped ance when the ISO pin is enabled TX ENAOTXEN Transmit Enable Input The TX EN pin is asserted by the MAC to indicate that data is present on TXD 3 0 When 7 wire 10BASE T mode is enabled this pin is the transmit enable signal TXD 3 1
66. igure 31 GPSI Transmit 10TXCLK and 10TXD Timing 58 Figure 32 Test Load for 10RXD 10CRS 10RXCLK 10TXCLK and 10COL 58 List of Tables Table 1 MII Pins That Relate to 10 Mbps 7 Wire GPSI Mode 16 Table 2 Code Group Mapping 1 19 Table 3 Speed and Duplex Capabilities 24 Table 4 Standard LED Selections 2 25 Table 5 Advanced LED Selections 1 1 26 Table 6 Clause 22 Management Frame Format 28 Table 7 PHY Address Setting Frame Structure 28 Table 8 Register Summary 29 Table 9 Legend for Register Table 29 Table 10 MII Management Control Register Register 0 30 Table 11 MII Management Status Register Register 1 31 Table 12 PHY Identifier 1 Register Register 2 31 Table 13 PHY Identifier 2 Register Register 3 32 Table 14 Auto Negotiation Advertisement Register Register 4 32 Table 15 Auto Negotiation Link Partner Ability Register in Base Page Format Re
67. ing Half or Full Duplex by the color and when data is being received by blinking Individual LEDs can indicate link detection collision detection and data being transmitted The NetPHY 1LP device needs only one external 25 MHz oscillator or crystal because it uses a dual speed clock synthesizer to generate all other required clock domains The receiver has an adaptive equalizer DC restoration circuit for accurate clock data recovery from the 100BASE TX signal The NetPHY 1LP device is available in the commercial 0 to 70 C or industrial 40 C to 85 C tempera ture ranges The industrial temperature range is well suited to environments such as enclosures with re stricted air flow or outdoor equipment 2 A Publication 22235 Rev l 0 Refer AMD s Website www amd com for the latest information issue Date April 2001 BLOCK DIAGRAM MAC MII Data Interface lt lt MDC MDIO PRELIMINARY Am79C874 PCS PMA TP PMD 100 4 Clock Recovery gt MLT 3 gt TX Carrier Detect Link Monitor BLW p 8 4B 5B Signal Detect Stream Cipher 100RX TX A 25 MHz Interface 10TX 10RX Transformer lt lt RX Control Status 20 MHz Y Y RX Serial Management PLL Ge
68. is 5 0 V Minor edits The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi cations and product descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intel lectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice Trademarks Copyright 1999 2000 2001 Advanced Micro Devices Inc All rights reserved AMD the AMD logo and combinations thereof PCnet PRO an
69. k re covery MAUs and transceiver functions The NetPHY 1LP transceiver receives 10 Mbps data from the MAC switch or repeater across the MII at 2 5 million nibbles per second parallel or 10 million bits per second serial It then Manchester encodes the data before transmission to the network Refer to Figure 4 for the 10BASE T transmit and re ceive data paths Clock Data Clock Data Manchester Decoder Manchester Encoder Squelch Circuit Loopback Register 0 moe TX RX TX Driver 222351 6 Figure 4 10BASE T Transmit Receive Data Paths Twisted Pair Transmit Process In 10BASE T mode Manchester code will be gener ated by the 10BASE T core logic which will then be synthesized through the output waveshaping driver This will help reduce any EMI emission eliminating the need for an external filter Data transmission over the 10BASE T medium requires use of the integrated 10BASE T MAU and uses the differential driver cir cuitry on the pins TXx is a differential twisted pair driver When properly terminated TX meets the transmitter electrical re quirements for 10BASE T transmitters as specified in IEEE 802 3 Section 14 3 1 2 The load is a twisted pair cable that meets IEEE 802 3 Section 14 4 The TX signal is filtered on the chip to reduce har monic content per Section 14 3 2 1 10BASE T Since filtering is performed in silicon TX can be connecte
70. link pulses In the Link Pass state re ceive activity which passes the pulse width amplitude requirements of the RX inputs cause the PCS Control block to assert Carrier Sense CRS signal at the MII interface Collision Detect Function Simultaneous activity presence of valid data signals from both the internal encoder transmit function and the twisted pair RX pins constitutes a collision thereby causing the PCS Control block to assert the COL pin at the MII Collisions cause the PCS Control block to assert the Carrier Sense CRS and Collision COL signals at the MII In the Link Fail state this block would cause the PCS Control block to de assert Carrier Sense CRS and Collision COL Jabber Function The Jabber function inhibits the 10BASE T twisted pair transmit function of the NetPHY 1LP transceiver device if the TX circuits are active for an excessive period 20 150 ms This prevents one port from disrupting the network due to a stuck on or faulty transmitter condi tion If the maximum transmit time is exceeded the data path through the 10BASE T transmitter circuitry is disabled although Link Test pulses will continue to be 22 Am79C874 PRELIMINAR Y sent The PCS Control block also asserts the COL pin at the MII and sets the Jabber Detect bit in MII Register 1 Once the internal transmit data stream from the MENDEC stops an unjab time of 250 750 ms will elapse before this block causes the PCS Control block t
71. m inates any random systematic offset on the receive path In 10BASE T and 100Base FX modes the base line wander correction circuit is not required and there fore will be bypassed 20 Am79C874 RJ45 Connector 470 pF 2 kV 222351 5 PRELIMI Isolation b Transformer with common mode Note 1 Note 1 chokes 1 1 or 1 25 1 TX C TX C 0 1 uF Ji 750 750 7503 e RX Note 2 2 0 1 uF SS 750 5 e 4 0 1 uF chassis ground Notes 1 49 90 if a 1 1 isolation transformer is used or 78 1 Q if a 1 25 1 isolation transformer is used 2 49 9 is normal but 54 9 can be used for extended cable length operation Figure 3 and RX Termination for 100BASE TX and 10BASE T Clock Data Recovery The equalized MLT 3 signal passes through a slicer cir cuit which then converts it to NRZI format The Net PHY 1LP device uses an analog phase locked loop APLL to extract clock information from the incoming NRZI data The extracted clock is used to re time the data stream and set the data boundaries The transmit clock is locked to the 25 MHz clock input while the re ceive clock is locked to the incoming data streams When initial lock is achieved the APLL switches to lock to the data stream extracts a 125 MHz clock from it and use that for bit framing to recover data The recovered 125 MHz
72. n LH Latch high until clear Am79C874 29 PRELIMINAR Y MII Management Control Register Register 0 Table 10 MII Management Control Register Register 0 Read Reg Bit Name Description Write Default 1 PHY reset 0 15 Reset 0 Normal operation RW SC 0 This bit is self clearing 1 Enable loopback mode This will loopback TXD to RXD thus it will ignore all the activity on the cable media During loopback a 0 14 Loopback 10 Mbps link is sent to the link partner Register 21 bit 14isforced RW 0 0 Disable Loopback mode Normal operation 1 100 Mbps 0 10 Mbps This bit will be ignored if Auto Set by 0 13 Speed Select Negotiation is enabled 0 12 1 RW TECH 2 0 Refer to Table 3 to determine when this bit can be changed pins 1 Enable auto negotiate process overrides 0 13 and 0 8 8 0 12 Auto Neg 0 Disable auto negotiate process Mode selection is controlled via RW ne e Enable bit 0 8 0 13 or through TECH 2 0 pins pin Refer to Table 3 to determine when this bit can be changed 1 Power down The NetPHY 1LP device will shut off all blocks except for MDIO MDC interface Setting PWRDN pin to high will 0 11 Power Down achieve the same result RW 0 0 Normal operation 1 Electrically isolate the PHY from However PHY is still able to respond to MDC MDIO The default value of this bit depends on Set by 0 10 lsolate ISODEF
73. n should be pulled low via a 1 resistor Crystal Inputs Analog Input These pins should be connected to a 25 MHz crystal The crystal should be parallel resonant and have a fre quency stability of 100 ppm and a frequency tolerance of 50 ppm REFCLK Pin 5 should be pulled low when the crystal is used as a clock source These pins may be left unconnected when REFCLK is used as a clock source CLK25 25 MHz Clock Output When the CLK25EN pin is pulled low the CLK25 pin provides a continuous 25 MHz clock to the MAC BURN Test Enable Input Pull Down When pulled high via 10 resistor this pin forces the NetPHY 1LP device into Burn in mode for reliability assurance control When left unconnected the device operates normally TEST2 Test Output Analog Output When BURN pin 7 is pulled high this pin serves as a test mode output monitor pin TEST2 can be left unconnected when the device is operating RST Reset Input Pull Up A LOW input forces the NetPHY 1LP device to a known reset state The chip can also be reset through internal power on reset or Register 0 bit 15 PWRDN Power Down Input Pull Down If this pin is pulled high via a 10 resistor on the rising edge of reset the device will power down the analog modules and reset the digital circuits However the de vice will still respond to MDC MDIO data The same power down state can also be achieved through the MII Regis
74. nchro nously with respect to CLK For each period which RX DV is asserted RXD 3 0 are transferred from the PHY to the MAC reconciliation sublayer B RX CLK receive clock output to the MAC reconcil iation sublayer is a continuous clock during LINK only that provides the timing reference for the transfer of the RX DV RXD and RX ER signals B DV receive data valid input from the PHY to in dicate the PHY is presenting recovered and de coded nibbles to the MAC reconciliation sublayer To interpret a receive frame correctly by the recon ciliation sublayer RX DV must encompass the frame starting no later than the Start of Frame de limiter and excluding any End Stream delimiter B RX ER receive error transitions synchronously with respect to RX CLK RX ER will be asserted for 1 or more clock periods to indicate to the recon ciliation sublayer that an error was detected some where in the frame being received by the PHY CRS carrier sense is asserted by the PHY when either the transmit or receive medium is non idle and deasserted by the PHY when the transmit and receive medium are idle 7 Wire GPSI Mode 7 Wire GPSI mode uses the existing MII pins but data is transferred only on TXD 0 and RXD 0 This mode is used in a General Purpose Serial Interface GPSI configuration for 10BASE T If the GPIO 0 pin is LOW at the rising edge of reset then GPSI mode is selected For this configuration
75. nerator 25 MHz Auto Interface and Registers Test LED Control Negotiation PHYAD A 0 XTL XTL CLK TEST LED Drivers 222351 1 PRELIMINAR Y CONNECTION DIAGRAM PCSBP ISODEF ISO TGND1 REFCLK CLK25 BURN_IN RST PWRDN PLLVCC PLLGND OGND1 OVDD1 PHYAD A 1 ORXD PHYAD 3 10RXD PHYAD 2 10TXD PHYAD 1 10TXD PHYAD O 1OTXD GPIO O 1 OTXD 7Wire GPIO 1 TP125 c c Nr me 555 oo O 2lh0 RLERZ ES gt gt x x O E E uu x x u u u O x x utu 80 79 78 77 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Q Am79C874 NetPHY 1LP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ipea MENS Ea lO Cy O xxx 5 ccc t nuccctaon C C Cra gt e uu 22 zu O f gt lt gt lt gt lt
76. ng acknowledge bit it stores these code words in MII Register 5 and waits for the next three identical code words Once the device detects the second code word it will configure itself to the highest technology that is common to both ends The technology priorities are 1 100BASE TX full duplex 2 100BASE TX half duplex 3 10BASE T full duplex and 4 10BASE T half duplex Parallel Detection The parallel detection circuit is enabled as soon as ei ther 10BASE T idle or 100BASE TX idle is detected The mode of operation gets configured based on the technology of the incoming signal The NetPHY 1LP device can also check for a 10BASE T NLP or 100BASE TX idle symbol If either is detected the de vice automatically configures to match the detected op erating speed in half duplex mode This ability allows the device to communicate with legacy 10BASE T and 100BASE TX systems Am79C874 23 PRELIMINAR Y Table 3 Speed and Duplex Capabilities ANEGA Tech 2 Tech 1 Tech 0 Speed Duplex ANEG EN Hardwired on Board Changeable in MII Register 0 Capabilities ANEG 0 0 0 0 Yes Note 1 Yes Note 1 No All Capabilities 0 0 0 1 No No No 10HD 0 0 1 0 No No No 100HD 0 0 1 1 No No No 100HD 0 1 0 0 Yes Note 1 Yes Note 1 No All Capabilities 0 1 0 1 No No No 10FD 0 1 1 0 No No No 100FD 0 1 1 1 No No No 100FD 1 0 0 0 Yes Note 3 Yes
77. o de assert the COL indication and re enable the transmit circuitry When jabber is detected this block causes the PCS control block to assert the COL pin and allows the PCS Control block to assert or de assert the CRS pin to in dicate the current state of the RX pair If there is no re ceive activity on this block causes the PCS Control block to assert only the COL pin at the MII If there is RX activity this block causes the PCS Control block to assert both COL and CRS at the MII The Jab ber function can be disabled by setting MII Register 21 bit 12 Reverse Polarity Detection and Correction Proper 10BASE T receiver operation requires that the differential input signal be the correct polarity That is the RX line is connected to the RX input pin and the RX line is connected to the RX input pin Improper setup of the external wiring can cause the polarity to be reversed The NetPHY 1LP receiver has the ability to detect the polarity of the incoming signal and compen sate for it Thus the proper signal will appear on the MDI regardless of the polarity of the input signals The internal polarity detection and correction circuitry is set during the reception of the normal link pulses NLP or packets The receiver detects the polarity of the input signal on the first NLP It locks the polarity cor rection circuitry after the reception of two consecutive packets The state of the polarity correction circuitry is locked
78. ode of operation MII Mode The purpose of the MII mode is to provide a simple easy to implement connection between the MAC Rec onciliation layer and the PHY The MII is designed to make the differences between various media transpar ent to the MAC sublayer The MII consists of a nibble wide receive data bus a nibble wide transmit data bus and control signals to fa cilitate data transfers between the PHY and the Recon ciliation layer B TXD transmit data is a nibble 4 bits of data that are driven by the reconciliation sublayer synchro nously with respect to TX CLK For each TX CLK period which TX EN is asserted TXD 3 0 are ac cepted for transmission by the PHY B TX transmit clock output to the MAC recon ciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TX EN TXD and TX ER signals B TX EN transmit enable input from the MAC recon ciliation sublayer to indicate nibbles are being presented on the MII for transmission on the physi cal medium TX ER transmit coding error transi tions synchronously with respect to TX CLK If TX ER is asserted for one or more clock periods and TX EN is asserted the PHY will emit one or more symbols that are not part of the valid data de limiter set somewhere in the frame being transmit ted Am79C874 15 receive data is a nibble 4 bits of data that is sampled by the reconciliation sublayer sy
79. order for the signal detect to be asserted It gets de asserted approximately 1 ms after the energy level is consistently less than 300 mV from peak to ground The link signal is forced to low during a local loopback operation i e when MII Register 0 bit 14 Loopback is asserted and forced to high when a remote loopback is taking place i e when MII Register 21 bit 3 RPBK is set In 100BASE TX mode when no signal or an invalid sig nal is detected on the receive pair the link monitor will enter in the link fail state where only the scrambled idle code will be transmitted When a valid signal is de tected for a minimum period of time the link monitor will then enter the link pass state when transmit and re ceive functions are entered In 100BASE FX mode the external fiber optic receiver performs the signal energy detection function and com municates this information directly to the NetPHY 1LP device through the 501 pin 18 Am79C874 PRELIMINARY Table 2 Code Group Mapping MII TXD 3 0 Name PCS Code Group Interpretation 0000 0 11110 Data 0 0001 1 01001 Data 1 0010 2 10100 Data 2 0011 3 10101 Data 3 0100 4 01010 Data 4 0101 5 01011 Data 5 0110 6 01110 Data 6 0111 7 01111 Data 7 1000 8 10010 Data 8 1001 9 10011 Data 9 1010 A 10110 Data A 1011 B 10111 Data B 1100 11010 Data 1101
80. ound via a 10 resistor on the rising edge of reset Auto Negotiation is dis abled When this pin is left unconnected on the rising edge of reset Auto Negotiation is enabled Note that this pin acts in conjunction with Tech Sel 2 0 on the rising edge of reset Refer to Table 3 to determine the desired configuration for the device Note By using resistors to hard wire the TECH SEL 2 0 pins and the ANEGA pin using the MDC MDIO management interface pins becomes op tional The device s speed duplex and auto negotia tion capabilities are set via hardware If the management interface is used the registers cannot be set to a higher capability than the hard wired setting The highest capabilities are Full Duplex 100 Mbps and Auto Negotiation enabled Mode Input This pin should be tied to ground via 10 resistor if repeater mode is to be disabled When this pin is pulled high via a 10 kO resistor repeater mode will be en abled Repeater mode can also enabled via MII Regis ter 16 bit 15 LED Port Pins LEDRX LED SEL Receive LED LED Configuration Select Input Output Pull Up When this pin is pulled low via a 5 resistor on the rising edge of reset the advanced LED configuration is enabled If there is no pull down resistor present on the rising edge of reset the standard LED configuration is enabled After the rising edge of reset this pin controls the Re ceive LE
81. r is received simulta neously during transmission and generating the Carrier Sense CRS and Collision COL signals at the MII The transmit process is implemented in compliance with the transmit state diagram as defined in Clause 24 of the IEEE 802 3u specification The NetPHY 1LP device transmit function converts synchronous 4 bit data nibbles from the MII to a 125 Mbps differential serial data stream The entire opera tion is synchronous to 25 MHz clock and 125 MHz clock Both clocks are generated by an on chip PLL clock synthesizer that is locked to an external 25 MHz clock source In 100BASE FX mode the NetPHY 1LP device will by pass the scrambler The output data is an NRZI PECL signal This PECL level signal will then drive the Fiber transmitter Receive Process The receive path includes a receiver with adaptive equalization and DC restoration MLT 3 to NRZI con version data and clock recovery at 125 MHz NRZI to NRZ conversion Serial to Parallel conversion de scrambling and 5B to 4B decoding The receiver circuit starts with a DC bias for the differential RX inputs fol lows with a low pass filter to filter out high frequency noise from the transmission channel media An energy detect circuit is also added to determine whether there is any signal energy on the media This is useful in the power saving mode See the description in Power Am79C874 17 Savings Mechanisms section All of the amplific
82. r that the management data being received by the NetPHY 1LP device does not require a preamble REGISTER DESCRIPTIONS The following registers given in Table 8 are supported register addresses are in decimal Table 8 Register Summary Register Address in Decimal Description 0 MII Management Control Register 1 MII Management Status Register 2 PHY Identifier 1 Register 3 PHY Identifier 2 Register 4 Auto Negotiation Advertisement Register 5 Auto Negotiation Link Partner Ability Register 6 Auto Negotiation Expansion Register 7 Next Page Advertisement Register 8 15 Reserved 16 Miscellaneous Features Register 17 Interrupt Control Status Register 18 Diagnostic Register 19 Power Management amp Loopback Register 20 Reserved 21 Mode Control Register 22 Reserved 23 Disconnect Counter 24 Receive Error Counter 25 31 Reserved The Physical Address of the PHY is set using the pins defined as PHYAD 4 0 These input signals are strapped externally and sampled as when reset goes high The PHYAD pins can be reprogrammed via soft ware Serial Management Registers A detailed definition of each Serial Management regis ter follows The mode legend is shown in Table 9 Table 9 Legend for Register Table Type Description RW Readable and writable SC Self Clearing LL Latch Low until clear RO Read Only RC Cleared on the read operatio
83. ring local 21 14 Force Link 10 loopback RW 0 0 Normal Operation 1 Ignore link in 100BASE TX and transmit data Auto 21 13 Force Link 100 Negotiation must be disabled at this time pin 56 tied low RW 0 0 Normal Operation 21 12 Jabber Disabl 1 Disable Jabber function in PHY RW 0 abber Disable 0 Enable Jabber function in PHY 1 Enable 7 wire interface for 10BASE T operation This bit is 21 11 7 Wire Enable useful only when the chip is not in PCS bypass mode RW 0 0 Normal operation 1 Activity LED only responds to receive operation 0 Activity LED responds to receive and transmit operations for 21 10 CONF ALED Half Duplex LED responds to receive activity in Full Duplex RW 0 operation This bit should be ignored when Register 0 8 is set to 1 or during repeater mode operation 1 Select NetPHY 1LP device s Standard LED configuration _Set by 21 9 LED SEL RW LEDRX 0 Use the Advanced LED configuration LED SEL Set by 0 Enable far end fault generation and detection function TECH 2 0 21 8 FEF_DISABLE 1 Disable far end fault RW FX_SEL This bit should be ignored when FX mode is disabled pen Force FEF 21 7 This bit is set to force to transmit Far End Fault pattern RW 0 Transmit 21 6 RX ER ONT Full When Receive Error Counter is full this bit will be set to 1 RO RC 0 i 1 Disable Receive Error Counter 21 5 Disable BW 0 RX ER CNT 0 Enable Receive Error Counter 1 Disable
84. s bit will shut off RX_CLK when incoming data is not present and only if there is LINK present RX_CLK will resume activity one clock cycle prior to RX_DV going high and shut off 64 clock cycles after RX_DV goes low 16 0 Receive Clock RW 3 36 Am79C874 PRELIMINAR Y Interrupt Control Status Register Register 17 Table 20 Interrupt Control Status Register Register 17 Read Reg Bit Name Description Write Default 17 15 Jabber IE Jabber Interrupt Enable RW 0 17 14 Er IE Receive Error Interrupt Enable RW 0 17 13 Rx IE Page Received Interrupt Enable RW 0 17 12 PD Fault IE Parallel Detection Fault Interrupt Enable RW 0 17 11 Ack IE Link Partner Acknowledge Interrupt Enable RW 0 17 10 j Link Not OK IE Link Status Not OK Interrupt Enable RW 0 17 9 R Fault IE Remote Fault Interrupt Enable RW 0 17 8 ANeg Comp IE Auto Negotiation Complete Interrupt Enable RW 0 17 7 Jabber Int This bit is set when a jabber event is detected RC 0 17 6 Rx Er Int This bit is set when RX ER transitions high RC 0 47 5 This bit is set when a new page is received from link partner RC 0 during Auto Negotiation 17 4 PD Fault Int This bit is set for a parallel detection fault RC 0 17 3 LP Ack Int This bit is set when an FLP with the acknowledge bit set is RC 0 received 47 2 Link
85. t Refer to Table 4 and Figure 4 in the LED Port Configu ration section if the device is operating in the standard LED mode See Table 5 and Figure 5 if the device is op erating in the advanced LED mode Am79C874 13 Note If 7 Wire mode is chosen the polarity of the LED should be reversed and the cathode of the LED should be tied to ground LEDSPD O LEDBTA FX SEL 100 Mbps Speed LED Advanced LED Fiber Select Input Output Pull Up When this pin is pulled low via a 1 resistor the rising edge of reset the device will be enabled for 100BASE FX operation When no pull down resistor is present on the rising edge of reset the device will be enabled for 100BASE TX or 10BASE T operation When the standard LED configuration is enabled see LEDRX LEDSEL pin description this pin serves as the 100 Mbps speed LED A logic low level indicates 100 Mbps operation A logic high level indicates 10 Mbps operation Refer to Table 4 and Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED When the advanced LED configuration is enabled this pin works in conjunction with LEDTX LEDBTB pin 47 Refer to Table 5 and Figure 6 in the LED Port Configu ration section to determine the correct polarity of the bi directional LED LEDTX LEDBTB Transmit LED Advanced LED Output When the standard LED configuration is enabled see LEDRX LEDSEL pin description this pin serves as the transmit
86. tPHY 1LP device communicates with a re peater switch or MAC device through either the Media Independent Interface MII or the 10 Mbps 7 wire GPSI interface The NetPHY 1LP device consists of the following func tional blocks B MI Mode B 7 Wire GPSI Mode PCS Bypass 5B Symbol Mode 100BASE X Block including Transmit Process Receive Process 4 5 Encoder and Decoder Scrambler and Descrambler Link Monitor MLT 3 Adaptive Equalizer Baseline Wander Compensation Clock Data Recovery PLL Clock Synthesizer 10BASE T Block including Transmit Process Receive Process Interface Status Collision Detect Jabber Reverse Polarity Detection and Correction Auto Negotiation and miscellaneous functions in cluding Auto Negotiation Parallel Detection Far End Fault SQE Heartbeat Loopback Operation Reset B LED Port Configuration Power Savings Mechanisms including Selectable Transformer Power Down Unplugged Wire PHY Control and Management Modes of Operation The MII GPSI 5B Symbol interface provides the data path connection between the NetPHY 1LP transceiver and the Media Access Controller MAC repeater or switch The MDC and MDIO pins are responsible for communication between the NetPHY 1LP transceiver and the station management entity STA The MDC and MDIO pins can be used in any m
87. ter 0 bit 11 However the device will respond ac tivity on the PWRDN pin even when bit 11 is not set When left unconnected the device operates normally PHYAD A 0 PHY Address Input Output Pull Up These pins allow 32 configurable PHY addresses The PHYAD will also determine the scramble seed which helps to reduce EMI when there are multiple ports switching at the same time repeater switch applica PRELIMINAR Y tions Each pin should either be pulled low via 1 4 7 resistor set bit to zero or left unconnected set bit to 1 in order to achieve the desired PHY ad dress New address changes take effect after a reset has been issued or at power up In PCS bypass mode PHYAD 4 0 and GPIO 1 0 serves as 10BASE T serial input and output Note In GPSI mode the PHYAD pins must be set to addresses other than 00h GPIO 0 10TXD 7Wire General Purpose I O 0 Input Output Pull Up If this pin is pulled low via a 10 kQ resistor on the rising edge of reset the device will operate in 10BASE T 7 wire GPSI mode If this pin is left unconnected dur ing the rising edge of reset the device will operate in standard MII mode After the reset operation has completed this pin can function as an input or an output dependent on the value of GPIO 0 DIR MII Register 16 bit 6 If MII Register 16 bit 6 is set HIGH GPIO 0 is an input The input value on the GPIO 0 pin will be reflected in MII Register 16 bit
88. the watchdog timer in the decipher 21 4 DIS WDT 0 0 Enable watchdog timer 1 Enable remote loopback MDI loopback for 100BASE TX 21 3 EN RPBK RW 0 0 Disable remote loopback 1 Enable data scrambling Set by 21 2 EN SCRM 0 Disable data scrambling RW SCRAM EN When FX mode is selected this bit will be forced to 0 pin 1 Bypass PCS Set by 21 1 PCSBP RW 0 Enable PC PCSBP 1 FX mode selected 21 EX SEL Rw SEEDY 0 Disable FX mode FX SEL pin Am79C874 39 Disconnect Counter Register Register 23 PRELIMINAR Y Table 24 Disconnect Counter Register 23 Read Reg Name Description Write Default 23 15 0 DLOCK drop Count of PLL lock drop events RW 0000 counter Receive Error Counter Register Register 24 Table 25 Receive Error Counter Register Register 24 Read Reg Bit Name Description Write Default 24 15 0 RX ER counter Count of receive error events RW 0000 40 Am79C874 PRELIMINAR Y ABSOLUTE MAXIMUM RATINGS Storage 55 to 150 Ambient Temperature Under Bias 55 C to 150 Supply 0 5 V to 45 5 V Voltage Applied to any input pin 0 5 V to Vpp Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure Function ality at or above these limits is not implied
89. to synchronize MDIO data When management is not used this pin should be tied to ground INTR Interrupt Output High Impedance This pin is used to signal an interrupt to the MAC The pin will be forced high or low normally high impedance to signal an interrupt depending upon the value of the INTR LEVL bit MII Register 16 bit 14 The events which trigger an interrupt can be programmed via the Interrupt Control Register Register 17 TECH SEL 2 0 Technology Select Input Pull Up The Technology Select pins in conjunction with the ANEGA pin set the speed and duplex configurations for the device on the rising edge of reset These capa bilities are reflected in MII Register 1 and MII Register 4 Table 3 lists the possible configurations for the de vice If the input is listed as LOW the pin should be pulled to ground via a 10 kO resistor on the rising edge of reset If the input is listed as HIGH the pin can be left unconnected Note By using resistors to hard wire the TECH SEL 2 0 pins and the ANEGA pin using the MDC MDIO management interface pins becomes op tional The device s speed duplex and auto negotia tion capabilities are set via hardware If the management interface is used the registers cannot be set to a higher capability than the hard wired setting The highest capabilities are Full Duplex 100 Mbps and Auto Negotiation enabled ANEGA Auto Negotiation Ability Input Pull Up When this pin is pulled to gr
90. ve Timing Start Reception 10 Mbps GPSI Receive Timing Symbol Parameter Description Min Max Unit laRCD Rising Edge of 10RXCLK to 10RXD or 10CRS 45 55 ns 1 O Bit N 1 BitN 5 tocRs 10RXD 222351 29 Figure 27 GPSI Receive Timing End of Reception Last Bit 0 56 Am79C874 PRELIMINAR Y 10 Mbps GPSI Receive Timing Symbol Parameter Description Min Max Unit t Delay from RX going to 1 to the Rising Edge of 10RXCLK which 190 GDOFF clocks out the last bit of data on 10RXD laRCD Rising Edge of 10RXCLK to 10RXD or 10CRS 45 55 ns 222351 30 Figure 28 GPSI Receive Timing End of Reception Last Bit 1 10 Mbps GPSI Collision Timing Symbol Parameter Description Min Max Unit tacsciH Collision Start to 10COL HIGH 80 150 ns tacECLL Collision End to 10COL LOW 125 185 ns Collision Presence tGCSCLH tGCECLL 10COL 222351 31 Figure 29 GPSI Collision Timing Am79C874 57 PRELIMINARY 10 Mbps GPSI Transmit Timing Symbol Parameter Description Min Max Unit t Delay from the rising edge of the 10TXCLK which first clocks 240 360 s GTTX 10TXEN HIGH to toggling LOW 10TXCLK ff a 10 vo tGTTX 222351 32 Figure 30 GPSI Transmit Timing Start of Transmission 10 Mbps
91. y over the data line The bit rate of TX data is 125 Mbps The maximum frequency using NRZI is half of 62 5 MHz MLT 3 reduces the maximum frequency to 31 25 MHz A data signal stream following MLT 3 rules is illustrated in Figure 2 The data stream is 1010101 MLT 3 22235l 4 Figure 2 MLT 3 Waveform The TX drivers convert the NRZI serial output to MLT 3 format The RX receivers convert the received MLT 3 signals to NRZI The transmit and receive sig nals will be compliant with IEEE 802 3u Section 25 The required signals MLT 3 are described in detail in ANSI X3 263 1995 TP PMD Revision 2 2 1995 The NetPHY 1LP device provides on chip filtering Ex ternal filters are not required for either the transmit or PRELIMINAR Y receive signals The traces from the transformer to the NetPHY 1LP device should have a controlled imped ance as a differential pair of 100 ohms The same is true between the transformer and the RJ 45 connector The TX pins can be connected to the media via either 1 1 transformer or a 1 25 1 transformer The 1 25 1 ratio provides a 20 transmit power savings over the 1 1 ratio Refer to Figure 3 Adaptive Equalizer The NetPHY 1LP device is designed to accommodate a maximum cable length of 140 meters UTP 5 ca ble 140 meters of UTP CAT 5 cable has an attenuation of 31 dB at 100 MHz The typical attenuation of a 100 meter cable is 21 dB The worst case attenuation is around 24 26 dB

AMD Am79C874 NetPHY -1LP Low Power 10/100-TX/FX Ethernet Transceiver service manual

Contents

Download Pdf Manuals

Related Search

Related Contents