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lnfineon HYB18T1G400AF HYB18T1G800AF HYB18T1G160AF 1 Gbit DDR2 SDRAM

1. the device it does not represent an actual circuit implementation Note DM is a unidirectional signal input only but is internally loaded to match the load of the bidi rectional DQ and DQS signals Block Diagram 64Mbit x 4 I O x 4 Internal Memory Banks 128 Mbit x 4 Organisation with 14 Row 3 Bank and 12 Column External Addresses Page 10 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM o CK o CK cS T 0 9 o Co 5 WE W ES CAS 0 ES s RAS 9 5 Bank7 o 2 AE CK CK 5 Y eere e S DLL Mode 9117 Registers Y 99 4T gT 558116 A8 525 Data lilii y 5 e 1 16384 x256x32 8 lt F 8 Sense Amplifiers PE mE gt gt gt pas 4 5 a Generator N DQ0 DQ7 18 g l 8 Das gt pM 2 S VO x COLO 1 Input Das 8 5 DRM ie 3 Register ke o 005 A0 A13 TN 9 IZ 5 ask Logic Write Mask 1 1 Das BAO BA2 9
2. Symbol Function Symbol Function 13 Row Address Inputs DQS DQS Differential Data Strobes A0 A9 Column Address Inputs RDQS RDQS Differential Read Data Strobes BAO BA1 BA2 Bank Address Inputs VDD Supply Voltage Column Address Input mund A10 AP for Auto Precharge 55 cs Chip Select VDDQ Supply Voltage for DQ RAS Row Address Strobe VSSQ Ground for DQs CAS Column Address Strobe VDDL Supply Voltage for DLL WE Write Enable VSSDL Ground for DLL DQ0 DQ7 Data Inputs Outputs x8 VREF Reference eae for SSTL CKE Clock Enable ODT On Die Termination Enable CK CK Differential Clock Inputs NC Not connected DM Data Input Mask 1 2 3 x16 Components Symbol Function Symbol Function A0 A12 Row Address Inputs LDQS LDQS Differential Data Strobes UDQS UDQS A0 A9 Column Address Inputs NC No Connection Chip to Pin BA0 BA1 BA2 Bank Address Inputs VDD Supply Voltage Column Address Input Ground for Auto Precharge vss cs Chip Select VDDQ Supply Voltage for DQ RAS Row Address Strobe VSSQ Ground for DQs CAS Column Address Strobe VDDL Supply Voltage for DLL WE Write Enable VSSDL Ground for DLL Ref Volt f TL LDQO 7 UDQ0 7 Data Inputs Outputs VREF SETERS inp or SS CKE Clock Enable ODT On Die Termination Enable CK CK Differential Clock Inputs NC Not connected LDM UDM Data Input Masks Page 5 Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF
3. NC NC VDD NC VSS UDQ6 VSSQ UDM VDDQ UDQ1 VDDQ UDQ4 VSSQ DQ3 VDD NC VSS LDQ6 VSSQ LDM VDDQ LDQ1 VDDQ LDQ4 VSSQ LDQ3 VDDL VREF vss CKE WE BA2 BAO BA1 A10 1 vss A3 A5 A7 A9 VDD A12 NC A14 NC NC Notes A NC NC B VSSQ UDQS VDDQ E UDQS VSSQ UDQ7 F VDDQ VDDQ G UDQ2 VSSQ UDQ5 H VSSQ 1 VDDQ J LDOS VSSQ LDQ7 K VDDQ L LDQ2 VSSQ LDQ5 M VSSDL VDD N RAS CK ODT P CAS cs R A2 AO VDD T AG AA U A11 A8 vss NC A15 NC A13 w x AA NC NC 1 UDQS UDQS is data strobe for upper byte LDQS LDQS is data strobe for lower byte 2 UDM is the data mask signal for the upper byte UDQ0 UDQ7 LDM is the data mask signal for the lower byte LDQ0 LDQ7 3 NC A13 NC A14 and NC A15 are additional address pins for future genera tion DRAMs and are not connected on this component Rev 1 02 May 2004 INFINEON Technologies 5 Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 1 5 Input Output Functional Description Symbol Type Function CK CK Input Clock CK and CK are differential system clock inputs All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK Output read data is referenced to the crossing of CK and CK both direction of crossing CKE Input Clock Enable CKE h
4. DQ i l l Din A0 Din A1 Din A2 Din A3 Din BO Din B1 Din B2 Din B3 J Dout B4 Din B5 Din B6 Din B7 1 1 1 1 1 1 I WBI Page 41 Rev 1 02 May 2004 INFINEON Technologies sx HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 2 7 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated The Precharge Com mand is triggered when CS RAS and WE are low and CAS is high at the rising edge of the clock The Pre charge Command can be used to precharge each bank independently or all banks simultaneously Three address bits A10 BAO BA2 are used to define which bank to precharge when the command is issued Bank Selection for Precharge by Address Bits A10 BAO BA1 BA2 eis LOW LOW LOW LOW Bank 0 only LOW LOW HIGH LOW Bank 1 only LOW HIGH LOW LOW Bank 2 only LOW HIGH HIGH LOW Bank 3 only LOW LOW LOW HIGH Bank 4 only LOW LOW HIGH HIGH Bank 5 only LOW HIGH LOW HIGH Bank 6 only LOW HIGH HIGH HIGH Bank 7 only HIGH Don t Care Don t Care Don t Care all banks Note The bank address assignment is the same for activating and precharging a specific bank 2 7 1 Burst Read Operation Followed by a Precharge The following rules apply as long as the tRTP timing parameter Internal Read to Precharge Command delay time is less or equal two clocks which is the case for operating frequencies less or equal 2
5. 5 1 3 Input and Output Leakage Currents Symbol Parameter Condition min max Units Notes liL Input Leakage Current any input OV lt Viy lt VDD 2 2 uA 1 IOL Output Leakage Current OV lt VouT lt VDDQ 5 5 uA 2 notes 1 all other pins not under test OV 2 DQ s DQS DQS and ODT are disabled Page 64 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 5 2 DC amp AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS 1 Enable DQS mode bit timing advantages of differential mode are realized in system design The method by which the DDR2 SDRAM pin timing are measured is mode dependent In single ended mode timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF In differential mode these timing relationships are measured relative to the crosspoint of DQS and its complement DQS This distinc tion in timing methods is verified by design and characterisatio but not subject to production test In single ended mode the DQS and RDQS signals are internally disabled and don t care 5 2 1 Single ended DC amp AC Logic Input Levels Symbol Parameter Min Max Units VIH dc input logic high VREF 0 125 VDDQ 0 3 V VIL dc DC input low 0 3 VREF 0 125 V VIH ac AC inp
6. eee e eee eee LOO eee E O OO wien OOOs wi oo 99 999 eee OO ee Bre O O O ah yer dee ee oes tee UE us s J 6 4 M Ote 6 4 rl 4 4 10 0 5 10 0 see balls through package Page 86 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 10 DDR2 Component Nomenclature Example 18 T 4010 A 5 INFINEON T 0 standard 1 Component Prefix HYB for DRAM Components 6 Product Variations 2 two dies in one package A 1st Generation 2 Power Supply Voltage 18 1 8 V Power Supply 7 Die Revision B 2nd Generation C 3rd Generation C BGA package 3 DRAM Technology T DDR2 8 Package Type F BGA packages lead and halogen free 256 256 Mb 5 DDR2 400 333 512 512 Mb 3 7 DDR2 533 444 4 Memory Density 1G 1024Mb 9 Speed Grade 3 DDR2 667 444 2G 2048 Mb 3S DDR2 667 555 40 x4 4 data in outputs 5 Memory Organisation 80 x8 8 data in outputs 16 x16 16 data in outputs Page 87 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 11 Content 1 Description 1 1 Ordering Information 1 2 Pin Description 1
7. Rev 1 02 May 2004 INFINEON Technologies amm Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 1 4 2 Package Pinout for x8 components 60 pins 8 support pins FBGA 68 Package top view Page 7 2 1 RDQS RDQS are enabled by EMRS 1 command If RDQS RDQS is enabled the DM function is disabled 3 When enabled RDQS amp RDQS are used as strobe signals during reads 4 VDDL and VSSDL are power and ground for the DLL They are isolated on the device from VDD VDDQ VSS and VSSQ 5 NC A14 and NC A15 are additional address pins for future generation DRAMs and are not connected on this component NC NC A NC NC B AU vss E 55 DQS VDDQ RDQS pae vssa pas VSSQ RDQS VDDQ VDDQ G VDDQ DQO VDDQ DQ4 VSSQ H DQ2 VSSQ DQ5 VDDL VREF VSS J VSSDL CK VDD CKE WE K RAS CK ODT BA2 BAO BA1 L CAS cs A10 A1 M A2 A0 VDD vss A3 A5 N A6 A4 A7 A9 P A11 A8 vss VDD A12 NC A14 R 15 A13 T U w NC NC Notes Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 1 4 3 Package Pinout for x16 components 84 pins 8 support pins FBGA 92 Package top view Page 8
8. 1 gt i i CL 3 1 i i I gt tRC i I 1 gt stRTP i 1 1 i 1 I I I I 1 CMD Post CAS NOP NOP NOP Bank A G READ A me 5 NOP NOP Activate AL clks tRP I I 1 l 4 i s DQS b n DQS 1 1 n if y x i i b Ld ic i i S SERRE U i H 1 1 Dout AO Dout A1 Dout A24 Dout Dout A4 Dout ss Dout A64 Dout A7 1 I o iRAS i CL 3 1 I l H I he lt a T t t l i gt stRTP i 1 I 4 1 1 1 first 4 bit prefetch second 4 bit prefetch 43 Rev 1 02 2004 INFINEON Technologies n HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Burst Read Operation Followed by Precharge RL 5 AL 2 CL 3 BL 4 tRTP lt 2 clocks eY Va NOP s NOP x NOP em NOP HE Bank A NOP BERD A T T T T AL BL 2 clks MEM NEN MEE NENNEN gt 005 i i j y n i Das I i i L C 1 ME RL 5 i i DQ I i i I gt 1 1 4 Deut AO Dout A1 Dout A2 dr 1 gt tRAS L 1 1 0 1
9. 5 2 3 Differential DC and AC Input and Output Logic Levels Symbol Parameter min max Units Notes VIN dc DC input signal voltage 0 3 VDDQ 0 3 1 VID dc DC differential input voltage 0 25 VDDQ 0 6 2 VID ac AC differential input voltage 0 5 VDDQ 0 6 3 VIX ac AC differential cross point input voltage 0 5 VDDQ 0 175 0 5 VDDQ 0 175 4 VOX ac AC differential cross point output voltage 0 5 VDDQ 0 125 0 5 VDDQ 0 125 5 notes 1 VIN dc specifies the allowable DC execution of each input of differential pair such as CK CK DQS DQS etc 2 VID dc specifies the input differential voltage VTR VCP required for switching The minimum value is equal to VIH dc VIL dc 3 VID ac specifies the input differential voltage VTR VCP required for switching The minimum value is equal to VIH ac VIL ac 4 The value of VIX ac is expected to equal 0 5 x VDDQ of the transmitting device and VIX ac is expected to track variations in VDDQ VIX ac indicates the voltage at which differential input signals must cross 5 The value of VOX ac is expected to equal 0 5 x VDDQ of the transmitting device and VOX ac is expected to track variations in VDDQ VOX ac indicates the voltage at which differential input signals must cross Crossing Point SSTL18 3 Page 66 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2
10. Read followed by a write to the same bank Activate to Read delay gt tRCDmin AL 1 CL 3 RL 4 WL 3 BL 4 CMD i tRCD gt tRCDmin DQS DQS DQ PostCAS5 Page 31 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 6 2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations write cycle or from memory locations read cycle The parameters that define how the burst mode will operate are burst sequence and burst length The DDR2 SDRAM supports 4 bit and 8 bit burst modes only For 8 bit burst mode full interleave address ordering is supported however sequential address ordering is nibble based for ease of implementation The burst length is programmable and defined by the addresses AO A2 of the MRS The burst type either sequential or interleaved is programmable and defined by the address bit 3 A3 of the MRS Seamless burst read or write operations are supported Interruption of a burst read or write operation is prohibited when burst length 4 is pro grammed For burst interruption of a read or write burst when burst length 8 is used see the Burst Interruption section of this datasheet A Burst Stop command is not supported on DDR2 SDRAM devices Burst Length and Sequence Burst Length Sta
11. Units Maximum peak amplitude allowed for overshoot area 0 9 0 9 0 9 V Maximum peak amplitude allowed for undershoot area 0 9 0 9 0 9 V Maximum overshoot area above VDD 0 75 0 56 0 45 V ns Maximum undershoot area below VSS 0 75 0 56 0 45 V ns Volts V Maximum Amplitude Overshoot Area Undershoot Area Maximum Amplitude Time ns 8 4 2 AC Overshoot Undershoot Specification for Clock Data Strobe and Mask Pins Parameter prion ii Units Maximum peak amplitude allowed for overshoot area 0 9 0 9 0 9 V Maximum peak amplitude allowed for undershoot area 0 9 0 9 0 9 V Maximum overshoot area above VDDQ 0 38 0 28 0 23 V ns Maximum undershoot area below VSSQ 0 38 0 28 0 23 V ns Volts V Maximum Amplitude Overshoot Area Undershoot Area Maximum Amplitude gt Time ns Page 85 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 9 Package Dimensions 68 balls FBGA Package 92 balls FBGA Package 10 0 mm x 20 0 mm 10 0 mm x 20 0 mm MO 207 Variation DM z x4 x8 MO 207 Variation DL z x16 0 8 0 8 apo Aw 295 90 Sus me nn mr MESE T m prs au Pss 1555 Pow bu 0 45 eee eee CERE eee eee
12. n x a eem TA T r DV Dy 1 DX 1 4 1 1 l f 1 1 1 1 1 1 1 EU TE x x 7 n H 1 Dout AO Dout A1 Dout 24 Dout A3 Dout A4 1 Dout A5 Dout A6 Dout A7 I I I 2 i i BRead303 Burst Read followed by Burst Write RL 5 WL RL 1 4 BL 4 TO T1 T3 T4 T5 T6 T7 T8 T9 CK CK CMD qu cas NOP JE asied B NOP ac z READ A WRITE A pas DQS T I if oL l od WE WLZRL 1 4 DQ I mm Dout AO o A1 A2 A3 I i BRBW514 The minimum time from the burst read command to the burst write command is defined by a read to write turn around time which is BL 2 2 clocks Page 34 Rev 1 02 May 2004 INFINEON Technologies a Infineon Seamless Burst Read Operation RL 5 AL 2 CL 3 BL 4 HYB18T1G400 800 160AF 1Gb DDR2 SDRAM E i oa NOP Post CAS NOP NOP NOP NOP NOP cuo 5 0 ae 0 NOP 0 0 0 o pas uf 005 li NET EN to dj AL 2 CL 3 i D Q 1 Dout A0 ows Al ow Dout a om B1 Dout Dout es I SBR523 The seamless burst read operation is supported by enabling a read command at every BL 2 number of clocks This operation is al
13. 0 2 1 6 7 5 mA DQ added IDDQ current for ODT enabled IODTO ODT is HIGH Data Bus inputs are FLOATING 198 ee mao Active ODT current per DQ A6 0 A2 1 tbd 12 15 mA DQ added IDDQ current for ODT enabled IODTT ODT is HIGH worst case of Data Bus inputs A6 1 A2 0 thd 6 7 5 mA DQ are STABLE SWITCHING note For power consumption calculations the ODT duty cycle has to be taken into account Page 74 Rev 1 02 May 2004 INFINEON Technologies aa Infineon 7 Electrical Characteristics amp AC Timing Absolute Specification 7 1 Timing Parameter by Speed Grade DDR2 400 amp DDR2 533 VDDQ 1 8V 0 1V Vpp 1 8V 0 1V notes 1 4 HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 5 3 7 Symbol Parameter cue Unit Notes min max min max tac DQ output access time from CK CK 600 600 500 500 ps tpasck output access time from CK CK 500 500 450 450 ps tcH CK high level width 0 45 0 55 0 45 0 55 tcL CK CK low level width 0 45 0 55 0 45 0 55 tck tup Clock half period min tcL tCH min tCH 5 CL 3 5000 8000 5000 8000 ps 6 Clock cycle time CL 48 amp 5 5000 8000 3750 8000 ps 6 tis Address and control input setup time 350 250 ps 7 Address and control input hold time 475 375 ps 7 tps DQ and D
14. VREF de VIL ac max tangent line VREF dc VIL ac max fallin Setup Slew Rate falling signal Alling Ce Delta TFS 979 Setup Slew Rate Delta TES signal Seotus Slew Rai VIH ac min VREF dc tangent line VIH ac min VREF dc rising etup Slew Rate BHSTES g sig Setup Slew Rate Delta TRS signal VREF dc ViL dc max tangent line VREF dc VIL dc max rising Hold Slew Rate rising signal Hold Slew Rate signal Delta IRM Delta TRH rise VIH dc min VREF mitem tangent line VIH dc min VREF dc falling O VIEW alee Delta g sig Hold Slew Rate Della TER signal fig A fig B Page 83 Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 8 3 4 Input Setup tIS and Hold Time Derating Table CK CK Differential Slew Rate 2 0 V ns 1 5 V ns 1 0 V ns A tIS A tIS A tIS Unit 4 0 187 94 217 124 247 154 ps 3 5 179 89 209 119 239 149 ps 3 0 167 83 197 4113 4227 4143 ps 2 5 150 75 180 105 210 135 5 2 0 125 45 155 75 185 105 5 A 1 5 83 21 113 51 143 81 ps g 1 0 0 0 430 30 60 60 ps 2 09 11 14 19 16 49 46 ps SE Us 25 31 5 1 35 29 ps 07 43 54 13 24 17 6 ps o 0 6 67 83 37 53 7 23 ps 0 5 110 125 80 95 50 65 ps 8 0 4 175 188 145 158 115 128 ps
15. 0 1 0 3 0 1 0 2 optional 1 Slow exit use IXARDS 0 1 1 4 0 1 1 3 1 0 0 5 1 0 0 4 1 0 1 6 1 0 1 5 BA1 BAO MRS mode 1 1 0 Reserved 1 1 0 Reserved 0 0 MRS 1 1 1 Reserved 1 1 1 Reserved 0 1 EMRS 1 1 0 EMRS 2 Reserved 1 1 EMRS 3 Reserved Must be programmed to 0 when setting the mode register A13 A15 and BA2 are reserved for future use and must be programmed to 0 when setting the mode register MRS The programmability of WR Write Recovery is for Writes with Auto Precharge only and defines the time when the device starts precharge internally WR must be programmed to fulfill the minimum requirement for the analogue tWR timing CAS Latency 2 is implemented in this design but functionality is not tested and guaranteed Page 16 Rev 1 02 May 2004 INFINEON Technologies Infineon 2 2 4 DDR2 SDRAM Extended Mode Register Set EMRS 1 The extended mode register EMRS 1 stores the data for enabling or disabling the DLL output driver strength additive latency OCD program ODT DQS and output buffers disable RQDS and RDQS enable The default value of the extended mode register EMRS 1 is not defined therefore the extended mode register must be writ ten after power up for proper operation The extended mode register is written by asserting low on CS RAS CAS WE 1 BA2 and high on BAO while controlling the state of the address pins The DDR2 SDRAM should be in all bank precharge with CKE alr
16. 0 3 285 292 255 262 225 232 ps 0 25 350 375 320 345 290 315 ps 0 2 525 500 495 470 465 440 ps 0 15 800 708 770 678 740 648 ps 0 1 1450 1125 1420 1095 1390 1065 ps 1 For all input signals the total tIS input setup time and input hold time required is calculated by adding the individual datasheet value to the derating value listed in the previous table 2 For slow slewrate the total setup time might be negativ i e valid input signal will not have reached VIH ac VIL ac at the time of the rising clock a valid input signal is still required to complete the transistion and reach VIH ac VIL ac For slew rates in between the values listed in the next tables the derating values may be obtained by linear interpolation These val ues are not subject to production test They are verified only by design and characterisation 8 3 5 Data Setup tDS and Hold Time tDH Derating Tablefor differential DQS DQS DGS DGS Differential Slew Rate 4 0V ns 3 0V ns 20V ns 1 8V ns 1 6V ns 1 4V ns 1 2V ns 1 0V ns 0 8 V ns AtDS AtDS AEDH AtDS AEDS AtDH AEDS AtDH AtDS AEDS AtDH AEDS AEDH AtDS AtDH Unit 2 0 125 45 125 45 125 445 ps A 1 5 83 21 83 21 83 21 95 33 i i ps 10 0 0 0 0 0
17. 1Gb DDR2 SDRAM 1 3 1Gbit DDR2 Addressing Configuration 256Mb x 4 128Mb x 8 64Mb x 16 of Banks 8 8 8 Bank Address BAO BA1 2 BAO BA1 BA2 BAO BA1 BA2 Auto Precharge A10 A10 AP A10 AP Row Address 0 A13 A13 AO A12 Column Address AO A9 A11 A9 9 Page Length 2048 bits 1024 bits 1024 bits Page Size 1024 1kB 1024 1kB 2048 2kB page length 2 20 0 page size in bytes 2 9585 x 8 where colbits is the number of column address bits and ORG the number of I O DQ bits 1 4 Package Pinout amp Addressing 1 4 1 Package Pinout for x4 components 60 pins 8 support pins FBGA 68 Package top view Page 6 A B C D VDD NC vss E NC VSSQ DM F VDDQ DQ1 VDDQ G NC VSSQ DQ3 H VDDL VREF VSS J CKE WE K BA2 BAO BA1 L A10 A1 M vss A3 A5 N A7 A9 P VDD A12 NC A14 R T U V NC NC w DQS Das VSSQ NC DQ2 VSSQ NC VSSDL CK VDD RAS CK ODT CAS CS A2 A0 VDD A6 A4 A11 A8 vss NC A15 A13 NC NC Notes device 1 VDDL and VSSDL are power and ground for the DLL They are isolated on the from VDD VDDQ VSS and VSSQ 2 NC A14 andNC A15 are additional address pins for future generation DRAMs and are not connected on this component
18. 7 2 Timing Parameter by Speed Grade DDR2 667 VDDQ 1 8V 0 1V Vpp 1 8V 0 1V notes 1 4 3S 3 Symbol Parameter DDR2 667 555 DDR2 667 444 Unit Notes min max min max tgp Precharge command period single bank 15 12 ns tRP A Precharge All 8 banks command period tRP 1tcK i tRP 1tcK ns 22 x4 amp x8 t Active bank A to Active bank B com 1k page size 7 5 7 5 s ns RRD j 23 mand period x16 2k page size 10 10 ns x4 amp x8 37 5 37 5 ns tFAW Four Activate Window period 1k page size 24 x16 2k page size 50 50 ns tccp CASA to CAS B Command Period 2 2 twR Write recovery time 15 15 ns tpAL Auto Precharge write recovery precharge time WR tRP WR tRP tcK 14 twTR Internal Write to Read command delay 7 5 7 5 15 tRTP Internal Read to Precharge command delay 7 5 7 5 i ns Exit power down to any valid command tXARD other than NOP or Deselect 2 7 7 tek 1e Exit active power down mode Read command tXARDS slow exit lower power G 7 CAL 7 tek 16 Exit precharge power down to any valid command other than NOP or Deselect 2 2 7 Exit Self Refresh to Read command 200 200 txsNR Exit Self Refresh to non Read command tRFC 10 tRFC 10 ns tCKE minimum high and low pulse width 3 3 i tcK 0 C 85 C 7 8 7 8 us tREFI Average periodic refresh In
19. EET NER NAE MEN NS ME i L y BR P525 Burst Read Operation Followed by Precharge RL 6 AL 2 CL 4 BL 4 tRTP lt 2 clocks TO T1 T2 T3 T4 T5 T6 T7 T8 i Bank A H Activate BR P6P4 Page 44 Rev 1 02 May 2004 INFINEON Technologies is HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Burst Read Operation Followed by Precharge RL 4 AL 0 CL 4 BL 8 tRTP gt 2 clocks AL BL 2 clks 1 D READA H Y NOP NOP Precharge J Bank A Pus em i A vee x Actvate H i n NEN IRP i pos 1 W DOS 1 I Ba te eee et nnn net bh o4 3 E I I I 1 M 1 M 1 H I RL 4 d I 1 DQ i oa AO om At Dout Dout 1 oo i A5 Dout Dout Hr I I I A I 4 i 1 gt stRAS hi 7 do 7 d 4 I 1 I 1 j I I I RTP 1 l Eu Ep oy we 3 Los 4 d 4 404 8 first 4 bit prefetch second 4 bit prefetch n Page 45 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 2 7 2 Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank WL BL 2 tWR For write cycles a delay must be satisfied from the completion of the last burst write cycle unti
20. JEDEC ballot item 1293 15 No more than 4 banks may be activated in a rolling tFAW window Converting to clocks is done by deviding tFAW ns by tCK ns and rounding up to next integer value As an example of the rolling window if tFAW tCK rounds up to 10 clocks and an activate command is issued in clock N no more than three further activate commands may be issued in clocks N 1 through N 9 2 Precharge All Allowance tRP for a Precharge All command will equal to tRP 1 tCK where tRP is the value for a single bank precharge Bank Activate Command Cycle tRCD 3 AL 2 tRP 3 tRRD 2 2 Tn 3 CK CK t i i Internal RAS CAS delay tRCDmin lt es ae M AN Bank A Bank B Bank A NOP Bank B Bank A Address pau Row Adar Addr H Adar Row Addr Bank A to Bank B delay tRRD H additive latency AL 2 iRead A Begins Command Bank A osted CAS Bank B osted CAS Activate iuc A Activate Read B Bank A Bank B Bank A Precharge pee Activate 1 4 HRAS Row Active Time Bank A gt tRP Row Precharge Time Bank A 1 l 1 n L 14 tRC Row Cycle Time Bank A ACT Page 28 Rev 1 02 May 2004 INFINEON Technologies T5 HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 6 Read and Write Commands and Access Modes After
21. The extended mode register EMRS 2 is written by asserting low on CS RAS CAS WE BA2 BA0 and high on BA1 while controlling the state of the address pins The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register The mode register set command cycle time tMRD must be satisfied to complete the write operation to the EMRS 2 Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state Address Field Extended Mode rT 0 1 0 0 Register 2 must be programmed to 0 EMRS 2 2 2 6 EMRS 3 Extended Mode Register The Extended Mode Register EMRS 3 is reserved for future use and all bits except BAO and BA1 must be pro grammed to 0 when setting the mode register during initialization Address Field ETEA G l s 0 Register 3 must be programmed to 0 Page 19 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 3 Off Chip Driver OCD Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence Every calibration mode command should be followed by OCD calibration mode exit before any other command being issued MRS should be set before entering OCD impedance adjustment and ODT On Die Termination should be carefully controlled
22. all 28 32 39 mA Active Power Down Standby MRS 12 0 all 13 17 21 Current MRS 12 1 all 5 5 5 mA IDD3N Active Standby Current all 40 50 60 mA 4 11 130 IDD4R Operating Current Burst Read s us 120 155 4 8 95 115 135 IpD4w Operating Current Burst Write x16 110 135 165 mA IDD5B Burst Auto Refresh Current tRFC tRFCmin all 180 185 190 mA IDD5D Distributed Auto Refresh Current tRFC 7 8 us all 7 7 7 mA Ippe Self Refresh Current for standard products all 5 5 5 mA IDD6L Self Refresh Current for low power products all 2 2 2 mA x4 x8 195 205 215 Ippz Operating Current 8 banks interleave x16 255 270 285 mA Page 72 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 6 2 IDD Measurement Conditions VDDQ 1 8V 0 1V VDD 1 8V 0 1V Symbol Parameter Condition Operating Current One bank Active Precharge Ippo tCK IDD tRC tRC IDD tRAS tRASmin IDD is HIGH CS is HIGH between valid commands Address and control inputs are SWITCHING Data bus inputs are SWITCHING Operating Current One bank Active Read Precharge Ipp1 IOUT 0 mA BL 4 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CL CL IDD AL 0 CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING Precharge Power Down Current All banks idle is LOW tCK tCK IDD Other cont
23. i pQ T 1 om ao ons om on as me mes Active Active Power Down Power Down Act PD 2 Entry Exit note Active Power Down mode exit timing tXARD fast exit or tXARDS slow exit depends on the programmed Active Power Down Mode Entry and Exit after a Write Command with AP WL 2 tWR 3 BL 4 TO T2 T3 T4 T5 T6 T7 Tn Tn 1 Tn 2 FON r 7 qM q wm TY LEY EYE YX YY X E MICA Nt CMD 4 H NOP NOP NOP NOP NOP NOP P nop V Bm WL BL 2 WR tls c IS I I a NA Po d d a DOS EL Hee NES DER ME E Wee RL 14 2 0 0 X 4 WR i xARDor gt gt 1 n o d M tXARDS DQ vo om as ona om as l i i i i t 1 1 1 1 Active Active Power Down Power Down Act PD 3 Entry Exit note Active Power Down mode exit timing tXARD fast exit or IXARDS slow exit depends on the programmed state in the MRS address bit A12 WR is the programmed value in the MRS mode register Page 57 Rev 1 02 May 2004 INFINEON Technologies n HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Precharge Power Down Mode Entry and Exit TO T1 T2 T3 1 2 i r yoann U i gt pem CK CK L3 Tod i A A E
24. 0 25 pF Input output capacitance CIO DQ DM DOS DAS RDAS RDQS ae Input output capacitance delta CDIO DM bas DAS RDQS RDQS oe 5 6 Power amp Ground Clamp V I Characteristics Power and Ground clamps are provided on address A0 A13 BAO BA2 RAS CAS CS WE and ODT pins The V I characteristics for pins with clamps is shown in the following table Voltage across clamp Minimum Power Minimum Ground V Clamp Current mA Clamp Current mA 0 0 0 0 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 1 0 1 0 9 1 0 1 0 1 0 2 5 2 5 1 1 4 7 4 7 1 2 6 8 6 8 1 3 9 1 9 1 1 4 11 0 11 0 1 5 13 5 13 5 1 6 16 0 16 0 1 7 18 2 18 2 1 8 21 0 21 0 Page 71 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 6 IDD Specifications and Measurement Conditions 6 1 IDD Specifications VDDQ 1 8V 0 1V VDD 1 8V 0 1V 0 C to TcASEmax 5 3 7 3 amp 3S Unit Symbol Parameter Condition yo DOARA Behe max max max 4 8 70 75 80 Ippo Operating Current x16 75 80 85 mA i x4 x8 80 85 95 Ipp1 Operating Current x16 90 95 105 mA Ipp2p Precharge Power Down Current all 5 5 5 mA IDD2N Precharge Standby Current all 35 46 56 mA Ipp2Q Precharge Quiet Standby Current
25. 11 5 11 8 13 3 0 3 14 3 16 0 16 6 17 4 20 0 0 4 18 7 21 0 21 6 23 0 27 0 The driver characteristics evaluation conditions are Nominal 25 C Tcase VDDQ 1 8 V typical process Nominal Low and Nominal High 25 C Tcase VDDQ 1 8V any process Nominal Minimum 95 C Tcase VDDQ 1 7 V any process Nominal Maximum 0 C Tcase VDDQ 1 9 V any process Full Strength Calibrated Pull up Driver Characteristics Calibrated Pull up Driver Current mA Voltage V Nominal Minimum Normal Low Nominal Normal High Nominal Maximum 21 Ohms 18 75 Ohms 18 ohms 17 25 Ohms 15 Ohms 0 2 9 5 10 7 11 4 11 8 13 3 0 3 14 3 16 0 16 5 17 4 20 0 0 4 18 3 21 0 21 2 23 0 27 0 The driver characteristics evaluation conditions are Nominal 25 C Tcase VDDQ 1 8 V typical process Nominal Low and Nominal High 25 C Tcase VDDQ 1 8V any process Nominal Minimum 95 C Tcase VDDQ 1 7 V any process Nominal Maximum 0 C Tcase VDDQ 1 9 V any process Page 70 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 5 5 Input Output Capacitance Symbol Parameter min max Units CCK Input capacitance CK and CK 1 0 2 0 pF CDCK Input capacitance delta CK and CK 0 25 pF CI Input capacitance all other input only pins 1 0 2 0 pF CDI Input capacitance delta all other input only pins
26. 1Gb DDR2 SDRAM 8 Reference Loads Setup amp Hold Timing Definition and Slew Rate Derating 8 1 Reference Load for Timing Measurements The figure represents the timing reference load used in defining the relevant timing parameters of the device It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the tim ing reference load to a system environment Manufacturers correlate to their production test conditions generally a coaxial transmission line terminated at the tester electronics This reference load is also used for output slew rate characterisation VDDQ o DQ CK CK 005 DUT DQS Vtt VDDQ 2 RDQS 25 Ohm RDQS L Timing Reference Points The output timing reference voltage level for single ended signals is the crosspoint with VTT The output timing reference voltage level for differential signals is the crosspoint of the true e g DQS and the complement e g DQS signal 8 2 Slewrate Measurements 8 2 1 Output Slewrate With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT 250 mV and VTT 250 mV for single ended signals For differential signals e g DQS DQS out put slew rate is measured between DQS DQS 500 mV and DQS DQS 500 mV Outp
27. 3 DDR2 SDRAM Addressing 1 4 Package Pinouts 1 5 Input Output Functional Description 16 Block Diagrams 2 Functional Description 2 1 Simplified State Diagram 2 2 NNNN 2 7 2 8 Basic Functionality 2 2 1 Power On and Initialization 2 Programming the Mode Registers 3 Mode Register Set MRS 4 Extended Mode Register Set EMRS 1 5 Extended Mode Register Set EMRS 2 6 Extended Mode Register Set EMRS 3 Chip Driver OCD Impedance Adjustment ODT On Die Active Termination Bank Activate Command Read and Write Command 2 6 1 Posted CAS 6 2 Burst Mode Operation 6 3 Burst Read Operation 6 4 Burst Write Operation 6 5 6 6 2 2 2 2 2 2 2 2 2 2 Off 2 2 2 2 Write Data Mask 2 Burst Interruption Precharge Command 2 7 1 Burst Read Operation followed by a Precharge 2 7 2 Burst Write Operation followed by a Precharge Auto Precharge Command 2 8 1 Read with Auto Precharge 2 8 2 Write with Auto Precharge 2 8 3 Read or Write to Precharge Command Spacing Summary 2 8 4 Concurrent Auto Precharge Refresh Commands 2 9 1 Auto Refresh Command 2 9 2 Self Refresh Command Power Down Other Commands 2 11 1 No Operation 2 11 2 Deselect Input Clock Frequency Change Asynchronous CKE Low Event 3 Truth Tables 3 1 3 2 3 3 Command Truth Table Clock Enable CKE Truth Table Data Mask DM Truth Table 4 Operating Conditions 4 1 4 2 Page 88 Absolute Maximum Ratings DRA
28. 5 239 Data Array 1 e192 x 256 x 64 SL 56 2 L 64 8 29 x 16 y Sense Amplifiers 16 3 i Generator 5 8 9 8 j N bos to LDQO LDQ7 2 ER er COLO input DOS LDM gt 08 218 ig Register lt gt upoo upo7 A0 A12 Te 51455 DM Mask Logic Wu Mask 2 le 2 UDM 9 tc Oo E 2 t 256 lt s Drivers cL 2 cz f es Sept E 8 2 KJ j cc r r g8 n s 8 Z lt UDQS mE UDQS Column lt Decoder 16 16 lt 64 18 18 T0 Column Address 16 Counter Latch COLO k E CK CK of the device it does not represent an actual circuit implementation Note DM is a unidirectional signal input only but is internally loaded to match the load of the Block Diagram 16Mbit x 16 I O x 4 Internal Memory Banks 32Mb x 16 Organisation with 13 Row 3 Bank and 11 Column External Addresses Page 12 Rev 1 02 May 2004 INFINEON Technologies T HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 Functional Description 2 1 Simplified State Diagram CKEL Initialization REFSX Sequence tRFC CKEL tRCD WL BL 2 WR tRP RL BL 2 tRTP Read AP Read gt Automatic Sequence Command MS uence This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and the commands to control them In parti
29. D A4 RA4 D A5 RAS D A6 RAG D A7 RAT D D 26 clocks 3 Timing pattern for x16 components DDR2 400 AO RAO 1 RA1 A2 RA2 D D A4 RA4 A5 RAS A6 RAG A7 RA7 D D 20 clocks DDR2 533 AO RAO D A1 RA1 D A2 RA2 D D D D A4 RA4 D A5 RAS D RAG D A7 RAT D D D 28 clocks DDR2 667 AO RAO D D A1 RA1 D D A2 RA2 D D RA3D D D A4 RA4 D D A5 RA5 D D AG RA6 D D A7 RA7 DD D 34 clocks 4 Legend A Activate RA Read with Auto Precharge DZDESELECT IDD7 1 IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled 2 Data Bus consists of DQ DM DOS DQS RDQS RDQS LDQS LDQS UDQS and 3 Definitions for IDD LOW is defined as VIN lt VILAC max HIGH is defined as VIN gt VIHAC min STABLE is defined as inputs are stable at a HIGH or LOW level FLOATING is defined as inputs are VREF VDDQ 2 SWITCHING is defined as Inputs are changing between HIGH and LOW every other clock once per two clocks for address and control signals and inputs changing between HIGH and LOW every other data transfer once per clock for DQ signals not including mask or strobes 4 Timing parameter values for IDD current measurements are defined in the following table Page 73 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 6 2 IDD Measurement Conditions cont d For testing
30. Device must be in the All banks idle state before entering Self Refresh mode tXSRD gt 200 has to be satisfied for a Read or a Read with Auto Precharge command tXSNR has to be satisfied for any command except a Read or a Read with Auto Precharge command Since CKE is an SSTL input VREF must be maintained during Self Refresh Page 54 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Intineon 1Gb DDR2 SDRAM 2 10 Power Down Power down is synchronously entered when CKE is registered low along with NOP or Deselect command CKE is not allowed to go low while mode register or extended mode register command time or read or write operation is in progress CKE is allowed to go low while any other operation such as row activation Precharge Auto Pre charge or Auto Refresh is in progress but power down IDD specification will not be applied until finishing those operations The DLL should be in a locked state when power down is entered Otherwise DLL should be reset after exiting power down mode for proper read operation DRAM design guarantees it s DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications If power down occurs when all banks are precharged this mode is referred to as Precharge Power down if power down occurs when there is a row active in any bank this mode is referred to as Active Power down For Active Power down two differe
31. May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 7 1 Timing Parameter by Speed Grade DDR2 400 amp DDR2 533 VDDQ 1 8V x 0 1V Vpp 1 8V 0 1V notes 1 4 5 3 7 Symbol Parameter DDR2 400 333 DDR2 533 444 Unit Notes min max min max tRP A Precharge All 8 banks command period tRP 1tcK tRP 1tcK ns 22 x4 amp x8 Active bank A to Active bank B 1k page size 7 5 i 7 5 ns RRD i 23 mand period x16 2k page size 10 10 ns x4 amp x8 A 37 5 37 5 ns traw Four Activate Window period fk page size x16 2k page size 50 50 ns tccp CAS Ato CAS B Command Period 2 2 twR Write recovery time 15 15 ns tpAL Auto Precharge write recovery precharge time WR tRP WR tRP 14 twTR Internal Write to Read command delay 10 7 5 ns 15 tRTp Internal Read to Precharge command delay 7 5 7 5 B ns Exit power down to any valid command IXARD other than NOP or Deselect 2 j 2 7 tck 16 Exit active power down mode to Read command IXARDS slow exit lower power I ert i 16 Exit precharge power down to any valid command other than NOP or Deselect 2 2 txsRD Exit Self Refresh to Read command 200 200 txsNR Exit Self Refresh to non Read command tRFC 10 tRFC 10 2 ns minimum high and low pulse width 3 3 tck
32. SDRAM 5 3 Output Buffer Levels 5 3 1 SSTL_18 Output DC Current Drive Symbol Parameter SSTL_18 Class II Units Notes IOH Output Minimum Source DC Current 13 4 mA 1 3 4 IOL Output Minimum Sink DC Current 13 4 mA 2 3 4 AO 1 VDDQ 1 7 V VouT 1 42 V Voy T VDDQ IOH must be less than 21 ohm for values of VoUT between VDDQ and VDDQ 280 mV 2 VDDQ 1 7 V VoyT 280 mV Vout IOL must be less than 21 ohm for values of VOUT between OV and 280 mV The dc value of VREF applied to the receiving device is set to VTT The values of loH dc and Io dc are based on the conditions given in note 1 and 2 They are used to test drive current capa bility to ensure VIHmin plus a noise margin and ViLmax minus a noise margin are delivered to an SSTL 18 receiver The actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement 5 3 2 SSTL 18 Output AC Test Conditions Symbol Parameter SSTL 18 Class II Units Notes VOH Minimum Required Output Pull up VTT 0 603 V 1 VoL Maximum Required Output Pull down VTT 0 603 V 1 VoTR Output Timing Measurement Reference Level 0 5 VpDQ V 2 2 The VDDQ of the device under test is referenced 1 SSTL 18 test load for VOH and VOL is different from the reference load described in section 8 1 ofthis datasheet The SSTL 18 test load has a 20 Ohm series resistor addition
33. a bank has been activated a read or write cycle can be executed This is accomplished by setting RAS high CS and CAS low at the clock s rising edge WE must also be defined at this time to determine whether the access cycle is a read operation WE high or a write operation WE low The DDR2 SDRAM provides a wide variety of fast access modes A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667Mb sec pin for main memory The boundary of the burst cycle is restricted to specific segments of the page length For example the 64Mbit x 4 I O x 4 Bank chip has a page length of 2048 bits defined by 9 amp 11 In case of a 4 bit burst operation burst length 4 the page length of 2048 is divided into 512 uniquely address able segments 4 bits x 4 I O each The 4 bit burst operation will occur entirely within one of the 512 segments defined by CA0 CA8 beginning with the column address supplied to the device during the Read or Write Com mand 9 amp A11 The second third and fourth access will also occur within this segment however the burst order is a function of the starting address and the burst sequence In case of a 8 bit burst operation burst length 8 the page length of 2048 is divided into 256 uniquely address able double segments 8 bits x 4 I O each The 8 bit burst operation will occur entirely within one of the 256 dou ble se
34. ala X on jJ 3 5 4 5 1 BW APA28 2 8 3 Read or Write to Precharge Command Spacing Summary The following table summarizes the minimum command delays between Read Read w AP Write Write w AP to the Precharge commands to the same banks and Precharge All commands From Command To Command Minimum Delay between From Command to To Command Units Notes PRECHARGE to same banks as READ AL BL 2 max tRTP 2 2 tck tCK 1 2 READ PRECHARGE ALL AL BL 2 max tRTP 2 2 tck tCK 1 2 PRECHARGE to same banks as READ w AP AL BL 2 max tRTP 2 2 tck tCK 1 2 READ w AP PRECHARGE ALL AL BL 2 max tRTP 2 2 tck tCK 1 2 PRECHARGE to same banks as WRITE WL BL 2 4 tWR tCK 2 WRITE PRECHARGE ALL WL BL 2 tCK 2 PRECHARGE to same banks as WRITE w AP WL BL 2 WR tCK 2 WRITE w AP PRECHARGE ALL WL BL 2 WR tCK 2 PRECHARGE to same banks as PRECHARGE 1 tck tCK 2 PRECHARGE PRECHARGE ALL 1 tck tCK 2 PRECHARGE 1 tck tCK 2 PRECHARGE ALL PRECHARGE ALL 1 tck tCK 2 Note 1 RTP cycles RU tRTP ns tCK ns where RU stands for round up Note 2 For a given bank the precharge period should be counted from the latest precharge command either one bank precharge or precharge all issued to that bank The precharge period is satisfied after tRP or tRPall depending on the latest prechargte com mand issued to that ba
35. and tRTP are satisfied If tRAS min is not satisfied at the edge the start point of Auto Precharge operation will be delayed until tRAS min is satisfied If tRTPmin is not satisfied at the edge the start point of Auto Precharge operation will be delayed until tRTPmin is satisfied In case the internal precharge is pushed out by tRTP tRP starts at the point where the internal precharge happens not at the next rising clock edge after this event So for BL 4 the minimum time from Read with Auto Precharge to the next Activate command becomes AL tRTP tRP For BL 8 the time from Read with Auto Precharge to the next Activate command is AL 2 tRP Note that tRTP has to be rounded up to the next inte ger value In any event internal precharge does not start earlier than two clocks after the last 4 bit prefetch A new bank active command may be issued to the same bank if the following two conditions are satisfied simul taneously 1 The RAS precharge time tRP has been satisfied from the clock at which the Auto Precharge begins 2 The RAS cycle time tRC from the previous bank activation has been satisfied Page 47 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM Examples Burst Read with Auto Precharge followed by an activation to the Same Bank tRC Limit RL 5 AL 2 CL 3 BL 4 tRTP lt 2 clocks TO
36. completion of the burst write to bank precharge is named write recovery time tWR and is the time needed to store the write data into the memory array tWR is an analog timing parameter see the AC table in this specification and is not the programmed value for WR in the MRS Basic Burst Write Timing Example Burst Write Operation RL 5 AL 2 CL 3 WL 4 BL 4 TO T1 T2 T3 T4 T5 T6 T7 T9 jx vx eS CK CK 22 21 j A E NE CMD Post CAS NOP NOP H o H o Precharge i H 1 H D I 1 lt 10055 Completion of I b peep poets i 1p the Burst Write DQS I L oof ay Dy 005 i COSA rA ii 1 E d TE 1 i WL RL 1 4 i W i BO eat NEHME wm I l I BW543 Page 36 Rev 1 02 May 2004 INFINEON Technologies SDRAM T HYB18T1G400 800 160AF Infineon 1Gb DDR2 Burst Write Operation RL 3 AL 0 CL 3 WL 2 BL 4 TO T1 T2 T3 T4 T5 T6 T7 T9 CK CK t l l MEM i Bank CMD ym P NOP E NOP Ars 1 lt 0055 Completion of DOS SENE La oe
37. conditions are satisfied 1 The last data in to bank activate delay time tDAL WR has been satisfied 2 The RAS cycle time tRC from the previous bank activation has been satisfied In DDR2 SDRAM s the write recovery time delay WR has to be programmed into the MRS mode register As long as the analog twr timing parameter is not violated WR can be programmed between 2 and 6 clock cycles Minimum Write to Activate command spacing to the same bank WL BL 2 tDAL Examples Burst Write with Auto Precharge Limit WL 2 tDAL 6 WR 3 tRP 3 BL 4 TO T1 T2 T3 T4 T5 T6 T7 CK CK 1 1 BENE i WRITE Bank A LE yx i c i H G mir E Ls s an A10 high i NM Compson ot ne BE wie hte M Begins DQS 3 1 DQS ae ho 3 WL RL 1 2 1 lt pi mE DAL DQ 1 on r p d E fr tRCmin i r H H gt tRASmin y H I i 1 1 H BW AP223 Page 50 Rev 1 02 May 2004 INFINEON Technologies am Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM Burst Write with Auto Precharge WR tRP Limit WL 4 tDAL 6 WR 3 tRP 3 BL 4 TO T3 T4 5 T6 T7 T8 T9 T12 CMD um CA MUS Precharge segs WRITE w AP A10 high jum DQS w DQ C KC
38. don t care Burst Write Operation with Data Mask RL 3 AL 0 CL 3 WL 2 3 BL 4 TO T1 T2 T3 T4 T5 T6 T7 T9 __ Oo uM O p puc r dp CK CK el k Sl i d i 3 Bank A CMD ware mH NOP H NOP H NOP H NOP H NOP Activate Y lt 10085 s asss o X 7 DQS i l i l l WR 1 1 1 DM Page 39 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 6 6 Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions 1 C N O A A Read Burst of 8 can only be interrupted by another Read command Read burst interruption by a Write or Precharge Command is prohibited A Write Burst of 8 can only be interrupted by another Write command Write burst interruption by a Read or Precharge Command is prohibited Read burst interrupt must occur exactly two clocks after the previous Read command Any other Read burst interrupt timings are prohibited Write burst interrupt must occur exactly two clocks after the previous Write command Any other Read burst interrupt timings are prohibited Read or Write b
39. eight Auto Refresh commands can be posted to any given DDR2 SDRAM meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 tREFI Lu MK high CKE i gt tap x x ME Ae x bi gt ea REFRESH Page 53 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Chien 1Gb DDR2 SDRAM 2 9 2 Self Refresh Command The Self Refresh command can be used to retain data even if the rest of the system is powered down When in the Self Refresh mode the DDR2 SDRAM retains data without external clocking The DDR2 SDRAM device has a built in timer to accommodate Self Refresh operation The Self Refresh Command is defined by having CS RAS CAS and CKE held low with WE high at the rising edge of the clock ODT must be turned off before issuing Self Refresh command by either driving ODT pin low or using EMRS 1 command Once the command is regis tered CKE must be held low to keep the device in Self Refresh mode The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh When the DDR2 SDRAM has entered Self Refresh mode all of the external control signals except CKE are don t care The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode The clock is internally disabled during Self Refresh Operation to save power Th
40. have to be applied The Bank Activate command must be applied before any Read or Write operation can be executed Immediately after the bank active command the DDR2 SDRAM can accept a read or write command with or without Auto Precharge on the following clock cycle If a R W command is issued to a bank that has not satisfied the tRCDmin specification then additive latency must be programmed into the device to delay the R W command which is internally issued to the device The additive latency value must be chosen to assure tRCDmin is satisfied Additive latencies of 0 1 2 3 and 4 are supported Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank The bank active and precharge times are defined as tRAS and tRP respectively The minimum time interval between successive Bank Activate commands to the same bank is determined tRC The minimum time interval between Bank Active commands to any other bank is the Bank A to Bank B delay time tRRD In order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supply ing capability certain restrictions on operation of the 8 banks must be observed There are two rules One for restricting the number of sequential Active commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command The rules are as follows 1 Sequential Bank Activation Restriction
41. i FIFO 1 1 s re 8 32 amp lt 1 2 8 p Drivers 21 1 jel 4 4 lt oo ecoqer 8 8 5 8 lt 2 TO M Column Address 32 8 le 8 8 5 Counter Latch yCOL0 1 lt 7 8 ies 2 Data i lt CK CK i COLO 1 Note This Functional Block Diagram is intended to facilitate user understanding of the operation of the device it does not represent an actual circuit implementation Note DM is a unidirectional signal input only but is internally loaded to match the load of the bidi rectional DQ and DQS signals Block Diagram 32Mbit x 8 I O x 4 Internal Memory Banks 64Mb x 8 Organisation with 14 Row 3 Bank and 11 Column External Addresses Page 11 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM Note This Functional Block Diagram is intended to facilitate user understanding of the operation CO Ei CK x CK gt CS Wwe D WE 3 CAS 59 s RAS gt 5 Bank7 E x 4 z 5 DLL Mode 16 8 7 LN Registers o ood 1 49 558 ED Lew
42. low active power down mode MRS A12 1 a slow power down exit timing tXARDS has to be satisfied The clock frequency is allowed to change during self refresh mode or precharge power down mode In case of clock fre quency change during power down a specific procedure is required as describes in section 2 12 Consists of data pin skew and output pattern effects and p channel to n channel variation of the output drivers as well as output slew rate mis match between DQS DQS and associated DQ in any given cycle The Auto Refresh command interval has be reduced to 3 9 us when operating the DDR2 DRAM in a temperature range between 85 C and 95 C ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on ODT turn on time max is when the ODT resistance is fully on Both are measure from tAOND ODT turn off time min is when the device starts to turn off ODT resistance ODT turn off time max is when the bus is in high impedance Both are measured from tAOFD tRP A for a Precharge All command for an 8 bank device is equal to trp 1 tck where trp are the values for a single bank precharge The tRRD timing parameter depends on the page size of the DRAM organisation see section 1 3 of the datasheet 8 bank device Sequential Activation Restriction No more than 4 banks may be activated in a rolling tFAW window Page 80 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon
43. of Command N All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period Read commands may be issued only after tXSRD 200 clocks is satisfied Self Refresh mode can only be entered from the All Banks Idle state Must be a legal command as defined in the Command Truth Table Valid commands for Power Down Entry and Exit are NOP and DESELECT only Valid commands for Self Refresh Exit are NOP and DESELCT only Power Down and Self Refresh can not be entered while Read or Write operations Extended mode Register operations Precharge or Refresh operations are in progress See section 2 8 Power Down and section 2 7 2 Self Refresh Com mand for a detailed list of restrictions Minimum CKE high time is 3 clocks minimum CKE low time is 3 clocks The state of ODT does not affect the states described in this table The ODT function is not available during Self Refresh The Power Down Mode does not perform any refresh operations The duration of Power Down Mode is therefor limited by the refresh requirements CKE must be maintained high while the device is in OCD calibration mode X means don t care including floating around VREF in Self Refresh and Power Down However ODT must be driven high or low in Power Down if the ODT function is enabled Bit A2 or A6 set
44. than 0 must be written into the EMRS 1 The Write Latency WL is always defined as RL 1 Read Latency 1 where Read Latency is defined as the sum of Additive Latency plus CAS latency RL AL CL If a user chooses to issue a Read command after the tRCDmin period the Read Latency is also defined as RL AL CL Examples Read followed by a write to the same bank Activate to Read delay lt tRCDmin AL 2 and CL 3 RL AL CL 5 WL RL 1 4 BL 4 ate gt Das lt bas tRCD el us ME AL AL CL 5 PostCAS1 P ooo oot pse pou ono Din1 ove Read followed by a write to the same bank Activate to Read delay lt tRCDmin AL 2 and CL 3 RL AL CL 5 WL RL 1 4 BL 8 p pM p os ooo ogee lt V Activate Read i i i Write Bank a AL i E Bee i tRCD 4 T gt j i h i i RL AL CL 5 I DQ lt i I I t y om owe PostCAS3 Page 30 Rev 1 02 May 2004 INFINEON Technologies T HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Read followed by a write to the same bank Activate to Read delay tRCDmin AL 0 CL 3 RL AL CL 3 WL RL 1 2 BL 4 PostCAS2
45. the IDD parameters the following timing parameters are used 5 3 7 3S 3 Unit Parameter Symbol DDR2 400 DDR2 533 DDR2 667 DDR2 667 3 3 3 4 4 4 5 5 5 4 4 4 CAS Latency CL IDD 3 4 5 4 tCK Clock Cycle Time tCK IDD 5 3 75 3 3 ns Active to Read or Write delay tRCD IDD 15 15 15 12 ns pote to Active Auto Refresh command tRC IDD 60 60 60 57 ns x4 amp x8 37 5 37 5 37 5 37 5 ns Four Active Window Period tFAW IDD x16 50 50 50 50 ns x4 amp x8 7 5 7 5 7 5 7 5 ns Active bank A to Active 1 KB page size tRRD IDD bank B command delay x16 2 kB page size 10 10 10 10 ns tRASmin IDD 45 45 45 45 ns Active to Precharge Command tRASmax IDD 70000 70000 70000 70000 ns Precharge Command Period tRP IDD 15 15 15 12 ns Auto Refresh to Active Auto Refresh com mand period tRFC IDD 127 5 127 5 127 5 127 5 ns 6 33 ODT On Die Termination Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS 1 Depending on address bits A6 amp A2 in the EMRS 1 a week or strong termination can be selected The current consumption for any terminated input pin depends on the input pin is in tri state or driving O or 1 as long a ODT is enabled during a given period of time ODT current per terminated input pin EMRS 1 State Unit min typ max Enabled ODT current per DQ
46. to 1 in EMRS 1 Operation that is not specified is illegal and after such an event in order to guarantee proper operation the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue 3 3 Data Mask DM Truth Table Name Function DM DQs Notes Write Enable L Valid 1 Write Inhibit H X 1 1 Used to mask write data provided coincident with the corresponding data Page 62 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Intineon 1Gb DDR2 SDRAM 4 Operating Conditions 4 1 Absolute Maximum Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to VSS 1 0 to 2 3 V 1 VDDQ Voltage on VDDQ pin relative to VSS 0 5 to 2 3 V 1 VDDL Voltage on VDDL pin relative to VSS 0 5 to 2 3 V 1 Vin VoUT Voltage on any pin relative to VSS 0 5 to 2 3 V 1 Storage Temperature 55 to 100 C 1 2 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reli ability 2 Storage Temperature is the case surface temperature on the c
47. to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM DATASHEET Rev 1 02 05 04 Features High Performance 5 3 7 35 3 Speed Sorts DDR2 DDR2 DDR2 DDR2 Units 400 533 667 667 Bin CL tRCD TRP 3 3 3 4 4 4 5 5 5 4 4 4 tck max Clock Frequency 200 266 333 MHz Data Rate 400 533 667 Mb s pin CAS Latency CL 3 4 5 4 tck tRCD 15 15 15 12 ns tRP 15 15 15 12 ns tRAS 40 45 45 45 ns tRC 55 60 60 57 ns 1 8V 0 1V Power Supply 1 8 V 0 1V SSTL_18 compatible I O DRAM organisations with 4 8 and 16 data in outputs Double Data Rate architecture two data transfers per clock cycle eight internal banks for concurrent operation CAS Latency 3 4 and 5 Burst Length 4 and 8 Differential clock inputs CK and CK Bi directional differential data strobes DQS and DQS are transmitted received with data Edge aligned with read data and center aligned with write data DLL aligns DQ and DQS transitions with clock DQS can be disabled for single ended data strobe opera tion Commands entered on each positive clock edge data and data mask are referenced to both edges of DQS Data masks DM for write data Posted CAS by programmable additi
48. 0 high AL tRP cde 4 POE ott Begins Et DQS i i i h you a 005 f l CL 3 1 L4 401 31 1 lt gt lt T gt i RL 4 t i D Q 4 1 i P ooa A0 Jou Al Dout Dout A4 low A5 Dout Dout 1 1 I d 1 i i gt tRTP MEME a 1 1 H H H 1 i t BR AP413 8 2 first 4 bit prefetch second 4 bit prefetch Burst Read with Auto Precharge followed by an Activation to the Same Bank RL 4 AL 1 CL 3 BL 4 tRTP gt 2 clocks 1 MD osted CAS Bank i EL A vro Aio high 9 AL RTP tRP Auto Precharge Begins H n T T DQ t BR AP4133 first 4 bit prefetch Page 49 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Chien 1Gb DDR2 SDRAM 2 8 2 Burst Write with Auto Precharge If A10 is high when a Write Command is issued the Write with Auto Precharge function is engaged The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay WR programmed in the MRS register as long as tRAS is satisfied The bank undergoing Auto Pre charge from the completion of the write burst may be reactivated if the following two
49. 0 C 85 C 7 8 7 8 us tREFI Average periodic refresh Interval 19 85 C 95 C 3 9 3 9 us OCD drive mode output delay 0 12 0 12 ns Minimum time clocks remain ON after CKE asynchro tDELAY nously drops LOW tIS tCK tlH tIS tCK tlH ns 17 Timing that is not specified is illegal and after such an event in order to guarantee proper operation the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue Page 76 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 7 2 Timing Parameter by Speed Grade DDR2 667 VDDQ 1 8V 0 1V Vpp 1 8V 0 1V notes 1 4 3S 3 Symbol Parameter DARE GO SES ue Unit Notes min max min max tac DQ output access time from CK CK 450 450 450 450 ps tpasck output access time from CK CK 400 400 400 400 ps tcH CK CK high level width 0 45 0 55 0 45 0 55 tck tcL CK CK low level width 0 45 0 55 0 45 0 55 tck tup Clock half period min tCH min tCH 5 CL 3 5000 8000 5000 8000 ps tck Clock cycle time CL 4 5000 8000 3000 8000 ps 6 CL 5 3000 8000 3000 8000 ps 115 Address and control input setup time 150 150 ps 7 Address and control input hold time 275 275 ps 7 tps DQ and DM input setup tim
50. 1 6 20 4 37 6 58 4 94 9 1 7 20 6 37 7 59 6 97 0 1 8 37 9 60 9 99 1 1 9 101 1 The driver characteristics evaluation conditions are Nominal Default 25 C Tcase VDDQ 1 8 V typical process Minimum 95 C Tcase VDDQ 1 7V slow slow process Maximum 0 C Tcase VDDQ 1 9 V fast fast process 120 100 Minimum E Nominal Default Low Nominal Default High Pulldown current mA o e Page 69 40 lt Maximum 20 0 T T T T 0 02 0 06 0 8 1 12 1 4 1 6 1 8 2 VOUT to VSSQ V Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 5 4 3 Calibrated Output Driver V I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off Chip Driver OCD Impedance Adjustment The following tables show the data in tabular format suitable for input into simulation tools The nominal points represent a device at exactly 18 ohms The nominal low and nominal high values represent the range that can be achieved with a maximum 1 5 ohms step size with no calibration error at the exact nominal conditions only i e perfect calibration procedure 1 5 ohm maximum step size guaranteed by specification Real system calibration error needs to be added to these values It must be understood that these V I curves are represented here or in supplier IBIS mode
51. 17 18 19 20 21 22 23 24 Timings are guaranteed with CK CK differential slew rate of 2 0 V ns For DQS signals timings are guaranteed with a dif ferential slew rate of 2 0 V ns in differential strobe mode and a slew rate of 1 V ns in single ended mode For other slew rates see Section 8 of this datasheet The CK CK input reference level for timing reference to CK CK is the point at which CK and CK cross The DQS DQS RDQS RDQS input reference level is the crosspoint when in differential strobe mode The input reference level for signals other than CK CK DQS DQS RDQS RDQS tIS tiH 105 is VREF For tIS 105 tDH input reference levels see section 8 3 of this datasheet Inputs are not recognized as valid until VREF stabilizes During the period before VREF stabilizes CKE 0 2 x VDDQ is recognized as LOW The output timing reference voltage level is VTT See section 8 for the reference load for timing measurements Min tCL tCH refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tCL and tCH For input frequency change during DRAM operation see the 2 11 section of this datasheet For timing definition slew rate and slew rate derating see Section 8 3 For timing definition slew rate and slew rate derating see Section 8 3 The tHZ tRPS
52. 3 Truth Tables 3 1 Command Truth Table Function Previous CS RAS CAS WE BA1 A13 A11 A10 A9 AO0 Notes Cycle Cycle int Extended Mode Register Set H L L L L BA OP Code 1 2 Auto Refresh H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1 Self Refresh Exit L H H x x x x x x x 1 Single Bank Precharge H H L L H L BA x L X 1 2 Precharge all Banks H H L L H L x x H x 1 Bank Activate H H L L H H BA Row Address 1 2 Write H H L H L L BA Column L Column 1 2 3 Write with Auto Precharge H H L H L L BA Column Column 1 2 3 Read H H L H L H BA Column L Column 1 2 3 Read with Auto Precharge H H E H L H BA Column H Column 1 2 3 No Operation H X L H H H X x x x 1 Device Deselect H x H x x x x x x x 1 H x x x Power Down Entry H L x x x x 1 4 L H H H H X X X Power Down Exit L H X X X X 1 4 L H H H All DDR2 SDRAM commands are defined by states of CS WE RAS CAS and CKE at the rising edge of the clock Bank addresses BAO BA2 determine which bank is to be operated upon For E MRS BAx selects an Extended Mode Register Burst reads or writes at BL 4 cannot be terminated See sections Reads interrupted by a Read and Writes inter rupted by a Write in section 2 4 6 for details The Power Down Mode does not perform any refresh operations The duration of Power Down is therefore limited by the refresh requirements outlined in section 2 7 The state of ODT does not affect the states described
53. 3 4 amp 5 8 banks x 16 Mbits x 8 68 pin FBGA HYB18T1G160AF L 3 8 banks x 8 Mbits x 16 92 pin FBGA 333 DDR2 667 HYB18T1G400AF L 3S 8 banks x 32 Mbits x 4 68 pin FBGA HYB18T1G800AF L 3S 5 8 banks x 16 Mbits x 8 68 pin FBGA HYB18T1G160AF L 3S 8 banks x 8 Mbits x 16 92 pin FBGA Notes 1 For product nomenclature see section 10 of this datasheet 2 Versions with an L in the part numbers are Low Power versions of the standard component with reduced IDD6 Self Refresh current See section 6 1 for IDD current specifications 3 All FBGA packages are lead free 1 2 Pin Description 1 2 1 x4 Components Symbol Function Symbol Function A0 A13 Row Address Inputs pos DAS Differential Data Strobes A0 A9 A11 Column Address Inputs NC No Connection Chip to Pin BAO BA1 BA2 Bank Address Inputs VDD Supply Voltage Column Address Input for Auto Precharge VSS Ground cs Chip Select VDDQ Supply Voltage for DQ RAS Row Address Strobe VSSQ Ground for DQs CAS Column Address Strobe VDDL Supply Voltage for DLL WE Write Enable VSSDL Ground for DLL DQ0 DQ3 Data Inputs Outputs x4 VREF jefe q OSSIE CKE Clock Enable ODT On Die Termination Enable CK CK Differential Clock Inputs NC Not connected DM Data Input Mask Page 4 Rev 1 02 May 2004 INFINEON Technologies Infineon 1 2 1 x8 Components HYB18T1G400 800 160AF 1Gb DDR2 SDRAM
54. 47 7 0 7 18 6 29 8 36 9 55 0 0 8 19 0 31 9 40 8 62 3 0 9 19 3 33 4 44 5 69 4 1 0 19 7 34 6 47 7 75 3 1 1 19 9 35 5 50 4 80 5 1 2 20 0 36 2 52 5 84 6 1 3 20 1 36 8 54 2 87 7 1 4 20 2 37 2 55 9 90 8 1 5 20 3 37 7 57 1 92 9 1 6 20 4 38 0 58 4 94 9 1 7 20 6 38 4 59 6 97 0 1 8 38 6 60 8 99 1 1 9 101 1 The driver characteristics evaluation conditions are Nominal Default 25 C Tcase VDDQ 1 8 V typical process Minimum 95 C Tcase VDDQ 1 7V slow slow process Maximum 0 C Tcase VDDQ 1 9 V fast fast process 0 20 lt 40 Minimum E Nominal Default Low 5 60 Nominal Default High Maximum 2 80 a 100 120 0 02 0 4 0 6 0 1 12 1 4 1 6 1 8 2 VDDQ to VOUT V Page 68 Rev 1 02 May 2004 INFINEON Technologies am Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 5 4 2 Full Strength Default Pull down Driver Characteristics Pull down Driver Current mA Voltage V Minimum Nominal Default low Nominal Default high Maximum 0 2 8 5 11 3 11 8 15 9 0 3 12 1 16 5 16 8 23 8 0 4 14 7 21 2 22 1 31 8 0 5 16 4 25 0 27 6 39 7 0 6 17 8 28 3 32 4 47 7 0 7 18 6 30 9 36 9 55 0 0 8 19 0 33 0 40 9 62 3 0 9 19 3 34 5 44 6 69 4 1 0 19 7 35 5 47 7 75 3 1 1 19 9 36 1 50 4 80 5 1 2 20 0 36 6 52 6 84 6 1 3 20 1 36 9 54 2 87 7 1 4 20 2 37 1 55 9 90 8 1 5 20 3 37 4 57 1 92 9
55. 66 Mhz DDR2 400 and 533 speed sorts Minimum Read to Precharge command spacing to the same bank AL BL 2 clocks For the earliest possible precharge the precharge command may be issued on the rising edge which is Additive Latency AL BL 2 clocks after a Read Command as long as the minimum tRAS timing is satisfied A new bank active command may be issued to the same bank if the following two conditions are satisfied simulta neously 1 The RAS precharge time tRP has been satisfied from the clock at which the precharge begins 2 The RAS cycle time tRCmin from the previous bank activation has been satisfied For operating frequencies higher than 266 MHz tRTP becomes gt 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing which now becomes AL BL 2 1 clocks Page 42 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Examples Burst Read Operation Followed by Precharge RL 4 AL 1 CL 3 BL 4 tRTP lt 2 clocks TO T1 T2 T3 T4 T5 T6 T7 T8 Post CAS NOP NOP Precharge NOP Bank A READA siiis H l H 1 T I a i 1 1 n T T 0 i I i z i I H a i gt i DQ I I h I g AO owen Dout x Dout t I l D d i
56. 8 and low to BAO BA2 and A13 A15 9 Issue Precharge all command 10 Issue 2 or more Auto Refresh commands 11 Issue a MRS command with low on A8 to initialize device operation i e to program operating parameters with out resetting the DLL 12 At least 200 clocks after step 8 execute OCD Calibration Off Chip Driver impedance adjustment If OCD calibration is not used EMRS OCD Default command A9 A8 A7 1 followed by EMRS 1 OCD Calibration Mode Exit command A9 A8 A7 0 must be issued with other parameters of EMRS 1 13 The DDR2 SDRAM is now ready for normal operation Page 14 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Example CK CK COXTOHICIOHIOHOHOUHO OD sci 1 GILL ILL Li rt 39243 400 MRS MRS MRS tMRS REC E pi _ IMRS gt i gt gt gt 4 i 7 lt P 1 j 1 I PRE i PRE 15 Aul 2nd Auto EMRS 1 V EMRS 1 Any NOP ALL EMRS 2 EMRS 3 EMRS 1 MRS M ALL afresh refresh MRS OCD io Command H 1 ih min 200 cycles to lock the DLL Extended Mode Mode t 1 Mode Register Register OCD Drive 1 OCD Register 1 Set Set with Set w o or calibration with DLL enable DLL reset DLL reset OCD default mode exit 2 2 2 Programming the Mode Register and Extended Mod
57. DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval The necessary refresh can be generated in one of two ways by explicit Auto Refresh commands or by an internally timed Self Refresh mode 2 9 1 Auto Refresh Command Auto Refresh is used during normal operation of the DDR2 SDRAM s This command is non persistent so it must be issued each time a refresh is required The refresh addressing is generated by the internal refresh controller This makes the address bits don t care during an Auto Refresh command The DDR2 SDRAM requires Auto Refresh cycles at an average periodic interval of tREFI maximum When CS RAS and CAS are held low and WE high at the rising edge of the clock the chip enters the Auto Refresh mode All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time tgp before the Auto Refresh Command can be applied An internal address counter supplies the addresses during the refresh cycle No control of the external address bus is required once this cycle has started When the refresh cycle has completed all banks of the SDRAM will be in the precharged idle state A delay between the Auto Refresh Command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the Auto Refresh cycle time trrc To allow for improved efficiency in scheduling and switching between tasks some flexibility in the absolute refresh interval is provided A maximum of
58. DQS differential DQS signals 0 Disable 1 Disable DM Hi Z DQS Hi Z single ended DQS signals 1 Enable 0 Enable RDQS RDQS DQS DQS differential DQS signals 1 Enable 1 Disable RDQS Hi Z DQS Hi Z single ended DQS signals DLL Enable Disable The DLL must be enabled for normal operation DLL enable is required during power up initialization and upon returning to normal operation after having the DLL disabled The DLL is automatically disabled when entering Self Refresh operation and is automatically re enabled and reset upon exit of Self Refresh operation Any time the DLL is reset 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock Less clock cycles may result in a violation of the tAC or tDQSCK parameters Output Disable Qoff Under normal operation the DRAM outputs are enabled during Read operation for driving data Qoff bit in the EMRS 1 is set to 0 When the Qoff bit is set to 1 the DRAM outputs will be disabled Disabling the DRAM out puts allows users to measure IDD currents during Read operations without including the output buffer current Page 18 Rev 1 02 May 2004 INFINEON Technologies yk HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 2 5 EMRS 2 Extended Mode Register The Extended Mode Registers EMRS 2 and EMRS 3 are reserved for future use and must be programmed when setting the mode register during initialization
59. DRAM controller to independently turn on off termination resistance for any or all DRAM devices The ODT function can be used for all active and standby modes ODT is turned off and not supported in Self Refresh mode Functional Representation of ODT VDDQ VDDQ DRAM Input Buffer sw1 sw2 VSSQ VSSQ Switch sw1 or sw2 is enabled by the ODT pin Selection between sw1 or sw2 is determined by Rtt nominal in EMRS 1 address bits amp A2 Target Rtt 0 5 Hval1 or 0 5 Rval2 The ODT pin will be ignored if the Extended Mode Register EMRS 1 is programmed to disable ODT Page 23 Rev 1 02 May 2004 INFINEON Technologies oe HYB18T1G400 800 160AF 4 3 1Gb DDR2 SDRAM ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS 1 for all three device organisations x4 x8 and x16 To activate termination of any of these pins the ODT function has to be enabled in the EMRS 1 by address bits A6 and A2 Input Pin 5 1 Address Bit A10 Address Bit 11 x4 components x x DQS x X DQS 0 X DM X X x8 components DQ0 DQ7 X X DQS X X Das 0 X RDQS X 1 RDQS 0 1 DM X 0 X16 components LDQ0 LDQ7 X X UDQ0 UDQ7 x x LDQS x x LDQS 0 X UDQS X X UDQS 0 X LDM X X UDM X X X don t care 0 bit set
60. Data Sheet V1 02 May 2004 Memory Products Never stop thinking Edition 2004 05 03 Published by Infineon Technologies AG St Martin Strasse 53 81669 Munchen Germany Infineon Technologies AG 5 7 04 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended
61. Definition for Data Setup tDS and Hold Time tDH Data input setup time tDS with differential data strobe enabled MR bit10 0 is referenced from the input signal crossing at the VIH ac level to the differential data strobe crosspoint for a rising signal and from the input signal crossing at the VIL ac level to the differential data strobe crosspoint for a falling signal applied to the device under test 005 505 signals must be monotonic between VIL dc max and VIH dc min Data input hold time with differential data strobe enabled MR bit10 20 is referenced from the input signal crossing at the VIL dc level to the differential data strobe crosspoint for a rising signal and VIH dc to the differential data strobe crosspoint for a fall ing signal applied to the device under test DQS DQS signals must be monotonic between VIL dc max and VIH de Data input setup time tDS with single ended data strobe enabled MR bit10 21 is referenced from the input sig nal crossing at the VIH ac level to the data strobe crossing VREF for a rising signal and from the input signal crossing at the VIL ac level to the single ended data strobe crossing VREF for a falling signal applied to the device under test Data input hold time tDH with single ended data strobe enabled MR bit10 21 is referenced from the input signal crossing at the VIL dc level to the single ended data strobe crossing VREF for a rising signal and VIH dc to the single ended d
62. IDD tCK tCK IDD Ipp4w tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address inputs are SWITCH ING Data Bus inputs are SWITCHING Burst Auto Refresh Current tCK tCK IDD Refresh command every tRFC tRFC IDD interval CKE is HIGH CS is DD5B HIGH between valid commands Other control and address inputs are SWITCHING Data bus inputs are SWITCHING Distributed Auto Refresh Current tCK tCK IDD Refresh command every tREFI 7 8 us interval is LOW CS is 0050 HIGH between valid commands Other control and address inputs are SWITCHING Data bus inputs are SWITCHING Self Refresh Current lt 0 2V external clock off and CK at OV Other control and address inputs are FLOATING 006 Data Bus inputs are FLOATING Eight Bank Interleave Read Current 1 All banks interleaving reads IOUT 0 mA BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD tRC tRC IDD tRRD tRRD IDD tFAW tFAW IDD CKE is HIGH CS is high between valid com mands Address bus inputs are STABLE during DESELECTS Data bus is SWITCHING 2 Timing pattern for x4 and x8 components DDR2 400 RAO A1 A2 RA2 A4 A5 RAS A6 RAG A7 RA 16 clocks DDR2 533 AO RAO A1 RA1 A2 RA2 D D A4 5 RAS RAG A7 D D 20 clocks DDR2 667 AO RAO D A1 RA1 D A2 RA2 D D
63. M Component Operating Temperature Range Rev 1 02 May 2004 INFINEON Technologies Infineon Content 5 AC amp DC Operation Conditions 5 1 DC Operation Conditions 5 1 1 Recommended DC Operation Conditions 2 ODT DC Operation Conditions Input and Output Leakage Current AC Logic Input Levels 3 5 2 amp 1 Single ended DC amp AC Logic Input Levels 2 3 5 1 5 1 DC 5 2 5 2 2 Single ended AC Input Test Conditions 5 2 3 Differential DC and AC Input and Output Logic Levels 5 3 Output Buffer Levels 5 31 Output AC Test Conditions 5 3 2 Output DC Current Drive 5 3 5 Full Strength Pull up Driver Characteristics 5 3 6 Full Strength Pull down Driver Characteristics 5 3 7 Calibrated Output Driver V I Characteristics t Output Capacitances wer amp Ground Clamp V I Characteristics de 25 6 IDD Specifications 6 1 IDD Specifications 6 2 IDD Measurement Conditions 6 2 ODT current 7 AC Timing Specifications 7 1 Timing parameters by speed grade DDR2 400 amp DDR2 533 7 2 Timing parameters by speed grade DDR2 667 7 3 ODT AC Electrical Characteristics and Operating Conditions 7 4 Notes for AC Timing Specifications 8 Reference Loads Slew Rates and Slew Rate Derating 8 1 Reference Load for Timing Measurements 8 2 Output Slew Rate Measurements 8 3 Input and Data Setup and Hold Time 8 3 1 Timing Definition for Input Setup and Hold Time 8 3 2 Timing Definition for Data Setup and Hold Time 8 3 3 Slew Ra
64. M input setup time 150 100 ps 8 tpH DQ and DM input hold time 275 225 ps 8 tpw Address and control input pulse width each input 0 6 0 6 tpipw DQ and DM input pulse width each input 0 35 0 35 tcK tuz Data out high impedance time from CK CK tACmax tACmax ps 9 tLz po low impedance time from CK CK 2 tACmin tACmax 2 tACmin tACmax ps 9 tLz pas DQS low impedance from CK CK tACmin tACmax tACmin tACmax ps 9 tpasq DQS DQ skew for DQS amp associated DQ signals 350 300 ps 18 tous Data hold skew factor 450 400 ps Data output hold time from DQS typ taHs tHP toHS tooss Write command to 1st DQS latching transition WL 0 25 WL 0 25 WL 0 25 WL 0 25 tDQSL H DQS input low high pulse width write cycle 0 35 0 35 toss DQS falling edge to CK setup time write cycle 0 2 0 2 tck DGS falling edge hold time from CK write cycle 0 2 0 2 tMRD Mode register set command cycle time 2 2 tck twPRE Write preamble 0 25 0 25 tcK twPST Write postamble 0 40 0 60 0 40 0 60 10 tRPRE Read preamble 0 9 1 1 0 9 1 1 9 tRPST Read postamble 0 40 0 60 0 40 0 60 tcK 9 tRAS Active to Precharge command 40 70000 45 70000 ns 11 tRc Active to Active Auto Refresh command period 55 60 ns tRFC Auto Refresh to Active Auto Refresh command period 127 5 127 5 ns 12 J 18 T8 trp Precharge command period single bank 15 15 ns Page 75 Rev 1 02
65. O 12 12 24 24 E i ps o 09 14 11 44 1 2 13 410 425 22 i z ps EN 08 25 31 13 19 1 7 11 5 23 17 07 31 42 19 30 7 1 18 5 6 7 6 ps 06 4 49 31 47 19 35 7 23 5 1 ps 2 20 5 74 89 62 77 50 65 38 53 ps 04 127 140 115 128 103 116 ps For all input signals the total tD ating value listed in the previous table S setup time and tDH ho are verified only by design and characterisation d time required is calculated by adding the individual datasheet value to the der For slow slewrate the total setup time might be negativ i e a valid input signal will not have reached VIH ac at the time of the ris ing DQS a valid input signal is still required to complete the transistion and reach VIH ac VIL ac For slew rates in between the values listed in the next tables the derating values may be obtained by linear interpolation These values are not subject to production test They Page 84 Rev 1 02 May 2004 INFINEON Technologies a Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 8 4 Overshoot and Undershoot Specification 8 4 1 AC Overshoot Undershoot Specification for Address and Control Pins Parameter yos pios
66. ODT turn off time max tAOF max is when the bus is in high impedance Both are measured from tAOFD ODT Timing for Precharge Power Down and Active Power Down Mode with slow exit Asynchronous ODT timings T pee TO T1 T2 T3 T4 T5 6 T7 T8 mf YY YY XY YEE Y PREY K CK is Loo I Loa I Loa I CKE FPD min tAO DQ tAONPD max ODT02 1 Asynchronous ODT timings apply for Precharge Power Down Mode and Slow Exit Active Power Down Mode MRS bit A12 set to 1 where the on die DLL is disabled in this mode of operation Page 25 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM ODT timing mode switch When entering the Power Down Modes Slow Exit Active Power Down and Precharge Power Down two addi tional timing parameters ANPD and tAXPD define if synchronous or asynchronous ODT timings have to be applied Mode entry As long as the timing parameter tANPDmin is satisfied when ODT is turned on or off before entering these power down modes synchronous timing parameters can be applied If tANPDmin is not satisfied asynchronous timing parameters apply T 3 T 2 T 1 TO T1 T 5 T 4 ODT turn off tANPD gt 3 tck ODT Synchronous timings apply ODT turn off tANPD lt 3 tck ODT Asynchronous timings apply tAOFPDmax ODT tur
67. T and tLZ tRPRE parameters are referenced to a specific voltage level which specify when the device out put is no longer driving tHZ tRPST or begins driving tLZ tRPRE tHZ and tLZ transitions occur in the same access time windows as valid data transitions These parameters are verified by design and characterisation but not subject to production test The maximum limit for this parameter is not a device limit The device operate with a greater value for this parameter but System performance bus turnaround degrades accordingly tRAS max is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 tREFI A maximum of eight Auto Refresh commands can be posted to any given DDR2 SDRAM device The tRCD timing parameter is valid for both activate command to read or write command with and without Auto Precharge Therefore a separate parameter tRAP for activate command to read or write command with Auto Precharge is not neces sary anymore For each of the terms if not already an integer round to the next highest integer tCK refers to the application clock period WR refers to the WR parameter stored in the MRS tWTR is at least two clocks independent of operation frequency User can choose two different active power down modes for additional power saving via MRS address bit A12 In standard active power down mode MRS A12 0 a fast power down exit timing tXARD can be used In
68. T1 T2 T3 T4 T5 T6 T7 T8 CK CK LL 3j MEME Pg 4 2 on o Hom C8 G8 EAD w AP Activate l T T PG IP pi Pid i AL BL 2 Auto Pyecharge Begins 005 i DQS i 73 WM EEUU x AL 2 i CL 3 3 5 I 1 I DQ lt t I i u Ao ona M len Dout A3 3 34 I X de 4 tRCmin i i i i BR AP5231 Burst Read with Auto Precharge followed by an Activation to the Same Bank tRAS Limit RL 5 AL 2 CL 3 BL 4 tRTP lt 2 clocks i i H L i 1 H H CMD osted CAS NOP NOP NOP Bank fax T me ead 2 Activate NOP H M T T T H i i i 10 k Auto precharge Begins DQ H 1 Dout AO Dout A1 Dout A2 Dout A BR AP5232 Page 48 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Intineon 1Gb DDR2 SDRAM Burst Read with Auto Precharge followed by an Activation to the Same Bank RL 4 AL 1 CL 3 BL 8 tRTP lt 2 clocks TO T1 T2 T3 T4 T5 T6 T7 T8 CK CK a 1 cs 2 M a READ w AP 1 1 1 i A1
69. UDM are the input mask signals for x16 compo nents and control the lower or upper bytes For x8 components the data mask function is disabled when RDQS RQDS are enabled by EMRS 1 command BAO BA1 BA2 Input Bank Address Inputs BAO BA1 BA2 define to which of the 8 internal memory banks an Activate Read Write or Precharge command is being applied BAO and 1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle AO A13 Address Inputs Provides the row address for Activate commands and the column address and Auto Precharge bit A10 AP for Read Write commands to select one location out of the memory array in the respective bank A10 AP is sampled during a Precharge command to determine whether the Precharge applies to one bank A10 low or all banks A10 high If only one bank is to be precharged the bank is selected by BAO BA1 and BA2 The address inputs also provide the op code during Mode Register Set commands Row address A13 is used on x4 and x8 components only LDQx UDQx DQx Data Inputs Output Bi directional data bus DQ0 DQ3 for x4 components DQ0 DQ7 for x8 components LDQO LDQ7 and UDQ0 UDQ7 for x16 components Das DQS LDQS LDQS UDQS UDQS Data Strobe output with read data input with write data Edge aligned with read data centered with write data For the x16 LDQS corresponds to the data on LDQO LDQ7 UDQS corresponds to th
70. a D i edit j l A Precharge Valid CMD 5 H NOP H NOP H NOP M NOP Msg TT NOP y 1 1 1 CKE 1 ie 1 1 HRP lt I gt 1 H 1 1 Precharge Precharge Power Down Power Down Entry Exit Precharge may be an external command or an internal precharge following Write with AP PrePD Auto Refresh command to Power Down entry CKE can go low one clock after an Auto Refresh command ARPD When tRFC expires the DRAM is in Precharge Power Down Mode MRS EMRS command to Power Down entry T6 T7 Lm us U _ lMRD i t Enters Precharge Power Down Mode MRS_PD Page 58 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Intineon 1Gb DDR2 SDRAM 2 11 Other Commands 2 11 1 No Operation Command NOP The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between opera tions A No Operation Command is registered when CS is low with RAS CAS and WE held high at the rising edge of the clock A No Operation Command will not terminate a previous operation that is still executing such as a burst read or write cycle 2 10 Deselect Command The Deselect Command performs the same function as a No Operation Command Deselect Command occurs when CS is brought high th
71. a given DDR2 SDRAM will be adjusted to the same driver strength setting The maximum step count for adjustment is 16 and when the limit is reached further increment or decrement code has no effect The default setting may be any step within the maxi mum step count range When Adjust mode command is issued AL from previously set value must be applied Off Chip Driver Adjust Program 4 bit burst code inputs to all DQs Operation DT2 DrT3 Pull up driver strength Pull down driver strength 0 0 0 0 NOP no operation NOP no operation 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved Reserved Page 21 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM For proper operation of adjust mode WL RL 1 AL CL 1 clocks and 105 tDH should be met as the follow ing timing diagram Input data pattern for adjustment DTO DT3 is fixed and not affected by MRS addressing mode i e sequential or interleave Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment DQ in docs adjust
72. alid data DQ is driven onto the data bus The first bit of the burst is synchronized with the rising edge of the data strobe DQS Each subsequent data out appears on the DQ pin in phase with the DQS signal in a source synchronous manner The RL is equal to an additive latency AL plus CAS latency CL The CL is defined by the Mode Register Set MRS The AL is defined by the Extended Mode Register Set EMRS 1 Basic Burst Read Timing CLK CLK DGS DQS DQ tDasamax DO Read Examples Burst Read Operation RL 5 AL 2 CL 3 BL 4 TO T1 T2 T3 T4 T5 T6 T7 T8 CK CK U 4 oo L oe MD AH C HEAD A NOP H NOP H NOP H NOP I I I ENEEBSNUENNM pas wc e d Ded 505 I i A 1 I i AL 2 CL 3 RLS 5 DQ m I I os AO ona A1 Dout Dout I I I I i BRead523 Page 33 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM Burst Read Operation RL 3 AL 0 CL 3 BL 8 on Ks NOP a NOP H NOP H NOP H NOP H NOP H NOP H NOP c wee 1 l 1 h j my l I I e S 3 1 1 1 1 1 1
73. ally to the 25 Ohm termination resistor into VTT The SSTL_18 definition assumes that 335 mV must be developed across the effectively 25 Ohm termination resistor 13 4 mA x 25 Ohm 335 mV With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT at the out put device 13 4 mA 45 Ohm 603 mV 5 3 3 OCD Off Chip Driver Default Characteristics Symbol Description min nominal max Unit Notes gt Output Impedance 12 6 18 23 4 Ohms 1 2 Pull up Pull down mismatch 0 4 Ohms 1 2 3 Output Impedance step size for OCD calibration 0 a 1 5 Ohms 8 Sout Output Slew Rate 1 5 5 0 V ns 1 Es 6 1 1 8 V 0 1 V Vpp 1 8 V 0 1 V 2 Impedance measurement condition for output source dc current VDDQ 1 7 V VOUT 1420 mV VOUT VDDQ IOH must be less than 23 4 ohms for values of VOUT between VDDQ and VDDQ 280 mV Impedance measurement condition for output sink dc current VDDQ 1 7 V VOUT 280 mV VOUT IOL must be less than 23 4 ohms for values of VOUT between 0 V and 280 mV 3 Mismatch is absolute value between pull up and pull down both are measured at same temperature and voltage 4 Slew rates measured from VIL ac to VIH ac with the load specified in Section 8 2 5 The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC This is ver
74. ata strobe crossing VREF for a falling signal applied to the device under test DQS FS ren Differential Input Das 23 AP Waveform Single ended Input DQS B Waveform VREF min VREF Vit max V L ac max Vss Page 82 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 8 3 3 Slew Rate Definition for Input and Data Setup and Hold Times Setup tIS amp 105 nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF do and the first crossing of VIH ac min Setup tIS amp 105 nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF dc and the first crossing of VIL ac max If the actual signal is always earlier than the nominal slew rate line between shaded VREF dc to ac region use nominal slew rate for derating value see fig A If the actual signal is later than the nominal slew rate line anywhere between shaded VREF dc to ac region the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value see fig B Hold tlH amp tDH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL dc max and the first crossing of VREF dc Hold tlH amp tDH nominal slew rate for a falling signal is d
75. cular situations involving more than one bank enabling disabling on die termination Power Down entry exit among other things are not captured in full detail Page 13 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 2 Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a selected location and con tinue for the burst length of four or eight in a programmed sequence Accesses begin with the registration of an Activate command which is followed by a Read or Write command The address bits registered coincident with the activate command are used to select the bank and row to be accessed BAO BA2 select one of the eight banks A0 A13 select the row for x4 and x8 components AO A12 select the row for x16 components The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto Precharge command is to be issued Prior to normal operation the DDR2 SDRAM must be initialized The following sections provide detailed information covering device initial ization register definition command description and device operation 2 2 1 Power On and lnitialization DDR2 SDRAM s must be powered up and initialized in a predefined manner Operational procedures other than those specified may result in undefined operation The following sequenc
76. depending on system environment v MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS OCD calibration mode exit EMRS Drive 1 EMRS Drive 0 DQ amp DQS High DQSLow DQ amp DQS Low DQS High Calibration EMRS OCD calibration mode exit EMRS Enter Adjust Mode Y Need Calibration EMRS OCD calibration mode exit EMRS Enter Adjust Mode BL 4 code input to all DQs Inc Dec or NOP BL 4 code input to all DQg Inc Dec or NOP EMRS OCD calibration mode exit EMRS OCD calibration mode exit EMRS OCD calibration mode exit End Page 20 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM am Infineon Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS 1 mode In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS 1 bit enabling RDQS operation In Drive 1 mode all DQ DQS and RDQS signals are driven high and DQS and RDQS signals are driven low In Drive 0 mode DQ DQS and RDQS signals are driven low and all DQS and RDQS signals are driven high In adjust mode BL 4 of operation code data must be used In case of OCD calibration default output driver characteristics have a nominal impedance value of 18 Ohms during nominal temp
77. e 50 50 ps 8 tpH DQ and DM input hold time 175 175 ps 8 tpw Address and control input pulse width each input 0 6 0 6 tpipw DQ and DM input pulse width each input 0 35 0 35 tck tyz Data out high impedance time from CK CK tACmax tACmax ps 9 tLZ DQ low impedance time from CK CK 2 tACmin tACmax 2 tACmin tACmax ps 9 tLz Das DQS low impedance from CK CK tACmin tACmax tACmin tACmax ps 9 tpaso DQS DQ skew for DQS amp associated DQ signals 250 250 ps 18 tous Data hold skew factor 350 350 ps toH Data output hold time from DQS typ taHs tHP toHS tpass Write command to 1st DQS latching transition WL 0 25 WL 0 25 WL 0 25 WL 0 25 tcK tDQSL H DQS input low high pulse width write cycle 0 35 0 35 toss DQS falling edge to CK setup time write cycle 0 2 0 2 tpsH DQS falling edge hold time from CK write cycle 0 2 0 2 tmRD Mode register set command cycle time 2 2 tcK twPRE Write preamble 0 35 0 35 tck twPST Write postamble 0 40 0 60 0 40 0 60 10 tRPRE Read preamble 0 9 1 1 0 9 1 1 9 tRpsT Read postamble 0 40 0 60 0 40 0 60 9 tras Active to Precharge command 45 70000 45 70000 ns 11 tRC Active to Active Auto Refresh command period 60 57 ns tRFc Auto Refresh to Active Auto Refresh command period 127 5 127 5 z ns 12 e un s s ef mss Page 77 Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM
78. e RAS CAS and WE signals become don t care 2 12 Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions a During Self Refresh operation b DRAM is in precharged power down mode and ODT is completely turned off The DDR2 SDRAM has to be in Precharged Power down mode and idle ODT must be already turned off and CKE must be at a logic low state After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed A stable new clock frequency has to be provided before CKE can be changed to a high logic level again After tXP has been satisfied a DLL RESET command via EMRS 1 has to be issued During the following DLL re lock period of 200 clock cycles ODT must remain off After the DLL re lock period the DRAM is ready to operate with the new clock frequency Example Input frequency change during Precharge Power Down mode T4 Ty 1 2 Ty 3 ILE fou valid NOP NOP NOP N NOP NOP NOP RESET P ali Comman T J R T T T T H I T 7 Eomma 3 l 1 H 1 l 1 l 1 H L 1 T T l 1 I l 1 H 1 L 1 l 1 H 1 L 1 x Ro OX dk NE i GE i x i i i tXI 200 lock 3 gt Minimum 2 clocks gt i 1 i pel 4 2 8 56 t gt 1 Frequency Change Stable new clock required bef
79. e Registers For application flexibility burst length burst type CAS latency DLL reset function write recovery time WR are user defined variables and must be programmed with a Mode Register Set MRS command Additionally DLL disable function additive CAS latency driver impedance ODT On Die Termination single ended strobe and OCD off chip driver impedance adjustment are also user defined variables and must be programmed with an Extended Mode Register Set EMRS command Contents of the Mode Register MRS and Extended Mode Reg isters EMRS can be altered by re executing the MRS and EMRS Commands If the user chooses to modify only a subset of the MRS or EMRS variables all variables must be redefined when the MRS or EMRS commands are issued Also any programming of EMRS 2 or EMRS 3 must be followed by programming of MRS and EMRS 1 After initial power up all MRS and EMRS Commands must be issued before read or write cycles may begin All banks must be in a precharged state and CKE must be high at least one cycles before the Mode Regis ter Set Command can be issued Either MRS or EMRS Commands are activated by the low signals of CS RAS CAS and WE at the positive edge of the clock When all bank addresses BAO BA2 are low the DDR2 SDRAM enables the MRS command When the bank addresses BAO is high and BA1and BA2 are low the DDR2 SDRAM enables the EMRS 1 command The address input data during this cycle defines the parameters to be se
80. e data on UDQ0 UDQ7 The data strobes DQS LDQS UDQS may be used in single ended mode or paired with the optional complementary signals DQS LDQS UDQS to provide differential pair signaling to the system during both reads and writes An EMRS 1 control bit enables or disables the complementary data strobe signals RDQS RDQS Read Data Strobe For the x8 components a RDQS RDQS pair can be enabled via the EMRS 1 for read timing RDQS RDQS is not supported on x4 and x16 components RDQS RDQS are edge aligned with read data If RDQS RDQS is enabled the DM function is disabled on x8 components On Die Termination ODT registered HIGH enables termination resistance internal to the DDR2 SDRAM When enabled ODT is applied to each DQ DQS DQS and DM signal for x4 and DQ DQS DQS RDQS RDQS and DM ODT Input for x8 configurations For x16 configuration ODT is applied to each DQ UDQS UDQS LDQS LDQS UDM and LDM signal The ODT pin will be ignored if the Extended Mode Register EMRS 1 is programmed to disable ODT NC No Connect no internal electrical connection is present VDDQ Supply DQ Power Supply 1 8V 0 1V Vssa Supply DQ Ground VDDL Supply DLL Power Supply 1 8V 0 1V VSSDL Supply DLL Ground Vpp Supply Power Supply 1 8V 0 1V Vss Supply Ground VREF Supply Reference Voltage A14 A15 A14 A15 are additional address pins for future generation DRAMs and are n
81. e is required for POWER UP and Initialization 1 Apply power and attempt to maintain CKE below 0 2 VDDQ and ODT at a low state all other inputs may be undefined To guarantee ODT off VREF must be valid and a low level must be applied to the ODT pin Maximum power up interval for VDD VDDQ is specified as 10 0 ms The power interval is defined as the amount of time it takes for VDD VDDQ to power up from OV to 1 8 V 100 mV VDD VDDL and VDDQ are driven from a single power converter output AND VTT is limited to 0 95 V max AND VREF tracks VDDQ 2 or Apply VDD before or at the same time as VDDL Apply VDDL before or at the same time as VDDQ Apply VDDQ before or at the same time as VTT amp VREF at least one of these two sets of conditions must be met 2 Start clock CK CK and maintain stable power and clock condition for a minimum of 200 us 3 Apply NOP or Deselect commands amp take CKE high 4 Wait minimum of 400ns then issue a Precharge all command 5 Issue EMRS 2 command To issue EMRS 2 command provide low to BAO and BA2 and high to BA1 6 Issue EMRS 3 command To issue EMRS 3 command provide low to BA2 and high to BAO and BA1 7 Issue EMRS 1 command to enable DLL To issue DLL Enable command provide low to AO and high to BAO and low to BA1 BA2 and A13 A15 8 Issue MRS command Mode Register Set for DLL reset To issue DLL reset command provide high to A
82. e minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered however the clock must be restarted and stable before the device can exit Self Refresh operation The procedure for exiting Self Refresh requires a sequence of commands First the clock must be stable prior to CKE going back HIGH Once Self Refresh Exit command is registered a delay of at least tXSNR must be satis fied before a valid command can be issued to the device to allow for any internal refresh in progress CKE must remain high for the entire Self Refresh exit period tXSRD for proper operation Upon exit from Self Refresh the DDR2 SDRAM can be put back into Self Refresh mode after tXSNR expires NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR ODT should be turned off dur ing tXSRD The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode Upon exit from Self Refresh the DDR2 SDRAM requires a mini mum of one extra auto refresh command before it is put back into Self Refresh Mode T5 Tm am tr rr rm tis CKE ODT CMD i elf Retreat Entry CK CK may CK CK must be halted be stable
83. eady high prior to writing into the extended mode register The mode register set command cycle time tMRD must be satisfied to complete the write operation to the EMRS 1 Mode register con tents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state EMRS 1 Extended Mode Register Operation Table Address Input For Mode Set BA2 BA1 13 15 12 A11 A10 AQ A8 7 A6 5 A 2 AO Address Field vd yy 1 1 0 mm Register 2 Rtt nom A11 9005 Enable 0 ODT disabled po T mom ESL 150 ohm DLL Enable 1 Enable 0 Enable 5 RDQS Disable AdditiveLatency a Disables DQ DQS DQS RDQS RDQS 0 Enable fo 0 qe 3 m rept pop ZETU S eumd FC 9 1 sN 1 1 1 Reserved OCD Cal Mode Exit maintain setting Output Driver Driver A1 Drive 1 Impedence Control Size Drive 0 1 a When Adjust mode is issued AL from previously set value must be applied b After setting to default OCD mode needs to be exited by setting A9 A7 to 000 Refer to the following 2 2 2 5 section for detailed information OCD Calibration Program must be programmed to 0 for compatibility with future DDR2 memory produc
84. echarge at the earliest possible moment during the burst read or write cycle If A10 is low when the Read or Write Command is issued then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence If A10 is high when the Read or Write Command is issued then the Auto Precharge function is enabled During Auto Precharge a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency CL clock cycles before the end of the read burst Auto Precharge is also implemented for Write Commands The Pre charge operation engaged by the Auto Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array This feature allows the precharge operation to be partially or completely hidden during burst read cycles dependent upon CAS Latency thus improving system performance for random data access The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the Auto Precharge command may be issued with any read or write com mand 2 8 1 Burst Read with Auto Precharge If A10 is high when a Read Command is issued the Read with Auto Precharge function is engaged The DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is AL BL 2 cycles later from the Read with AP command if tRAS min
85. efined as the slew rate between the last crossing of VIH dc min and the first crossing of VREF dc If the actual signal is always later than the nominal slew rate line between shaded dc to VREF region use nominal slew rate for derat ing value see fig A If the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to VREF dc region the slew rate of a tangent line to the actual signal from the dc level to VREF level is used for derating value see fig B TZS TZS CK CK for tIS and CK CK for tIS and DQS DQS for tDS and tDH DQS DQS for tDS and tDH l UH tis tin us tua tps ths tDH tps tbH tps tDH v aia aa e epe ee Cap Oe eee Se Seta ee ee oy es ee ool mA IUE DDQ VREF to ac NI ViH ac min VREF to ac region do to VREF IH dcymin region Bi N VREF A VREF dc to VREF egion region V Vit max VRE IL dc VREF to ac regidn wed region Vit ac max Vit ac max Sap ee 4 4 Vss Rees oe oa ea ee Vss gt e gt 4 gt F lt lt Me lt gt Delta TFS Delta TRH Delta TRS Delta TFH Delta TFS DeltaTRH DeltaTRS Delta TFH tangent line nominal line
86. enter top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 4 2 DRAM Component Operating Temperature Range Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 oc 1 4 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The operating temperature range are the temperatures where all DRAM specification will be supported During operation the DRAM case temperature must be maintained between 0 95 C under all other specification parameters 3 Some application may require to operate the DRAM up to 95 C case temperature In this case above 85 C case temperature the Auto Refresh command interval has to be reduced to tREFI 3 9 us 4 Self Refresh period is hard coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self refresh operation Page 63 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 5 AC amp DC Operating Conditions 5 1 DC Operating Conditions 5 1 1 Recommended DC Operating Conditions SSTL_18 Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 7 1 8 1 9 V 1 VDDDL Supply Voltage for DLL 1 7 1 8 1 9 V 1 VDDQ Supply Voltage for Outp
87. erature and voltage conditions Output driver characteristics for OCD calibration default are specified in the following table OCD applies only to normal full strength output drive setting defined by EMRS 1 and if half strength is set OCD default driver charac teristics are not applicable When OCD calibration adjust mode is used OCD default output driver characteristics are not applicable After OCD calibration is completed or driver strength is set to default subsequent EMRS 1 commands not intended to adjust OCD characteristics must specify A7 A9 as 000 in order to maintain the default or calibrated value Off Chip Driver program A9 A8 A7 Operation OCD calibration mode exit Drive 1 DQ DQS RDQS high and DQS RDQS low Drive 0 DQ DQS RDQS low and DQS RDQS high Adjust mode OCD calibration default gt O gt O gt OCD impedance adjust To adjust output driver impedance controllers must issue the ADJUST EMRS 1 command along with a 4 bit burst code to DDR2 SDRAM as in the following table For this operation Burst Length has to be set to BL 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time DTO in the table means all DQ bits at bit time 0 DT1 at bit time 1 and so forth The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration all DQs of
88. exit timing tXARD fast exit or tXARDS slow exit depends on the programmed state in the MRS address bit A12 Active Power Down Mode Entry and Exit after a Read Command RL 4 AL 1 CL 23 BL 4 Ti T3 T7 Tn 1 Tn 2 0 T1 T2 T4 T5 T6 Tn AAA i i i READ NOP NOP P nop valle T NOR JA NOR NOP 9 Command E RLE BU 0 i i Ais Das d j r r a t amp XARD 10 tXARDS DQ i H Active Active Power Down Power Down Act PD 1 Entry Exit note Active Power Down mode exit timing tXARD fast exit or IXARDS slow exit depends on the programmed state in the MRS address bit A12 Page 56 Rev 1 02 May 2004 INFINEON Technologies am Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM Active Power Down Mode Entry and Exit after a Write Command WL 2 tWTR 2 BL 4 state in the MRS address bit A12 TO T1 T2 T3 T4 T5 T6 T7 Tn Tn 1 2 _ yy prep rm Le YER EX ERY LL E ti i N pom i DE Icd P A cd CMD 4 write NOP NOP NOP NOP NOP GE CKE i DOS Popo eh i DQs _ i oS NE ME ARDor a P 1 H gt di i tXARDS
89. f differential clocks CK rising and CK fall ing All I Os are synchronized with a single ended DQS or dif ferential DQS DQS pair in a source synchronous fashion A 17 bit address bus for x 4 and x 8 organised components and a 16 bit address bus for x16 components is used to convey row column and bank address information in a RAS CAS multi plexing style The DDR2 devices operate with a 1 8V 0 1V power supply and are available in FBGA packages An Auto Refresh and Self Refresh mode is provided along with various power saving power down modes The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation Page 3 Rainer Weidlich Infineon com Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 1 1 Ordering Information CAS Clock Speed DA Part Number Latency MHz Sort DRAM Organisation Package HYB18T1G400AF L 5 8 banks x 32 Mbits x 4 68 pin FBGA HYB18T1G800AF L 5 3 485 200 DDR2 400 8 banks x 16 Mbits x 8 68 pin FBGA HYB18T1G160AF L 5 8 banks x 8 Mbits x 16 92 pin FBGA HYB18T1G400AF L 3 7 8 banks x 32 Mbits x 4 68 pin FBGA HYB18T1G800AF L 3 7 4 amp 5 266 DDR2 533 8 banks x 16 Mbits x 8 68 pin FBGA HYB18T1G160AF L 3 7 8 banks x 8 Mbits x 16 92 pin FBGA HYB18T1G400AF L 3 8 banks x 32 Mbits x 4 68 pin FBGA HYB18T1G800AF L
90. gments defined by CA0 CA7 beginning with the column address supplied to the device during the Read or Write Command 9 amp 11 A new burst access must not interrupt the previous 4 bit burst operation in case of BL 4 setting Therefore the minimum CAS to CAS delay tCCD is a minimum of 2 clocks for read or write cycles For 8 bit burst operation BL 8 the minimum CAS to CAS delay tCCD is 4 clocks for read or write cycles Burst interruption is allowed with 8 bit burst operation For details see the Burst Interrupt Section of this datasheet Example Read Burst Timing Example CL 3 AL 0 RL 3 BL 4 DQ ow AO oa A1 D I I Dout A24 Dout I I I ia ee b Page 29 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 2 6 1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM In this operation the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command or any time during the RAS to CAS delay time tRCD period The command is held for the time of the Additive Latency AL before it is issued inside the device The Read Latency RL is the sum of AL and the CAS latency CL Therefore if a user chooses to issue a Read Write command before the tRCDmin then AL greater
91. ified by design and characterisation but not subject to production test 6 DRAM output slew rate specification applies to 400 533 and 667 MT s speed bins 7 Timing skew due to DRAM output slew rate mis match between DQS DQS and associated DQ s is included in tDQSQ and tQHS specifi cation 8 This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty A 0 Ohm value no calibration can only be achieved if the OCD impedance is 18 0 75 ohms under nominal condi tions Page 67 Rev 1 02 May 2004 INFINEON Technologies e Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 5 4 Default Output V I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS 1 bits A7 A9 111 Figures in Section 5 3 5 and 5 3 6 show the driver characteristics graphically and the tables sow the same data suitable for input into simulation tools 5 4 1 Full Strength Default Pull up Driver Characteristics Pull up Driver Current mA Voltage V Minimum Nominal Default low Nominal Default high Maximum 0 2 8 5 11 1 11 8 15 9 0 3 12 1 16 0 17 0 23 8 0 4 14 7 20 3 22 2 31 8 0 5 16 4 24 0 27 5 39 7 0 6 17 8 27 2 32 4
92. igh activates and CKE low deactivates internal clock signals and device input buffers and out put drivers Taking CKE low provides Precharge Power Down and Self Refresh operation all banks idle or Active Power Down row Active in any bank CKE is synchronous for power down entry and exit and for self refresh entry Input buffers excluding CKE are disabled during self refresh CKE is used asynchronously to detect self refresh exit condition Self refresh termination itself is synchronous After VREF has become stable during power on and initiali sation sequence it must be maintained for proper operation of the CKE receiver For proper self refresh entry and exit VREF must be maintained to this input CKE must be maintained high throughout read and write accesses Input buffers excluding CK CK ODT and CKE are disabled during dower down Input Chip Select All command are masked when CS is registered high CS provides for external rank selection on sys tems with multiple memory ranks CS is considered part of the command code RAS CAS WE Input Command Inputs RAS CAS and WE along with CS define the command being entered DM LDM UDM Input Input Data Mask DM is an input mask signal for write data Input data is masked when DM is sampled high coinci dent with that input data during a Write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading LDM and
93. in this table The ODT function is not available during Self Refresh X means H or L but a defined logic level Operation that is not specified is illegal and after such an event in order to guarantee proper operation the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue Page 61 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 3 2 Clock Enable CKE Truth Table for Synchronous Transitions CKE Command 3 12 Current State Previous Current Action N 3 Notes Cycle Cycle RAS CAS WE CS N 1 N L L X Maintain Power Down 11 13 15 Power Down L H DESELECT or NOP Power Down Exit 4 8 11 13 L L X Maintain Self Refresh 11 15 Self Refresh L H DESELECT or NOP Self Refresh Exit 4 5 9 Bank pe H L DESELECT or NOP Active Power Down Entry 4 8 10 11 13 H L DESELECT or NOP Precharge Power Down Entry 4 8 10 11 All Banks Idle H L AUTOREFRESH Self Refresh Entry 6 9 11 13 Any State other H H Refer to the Command Truth Table 7 than listed above 1 CKE N is the logic state of CKE at clock edge N CKE N 1 was the state of CKE at the previous clock edge 2 Current state is the state of the DDR2 SDRAM immediately prior to clock edge N 3 4 5 Command N is the command registered at clock edge N and Action N is a result
94. l the Precharge command can be issued This delay is known as a write recovery time tWR referenced from the completion of the burst write to the Pre charge command No Precharge command should be issued prior to the tWR delay as DDR2 SDRAM does not support any burst interrupt by a Precharge command tWR is an analog timing parameter see the AC table in this datasheet and is not the programmed value for tWR in the MRS Examples Burst Write followed by Precharge WL RL 1 3 BL 4 tWR 3 t GEC am ewe 1 l i Completion of the Burst Write II I I I I I I i on rolon a3 I i l l l H DQ 4 4 esse BW P3 NOP H NOP H 1 Completion of hr ee Burst Write CMD Jj Post CAS NOP Precharge WRITE A A 005 DQ Page 46 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 8 Auto Precharge Operation Before a new row in an active bank can be opened the active bank must be precharged using either the Pre charge Command or the Auto Precharge function When a Read or a Write Command is given to the DDR2 SDRAM the CAS timing accepts one extra address column address A10 to allow the active bank to automati cally begin pr
95. lowed regardless of same or different banks as long as the banks are activated Seamless Burst Read Operation RL 3 AL 0 CL 3 BL 8 non interrupting TO T1 T2 T3 T4 T5 T6 T7 T8 T9 Post CAS SBR BL8 The seamless non interrupting 8 bit burst read operation is supported by enabling a read command at every BL 2 number of clocks This operation is allowed regardless of same or different banks as long as the banks are acti vated Page 35 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 2 6 4 Burst Write Command The Burst Write command is initiated by having CS CAS and WE low while holding RAS high at the rising edge of the clock The address inputs determine the starting column address Write latency WL is defined by a read latency RL minus one and is equal to AL CL 1 A data strobe signal DQS has to be driven low preamble a time tWPRE prior to the WL The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble The tDQSS specification must be satisfied for write cycles The subse quent burst bit data are issued on successive edges of the DQS until the burst length is completed When the burst has finished any additional data supplied to the DQ pins will be ignored The DQ signal is ignored after the burst write operation is complete The time from the
96. ls need to be adjusted to a wider range as a result of any system calibration error Since this is a system specific phenomena it cannot be quantified here The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only If the calibration procedure is used it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure In such a situation the timing parameters in the specifica tion cannot be guaranteed It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times If this can t be guaranteed by the system calibration proce dure re calibration policy and uncertainty with DQ to DQ variation it is recommended that only the default values to be used The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum con ditions If calibrated at an extreme condition the amount of variation could be as much as from the nominal mini mum to the nominal maximum or vice versa Full Strength Calibrated Pull down Driver Characteristics Calibrated Pull down Driver Current mA Voltage V Nominal Minimum Normal Low Nominal Normal High Nominal Maximum 21 Ohms 18 75 Ohms 18 ohms 17 25 Ohms 15 Ohms 0 2 9 5 10 7
97. mode DTO DT1 jore DT3 7 i H H OCD calitiration mode exit Drive Mode Drive mode both Drive 1 and Drive 0 is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment In this mode all outputs are driven out tOIT after enter drive mode com mand and all output drivers are turned off tOIT after OCD calibration mode exit command as the following timing diagram Enter Drive Mode ocp calibration mode exit Page 22 Rev 1 02 May 2004 INFINEON Technologies T HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 5 On Die Termination ODT ODT On Die Termination is a new feature on DDR2 components that allows a DRAM to turn on off termination resistance for each DQ DOS DQS and DM for x4 and DQ DQS DQS DM RDQS DM and RDQS share the same pin and RDQS for x8 configuration via the ODT control pin where DQS is terminated only when enabled in the EMRS 1 by address bit A10 0 For x8 configuration RDQS is only terminated when enabled in the EMRS 1 by address bits A10 0 and A11 1 For x16 configuration ODT is applied to each UDQ LDQ UDQS UDQS LDQS LDQS UDM and LDM signal via the ODT control pin where UDQS and LDQS are terminated only when enabled in the EMRS 1 by address bit A10 0 The ODT feature is designed to improve signal integrity of the memory channel by allowing the
98. n on tANPD gt 3 tck ob Synchronous timings apply tAONPDmax ODT turn on tANPD 3tck Asynchronous timings apply ODT Page 26 Rev 1 02 May 2004 INFINEON Technologies amm Infineon Mode exit HYB18T1G400 800 160AF 1Gb DDR2 SDRAM As long as the timing parameter tAXPDmin is satisfied when ODT is turned on or off after exiting these power down modes synchronous timing parameters can be applied If tAXPDmin is not satisfied asynchronous timing parameters apply CKE T8 T10 tAXPD TO T1 TERS 2 mn ODT turn off tAXPD gt tAXPDmin Synchronous ODT timings apply ODT turn off tAXPD lt tAXPDmin Asynchronous ODT timings apply ODT turn on tAXPD gt tAXPDmin Synchronous timings apply ODT ODT turn on tAXPD lt tAXPDmin Asynchronous ODT timings apply LIO NV nee tAONPDmax ODTO4 Page 27 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 5 Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock The bank addresses BAO BA2 are used to select the desired bank The row addresses AO through A13 are used to determine which row to activate in the selected bank for x4 and x8 organised components For x16 components row addresses AO through A12
99. ne Burst Write i DQS 1 1 1 NE i I 1 l l 1 1 WL RL 1 2 i DQ i DIN sofon i X i BW322 NY cd Write to Read CL 1 BL 2 BU CMD NOP NOP Pos CAS NOP NOP NOP m s jg T x EM DQS t y I LAC u A l dade E o i i i L cm wann oM DQ a 5 i i T i EE Lolo j dimisi BWBR The minimum number of clocks from the burst write command to the burst read command is CL 1 BL 2 tWTR where tWTR is the write to read turn around time tWTR expressed in clock cycles The tWTR is not a write recov ifiers in the ery time tWR but the time required to transfer 4 bit write data from the input buffer into sense ampl array Page 37 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Seamless Burst Write Operation RL 5 WL 4 BL 4 CMD Post CAS Post CAS G EEE my am ME i WL RL 1 4 1 oooh hA on sofon safon sofon B1 DIN B2 DIN SBR DQ The seamless burst write operation is supported by enabling a write command every BL 2 number of clocks This operation i
100. nk Page 51 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 8 4 Concurrent Auto Precharge DDR2 devices support the Concurrent Auto Precharge feature A Read with Auto Precharge enabled or a Write with Auto Precharge enabled may be followed by any command to the other bank as long as that command does not interrupt the read or write data transfer and all other related limitations e g contention between Read data and Write data must be avoided externally and on the internal data bus The minimum delay from a Read or Write command with Auto Precharge enabled to a command to a different bank is summarized in the table below As defined the WL RL 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized To Command Minimum Delay with From Command different bank Concurrent Auto Pre Units Note non interrupting command charge Support Read or Read w AP CL 1 BL 2 tCK WRITE w AP Write or Write w AP BL 2 tCK Precharge or Activate 1 tCK 1 Read or Read w AP BL 2 tCK Read w AP Write or Write w AP BL 2 2 Precharge or Activate 1 1 Note 1 This rule only applies to a selective Precharge command to another banks a Precharge All command is illegal Page 52 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Intineon 1Gb DDR2 SDRAM 2 9 Refresh
101. nt power saving modes can be selected within the MRS register address bit A12 When A12 is set to low this mode is referred as standard active power down mode and a fast power down exit timing defined by the tXARD timing parameter can be used When A12 is set to high this mode is referred as a power saving low power active power down mode This mode takes longer to exit from the power down mode and the tXARDS timing parameter has to be satisfied Entering power down deactivates the input and output buffers excluding CK CK ODT and CKE Also the DLL is disabled upon entering Precharge Power down or slow exit active Power down but the DLL is kept enabled dur ing fast exit active power down In power down mode CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM and all other input signals are Don t Care Power down duration is limited by 9 times tREFI of the device The power down state is synchronously exited when CKE is registered high along with a NOP or Deselect com A valid executable command can be applied with power down exit latency tXP tXARD or tXARDS after CKE goes high Power down exit latencies are defined in the AC spec table of this data sheet Power Down Entry Active Power down mode can be entered after an activate command Precharge Power down mode can be entered after a Precharge Precharge All or internal precharge command It is also allowed to enter power mode after an Au
102. ore ODT is off during Occurs here before power down exit changing the frequency DLL RESET Frequ Ch Page 59 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 2 13 Asynchronous CKE Low Reset Event In a given system Asynchronous Reset event can occur at any time without prior knowledge In this situation memory controller is forced to drop CKE asynchronously low immediately interrupting any valid operation DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet If CKE asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of the memory array If this event occurs the memory controller must satisfy a time delay tdelay before turning off the clocks Stable clocks must exist at the input of DRAM before CKE is raised high again The DRAM must be fully re initialized as described the initialization sequence section 2 2 1 step 4 thru 13 DRAM is ready for normal operation after the initialization sequence See AC timing parametric table for tgejay specification stable clocks CKE drops low due to an Clocks can be turned off after asynchronous reset event this point Page 60 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM
103. ot connected on this component Page 9 Rev 1 02 May 2004 INFINEON Technologies Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 1 6 Block Diagrams Note This Functional Block Diagram is intended to facilitate user understanding of the operation of Row Address Latch amp Decoder Bank Control Logic o CK CS WE 2 138 9 WE CAS RAS 9 5 x 3 gt Bl Registers E g 4T 1 lt l gt 7 AP BE c i gt s 16 e i D 7 e 9 2 A0 A13 TN v 8 77 BAO BA2 4 8 I m ace ene lt yp H1M Column Address Counter Latch 16384 x 512 16 Gating DM Mask Logic p 8 1512 x16 Column Decoder 9 a lt CcsOoL o 1 2 Sense Amplifiers a CK DLL Data s 8 94 x 3 gt 1 60 2 pos a Generator N DQ0 DQ3 P 005 gt om Input DOS Register gt 005 Write Mask 1 le DQS FIFO 1 1 16 amp lt 1 Drivers 7 1 1 4 lt 1 1 o lt e 4 D 4 lt 4 4 16 lt 4 44 I Data 4 4 lt CK CK COLO 1
104. rol and address inputs are STA DD2P BLE Data Bus inputs are FLOATING Precharge Standby Current All banks idle CS is HIGH CKE is HIGH tCK tCK IDD Other control and address bus inputs DD2N are SWICHTING Data bus inputs are SWITCHING Precharge Quiet Standby Current All banks idle CS is HIGH is HIGH tCK tCK IDD Other control and address bus DD2Q inputs are STABLE Data bus inputs are FLOATING Active Power Down Current All banks open tCK tCK IDD CKE is LOW Other control and address inputs are STABLE DD3P 0 Bus inputs are FLOATING MRS 12 bit is set to 0 Fast Power down Exit Active Power Down Current All banks open tCK tCK IDD CKE is LOW Other control and address inputs are STABLE DD3P 1 Data Bus inputs are FLOATING MRS A12 bit is set to 1 Slow Power down Exit Active Standby Current All banks open tCK IDD tRAS tRASmax IDD tRP IDD CKE is HIGH CS is DD3N HIGH between valid commands Other control and address inputs are SWITCHING Data Bus inputs are SWITCHING Operating Current Burst Read All banks open Continuous burst reads BL 4 AL 0 CL CL IDD tCK IDD Ipp4R tRAS tRASmax IDD tRP IDD CKE is HIGH CS is HIGH between valid commands Address inputs are SWITCH ING Data bus inputs are SWITCHING IOUT 0mA Operating Current Burst Write All banks open Continuous burst writes BL 4 AL 0 CL CL
105. rting adress Sequential Addressing decimal Interleave Addressing decimal A2 A1 A0 x00 0 1 2 3 0 1 2 3 x01 1 2 3 0 1 0 3 2 4 x10 2 3 0 1 2 3 0 1 x11 3 0 1 2 3 2 1 0 000 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 001 1 2 3 0 5 6 7 4 1 0 3 2 5 4 7 6 010 2 3 0 1 6 7 4 5 2 3 0 1 6 7 4 5 011 3 0 1 2 7 4 5 6 3 2 1 0 7 6 5 4 8 100 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 101 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 110 6 7 4 5 2 3 0 1 6 7 4 5 2 3 0 1 111 7 4 5 6 3 0 1 2 7 6 5 4 3 2 1 0 Notes 1 Page length is a function of I O organization 256 Mb x 4 organization CA0 CA9 CA11 Page Size 1 kByte 128 Mb x 8 organization CA0 CA9 Page Size 1 kByte 64 Mb x 16 organization CA0 CA9 Page Size 2 kByte 2 Order of burst access for sequential addressing is nibble based and therefore different from SDR or DDR components Page 32 Rev 1 02 May 2004 INFINEON Technologies T HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 6 3 Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock The address inputs determine the starting column address for the burst The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency RL The data strobe output DQS is driven low one clock cycle before v
106. s allowed regardless of same or different banks as long as the banks are activated Seamless Burst Write Operation RL 3 WL 2 BL 8 non interrupting ne eee oe DQ I DIN sofon on A7 DIN J fes B2 DIN de ssl DIN H 1 H 1 H I SBW_BL8 The seamless non interrupting 8 bit burst write operation is supported by enabling a write command at every BL 2 number of clocks This operation is allowed regardless of same or different banks as long as the banks are acti vated Page 38 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 2 6 5 Write Data Mask One write data mask input DM for x4 and x8 components and two write data mask inputs LDM UDM for x16 components are supported on DDR2 SDRAWM s consistent with the implementation on DDR SDRAM s It has identical timings on write operations as the data bits and though used in a uni directional manner is internally loaded identically to data bits to insure matched system timing Data mask is not used during read cycles If DM is high during a write burst coincident with the write data the write data bit is not written to the memory For x8 com ponents the DM function is disabled when RDQS RDQS are enabled by EMRS 1 Write Data Mask Timing tposu tpast gt DQ DM
107. t as shown in the MRS and EMRS table A new command may be issued after the mode register set command cycle time tMRD MRS EMRS and DLL Reset do not affect array contents which means reinitializazion including those can be executed any time after power up without affecting array contents 2 2 3 DDR2 SDRAM Mode Register Set MRS The mode register stores the data for controlling the various operating modes of DDR2 SDRAM It programs CAS latency burst length burst sequence test mode DLL reset WR write recovery and various vendor specific options to make DDR2 SDRAM useful for various applications The default value of the mode register is not defined therefore the mode register must be written after power up for proper operation The mode register is written by asserting low on CS RAS CAS WE BAO BA1 and 2 while controlling the state of address pins AO A13 The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register The mode register set command cycle time tMRD is required to complete the write operation to the mode register The mode register contents can be changed using the same command and clock cycle require ments during normal operation as long as all banks are in the precharge state The mode register is divided into various fields depending on functionality Burst length is defined by AO A2 with options of 4 and 8 bit burst length Burst address sequence type is defined b
108. te Definition for Input and Data Setup and Hold Time 8 3 4 Input Setup and Hold Time Derating Table 8 3 5 Data Setup and Hold Time Derating Table 8 4 Overshoot and Undershoot Specification 9 Package Dimensions 10 DDR2 Component Nomenclature Page 89 Rev 1 02 May 2004 HYB18T1G400 800 160AF 1Gb DDR2 SDRAM INFINEON Technologies
109. terval 19 85 C 95 C 3 9 3 9 us toir OCD drive mode output delay 0 12 0 12 ns Minimum time clocks remain ON after CKE asynchro tDELAY nously drops LOW tIS tCK tlH tIS tCK tlH ns 17 Timing that is not specified is illegal and after such an event in order to guarantee proper operation the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue Page 78 Rev 1 02 May 2004 INFINEON Technologies amm Infineon HYB18T1G400 800 160AF 1Gb DDR2 SDRAM 7 3 ODT AC Electrical Characteristics and Operating Conditions all speed bins Symbol Parameter Condition min max Units Notes taOND ODT turn on delay 2 2 400 amp 533 tAC min tAC max 1 ns ns 20 tAON ODT turn on 667 tAC min tAC max 0 7 ns tAONPD ODT turn on Power Down Modes tAC min 2 ns 2 tcK tAC max 1 ns ns taoFD ODT turn off delay 2 5 2 5 tAOF ODT turn off tAC min tAC max 0 6 ns ns 21 taorPD ODT turn off Power Down Modes tAC min 2 ns 2 5 tek tAC max 1 ns ns tANPD ODT to Power Down Mode Entry Latency 3 tcK tAXPD ODT Power Down Exit Latency 8 79 Rev 1 02 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM 7 4 Notes for Electrical Characteristics amp AC Timing ON O gt 10 11 12 13 14 15 16
110. to Refresh command or MRS EMRS 1 command when tMRD is satisfied Active Power down mode entry is prohibited as long as a Read Burst is in progress meaning CKE should be kept high until the burst operation is finished Therefore Active Power Down mode entry after a Read or Read with Auto Precharge command is allowed after RL BL 2 is satisfied Active Power down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress In case of a write command active power down mode entry is allowed when WL BL 2 tWTR is satisfied In case of a write command with Auto Precharge Power down mode entry is allowed after the internal precharge command has been executed which is WL BL 2 WR starting from the write with Auto Precharge command In case the DDR2 SDRAM enters the Precharge Power down mode Page 55 Rev 1 02 May 2004 INFINEON Technologies m HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Examples Active Power Down Mode Entry and Exit after an Activate Command 2 I r a I r m h I CK CK x AEN La ENDE V x gt a o Es z EZ pa 3 a gt a I 1 1 H H H i I i E i E i i tXARDS i i T Act PD 0 Active Active Power Down Power Down Entry Exit note Active Power Down mode
111. to low 1 bit set to high ODT timing modes Depending on the operating mode synchronous or asynchronous ODT timings apply Synchronous timings tAOND tAOFD tAON and tAOF apply for all modes when the on die DLL is not disabled These modes are Active Mode Standby Mode Fast Exit Active Power Down Mode with MRS bit A12 is set to 0 Asynchronous ODT timings AOFPD tAONPD apply when the on die DLL is disabled These modes are Slow Exit Active Power Down Mode with MRS bit A12 is set to 1 Precharge Power Down Mode Page 24 Rev 1 02 May 2004 INFINEON Technologies Infi HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM ODT Timing for Active and Standby Idle Modes Synchronous ODT timings CKE see note 1 H TO T1 T2 T3 T4 T5 T6 T7 T8 LE cr tAOND 2 tck i tAOFD 2 5 tek DQ tAOF min a tAON max tAOF max ODT01 1 Synchronous ODT timings apply for Active Mode and Standby Mode with CKE high and for the Fast Exit Active Power Down Mode MRS bit A12 set to 0 In all these modes the on die DLL is enabled 2 ODT turn on time taON min is when the device leaves high impedance and ODT resistance begins to turn on ODT turn time max tAON max is when the ODT resistance is fully on Both are measured from tAOND 3 ODT turn off time min taOF min is when the device starts to turn off the ODT resistance
112. ts Page 17 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF 1Gb DDR2 SDRAM HYB18T1G400 800 160AF 1Gb DDR2 SDRAM AO is used for DLL enable or disable A1 is used for enabling half strength data output driver A2 and A6 enables ODT On Die termination and sets the Rtt value A3 A5 are used for additive latency settings and A7 A9 enables the OCD impedance adjustment mode A10 enables or disables the differential DQS and RDQS signals A11 disables or enables RDQS Address bit A12 have to be set to low for normal operation With A12 set to high the SDRAM outputs are disabled and in Hi Z High on BAO and low for BA1 and BA2 have to be set to access the EMRS 1 A13 and all higher address bits have to be set to low for compatibility with other DDR2 memory products with higher memory densities Refer to the table for specific codes on the previous page Single ended and Differential Data Strobe Signals The following table lists all possible combinations for DQS DQS RDQS RQDS which can be programmed by A10 amp A11 address bits in EMRS 1 RDQS and RDQS are available in x8 components only If RDQS is enabled in x8 components the DM function is disabled RDQS is active for reads and don t care for writes EMRS 1 Stobe Function Matrix Signaling A11 A10 RDQS Enable 095 Enable RDQS DM RDQS pas DQS 0 Disable 0 Enable DM Hi Z DQS
113. urst interruption is allowed to any bank inside the DDR2 SDRAM Read or Write burst with Auto Precharge enabled is not allowed to be interrupted Read burst interruption is allowed by a Read with Auto Precharge command Write burst interruption is allowed by a Write with Auto Precharge command All command timings are referenced to burst length set in the mode register They are not referenced to the actual burst For example Minimum Read to Precharge timing is AL BL 2 where BL is the burst length set in the mode register and not the actual burst which is shorter because of interrupt Minimum Write to Precharge timing is WL BL 2 tWR where tWR starts with the rising clock after the un interrupted burst end and not form the end of the actual burst end Examples Read Burst Interrupt Timing Example CL 3 AL 0 RL 3 BL 8 D 4 D i u 1 I I i t I l Dout AO Dout A1 Dout B4 Dout B5 Dout B6 Dout h I 1 I I l I RBI Page 40 Rev 1 02 May 2004 INFINEON Technologies Inf HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM Write Burst Interrupt Timing Example CL 3 AL 0 WL 2 BL 8 TO T1 T2 T3 T4 T5 T6 T7 T8 qom ferm s p CK CK 5 DN vena L 1 CMD NOP H NOP H I 1 1 1 pas i 005 1 f
114. ut 1 7 1 8 1 9 V 1 VREF Input Reference Voltage 0 49 VDDQ 0 5 VDDQ 0 51 VDDQ V 2 3 VTT Termination Voltage VREF 0 04 VREF VREF 0 04 V 4 1 VDDQ tracks with VDD VDDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDDL tied together 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF dc 4 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in die dc level of VREF 5 1 2 ODT DC Electrical Characteristics Parameter Condition Symbol min nom max Units Notes Rtt eff impedance value for EMRS 1 A6 A2 0 1 75 ohm Rtt1 eff 60 75 90 Q 1 Rtt eff impedance value for EMRS 1 A6 A2 1 0 150 ohm Rtt2 eff 120 150 180 Q 1 Deviation of VM with respect to VDDQ 2 delta VM 6 00 6 00 2 1 Measurement Definition for Rtt eff Apply ViH ac and to test pin separately then measure current I VIHac and I VILac respectively Rtt eff VIH ac VIL ac I VIHac I ViLac 2 Measurement Definition for VM Measure voltage VM at test pin midpoint with no load delta VM 2 VM VDDQ 1 x 100
115. ut logic high VREF 0 250 V VIL ac AC input low VREF 0 250 V 5 2 2 Single ended AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0 5 VDDQ V 1 2 VSWING max Input signal maximum peak to peak swing 1 0 V 1 2 SLEW Input signal minimum slew rate 1 0 V ns 3 4 E This timing and slew rate definition is valid for all single ended signals except tis tih tds tdh 2 Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test 3 The input signal minimum slew rate is to be maintained over the range from VIL dc max to VIH ac min for rising edges and the range from VIH dc min to VIL ac max for falling edges as shown in the below figure 4 AC timings are referenced with input waveforms switching from VIL ac to VIH ac on the positive transitions and VIH ac to ViL ac on the negative transitions Start of Falling Edge Input Timing Start of Rising Edge Input Timing V ee SS Lc DDQ ViH ac min eS Vin de min ue I VREF MiL dc VswING MAX max V ERES rd 55 delta lt delta TR min Vi max MIN Vi max Falling Slew Rising Slew delta TF delta TR Page 65 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM
116. ut slew rate is veri fied by design but not subject to production test 8 2 2 Input Slewrate Differential signals Input slewrate for differential signals CK CK DQS DQS RDQS RDQS for rising edges are measured from f e CK CK 250 mV to CK CK 500 mV and from CK CK 250 mV to CK CK 500mV for falling edges 8 2 3 Input Slewrate Single ended signals Input slew rate for single ended signals other than tis tih tds and tdh are measured from dc level to ac level VREF 125 mV to VREF 250 mV for rising edges and from VREF 125 mV to VREF 250 mV for falling edges For slew rate definition of the input and data setup and hold parameters see section 8 3 of this datasheet Page 81 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Chien 1Gb DDR2 SDRAM 8 33 Input and Data Setup and Hold Time 8 3 1 Timing Definition for Input Setup tlS and Hold Time Address and control input setup time tIS is referenced from the input signal crossing at the VIH ac level for a ris ing signal and for a falling signal applied to the device under test Address and control input hold time is referenced from the input signal crossing at the VIL dc level for a rising signal and VIH dc for a falling signal applied to the device under test ViH de min VREF Vit gc max Vit ac max Vss 8 3 2 Timing
117. ve latency for better command and data bus efficiency Off Chip Driver impedance adjustment OCD and On Die Termination ODT for better signal quality Auto Precharge operation for read and write bursts Auto Refresh Self Refresh and power saving Power Down modes Average Refresh Period 7 8us at a TcAsg lower than 85 C 3 9us between 85 C and 95 C Strong and Weak Strength Data Output Driver 1k page size for x 4 amp x8 2k page size for x16 Lead free Packages 68 pin FBGA for x4 amp x8 components 92 pin FBGA for x16 components 1 0 Description The 1Gb Double Data Rate 2 DDR2 DRAMs are high speed CMOS Double Data Rate 2 Synchronous DRAM devices con taining 1 073 741 824 bits and is internally configured as a octal bank DRAM The 1Gb chip is organized as either 32Mbit x 4 I O x 8 banks 16Mbit x 8 I O x 8 banks or 8Mbit x 16 I O x 8 banks device These synchronous devices achieve high speed double data rate transfer rates of up to 667 Mb sec pin for gen eral applications The chip is designed to comply with all key DDR2 DRAM key features 1 posted CAS with additive latency 2 write latency read latency 1 3 normal and weak strength data output driver 4 Off Chip Driver OCD impedance adjustment and 5 an ODT On Die Termination function All of the control and address inputs are synchronized with a pair of externally supplied differential clocks Inputs are latched at the cross point o
118. y and CAS latency is defined by A4 A6 A7 is used for test mode and must be set to low for normal MRS operation A8 is used for DLL reset A9 A11 are used for write recovery time WR definition for Auto Precharge mode With address bit A12 two Power Down modes can be selected a standard mode and a low power Power Down mode where the DLL is disabled Address bit A13 and all higher address bits including BAO BA2 have to be set to low for compatibility with other DDR2 memory products with higher memory densities Page 15 Rev 1 02 May 2004 INFINEON Technologies HYB18T1G400 800 160AF Infineon 1Gb DDR2 SDRAM MRS Mode Register Operation Table Address Input For Mode Set BA2 BAI BAO Pa A12 11 A10 A9 AB A7 A6 AB a4 A2 A1 Address Field 0 0 0 0 PD WR DLL TM CAS Latency BT Burst Length Mode Register DLL Reset Mode Burst Type A2 A1 A0 Burst Length 0 No 0 Normal 0 Sequential 0 1 0 4 1 Test 1 Interleave 0 1 1 8 A12 Active Power Down A11 A10 9 WR AS Latency Mode Select 0 0 0 Reserved 0 0 0 Reserved 1 R 0 Fast exit use tXARD O 1 2 0 paved

lnfineon HYB18T1G400AF HYB18T1G800AF HYB18T1G160AF 1 Gbit DDR2 SDRAM

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