HYNIK HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM
Contents
1. lt CKE gt CS gt min Input signals are changed one time during 2clks All other pins 2 VDD 0 2V or 0 2V CKE gt VIH min Input signals are stable lt min lt VIL max gt CS gt min Input signals are changed one time during 2clks All other pins 2 VDD 0 2V or 0 2V CKE gt VIH min Input signals are stable gt tCK min gt tRAS min All banks active gt tRRC min All banks active KE lt 0 2V m m m m A A A A A A A A n2 150 150 140 120 120 250 250 1 IDD1 1004 depend on output loading and cycle rates Specified values are measured with the output open 2 Min of tRRC Refresh RAS cycle time is shown at AC CHARACTERISTICS II 3 HY57V561620T HP H 8 P S 4 HY57V561620LT HP H 8 P S Revision 1 8 Apr 01 hynix HY57V561620 L T AC CHARACTERISTICS Parameter Symbol System clock cycle sae l 1000 1000 time e pu Clock high pulse width 25 o 2 5 EB es pep m pl Wm m D 0 uL Wem eee _ Dewewm pep el ramai Fa Iw s e wp el el EL Tel ET2. 5 78 HY 57V 561620 hy HY57V561620 L T la u 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268 435 456bit CMOS Synchronous DRAM ideally suited for the main memory applications which require large memory density and high bandwidth HY57V561620 is organized as 4 banks of 4 194 304x16 The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock All inputs and outputs are synchronized with the rising edge of the clock input The data paths are internally pipelined to achieve very high bandwidth All input and output voltage levels are compatible with LVTTL Programmable options include the length of pipeline CAS latency of 2 or 3 the number of consecutive read or write cycles initiated by a single control command Burst length of 1 2 4 8 or full page and the burst count sequence sequential or interleave A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle This pipelined design is not restricted by a 2 rule FEATURES e Single 3 3V 0 3V power supply e Auto refresh and self refresh e All device pins are compatible with LVTTL interface e 8192 refresh cycles 64ms standard 400mil 54 with 0 8mm e Programmable Burst Length and Burst Type of pin pitch 1 2 4 8 and Full Page for Sequential Burst e
3. 70 c VbD 3 3 0 3V Vss 0V Note 1 Output load to measure access time is equivalent to two TTL gates and one capacitor 50pF For details refer to AC DC output circuit Revision 1 8 Apr 01 hynix HY57V561620 L T CAPACITANCE 25 f 1MHz 8 5 ui dug A12 BAO BA1 CKE CS RAS CAS 5 8 mE 5 5 Em WE UDQM LDQM Data 000 005 190 65 lt OUTPUT LOAD CIRCUIT Vit 1 4V RT 250 Q Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS tA 0 to 70 c vop 3 3 0 3V Input leakage current ILI Output leakage current ILO Output low voltage VOL Note 1 VIN 0 to 3 6V All other pins are not under test OV 2 DOUT is disabled VOUT 0 to 3 6V Revision 1 8 01 hynix HY57V561620 L T DC CHARACTERISTICS ll 0 to 70 C Vbp 3 3v 0 3V VSS 0V M Operating Current IDD1 IDD2P IDD2PS IDD2N IDD2NS IDD3PS IDD3N IDD3NS 1204 1005 Precharge Standby Current in power down mode Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode Burst Mode Operating Current Auto Refresh Current Self Refresh Current Note Test Condition Burst Length 1 One bank active tRAS 2 tRAS min tRP 2 tRP min lt VIL max min
4. mode Data Input Output Multiplexed data input output pin Power Supply Ground Power supply for internal circuits and input buffers RAS CAS and WE define the operation Refer function truth table for details Data Output Power Ground Power supply for output buffers Revision 1 8 Apr 01 hynix HY57V561620 L T FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x16 1 0 Synchronous DRAM Self Refresh Logic amp Timer Internal Row Counter 4Mx16 Bank 3 CLK Row Active Row 4Mx16 Bank 2 CKE Pre gt Decoders 4 16 1 a gt lt CS 5 4 16 0 D n RAS D S x lt a P DQ1 CAS D O 5 e Cell gt UJ Array lt c Column E Qo 5 Decoders Q e DQ14 D DQ15 Column Add Bank Select Counter A0 Address A1 Register gt Q Burst D Counter 119 l BIE o A12 BAO BA1 Mode ModeRegisters Data Data Out Control Control Pipe Line Control Revision 1 8 Apr 01 hynix HY57V561620 L T ABSOLUTE MAXIMUM RATINGS Note Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION to 70 c Note 1 All voltages are referenced to VSS 2 VIH max is acceptable 5 6V AC pulse width with lt 3ns of duration 3 VIL max is acceptable 2 0V AC pulse width with lt 3ns of duration AC OPERATING CONDITION to
5. All inputs and outputs referenced to positive edge of System clock 1 2 4 and 8 for Interleave Burst e Data mask function by UDQM and LDQM e Programmable CAS Latency 2 Clocks 4Banks x 4Mbits 400mil 54pin TSOP II e Internal four banks operation ORDERING INFORMATION x16 Lower Power This document is a general product description and is subject to change without notice Hyundai Electronics does not assume any responsibility for use of circuits described No patent licenses are implied Revision 1 8 Apr 01 hynix HY57V561620 L T PIN CONFIGURATION VSS DQ15 VSSQ DQ14 0013 VDDQ DQ12 0011 VSSQ DQ10 DQ9 VDDQ 54pin TSOP Il 008 400mil x 875mil Vss 0 8mm pin pitch NC UDQM CLK CKE A12 11 9 8 7 5 4 Vss PIN DESCRIPTION CLK Clock The system clock input All other inputs are registered to the SDRAM on the rising edge of CLK CKE Clock Enable Controls internal clock signal and when deactivated the SDRAM will be one of the states among power down suspend or self refresh Chip Select Enables or disables all inputs except CLK CKE UDQM and LDQM Selects bank to be activated during RAS activity e s Selects bank to be read written during CAS activity Row Address RAO RA12 Column Address CAO CA8 Address Auto precharge flag A10 Row Address Strobe Col umn Address Strobe Write Enable Data Input Output Mask Controls output buffers in read mode and masks input data in write
6. SI TD esa Er ksCr commana Sos om e we UeBYU mus fom s s s s 5125 Note 1 Assume tH tF input rise and fall time is 1ns 2 Access times to be measured with input signals of 1v ns slew rate 0 8v to 2 0v Revision 1 8 Apr 01 hynix HY57V561620 L T AC CHARACTERISTICS Il eS SS RAS cycle time pewe e e ep wewe 5 i es pese mew _ fl pT Precharge to data Note 1 A new command can be given tRRC after self refresh exit Revision 1 8 Apr 01 hynix HY57V561620 L T IBIS SPECIFICATION Characteristics Pull up 66MHz and 100MHz Pull up ud 100MHz 100MHz 66MHz eee Min Max Min mA mA mA 3 fa 3 39 ww m loh Min 100MHz s loh Min 66MHz I mA a loh Min 66 and 100MHz Characteristics Pull down 66MHz and 100MHz Pull down 100MHz 66MHz 250 200 _ 150 lt 100 50 0 0 0 5 1 1 5 2 2 5 3 3 5 Voltage V e 1 mA 100 4A mA 100 max IBIS spec is also applied to 133MHz device Revision 1 8 Apr 01 hynix HY57V561620 L T Voo Clamp CLK CKE CS DQM amp DQ Minimum clamp current Referen
7. ced to VDD Minimum Vss clamp current 3 2 5 2 1 5 1 0 5 0 0 e e Voltage mA Revision 1 8 Apr 01 hynix HY57V561620 L T DEVICE OPERATING OPTION TABLE HY57V561620 L T HP 133MHz 7 5ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 125MHz 8ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs x m 3 100MHz 10ns 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs HY57V561620 L T H 133MHz 7 5ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 125MHz 8ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 3ns HY57V561620 L T 8 125MHz 8ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 100MHz 10ns 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 83MHz 12ns 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 3n HY57V561620 L T P 100MHz 10ns 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs ma sama s 83MHz 12ns 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs Lows ar HY57V561620 L T S 100MHz 10 0ns 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs ma mama m 83MHz 12 0ns 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6 66MHz 15 0ns 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6 Revision 1 8 01 hynix HY57V561620 L T COMMAND TRUTH TABLE Mode Register Set Register Set OP code No Operation Bank Active Active Burst Stop UDQM LDQM Emy Self Refresh Exit Entry H L Precharge B B i B power down Exit Suspend Note 1 OP Code Ope
8. rand Code 2 V Valid X Dont care H Logic High L Logic Low RA Row Address CA Column Address B BB BB T lt lt Revision 1 8 Apr 01 400mil 54pin Thin Small Outline Package HY57V561620 L T vV Unit mm Inch JHHHHHHHHH H HU YL JHUHHHH HE LI Li Li Li LI Li Li LI Li LJ LI LJ LI Li Li Li LI LI LI LI LI Li Li LI Li LI LJ 22 327 0 8790 22 149 0 8720 UIA 0 80 0 0315 BSC 0 400 0 016 0 500 0 012 1 194 0 0470 0 991 0 0590 v 11 938 0 4700 11 735 0 4620 10 058 GAGE PLANE E BASE PLANE 5 v 0 10 262 0 4040 0 5960 Revision 1 8 01 SEATING PLANE 09 0 597 0 0235 0 210 0 0083 0 0020 0 406 0 0160 0 120 0 0047
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