Home

SPECTEK SDRAM 3.3V SYNCHRONOUS DRAM

1. 11x 13mm o 4 m Uu m a m te a a c 2 IU UUUUUUUUUOUUU HULU LI DILTEI m a 2 T V 4 o a a gt lt m V DQ12 a o z e x eo i e a lt eo z z z z z x 4 lt lt x 4 z uL 2 aL Depopulated Balls SpecTek reserves the right to change products or specifications without notice 2001 2002 2004 SpecTek PDF 09005aef80782716 Source 09005aef807825bd 128Mb SDRAM Rev 11 29 2004 www spectek com SPECTEK 128Mb x4 x8 x16 SDRAM 3 3V v FBGA FC PACKAGE 60 pin 11mm x 13mm 0 850 0 075 0 325 _ 0 205 SEATING PLANE 1 1 5 60 2 40 0 05 CTR 0 45 0 05 TYP 0 80 TYP PIN 1 ID 6 50 0 05 ooooooo oooooodgq 13 00 0 10 5 60 0 05 2 80 0 05 1 20 MAX __ 5 50 0 05 Qo oae 11 00 0 10 Bottom View NOTE 1 All dimensions in millimeters 2 Recommended Pad size for is 0 33nmz0 025mm PDF 09005aef807827f6 Source 09005aef807825bd 7 SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com SPECTEK 128Mb x4 x8 x16 SDRAM 3 3V v FBGA FB PACKAGE 60 pin 8mm x 16mm 0 850 0
2. 075 S 0 325 x 0 025 0 205 MAX SEATING PLANE 5 60 2 40 0 05 20 45 x 0 05 0 80 PIN 1 ID 8 00 x0 05 16 00 0 10 5 60 0 05 0 80 TYP 2 80 x0 05 4 0 1 20 u 0 x0 05 8 00 x0 10 Bottom View ooocooo oooopooo DODD DP PD oy 11 20 e ooooooo ooooooo OOOO OO e NOTE 1 All dimensions in millimeters 2 Recommended Pad size for PCB is 0 33mm 0 025mm PDF 09005aef807827f6 Source 09005aef807825bd g SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com SPECTEK 128Mb x4 x8 x16 v SDRAM 3 3V PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004 Options Marking Architecture 32 Meg x 4 8 Meg x 4 x 4 banks S40032LK8 16 Meg x 8 4 Meg x 8 x 4 banks S80016LK7 8 Meg x 16 2 Meg x 16 x 4 banks S16008LK9 Voltage and Refresh 3 3V Auto Refresh LK 3 3V Self or Auto Refresh MK Device Configuration 32 Meg x 4 8 16 Meg x 8 7 8 Meg x 16 9 Package Types 54 pin plastic TSOP 400 mil TW 60 ball FBGA 8mm x 16mm 60 ball FBGA 11mm x 13mm FC Timing Types PC100 3 3 3 8A PC133 3 3 3 75A Part number example S80016LK7TW 8A NOTES 1 Only when specified Consult Sales 2 Not available in x16 configuration http www spectek com menus part quides asp PDF 09005aef807827f6 Sou
3. 25 78 5160081 fg 128Mb x4 x8 x16 gt y SPECIEK SDRAM 3 3V SYNCHRONOUS DRAM Features tel PC 100 3 3 3 or PC133 3 3 3 compatible Fully synchronous all signals registered on positive edge of system clock Internal pipelmed operation column address can be changed every clock cycle ntemal banks for hidme row access precharge time Programmable burst lengths 1 2 or 4 using Interleaved Burst Addressing Auto Precharge and Auto Refresh modes 64ms 4 096 evele refresh quad row refresh 15 61 Tow PIN ASSIGNMENT Top View UOS US E La La d DOS pac n NC Do NC Self Refresh mode LVIIL compatible inputs and outputs ngle 3 3V 0 1V power supply The xl6 devices are optimized for both smele and dual rank DIMM applications The x8 devices are optimized for single rank DIMM applications Options Designation Family Spec Tek Memory Configuration Nate The symbol indicates signal is active LOS A dash 12 Meg x 4 8 Meg x 4 x 4 banks 32M4 indicates x and x4 pin function is same as x15 pin function 16 Meg x 8 4 Meg x B x 4 banks 16M8 SMegxi B Meg x 16 2 Meg x 16 x 4 banks SM16 Remeh oun X Design ID SDRAM 128 Mezabit Design Yx5x ATT Call SpecTek Sales for details an availability of x placeholders NOTES 1 Only when specified Consult Sales Voltage and Refresh 2 Not availabl
4. ACTIVEcommand 8 CK READ WRITE command to READ WRITE command tCCD 1 1 J CKE to clock disable or power down entry mode tCKED 1 j 1 J tCK 2 CKE toclockenableorpowerdownexitsetup PED tC AC ELECTRICAL CHARACTERISTICS Vdd 3 3V 10 V Temp 25 to 70 C LACCHARACTERISTICS PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES mop 9 L s J J T i WRITE command to input data delay 0 0 Data in to ACTIVATE command w Auto precharge 5 J 5 tCK 3 DDweitopecuge 2 gt LL c lt gt as i pe RT c LOAD MODE REGISTER command to command MRD 2 2 1 Data out to high impedance from precharge I G I k_ 1 _ NOTES 1 Clocks required specified by JEDEC functionality and not dependent on any timing parameter 2 Timing actually specified by tCKS clock s specified as a reference only at a minimum cycle rate 3 Timing actually specified by tWR plus tRP clock s specified as a reference only at a minimum cycle rate 4 tHZ defines the time at which the output achieves the open circuit condition it is not a reference to Voh or Vol The last valid data element will meet tOH before going high Z 5 Based on tCK 10ns for 8 and tCK 7 5ns for 75
5. BY CURRENT POWER DOWN mode CKE LOW Standard parts Idd2 2 ma 2 Self refresh parts Idd2 STANDBY CURRENT CS HIGH CKE HIGH all banks idle 6 OPERATING CURRENT BURST mode after tRCD met continuous burst READ Icc5 WRITE all banks active CL 3 AUTO REFRESH CURRENT tRC gt tRC MIN CL 3 AUTO REFRESH CURRENT tRC 15 6us CL 3 SELF REFRESH CURRENT Self refresh parts only part M Idd8 EE 3 3 STANDBY CURRENT CS HIGH CKE HIGH all banks active after tRCD met Icc4 53 no accesses in progress Notes 1 All voltages referenced to Vss 2 An initial pause of 100 Us is required after power up followed by two AUTO REFRESH commands before proper device operation is ensure Vdd and VddQ must be powered up simultaneously Vss and VssQ must be at the same potential The two AUTO REFRESH command wake ups should be repeated any time the REF refresh requirement is exceeded 3 cc specifications are tested after the device is properly initialized tCK 10ns for 8 and tCK 7 5ns for 75A PDF 09005aef807827f6 Source 09005aef807825bd 3 SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com A SPECTEK 128Mb x4 x8 x16 SDRAM 3 3V AC ELECTRICAL CHARACTERISTICS Vdd 3 3V 10 V Temp 25 to 70 C AC CHARACTERISTICS OA 75A 8A Ac
6. a PDF 09005aef807827f6 Source 09005aef807825bd 4 SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com SPECTEK 128Mb x4 x8 x16 v SDRAM 3 3V 54 PIN PLASTIC TSOP 400 mil Package TK SEE DETAIL A oe k PIN 1 ID 18 13 1 00 2X DETAIL A NOTE 1 All dimensions in millimeters MAX MIN or typical where noted 2 Package width and length do not include mold protrusion allowable mold protrusion is 0 25mm per side PDF 09005aef807827f6 Source 09005aef807825bd 5 SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com 128Mb x4 x8 x16 SDRAM 3 3V SPECTEK d FBGA PIN ASSIGNIVIENT Top View 16 Meg x 8 SDRAM 32 Meg x 4 SDRAM 11 x 13mm 11 x 13mm N O 2 O D U m 8 2 2 8 e 8 s 3 s le 8 s o Q 9 9 e Q o N Q BIHIEIHIHIHIBIBIBIBIBIBIBIBIE BIHIBIBIBIBIBIBIRIBIBIBIBIBIE BIBIHIBIBIHIBIBIBIBIBIBIBIBIB FEE BEEBE EI el SEE EEE EEE EEE LILILILI LI DIDI LI LI HINIMINIMIMIMIMIIMININUNINIE LLILILID DO EILTLI CI LIBI LTLITLI EEE EEE LES eel FEE EEE EEE EEE Vss Depopulated Balls Depopulated Balls 8 Meg x 16 SDRAM
7. cess time from CIK positive edge Access time from CLK positive edge CL 2 c NAT Address hold time Address setup time ASS CLK high level width o H 25 3 CLKlowlevelwidth o L 25 3 J Clock cycle time CL 3 K 75 j 10 y Clock cycle time CL 2 NA j j CKEholdtime o 08 p 1 CKEseuptime CK 15 2 CS7 CASE WEE DOM cma os L 1 La L CS RAS CASH WE DQM setuptime 15 J 2 J ns j Data inholdtime DE o8 1 J p ns j Data in setup time SS 2 nm J J Data outhigh impedancetime 9 9 ns 4 Data outlowimpedancetime Et i gt n jJ Data outholdtime OH 27 3 j j ns j ACTIVE to PRECHARGE command period RAS 44 16K 50 j 16K ms AUTO REFRESH to ACTIVE command period 60 80 ns jJ ACTIVE to READ or WRITEdelay RoD 225 30 s Refresh period 4096 cycles 64 m PRECHARGE command period 225 30 s ACTIVE bank A to bank B command period tRRD 15 20 j Transition time o r 03 2 03 2 ns j Writerecoverytime o 20 20 y nm 3 Exit SELF REFRESH to
8. e in x16 configuration 3 3V Auto Refresh 4K refresh L4 33V Self or Auto Refresh 4K refresh M4 General Description Package Types The 128Mb SDRAM is a high speed CMOS dynamic 34 pin plaste TSOP 400 mil TE random access memory contauung 1342172728 bita 6D ball FBGA fmm x 1 FB Each is internally configured as a quad bank DRAM 60 ball FEGA 11mm x 13mm PC Read and wmrte accesses to the SDRAM ae burst Timing Types PC100 3 3 3 BA PC133 3 3 3 T5A Part number example SAAIGMSYSSALATE 75 For part numbers prior to December 2004 reir to page 9 for decoding oriented accesses start at a selected location and contmue for a programmed mmber of location a programmed sequence Accesses begin with the registrahon of am ACTIVE command which 15 then followed by a READ or WRITE command The address bits registered coimeldent with the ACTIVE command are used to select the bank and row to be accessed BAD B select the bank AQ Al select the row The address bits registered s amem b w SPECTEK coincident with the READ or WRITE commands are used to select the starting column location for the burst access The SDRAM provides for programmable READ of WRITE burst lengths of 1 2 or 4 locatrons with burst temunate option wmz the Burst Interleaved Addressime mode only An AUTO PRECHARGE function may be enabled to provide a self timed row precharge that 15 initiated at the end of the burst
9. of shipment from SpecTek and SpecTek has no liability thereafter Any liability is limited to replacement of the defective items or return of amounts paid for defective items at buyers election n no event will SpecTek be responsible for special indirect consequential or incidental damages even if SpecTek has been advised for the possibility of such damages speclek s liability from any cause pursuant to this specification shall be limited to general monetary damages in an amount not to exceed the total purchase price of the products covered by this specification regardless of the form in which legal or equitable action may be brought against SpecTek ABSOLUTE MAXIMUM RAIINGS Voltage on Vdd Supply relative to Vss to 3 6V Operating Temperature T4 Ambient 25 ta 70 C Storage Temperature 55 tmn 150 C Power Dissipation 1 W Short Circuit Owiput Current 50 mA Stresses bevond these may cause permanent damage to the device This is a stress rating only and functional operation of the device at or bevond these condrnons is not implied Exposure to these conditons for extended periods nav affect reliability A SPECTEK 128Mb x4 x8 x16 SDRAM 3 3V ICC OPERATING CONDITIONS AND MAXIMUM LIMITS Vdd 3 3V 10 V Temp 25 to 70 L Supply Current Symbol SA Units OPERATING CURRENT ACTIVE mode burst 1 READ or WRITE tRC gt tRC Icc1 165 Notes 2 3 4 MIN one bank active CL 3 STAND
10. rce 09005aef807825bd 9 SpecTek reserves the right to change products or 128Mb SDRAM specifications without notice 2001 2002 2004 SpecTek Rev 11 29 2004 www spectek com
11. sequence Ihe 128Mb SDRAM uses an pipelined architecture to achieve Ingh speed operation This architecture 15 compatible with the Jn rule of prefetch architectures but it also allows the column address to be changed on every clock cycle to achieve a high speed fully random access Precharzinz ome bank while accessing one of the other three banks will hide the precharze cycles and provide seamless high speed random access operation The 128Mb SDRAM 15 designed to operate m 3 3V low power memory systems An auto refresh mode i provided along with a power saving power down mode All inputs and outputs are LVTITL compatible SDRAMs offer substantal advances m DRAM operatne performance includme the abilthes te synchronously burst data at a ogh data rate with automate columm address generation to mterleave between internal banks in order to hide precharge time and to randomly change column addresses on each clock cycle durma a burst access The x devices are optimized for single bank DIMM applications The xl6 device ave available for both single and dual bank DIMM applications CAPACITANCE 128Mb x4 x8 x16 SDRAM 3 3V Disclaimer Except as specifically provided in this documeni SpecIek makes no warrmaniies expressed or implied including but not limited to any implied warranties of merchantability or fitness for a particular purpose Any claim against SpecTek must be made within one year from the date

SPECTEK SDRAM 3.3V SYNCHRONOUS DRAM

Contents

Download Pdf Manuals

Related Search

Related Contents