CANACHIP PA7540 PEEL Array Programmable Electrically Erasable Logic Array
Contents
1. TT OTT TOO CUO 84 Product Terms aaaan To Logic Control Cells Lec UUU UU s a 84 Sum Terms PA7540 Logic Array Figure 3 PA7540 Logic Array True Product Term Sharing The PEEL logic array provides several advantages over common PLD logic arrays First it allows for true product term sharing not simply product term steering as commonly found in other CPLDs Product term sharing ensures that product terms are used where they are needed and not left unutilized or duplicated Secondly the sum of products functions provided to the logic cells can be used for clocks resets presets and output enables instead of just simple product term control The PEEL logic array can also implement logic functions with many product terms within a single level delay For example a 16 bit comparator needs 32 shared product terms to implement 16 exclusive OR functions The PEEL logic array easily handles this in a single level delay Other PLDs CPLDs either run out of product terms or require expanders or additional logic levels that often slow performance and skew timing Logic Control Cell LCC Logic Control Cells LCC are used to allocate and control the logic functions created in the logic array Each LCC has four primary inputs and three outputs The inputs to each LCC are complete sum of product logic functions from the array2. JK Register P Q toggles when J K 1 1 Q holds when J K 0 0 Q 1 when J K 1 0 Q 0 when J K 0 1 Z Combines features of both D and T registers 08 14 005A Figure 5 LCC Register Types SUM A can serve as the D T or J input of the register or a combinatorial path SUM B can serve as the K input or the preset to the register or a combinatorial path SUM C can be the clock the reset to the register or a combinatorial path SUM D can be the clock to the register or the output enable for the connected I O cell Note that the sums controlling clocks resets presets and output enables are complete sum of product functions not just product terms as with most other PLDs This also means that any input or I O pin can be used as a clock or other control function Several signals from the global cell are provided primarily for synchronous global register control The global cell signals are routed to all LCCs These signals include a high speed clock of positive or negative polarity global preset and reset and a special register type control that selectively allows dynamic switching of register type This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from D type registers to load and T type registers to count see Figure 10 Multiple Outputs Per Logic Cell An important feature of the logic control cell is i
3. Capacitances are tested on a sample basis Test conditions assume signal transition times of 5ns or less from the 10 and 90 points timing reference levels of 1 5V unless otherwise specified toE is measured from input transition to Veer 0 1V See test loads at end of Section 6 for VREF value toD is measured from input transition to VoH 0 1V or VoL 0 1V DIP System clock refers to pin 1 13 high speed clocks PLCC Sys tem clock refers to pin 2 16 high speed clocks For T or JK registers in toggle divide by 2 operation only 10 For combinatorial and async clock to LCC output delay 11 ICC for a typical application This parameter is tested with the device programmed as a 10 bit D type counter H tscx tco m External Set up Internal Feedback Ext Int 1 tscx tcol I O H tscx Ext 17 18 fMAx2 1 0 4 tcox ernal Set up External Feedback Ext Ext fMAx4 1 tscx tcox Test loads are specified in Section 5 of the Data Book Async Clock refers to the clock from the Sum term OR gate The LCC term indicates that the timing parameter is applied to the LCC register The LCC IOC term indicates that the timing parameter is applied to both the LCC and IOC registers The term input without any reference to another term refers to an external input pin The parameter tsp indicates that the PCLK
4. which can be used to implement combinatorial and sequential logic functions and to control LCC registers and I O cell output enables From Global Cell A f X System Clock Preset RegType Reset On Off MUX pee Array i prs T MUX J REG From lt Array y To O gt Cell 08 14 004A Figure 4 Logic Control Cell Block Diagram As shown in Figure 4 the LCC is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous D T or JK registers clocked SR registers which are a subset of JK are also possible See Figure 5 EEPROM memory cells are used for programming the desired configuration Four sum of product logic functions SUM terms A B C and D are fed into each LCC from the logic array Each SUM term can be selectively used for multiple functions as listed below 04 02 051B C Aralhin Sum A D T J or Sum A Sum B Preset K or Sum B Sum C Reset Clock Sum C Sum D Clock Output Enable D Register P Q D after clocked Best for storage simple counters shifters and state machines with few hold loop conditions T Register P Q toggles when T 1 Q holds whenT 0 Best for wide binary counters saves product terms and state machines with many hold loop conditions
5. Output pin Control t pdx gt LCC Logic LCC Logic LCC External Propagation Delay tPDI Internal Propagation Delay 04 02 051B C Aralhin Table 5 A C Electrical Characteristics Sequential 15 1 15 Symbol Parameter Max Unit tsc Internal set up to system clock LCC 6 S ta tsk tic tcx tscx Input EXT set up to system clock LCC tia tsci 8 ns tcol System clock to Array Int LCC IOC INC tek tic ns tcox System clock to Output Ext LCC tco tto 12 ns tux Input hold time from system clock LCC 0 ns tsk LCC Input set up to async clock LCC 3 ns tak Clock at LCC or IOC LCC output 1 ns tuk LCC input hold time from system clock LCC 4 ns ts Input set up to system clock IOC INC tsx tex 0 ns tH Input hold time from system clock IOC INC tsx tcx 4 ns tek Array input to IOC PCLK clock 6 ns tspi Input set up to PCLK clock IOC INC tsx tex ta 0 ns tHPI Input hold from PCLK clock IOC INC tpxttra tsx ns tck System clock delay to LCC IOC INC 7 ns tew System clock low or high pulse width 7 ns fMAX1 Max system clock frequency Int Int 1 tsci tco 71 4 MHz fMAX2 Max system clock frequency Ext Int 1 tscx tcoi 62 5 MHz fMax3 Max system clock frequency Int Ext 1 tsci tcox 55 5 MHz fMAX4 Max system clock frequency Ext Ext 1 tscx tcox 50 0 MHz fret Max sy
6. Vin Input HIGH Level 2 0 Vcc 0 3 V Vit Input LOW Level 0 3 0 8 V lit Input Leakage Current Vcc Max GND lt Vin Vec 10 yA loz Output Leakage Current 1 0 High Z GND lt Vo lt Vcc 10 yA Output Short Circuit Be A ts Isc Current Vec 5V Vo 0 5V TA 25 C 30 120 mA Vin OV or Vcc 15 80 lec Vcc Current f 25MHz 55 typ mA All outputs disabled 1 15 90 Cin Input Capacitance 6 pF Ta 25 C Vcc 5 0V f 1 MHz Cour Output Capacitance 12 pF 6 04 02 051B C Arnal hip Table 4 A C Electrical Characteristics Combinatorial Over the Operating Range 15 1 15 Symbol Parameter Unit Min Max tppi Propagation delay Internal ta tic 10 ns tppx Propagation delay External tia tar tic to 15 ns tia Input or I O pin to array input 2 ns ta Array input to LCC 9 ns tlc LCC input to LCC output 1 ns tLo LCC output to output pin 3 ns top tog Output Disable Enable from LCC output 3 ns tox Output Disable Enable from input pin 15 ns This device has been designed and tested for the recommended operating conditions Proper operation outside of these levels is not guaranteed Exposure to absolute maximum ratings may cause permanent damage Figure 14 Combinatorial Timing Waveforms and Block Diagram Array Array Input pee a tia LCC tAL A tLe LCC Output tA tAL tLe tLo Output pin pdi pdi
7. has been set The signature word can be used to identify the pattern programmed in the device or to record the design revision Figure 11 WinPLACE Architectural Editor for PA7540 E 1 H a n L E T i IE a WD ON a HOA A Mi EW td ee ee eee eg peg gee eee Figure 13 WinPLACE waveform and simulator screen 04 02 051B C Aral hip Table 1 Absolute Maximum Ratings Symbol Parameter Conditions Ratings Unit Vec Supply Voltage Relative to Ground 0 5 to 7 0 V Vi Vo Voltage Applied to Any Pin Relative to Ground 0 5 to Vcc 0 6 V lo Output Current Per pin lot lon 25 mA Tst Storage Temperature 65 to 150 C Tit Lead Temperature Soldering 10 seconds 300 C Table 2 Operating Ranges Symbol Parameter Conditions Min Max Unit Commercial 4 75 5 25 Vec Supply Voltage V Industrial 4 5 5 5 Commercial 0 70 Ta Ambient Temperature C Industrial 40 85 Tr Clock Rise Time See Note 2 20 ns Tr Clock Fall Time See Note 2 20 ns Trvcc Vcc Rise Time See Note 2 250 ms Table 3 D C Electrical Characteristics Over the Operating Range Symbol Parameter Conditions Min Max Unit Von Output HIGH Voltage TTL Vcc Min lon 4 0mA 2 4 V Vonc aa a Veo Min low 10A Voc 0 3 v VoL Output LOW Voltage TTL Vec Min lo 16mA 0 5 V Voc ha ees Vcc Min lo 104A 0 15 v
8. 42X2 Array Inputs true and Zs complement O Sooo00o0eco0og Global Cels 10 ceis _ yoo Ke 20 Cells 20 V0 Pins he 3 a Salo vet loc gt cH o S z H vo clt Te 20 ee AAI AAA logic CH uo Logic F i cH vo Array yp bogie H Logic functions H vo f fg Control nee to I O cells he JO Cells o 1D LCC cH vo a 4 36 cH vo 4 sum terms Ct CH uo 4 product terms 80 sum terms 20 Logic Control Cells 7 PA7540 ucLK2 for Global Cells four per LCC 2 output functions per cell 40 total output functions possible WeLK1 C 1 N aM vee vcLK1 OL4 1 24 Fo vec vo 2 23 vo vo cL2 23 Fo vo id 6 vo o3 22 n v0 o 3 22 vo o4 21 0 vo vo C 4 at C ro vo o5 20 0 1 0 vo 5 20 vo vo oje 18 Z0 vo o7 18 0 0 vo C 6 19 I vo vo a8 17 n o vo C7 18 I vo vo o9 16 0 vo vo Js 17 wo vo oj 10 15 Fm vo vo a11 14 20 0 VCLK4 vo C 9 16 vo GND o 12 13 0 I CLK2 vo C 10 15 1 vo va vo 1 14 vo solic up GND J 12 13 7 WcLk2 ug vo DIP oo are WO ee25g0900 eo302500 vo 2 5 5 575 Sfs2 gt 5 5 000000 Oooooon vo 4 4 3 21 282726 4 3 2 1 282726 va vo Os 2 Ovo woos 25 O vo vo vo O
9. 6 24 Ovo wo0e 24 O vo vo vo 7 23 Ovo wo 7 23 O vo GND NC 8 22 ONC NC H8 22 O NC vo O 9 2 Oro wogeo 21 O vo vo O 10 20 Ovo vo O10 20 O vo vo o 11 19 OVO vo g1 19 O vo 12 13 14 15 16 1718 1213 14 15 16 17 18 PLCC JN PLCC J 1 0 1 0 vO 1 0 1 0 1 0 o zZ GND GND 1 0 1 0 a z o 08 14 001B I CLK2 I CLK2 Logic Control Cells 08 14 002A 04 02 051B C Aralhin Inside the Logic Array The heart of the PEEL Array architecture is based on a logic array structure similar to that of a PLA programmable AND programmable OR The logic array implements all logic functions and provides interconnection and control of the cells In the PA7540 PEEL Array 42 inputs are available into the array from the I O cells and input global clock pins All inputs provide both true and complement signals which can be programmed to any product term in the array The PA7540 PEEL Arrays contains 84 product terms All product terms with the exception of certain ones fed to the global cells can be programmably connected to any of the sum terms of the logic control cells four sum terms per logic control cell Product terms and sum terms are also routed to the global cells for control purposes Figure 3 shows a detailed view of the logic array structure From 10 Cells lt IOC and VCLKs _ 42 Array Inputs TIN From Logic Control Cells LCC
10. APA TAR C Aral hip PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24 pin PLD Available 20 I Os 2 inputs clocks 40 registers latches 40 logic cell output functions PLA structure with true product term sharing Logic functions and registers can be O buried Ideal for Combinatorial Synchronous and Asynchronous Logic Applications Integration of multiple PLDs and random logic Buried counters complex state machines Comparators decoders multiplexers and other wide gate functions High Speed Commercial and Industrial Versions As fast as 10ns 15ns tpdi tpdx 71 4MHz fmax Industrial grade available for 4 5 to 5 5V Vec and 40 to 85 C temperatures General Description The PA7540 is a member of the Programmable Electrically Erasable Logic PEEL Array family based on ICT s CMOS EEPROM technology PEEL Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today s programmable logic designs The PA7540 is by far the most powerful 24 pin PLD available today with 20 I O pins 2 input global clocks and 40 registers latches 20 buried logic cells and 20 I O registers latches Its logic array implements 84 sum of products logic functions The PA7540 s logic and I O cells LCCs IOCs are extremely flexible offering two output functions per cell a total of 40 for all 20 logic cells Logic cells are con
11. erms for 10 bit loadable binary counter D uses 57 product terms 47 count 10 load T uses 30 product terms 10 count 20 load D T uses 20 product terms 10 count 10 load 08 14 010A Figure 10 Register Type Change Feature internal signals to be simulated and analyzed via a waveform display See Figures 10a c PEEL Array development is also supported by popular development tools such as ABEL via Anachip s PEEL Array fitters A special smart translator utility adds the capability to directly convert JEDEC files for other devices into equivalent JEDEC files for pin compatible PEEL Arrays Programming PEEL Arrays are EE reprogrammable in all package types plastic DIP PLCC and SOIC This makes them an ideal development vehicle for the lab EE reprogrammability is also useful for production allowing unexpected changes to be made quickly and without 04 02 051B C Aral hip waste Programming of PEEL Arrays is supported by many popular third party programmers Design Security and Signature Word The PEEL Arrays provide a special EEPROM security bit that prevents unauthorized reading or copying of designs Once set the programmed bits of the PEEL Arrays cannot be accessed until the entire chip has been electrically erased Another programming feature signature word allows a user definable code to be programmed into the PEEL Array The code can be read back even after the security bit
12. figurable as D T and JK registers with independent or global clocks resets Figure 1 Pin Configuration CMOS Electrically Erasable Technology Reprogrammable in 24 pin DIP SOIC and 28 pin PLCC packages Optional JN package for compatibility Flexible Logic Cell 2 output functions per logic cell D T and JK registers with special features Independent or global clocks resets presets clock polarity and output enables Sum of products logic for output enables 22V10 power ground Development and Programmer Support Anachip s WinPLACE Development Software Fitters for ABEL CUPL and other software Programming support by popular third party programmers presets clock polarity and other features making the PA7540 suitable for a variety of combinatorial synchronous and asynchronous logic applications With pin compatibility and super set functionality to most 24 pin PLDs 22V10 EP610 630 GAL6002 the PA7540 can implement designs that exceed the architectures of such devices The PA7540 supports speeds as fast as 10ns 15ns tpdi tpdx and 71 46MHZz fmax at moderate power consumption 80mA 55mA typical Packaging includes 24 pin DIP SOIC and 28 pin PLCC see Figure 1 Anachip and popular third party development tool manufacturers provide development and programming support for the PA7540 Figure 2 Block Diagram 2 Input Global Clock Pins p Global Cells 84
13. publication is believed to be accurate and reliable However there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use No license is granted under any patents or patent rights of Anachip Anachip s products are not authorized for use as critical components in life support devices or systems Marks bearing or are registered trademarks and trademarks of Anachip Corp 04 02 051B
14. rmined by the global cell It can also be bypassed for a non registered input The combination of LCC and IOC allows for multiple buried registers and logic paths See Figure 8 04 02 051B C Aralhin Q D Input with optional E register latch 1 0 a I O with lt independent le output enable E 1A DQ 1 B gt 2 10 gt o 1D gt 08 14 008A Figure 8 LCC amp IOC With Two Outputs Global Cells The global cells shown in Figure 9 are used to direct global clock signals and or control terms to the LCCs and IOCs The global cells allow a clock to be selected from the CLK1 pin CLK2 pin or a product term from the logic array PCLK They also provide polarity control for IOC clocks enabling rising or falling clock edges for input registers latches Note that each individual LCC clock has its own polarity control The global cell includes sum of products control terms for global reset and preset and a fast product term control for LCC register type used to save product terms for loadable counters and state machines see Figure 10 The PA7540 provides two global cells that divides the LCC and IOCs into two groups A and B Half of the LCCs and IOCs use global cell A half use global cell B This means for instance two high speed global clocks can be used among the LCCs PEEL Array Development Support Development support for PEEL Arrays i
15. s provided by Anachip and manufacturers of popular development tools Anachip offers the powerful WinPLACE Development Software free to qualified PLD designers The PLACE software includes an architectural editor logic compiler waveform simulator documentation utility and a programmer interface The PLACE editor graphically illustrates and controls the PEEL Array s architecture making the overall design easy to understand while allowing the effectiveness of boolean logic equations state machine design and truth table entry The PLACE compiler performs logic transformation and reduction making it possible to specify equations in almost any fashion and fit the most logic possible in every design PLACE also provides a multi level logic simulator allowing external and GroupA amp B m MUX gt LCC Clocks CLK1 Sia CLK2 d MUX gt IOC Clocks PCLK Daenen Reg Type gt LCC Reg Type Preset j gt gt LCC Presets Reset j gt LCC Resets Global Cell LCC amp IOC l 08 14 009A Figure 9 Global Cells Reg Type from Global Cell Register Type Change Feature P Global Cell can dynamically change user selected LCC registers from D to T or from D to JK This saves product terms for loadable counters or state machines Use as D register to load use as T or JK to count Timing allows dynamic operation Example P Product t
16. signal to the IOC register is always slower than the data from the pin or input by the absolute value of tsk tpx tia This means that no set up time for the data from the pin or input is required i e the external data and clock can be sent to the device simultaneously Additionally the data from the pin must remain stable for typ time i e to wait for the PCLK signal to arrive at the IOC register Typical typ ICC is measured at Ta 25 C freq 25MHZ Vcc 5V 04 02 051B C Arnal hip Table 6 Ordering Information Part Number Speed Temperature Package PA7540P 15 P24 PA7540J 15 J28 PA7540JN 15 Toons G JN28 PA7540S 15 524 PA7540PI 15 P24 PA7540JI 15 J28 PA7540JNI 15 Tenens JN28 PA7540SI 15 524 Figure 16 Part Number Device Suffix PA7540J 15 Package P 300mil DIP J Plastic J Leaded Chip Carrier PLCC JN PLCC Alternate Pin Out S SOIC 300 mil Gullwing Anachip USA Inc 780 Montague Expressway 201 San Jose CA 95131 TEL 408 321 9600 FAX 408 321 9696 2002 Anachip Corp Temperature Range Blank Commercial 0 to 70 C Industrial 40 to 85 C Email Speed 15 10ns 15ns tpd tpdx 08 14 016A Sales_usa anachip com Website http www anachip com Anachip reserves the right to make changes in specifications at any time and without notice The information furnished by Anachip in this
17. stem clock toggle frequency 1 tew tow 71 4 MHz tpr LCC presents reset to LCC output 1 ns tst Input to Global Cell present reset tia tac tpr 12 ns taw Asynch preset reset pulse width 8 ns tRT Input to LCC Reg Type RT 6 ns tRTV LCC Reg Type to LCC output register change ns tRTC Input to Global Cell register type change trt trrv 7 ns trw Asynch Reg Type pulse width 10 ns tRESET Power on reset time for registers in clear state 5 us 8 04 02 051B C Aralhin Figure 15 Sequential Timing Waveforms and Block Diagram tia Array Input for gt LCC Clock Control E lt lt k ta gt gt Array Input for IOC clock PCLK tek gt Clock from CLK Pin tck tew Clock at LCC or 10C tsk 4 t HK Data at LCC or 10C f tka LCC or IOC Output je tet tLo Output pin from LCC tst Register Change mia a tscl tco Internal Set up Internal Feedback Int Int fMax1 1 tsci tcol I O H tsci tcox Internal Set up External Feedback Int Ext fMAX3 1 tsci tcox Notes 1 Minimum DC input is 0 5V however inputs may under shoot to 2 0V for periods less than 20ns 2 Test points for Clock and Vcc in te tr teL tcH and treser are referenced at Oo 8 9 10 and 90 levels O pins are OV or Vcc Test one output at a time for a duration of less than 1 sec
18. ts capability to have multiple output functions per cell each operating independently As shown in Figure 4 two of the three outputs can select the Q output from the register or the Sum A B or C combinatorial paths Thus one LCC output can be registered one output can be combinatorial and the third an output enable The multi function PEEL Array logic cells are equivalent to two or three macrocells of other PLDs which have only one output per cell They also allow registers to be truly buried from I O pins without limiting them to input only see Figure 8 From Global Cell 1 0 Cell Clock REG Latch ak To MUX Array ll Input lt 4 l A B C Erori or MUX I O Pin Logic Q Control wux Cell D 1 0 7540 O Cell IOC 08 14 006A Figure 6 I O Cell Block Diagram D Qr IOC Register Q D after rising edge of clock i T holds until next rising edge L Q I0C Latch Q L when clock is high holds value when clock is low IL 08 14 007A Figure 7 IOC Register Configurations 1 O Cell IOC All PEEL Arrays have I O cells IOC as shown above in Figure 6 Inputs to the IOCs can be fed from any of the LCCs in the array Each IOC consists of routing and control multiplexers an input register transparent latch a three state buffer and an output polarity control The register latch can be clocked from a variety of sources dete
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CANACHIP PA7540 PEEL Array Programmable Electrically Erasable Logic Array