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MAXIM MAX187/MAX189 Data Sheet

1. AVLAZCLAWI 15V Low Power 12 Bit Serial ADCs Pin Description PIN NAME FUNCTION DIP WIDE SO 1 1 Vpp Supply voltage 5V 5 2 3 AIN Sampling analog input OV to VegF range Three level shutdown input Pulling SHDN low shuts the MAX187 MAX189 down to 10pA max supply current Both MAX187 and MAX189 are fully opera 3 6 SHDN tional with either SHDN high or floating For the MAX187 pulling SHDN high enables the internal reference and letting SHDN float disables the internal reference and allows for the use of an external reference Reference voltage sets analog voltage range and functions as a 4 096V output for the MAX187 with enabled internal reference REF also serves as a 2 5V to 4 8 REF Vpp input for a precision reference for both MAX187 disabled internal reference and MAX189 Bypass with 4 7uF if internal reference is used and with 0 1pF if an external reference is applied 5 GND Analog and digital ground 10 AGND Analog ground 11 DGND Digital ground 6 12 DOUT Serial data output Data changes state at SCLK s falling edge 7 15 cs Active low chip select initiates conversions on the falling edge When CS is high DOUT is high impedance 8 16 SCLK Serial clock input Clocks data out with rates up to 5MHz 2 4 5 7 9 13 14 N C Not internally connected Connect to AGND for best noise performance Detailed Description Converter Operatio
2. SERIAL INTERFACE ANALOG INPUT OV TO 45V SHUTDOWN REFERENCE INPUT 0 115 Figure 3b MAX189 Operational Diagram interval At this instant the T H switches the input side of Chorp to GND The retained charge on Chorp rep resents a sample of the input unbalancing the node ZERO at the comparator s input In hold mode the capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to OV within the limits of a 12 bit resolution This action is equivalent to transferring a charge from 0010 to the binary weighted capacitive DAC which in turn forms a digital representation of the analog input signal At the conversion s end the input side of Cuo_p switches back to AIN and Chorp charges to the input signal again The time required for the T H to acquire an input signal is a function of how quickly its input capacitance is charged If the input signal s source impedance is high the acquisition time lengthens and more time must be allowed between conversions Acquisition time is calculated by taco 9 Rs Rin 16pF where Riy 5kQ Rg the source impedance of the input signal and taco is never less than 1 545 Source impedances below 5kQ do not significantly affect the AC performance of the ADC 68TXVW Z8T XVIN MAX187 MAX189 15V Low Power 12 Bit Serial ADCs Input Bandwidth The ADCs input tracking circuitry has a 4 5MHz small signal bandwidth and an 8
3. ed by the 75ksps sample rate of the MAX187 MAX189 Therefore the maximum sinusoidal input frequency allowed is 37 5kHz Higher frequency signals cause aliasing problems unless undersampling techniques are used Reference The MAX187 can be used with an internal or external ref erence while the MAX189 requires an external reference Internal Reference The MAX187 has an on chip reference with a buffered temperature compensated bandgap diode laser trimmed to 4 096V 0 5 Its output is connected to REF and also drives the internal DAC The output can be used as a reference voltage source for other com ponents and can source up to 0 6mA Decouple REF with a 4 7uF capacitor The internal reference is enabled by pulling the SHDN pin high Letting SHDN float disables the internal reference which allows the use of an external reference as described in the External Reference section External Reference The MAX189 operates with an external reference at the REF pin To use the MAX187 with an external reference disable the internal reference by letting SHDN float Stay within the voltage range 2 5V to Vog to achieve speci fied accuracy The minimum input impedance is 12kQ for DC currents During conversion the external refer ence must be able to deliver up to 350pA DC load cur rent and have an output impedance of 100 or less The recommended minimum value for the bypass capacitor is 0 11 If the reference has higher output impedance
4. 40010 850 8 Plastic DIP 4 MAX189BEPA 40010 850 8 Plastic DIP 1 MAX189CEPA 40010 850 8 Plastic DIP 2 MAX189AEWE 40 C to 85 C 16 WideSO MAX189BEWE 40 C to 85 C 16 Wide SO 1 MAX189CEWE 40 C to 85 C 16 Wide SO 2 MAX189AMJA 55 C to 125 C 8 CERDIP n MAX189BMJA 55 C to 125 C 8 CERDIP 1 Dice are specified at T4 25 DC parameters only Contact factory for availability and processing to MIL STD 883 We APLAXLAW 15V Low Power 12 Bit Serial ADCs Chip Topography MAX187 MAX189 VDD SCLK D p 2 97mm TRANSISTOR COUNT 2278 SUBSTRATE CONNECTED TO Vpp MAKIM 68TXVW Z8T XVIN MAX187 MAX189 20 15V Low Power 12 Bit Serial ADCs Package Information E F E1 HHI 4 B1 P PACKAGE PLASTIC DUAL IN LINE DIM INCHES MILLIMETERS MIN MAX MIN MAX INCHES MIN 0 101mm 0 005in Printed USA INCHES MILLIMETERS MIN W PACKAGE SMALL O
5. MAXIB9 BUFFER ENABLE DISABLE CONTR TIMING NOTE PIN NUMBERS SHOWN ARE FOR 8 PIN DIPs ONLY MA KIM 15V Low Power 12 Bit Serial ADCs Features 12 Bit Resolution 4 LSB Integral Nonlinearity MAX187A MAX189A Internal Track Hold 75kHz Sampling Rate Single 5V Operation Low Power 2yA Shutdown Current 1 5mA Operating Current Internal 4 096V Buffered Reference MAX187 3 Wire Serial Interface Compatible with SPI QSPI and Microwire Small Footprint 8 Pin DIP and 16 Pin SO Ordering Information 9999 PART TEMP RANGE PIN PACKAGE SB MAXi87ACPA 0 Cto 70 C 8 Plastic DIP 4 MAX187BCPA 0 Cto 70 C 8 Plastic DIP 4 MAX187CCPA 0 Cto 70 C 8 Plastic DIP 2 MAX187ACWE 0 Cto 70 C 16WideSO 4 MAX187BCWE 0 Cto 70 C 16WideSO 1 MAX187CCWE 0 Cto 70 C 16WideSO 2 MAX187BC D 0 Cto 70 C Dice 1 Ordering Information continued on last page Dice are specified at TA 25 C DC parameters only Contact factory for availability and processing to MIL STD 883 Pin Configurations TOP VIEW 2 MAXIM MAX187 MAX189 Pin Configurations continued on last page SPI and QSPI are trademarks of Motorola Microwire is a trademark of National Semiconductor MAXIM Maxim Integrated Products 1 Call toll free 1 800 998 8800 for free samples or literature 68TXVW L8TXYW MAX187 MAX189 15V Low Power 12 Bit Se
6. gt MINIMUM CYCLE TIME Figure 8 MAX187 MAX189 Interface Timing Sequence INTERNAL TH Figure 9 MAX187 MAX189 Detailed Serial Interface Timing 12 AWLAXILMMW 15V Low Power 12 Bit Serial ADCs FULL SCALE TRANSITION w FS 4 096V 1Ls8 FS 4096 INPUT VOLTAGE LSBs FS 3 2LSB Figure 10 MAX187 MAX189 Unipolar Transfer Function 4 096V Full Scale Minimum cycle time is accomplished by using DOUT s rising edge as the EOC signal Clock out the data with 13 clock cycles at full speed Raise CS after the conver sion s LSB has been read After the specified minimum time taco CS can be pulled low again to initiate the next conversion Output Coding and Transfer Function The data output from the MAX187 MAX189 is binary and Figure 10 depicts the nominal transfer function Code transitions occur halfway between successive integer LSB values If VREF 4 096V then 1 LSB 1 00mV or 4 096V 4096 Dynamic Performance High speed sampling capability and a 75ksps through put make the MAX187 MAX189 ideal for wideband sig nal processing To support these and other related applications Fast Fourier Transform FFT test tech niques are used to guarantee the ADC s dynamic fre quency response distortion and noise at the rated throughput Specifically this involves applying a low distortion sine wave to the ADC input and recordi
7. or is noisy bypass it close to the REF pin with a 4 7uF capacitor COMPLETE CONVERSION SEQUENCE CONVERSION 0 POWERED UP POWERED DOWN Figure 5 MAX187 MAX189 Shutdown Sequence 10 CONVERSION 1 POWERED UP o AVLAZCLAWI 15V Low Power 12 Bit Serial ADCs REF 0 00000 CONVERSIONS PER SECON Figure 6 Average Supply Current vs Conversion Rate Serial Interface Initialization After Power Up and Starting a Conversion When power is first applied it takes the fully dis charged 4 7uF reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy With SHDN not pulled low the MAX187 MAX189 are now ready to convert To start a conversion pull CS low At CS s falling edge the T H enters its hold mode and a conversion is initiat ed After an internally timed 8 5us conversion period the end of conversion is signaled by DOUT pulling high Data can then be shifted out serially with the external clock Using SHDN to Reduce Supply Current Power consumption can be reduced significantly by shutting down the MAX187 MAX189 between conver sions This is shown in Figure 6 a pl
8. supplied to the converter and the isolated side of the opto couplers 74HC595 three state shift registers are used to construct a 12 bit paral lel data output The timing sequence is identical to the timing shown in Figure 8 Conversion speed is limited by the delay through the opto isolators With a 140kHz clock conversion time is 100129 The universal 12 bit parallel data output can also be used without the isolation stage when a parallel inter face is required Clock frequencies up to 2 9MHz are possible without violating the 20ns shift register setup time Delay or invert the clock signal to the shift regis ters beyond 2 9MHz Layout Grounding Bypassing For best performance use printed circuit boards Wire wrap boards are not recommended Board layout should ensure that digital and analog signal lines are separated from each other Do not run analog and digi tal especially clock lines parallel to one another or digital lines underneath the ADC package Figure 17 shows the recommended system ground connections A single point analog ground star ground point should be established at GND separate from the logic ground All other analog grounds should be connected to this ground The 16 pin versions also have a dedicated DGND pin available Connect DGND to this star ground point for further noise reduction No other digital system ground should be connected to this single point analog ground The ground return to the p
9. L 0 8 V SCLK CS Input Hysteresis Vuyst 0 15 SCLK CS Input Leakage lin Vin OV or Vpp 1 yA SCLK CS Input Capacitance Cin Note 4 15 pF SHDN Input High Voltage VINSH Vpp 0 5 V SHDN Input Low Voltage VINSL 0 5 V SHDN Input Current lins SHDN Vpp or OV 4 0 pA SHDN Input Mid Voltage Vim 1 5 Von 1 5 V SHDN Voltage Floating Vgr SHDN open 2 75 V A a SHDN open 100 100 nA DIGITAL OUTPUT DOUT Output Voltage Low VoL sink 5mA 0 4 V Isink 16mA 0 3 Output Voltage High VoH lsource 1mA 4 V Three State Leakage Current IL CS 5V 10 HA Cour CS 5V Note 4 15 pF POWER REQUIREMENTS Supply Voltage Von 4 75 5 25 V Operating mode 1 gt zi mA Supply Current lbp MAX189 1 0 2 0 Power down mode 2 10 HA Power Supply Rejection PSR Moa inte 19199000 4 096 0 06 0 5 mV MAKIM 15V Low Power 12 Bit Serial ADCs TIMING CHARACTERISTICS 1 00 5 0V 5 TA Tmin to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Track Hold Acquisition Time taco CS high Note 7 15 us SCLK Fall to Output Data Valid tbo Ci oap 100pF MATCE ee 130 ns MAX18__M 20 200 CS Fall to Output Enable tpv CLoap 100pF 100 ns CS Rise to Output Disable tr CLoap 100pF 100 ns SCLK Clock Frequency scLk 5 MHz SCLK Pulse Width High ton 100 ns SCLK Pulse Width Low teu 100 ns ed owo CS Fall teso 50 ns CS Pulse Width tes 500 ns Note 1 Tested at Vo
10. MAXIM MAX187 MAX189 MAXIM MAX187 MAX189 c MICROWIRE Figure 13 Common Serial Interface Connections to the MAX187 MAX189 MAKIM 15V Low Power 12 Bit Serial ADCs Applications Information Connection to Standard Interfaces The MAX187 MAX189 serial interface is fully compatible with SPI QSPI and Microwire standard serial interfaces If a serial interface is available set the CPU s serial interface in master mode so the CPU generates the ser ial clock Choose a clock frequency up to 2 5MHz 1 Use a general purpose 1 0 line on the CPU to pull CS low Keep SCLK low 2 Wait the for the maximum conversion time specified before activating SCLK Alternatively look for a DOUT rising edge to determine the end of conversion 3 Activate SCLK for a minimum of 13 clock cycles The first falling clock edge will produce the MSB of the DOUT conversion DOUT output data transitions on SCLK s falling edge and is available in MSB first for mat Observe the SCLK to DOUT valid timing charac teristic Data can be clocked into the uP on SCLK s rising edge 4 Pull CS high at or after the 13th falling clock edge If CS remains low trailing zeros are clocked out after the LSB 5 With CS high wait the minimum specified time tcs before launching a new conversion by pulling CS low If a conversion is aborted by pulling CS high before the conversions end wait for the minimum acquisition time tACQ before starting a new c
11. SIMAX187ACPA f RVR 19 0196 Rev 0 10 93 General Description The MAX187 MAX189 serial 12 bit analog to digital converters ADCs operate from a single 5V supply and accept a OV to 5V analog input Both parts feature an 8 5us successive approximation ADC a fast track hold 1 59 an on chip clock and a high speed 3 wire serial interface The MAX187 MAX189 digitize signals at a 75ksps throughput rate An external clock accesses data from the interface which communicates without external hardware to most digital signal processors and micro controllers The interface is compatible with SPITM QSPI and Microwire The MAX187 has an on chip buffered reference and the MAX189 requires an external reference Both the MAX187 and MAX189 save space with 8 pin DIP and 16 pin SO packages Power consumption is 7 5mW and reduces to only 10uW in shutdown Excellent AC characteristics and very low power con sumption combined with ease of use and small pack age size make these converters ideal for remote DSP and sensor applications or for circuits where power consumption and space are crucial Applications Portable Data Logging Remote Digital Signal Processing Isolated Data Acquisition High Accuracy Process Control Functional Diagram AV 1 638 10k 4 096V 2 5V BANDGAP REFERENCE MAX187 ONLY TH MAXUM COMPARATOR MAX187 CONTROL
12. UTLINE INCHES MILLIMETERS MIN MAX MIN MAX Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1993 Maxim Integrated Products MAXIM is a registered trademark of Maxim Integrated Products
13. V us slew rate It is possible to digitize high speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques To avoid aliasing of unwanted high frequency signals into the frequency band of interest an anti alias filter is rec ommended See the MAX274 MAX275 continuous time filters data sheet Input Protection Internal protection diodes that clamp the analog input allow the input to swing from GND 0 3V to Vpp 0 3V without damage However for accurate conversions near full scale the input must not exceed Vpp by more than 50mV or be lower than GND by 50mV If the analog input exceeds the supplies by more than 50mV beyond the supplies limit the input current to 2mA since larger currents degrade conversion accuracy Driving the Analog Input The input lines to AIN and GND should be kept as short as possible to minimize noise pickup Shield longer leads Also see the nput Protection section Because the MAX187 MAX189 incorporate a T H the drive requirements of the op amp driving AIN are less stringent than those for a successive approximation ADC without a T H The typical input capacitance is 16pF The amplifier bandwidth should be sufficient to handle the frequency of the input signal The MAX400 and OPO07 work well at lower frequencies For higher frequency operation the MAX427 and OP27 are practi cal choices The allowed input frequency range is limit
14. al clock 50 duty cycle MAX187 internal reference VREF 4 096V 4 7uF capacitor at REF pin or MAX189 external reference VREF 4 096V applied to REF pin 4 7uF capacitor at REF pin Ta Tmin to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Note 1 Resolution 12 Bits MAX18 A 4 Relative Accuracy Note 2 MAX18_B Z1 LSB MAX18 C 2 Differential Nonlinearity DNL No missing codes over temperature 1 LSB Offset Error MAX18_A 1 LSB MAX18_B C t3 MAX187 3 Gain Error Note 3 MAX189A t1 LSB MAX189B C 3 Gain Temperature Coefficient External reference 4 096V 0 8 ppm C DYNAMIC SPECIFICATIONS 10kHz sine wave input OV to 4 096V 75ksps SINAD 70 c s de Spurious Free Dynamic Range SFDR 80 dB Small Signal Bandwidth Rolloff 3dB 4 5 MHz Full Power Bandwidth 0 8 MHz 2 MAXIM 15V Low Power 12 Bit Serial ADCs ELECTRICAL CHARACTERISTICS continued Vpop 5V 596 GND OV unipolar input mode 75ksps fcLK 4 0MHz external clock 50 duty cycle MAX187 internal reference VREF 4 096V 4 7yF capacitor at REF pin or MAX189 external reference VRgr 4 096V applied to REF pin 4 7uF capacitor at REF pin TA TMIN to TMAx unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Conversion Time tconv 5 5 8 5 us Track Hold Acquis
15. ition Time taca 1 5 us Throughput Rate External clock 4MHz 13 clocks 75 ksps Aperture Delay taPR 10 ns Aperture Jitter 50 ps ANALOG INPUT Input Voltage Range Oto VREF V Input Capacitance Note 4 16 pF INTERNAL REFERENCE MAX187 only reference buffer enabled TA 25 C 4 076 4 096 4 116 REF Output Voltage Nace MAX187_C 4 060 4 132 V Ta Tn to Tax MAX187_E 4 050 4 140 MAX187_M 4 040 4 150 REF Short Circuit Current 30 mA MAX187AC BC 30 50 REF Tempco MAX187AE BE 30 60 ppm C MAX187AM BM 30 80 MAX187C 30 Load Regulation Note 5 OmA to 0 6mA output load 1 mV EXTERNAL REFERENCE AT REF Buffer disabled Vper 4 096V Input Voltage Range 2 50 Vpp 50mV V Input Current 200 350 HA Input Resistance 12 20 kQ Shutdown REF Input Current 1 5 10 HA MAKINN ps 68TXVW Z8TXVIA MAX187 MAX189 15V Low Power 12 Bit Serial ADCs ELECTRICAL CHARACTERISTICS continued Vpop 5V 596 GND OV unipolar input mode 75ksps 10161 4 0MHz external clock 50 duty cycle MAX187 internal reference VREF 4 096V 4 7uF capacitor at REF pin or MAX189 external reference VREF 4 096V applied to REF pin 4 7uF capacitor at REF pin TA TMIN to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS SCLK CS SHDN SCLK CS Input High Voltage VINH 2 4 V SCLK CS Input Low Voltage VIN
16. k out the 5V ON THIS SIDE OF BARRIER MUST BE ISOLATED POWER 12 bits of data with no trailing Os Figure 15 The maxi mum clock frequency to ensure compatibility with QSPI is 2 77MHz Opto Isolated Interface Serial to Parallel Conversion Many industrial applications require electrical isolation to separate the control electronics from hazardous electrical conditions provide noise immunity or pre vent excessive current flow where ground disparities exist between the ADC and the rest of the system Isolation amplifiers typically used to accomplish these tasks are expensive In cases where the signal is even tually converted to a digital form it is cost effective to isolate the input using opto couplers in a serial link The MAX187 is ideal in this application because it includes both T H amplifier and voltage reference operates from a single supply and consumes very little power Figure 16 CS START SCLK INPUT CLOCK QH SER GG 74HC595 QF QE QD D11 MSB 74HC04 74HC04 QU o SER oG 74HC595 QF SIGNAL GROUND ae 4 Figure 16 12 Bit Isolated ADC 16 QD Qc MAKIM 15V Low Power 12 Bit Serial ADCs The ADC results are transmitted across a 1500V isola tion barrier provided by three 6N136 opto isolators Isolated power must be
17. n 5V Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full scale range has been calibrated Note 3 MAX187 internal reference offset nulled MAX189 external 4 096V reference offset nulled Excludes reference errors Note 4 Guaranteed by design Not subject to production testing Note 5 External load should not change during conversion for specified ADC accuracy Note 6 DC test measured at 4 75V and 5 25V only Note 7 To guarantee acquisition time taca is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired AVLAZCLAWI 68TXVW Z8T XVIN MAX187 MAX189 15V Low Power 12 Bit Serial ADCs POWER SUPPLY REJECTION rriv SUPPLY CURENT mA 0 12 0 10 0 6 0 2 POWER SUPPLY REJECTION vs TEMPERATURE 60 20 20 60 100 140 EMPERATURE C SUPPLY CURRENT vs TEMPERATURE 60 20 20 60 100 140 TEMPERATURE C INTEFNAL FEFEFENCE VCLTAGE V 4 090 4 089 4 088 4 087 4 086 4 085 4 084 4 083 4 082 4 081 4 080 SHUTDOWN SUPPLY CURENT LA VREF vs Typical Operating Characteristics TEMPERATURE PERATURE C SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
18. n The MAX187 MAX189 use input track hold T H and successive approximation register SAR circuitry to convert an analog input signal to a digital 12 bit output No external hold capacitor is needed for the T H Figures 3a and 3b show the MAX187 MAX189 in their simplest configuration The MAX187 MAX189 convert input signals in the OV to Veer range in 10us including T H acquisition time The MAX187 s internal reference is trimmed to 4 096V while the MAX189 requires an external reference Both devices accept external refer ence voltages from 2 5V to Vpp The serial interface requires only three digital lines SCLK CS and DOUT and provides easy interface to microprocessors uPs Both converters have two modes normal and shut down Pulling SHDN low shuts the device down and reduces supply current to below 10pA while pulling SHDN high or leaving it floating puts the device into the operational mode A conversion is initiated by CS falling The conversion result is available at DOUT in AVLAZCLAWI unipolar serial format A high bit signaling the end of conversion EOC followed by the data bits MSB first make up the serial data stream The MAX187 operates in one of two states 1 internal reference and 2 external reference Select internal reference operation by forcing SHDN high and external reference operation by floating SHDN Analog Input Figure 4 illustrates the sampling architecture of the ADC s analog compara
19. ng the digital conversion results for a specified time The data is then analyzed using an FFT algorithm that deter mines its spectral content Conversion errors are then Seen as spectral elements outside of the fundamental AVLAZCLAWI fs 75ksps ft 10kHz TA 25 C AMPLITUDE dB Figure 11 MAX187 MAX189 FFT plot input frequency ADCs have traditionally been evaluat ed by specifications such as Zero and Full Scale Error Integral Nonlinearity INL and Differential Nonlinearity DNL Such parameters are widely accepted for speci fying performance with DC and slowly varying signals but are less useful in signal processing applications where the ADC s impact on the system transfer function is the main concern The significance of various DC errors does not translate well to the dynamic case so different tests are required Signal to Noise Ratio and Effective Number of Bits Signal to noise plus distortion SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS amplitude of all other ADC output signals The input bandwidth is limited to frequencies above DC and below one half the ADC sample conversion rate The theoretical minimum ADC noise is caused by quan tization error and is a direct result of the ADC s resolu tion SINAD 6 02N 1 76 dB where N is the number of bits of resolution An ideal 12 bit ADC can therefore do no better than 74dB An FFT plot of the outpu
20. onversion Data can be output in 1 byte chunks or continuously as shown in Figure 8 The bytes will contain the result of the conversion padded with one leading 1 and trailing Os if SCLK is still active with CS kept low HI Z EERE HI Z DOUT NMSBX D10 D7 v diu innii Figure 14 SPl Microwire Serial Interface Timing CPOL CPHA 0 Figure 15 QSPI Serial Interface Timing CPOL CPHA 0 MAKIM 15 68TXVW Z8T XVIN MAX187 MAX189 15V Low Power 12 Bit Serial ADCs SPI and Microwire When using SPI or QSPI set CPOL 0 and CPHA 0 Conversion begins with a CS falling edge DOUT goes low indicating a conversion in progress Wait until DOUT goes high or the maximum specified 8 5us con version time Two consecutive 1 byte reads are required to get the full 12 bits from the ADC DOUT out put data transitions on SCLK s falling edge and is clocked into the uP on SCLK s rising edge The first byte contains a leading 1 and 7 bits of conver sion result The second byte contains the remaining 5 bits and 3 trailing Os See Figure 13 for connections and Figure 14 for timing QSPI Set CPOL CPHA 0 Unlike SPI which requires two 1 byte reads to acquire the 12 bits of data from the ADC QSPI allows the minimum number of clock cycles necessary to clock in the data The MAX187 MAX189 require 13 clock cycles from the uP to cloc
21. ot of average sup ply current vs conversion rate Because the MAX189 uses an external reference voltage assumed to be pre sent continuously it wakes up from shutdown more quickly and therefore provides lower average supply currents The wakeup time twAKE is the time from SHDN deasserted to the time when a conversion may be initiated For the MAX187 this time is 2us For the MAX188 this time depends on the time in shutdown see Figure 7 because the external 4 7uF reference bypass capacitor loses charge slowly during shutdown see the specifications for shutdown REF Input Current 10pA max MAKLM 0 0001 0 001 Figure 7 twAKE vs Time in Shutdown MAX187 only External Clock The actual conversion does not require the external clock This frees the uP from the burden of running the SAR conversion clock and allows the conversion result to be read back at the uP s convenience at any clock rate from OMHz to 5MHz The clock duty cycle is unre stricted if each clock phase is at least 100ns Do not run the clock while a conversion is in progress Timing and Control Conversion start and data read operations are con trolled by the CS and SCLK digital inputs The timing diagrams of Figures 8 and 9 outline the operation of the serial interface A CS falling edge initiates a conver
22. ower supply for this ground should be low imped ance and as short as possible for noise free operation High frequency noise in the Von power supply may affect the ADC s high speed comparator Bypass this supply to the single point analog ground with 0 011 and 4 7uF bypass capacitors Minimize capacitor lead lengths for best supply noise rejection If the 5V power supply is very noisy a 109 resistor can be con nected as a lowpass filter to attenuate supply noise Figure 17 AVLAZCLAWI SUPPLIES 35V 04 MAXIM DIGITAL MAX187 CIRCUITRY MAX189 OPTIONAL Figure 17 Power Supply Grounding Condition 17 68TXVW L8TXYW MAX187 MAX189 15V Low Power 12 Bit Serial ADCs Ordering Information continued Pin Configurations continued PART TEMP RANGE PIN PACKAGE p MAX187AEPA 40010 850 8 Plastic DIP 4 MAX187BEPA 40 C to 85 C 8 Plastic DIP 1 MAX187CEPA 40 C to 85 C 8 Plastic DIP 2 MAX187AEWE 40 C to 85 C 16WideSO MAX187BEWE 40 C to 85 C 16 Wide SO 1 E xi MAX187CEWE 40 C to 85 C 16 Wide SO 2 MAX189 MAX187AMJA 55 C to 125 C 8 CERDIP 4 hg MAX187BMJA 55 C to 125 C 8 CERDIP 1 MAX189ACPA 0 Cto 70 C 8PlasticDIP 44 MAX189BCPA 0 Cto 70 C 8PlasticDIP 1 MAX189CCPA 0 Cto 70 C 8 Plastic DIP 2 Wide SO MAX189ACWE 0 Cto 70 C 16 Wide SO MAX189BCWE 0 Cto 70 C 16 Wide SO 1 MAX189CCWE 0 C to 70 C 16 Wide SO 2 MAX189BC D 0 Cto 70 C Dice 1 MAX189AEPA
23. rial ADCs ABSOLUTE MAXIMUM RATINGS VOD cp 0 3V to 6V Continuous Power Dissipation TA 70 C AIN to GND 0 3V to Vpp 0 3V 8 Pin Plastic DIP derate 9 09mW C above 70 C 500mW REF to GND 0 3V to Vpp 0 3V 16 Pin Wide SO derate 8 70mW C above 70 C 478mW Digital Inputs to GND 0 3V to Vpp 0 3V 8 Pin CERDIP derate 8 00mW C above 70 C 440mW Digital Outputs to GND 0 3V to Vpp 0 3V Operating Temperature Ranges SHDN to GND 0 3V to Vpp 0 3V MAX187 C MAX189 GC eeeeceeceereereeeeeee 0 C to 70 C REF Load Curre 4 0mA Continuous MAX187 E MAX189 E 40 C to 85 C REF Short Circuit Duration MAX187 ssssss MAX187 MJA MAX189 MJA 55 C to 125 C Storage Temperature Range 60 C to 150 C Lead Temperature soldering 10sec DOUT Current Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 5V 5 GND OV unipolar input mode 75ksps 1016 4 0MHz extern
24. sion sequence The T H stage holds input voltage the ADC begins to con vert and DOUT changes from high impedance to logic low SCLK must be kept inactive during the conversion An internal register stores the data when the conversion is in progress End of conversion EOC is signaled by DOUT going high DOUT s rising edge can be used as a framing signal SCLK shifts the data out of this register any time after the conversion is complete DOUT transitions on SCLK s falling edge The next falling clock edge pro duces the MSB of the conversion at DOUT followed by the remaining bits Since there are 12 data bits and one leading high bit at least 13 falling clock edges are needed to shift out these bits Extra clock pulses occur ring after the conversion result has been clocked out and prior to a rising edge of CS produce trailing Os at DOUT and have no effect on converter operation 11 68TXVW Z8TXVIA MAX187 MAX189 15V Low Power 12 Bit Serial ADCs SS 5 SS 55 c B11 B10 Bo Y Be Y B7 Y Be Y B5 Y B4 Y B3 Y B2 Y B1 Y B0 gc 1 12 l CONVERSION IN PROGRESS P CONVERSION INTERFACE IDLE oc gt CLOCK OUTPUT DATA gt AD TRACK gt TRACK 4 CON 1 STATE 8515 ico gt ops gt 12 x 0280us 3 25us tie e lt TOTAL 12 2545
25. t shows the output level in various spectral bands Figure 11 shows the result of sampling a pure 10kHz sine wave at a 75ksps rate with the MAX187 MAX189 13 68TXVW Z8T XVIN MAX187 MAX189 15V Low Power 12 Bit Serial ADCs UNDERSAMPLED 10 INPUT FREQUENCY Figure 12 Effective Bits vs Input Frequency The effective resolution effective number of bits the ADC provides can be determined by transposing the above equation and substituting in the measured SINAD N SINAD 1 76 6 02 Figure 12 shows the effective number of bits as a function of the input fre quency for the MAX187 MAX189 Total Harmonic Distortion If a pure sine wave is sampled by an ADC at greater than the Nyquist frequency the nonlinearities in the ADC s transfer function create harmonics of the input frequency present in the sampled output data Total Harmonic Distortion THD is the ratio of the RMS sum of all the harmonics in the frequency band above DC and below one half the sample rate but not includ ing the DC component to the RMS amplitude of the fundamental frequency This is expressed as follows V Va V32 V4 ee VN Vi where V4 is the fundamental RMS amplitude and Vo through Vy are the amplitudes of the 2nd through Nth harmonics The THD specification in the Electrical Characteristics includes the 2nd through 5th harmonics THD 20100 14 MAXIM MAX187 MAX189
26. tor The full scale input voltage depends on the voltage at REF ZERO FULL REFERENCE SCALE SCALE Internal Reference MAX187 only oy 4 096V External Reference ov VREF For specified accuracy the external reference voltage range spans from 2 5V to VDD 68TXVW L8TXVN MAX187 MAX189 15V Low Power 12 Bit Serial ADCs GLoan 100pF DGND a High Z to Voy and Voy to Voy Figure 1 Load Circuits for DOUT Enable Time CLoap 100pF DGND a Vgy to High Z Figure 2 Load Circuits for DOUT Disable Time CLoap 100pF DGND b High Z to Vo and Voy to VoL CLoap 100pF 040 b Voto High Z MAKIM 15V Low Power 12 Bit Serial ADCs ANALOG INPUT OV TO 45V SHUTDOWN INPUT ON or it 4 715 2 Figure 3a MAX187 Operational Diagram 12 BIT CAPACITIVE DAC REF 6 TRACK INPUT TD mp car 16pF COMPARATOR r o HOLD _ switch CPACKAGE _ mE 4 TRACK AT THE SAMPLING INSTANT THE INPUT SWITCHES FROM AIN TO GND Figure 4 Equivalent Input Circuit Track Hold In track mode the analog signal is acquired and stored in the internal hold capacitor In hold mode the T H switch opens and maintains a constant input to the ADC s SAR section During acquisition the analog input AIN charges capacitor 6 Bringing CS low ends the acquisition MAXIM

MAXIM MAX187/MAX189 Data Sheet

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