MAXIM MAX1065/MAX1066 datasheet
Contents
1. Read Convert Input Power up and put the MAX1065 MAX1066 in acquisition mode by holding R C low during the first falling edge of CS During the second falling edge of CS the level on R C determines whether the reference and reference buffer power down or remain on after conversion Set R C high during the second falling edge of CS to power down the reference and buffer or set R C low to leave the reference and buffer powered up Set R C high during the third falling edge of CS to put valid data on the bus End Of Conversion EOC drives low when conversion is complete Analog Supply Input Bypass with a 0 1uF capacitor to AGND Analog Ground Primary analog ground star ground 10 AGND Analog Input Analog Ground Connect Pin 14 to Pin 12 MAX1065 Connect Pin 10 to Pin 8 MAX1066 MAXIM Low Power 14 Bit Analog to Digital Converters with Parallel Interface Pin Description continued PIN NAME MAX1065 MAX1066 MAX1065 MAX1066 FUNCTION Reference Buffer Output Bypass REFADJ with a 0 1uF capacitor to AGND for 15 11 REFADJ internal reference mode Connect REFADJ to AVpp to select external reference mode Reference Input Output Bypass REF with a 1uF capacitor to AGND for internal reference mode External reference input when in external reference mode Reset Input Logic high resets the device High Byte Enable Input Used to multiplex the 14 bit con2. IDVDD Power Supply Rejection Ratio Note 4 AVpp 5V 5 full scale input TIMING CHARACTERISTICS Figures 1 and 2 AVpp 4 75V to 5 25V DVpp 2 7V to AVpp external reference 4 096V CREF 1uF CREFADJ 0 1uF Cp13 Do CEOC 20pF TA TMIN to Tmax unless otherwise noted Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS Acquisition Time taca Conversion Time tCONV CS Pulse Width High iCSH VDVDD 4 75V to 5 25V CS Pulse Width Low Note 5 VDVDD 2 7V to 4 74V RIC to CS Fall Setup Time D 4 75V to 5 25V D 2 7V to 5 25V RIC to CS Fall Hold Time VDVD VDVD VpvDpD 4 75V to 5 25V VDVD S to Output Data Valid DVDD 2 7V to 4 74V HBEN Transition To D 4 75V to 5 25V Output Data Valid MAX1066 only D 2 7V to 4 74V EOC Fall To CS Fall D 4 75V to 5 25V D 2 7V to 4 74V CS Rise To EOC Rise Bus Relinquish Time D 4 75V to 5 25V Note 5 D 2 7V to 4 74V Note 1 Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed Note 2 Offset nulled Note 3 Maximum specification is limited by automated test equipment Note 4 Defined as the change in positive full scale caused by a 5 variation in the nominal supply Note 5 To ensure best performance finish reading the data and wait tgr before starting a new acquisitio
3. The ADC may wake up from shutdown to an unknown state Put the ADC in a known state by completing one dummy conversion The MAX1065 MAX1066 will be in a known state ready for actual data acquisition after the completion of the dummy conversion A dummy conversion consists of one full conversion cycle The MAX1065 provides an alternative reset function to reset the device see RESET section Selecting Standby or Shutdown Mode The MAX1065 MAX1066 have a selectable standby or low power shutdown mode In standby mode the ADC s internal reference and reference buffer do not power down between conversions eliminating the need to wait for the reference to power up before performing the next conversion Shutdown mode powers down the reference and reference buffer after completing a con version Supply current is greatly reduced when in shutdown mode The reference and reference buffer require a minimum of 10ms CREFADJ 0 1uF CREF 1uF to power up and settle from shutdown The state of R C at the second falling edge of CS selects which power down mode the MAX1065 MAX1066 enters upon conversion completion Holding R C low causes the MAX1065 MAX1066 to enter stand by mode The reference and buffer are left on after the conversion completes R C high causes the MAX1065 MAX1066 to enter shutdown mode and shut down the reference and buffer after conversion Figures 5 and 6 When using an external reference set the REF power dow
4. capacitive DAC samples the analog input ce DATA VALID K gh mm gt oofa e D7 D13 D0 D8 HBEN AND BYTE WIDE DATA BUS AVAILABLE ON MAX1066 ONLY Figure 2 MAX1065 MAX1066 Timing Diagram 8 HIGH LOW BYTEVALID P HIGH LOW BYTE VALID MAXIM Low Power 14 Bit Analog to Digital Converters During the acquisition the analog input AIN charges capacitor CpAc The acquisition ends on the second falling edge of CS At this instant the T H switches open The retained charge on Cpac represents a sample of the input In hold mode the capacitive DAC adjusts during the remainder of the conversion time to restore node ZERO to zero within the limits of 14 bit resolution At the end of the conversion force CS low to put valid data on the bus The time required for the T H to acquire an input signal is a function of how quickly its input capacitance is charged If the input signal s source impedance is high the acquisition time lengthens and more time must be allowed between conversions The acquisition time taca is the maximum time the device takes to acquire the signal Use the following formula to calcu late acquisition time taca 11 Rs RIN x 35pF where RIN 800Q Rs the input signal s source impedance and tacqa is never less than 1 1us A source impedance less than 1kQ does not significantly affect the ADC s performance To improve the input si
5. should be switched immediately after acquisition rather than near the end of or after a conver sion This allows more time for the input buffer amplifier to respond to a large step change in input signal The input amplifier must have a high enough slew rate to complete MAXIM with Parallel Interface OUTPUT CODE A FULL SCALE nl TRANSITION ATO DOE FS VREF VREF 1LSB 76384 INPUT VOLTAGE LSB FS 3 2LSB Figure 8 MAX1065 MAX 1066 Transfer Function the required output voltage change before the beginning of the acquisition time At the beginning of acquisition the internal sampling capacitor array connects to AIN the amplifier output causing some output disturbance Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time If the frequency of interest is low AIN can be bypassed with a large enough capacitor to charge the internal sam pling capacitor with very little ripple However for AC use AIN must be driven by a wideband buffer at least 10MHz which must be stable with the ADC s capacitive load in parallel with any AIN bypass capacitor used and also settle quickly An example of this circuit using the MAX4484 is given in Figure 9 MAXIM MAX1065 MAX1066 ANALOG INPUT 10Q MAXIM MAX4434 Figure 9 MAX1065 MAX1066 Fast Settling Input Buffer 11 990 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Ana
6. shows a simplified internal architecture of the MAX1065 MAX1066 Figure 3 shows a typical application circuit for the MAX1066 Coan 20pF Croan 20pF DD DGND a HIGH Z TO Voy VoL TO Vou AND Vou TO HIGH Z b HIGH Z TO VoL VoH TO VoL A Vor TO HIGH Z Figure 1 Load Circuits for DO D13 Enable Time CS to DO D13 Delay Time and Bus Relinquish Time Fi Ia p UH ra taca e ei lou tps LI i e mmm Analog Input The equivalent input circuit is shown in Figure 4 A switched capacitor digital to analog converter DAC provides an inherent track and hold function The sin gle ended input is connected between AIN and AGND Input Bandwidth The ADC s input tracking circuitry has a 4MHz small signal bandwidth so it is possible to digitize high speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques To avoid aliasing of unwanted high frequency signals into the frequency band of interest use antialias filtering Internal protection diodes which clamp the analog input to AVpp and or AGND allow the input to swing from AGND 0 3V to AVpp 0 3V without damaging the device If the analog input exceeds 300mV beyond the sup plies limit the input current to 10mA Track and Hold T H In track mode the analog signal is acquired on the internal hold capacitor In hold mode the T H switches open and the
7. 20x log Effective Number of Bits Effective number of bits ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate An ideal ADC s error consists of quanti zation noise only With an input range equal to the full scale range of the ADC calculate the effective number of bits as follows ENOB SINAD 1 76 6 02 Total Harmonic Distortion Total harmonic distortion THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself This is expressed as Lu ENER EMS Vy L where V1 is the fundamental amplitude and Va through V5 are the 2nd through 5th order harmonics THD 20x log Spurious Free Dynamic Range Spurious free dynamic range SFDR is the ratio of the RMS amplitude of the fundamental maximum signal component to the RMS value of the next largest fre quency component Chip Information TRANSISTOR COUNT 15 140 PROCESS BiCMOS MAXIM Low Power 14 Bit Analog to Digital Converters with Parallel Interface MAXIM MAXIM MAX1065 D4 D12 Ds D13 D6 0 D7 0 AGND MAXIMA MAX1066 Pin Configurations D3 D11 D2 D10 D1 D9 D0 D8 DVpp DND REFADJ 13 990LXVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface Package Information Ra a Ww wo e Es fi O 2 a 2 H
8. A 400 3 T 2 70 0 005 c 200 60 S 3 S 0 S 0 2 5 i D G 200 Z 0 005 40 400 S 30 0 010 600 20 800 0 015 10 SAMPLE RATE 165ksps 0 0 020 0 40 20 0 2 4 60 80 40 20 0 2 4 60 80 01 1 10 100 TEMPERATURE C TEMPERATURE C FREQUENCY kHz MAA 5 990 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface TOTAL HARMONIC DISTORTION vs FREQUENCY MAX1065 MAX1066 toc10 THD dB 0 1 PIN 1 FREQUENCY 100 NAME SFDR dB Typical Operating Characteristics continued AVpp DVpp 5V external reference 4 096V CREF 1HF CREFADJ 0 1pF Ta 25 C unless otherwise noted SPURIOUS FREE DYNAMIC RANGE vs FREQUENCY FFT AT 1kHz SAMPLE RATE 165ksps MAX1065 MAX1066 toc11 MAX1065 MAX1066 toc12 MAGNITUDE dB MAX1065 1 MAX1066 1 MAX1065 D6 MAX1066 D4 D12 D5 D13 RATE 165ks 1 0 0 100 FREQUENCY kH N FREQUENCY kHz Pin Description FUNCTION Three S Three S i utput D13 is the MSB D6 0 Three S i utput D7 0 Three S i utput Three S i utput Three S i utput Three S Three State Digital Data Output MSB
9. COMMON DIMENSIONS 2 H IN H MIN MAX 043 002 006 033 037 007 012 007 010 0035 008 i i 0035 0053 SEE VARIATIONS SEE VARIATIONS BOTTOM VIEW 129 177 SEE DETAIL A 026 BSC 625 6 50 246 256 0 5 0 70 020 028 SEE VARIATIONS SEE VARIATIONS cl O ER ge ER SIDE VIEW MO 153 N AB 1 025 PARTING BSC A ee WITH PLATING AD 7 20 28 D 9 60 9 80 i Cl E DETAIL A BASE METAL NOTES LEAD TIP DETAIL 1 DIMENSIONS D AND E DO NOT INCLUDE FLASH 2 MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0 15mm PER SIDE E 3 CONTROLLING DIMENSION MILLIMETER AWN 4A X l AWN A MEETS JEDEC OUTLINE MO 153 SEE JEDEC VARIATIONS TABLE Nr REFERS TO NUMBER OF LEADS PROPRIETARY TNETRAATION THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE THIS TOLERANCE d ZONE IS DEFINED BY TWO PARALLEL PLANES ONE PLANE IS THE SEATING PLANE PACKAGE OUTLINE TSSOP 4 40 MM BODY DATUM C THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM C IN THE APPROVAL DOCUMENT CONTROL NO SCT DIRECTION INDICATED 21 0066 E d Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 14 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2002 Maxim Integrated Products Printed USA MAXIM is a registered
10. D with 1uF and 0 1uF respectively Fine adjustments can be made to the internal reference voltage by sinking or sourcing current at REFADJ The input impedance at REFADJ is nominally 5kQ The internal reference volt age is adjustable to 1 5 with the circuit of Figure 7 External Reference An external reference can be placed at either the input REFADJ or the output REF of the MAX1065 MAX1066 s internal buffer amplifier When connecting an external reference to REFADu the input impedance is typically 5kQ Using the buffered REFADJ input makes buffering the external reference unnecessary however the internal buffer output must be bypassed at REF with a 1uF capacitor Connect REFADJ to AVpp to disable the internal buffer Directly drive REF using an external reference During conversion the external reference must be able to drive 100A of DC load current and have an output impedance of 10Q or less REFADu s impedance is typ ically 5kQ The DC input impedance of REF is 40kQ minimum For optimal performance buffer the reference through an op amp and bypass REF with a 1uF capacitor Consider the MAX1065 MAX1066 s equivalent input noise 8OUVRMS when choosing a reference Le DATA a our i REFPOWER DOWN BIT Figure 6 Selecting Shutdown Mode MAXIM Low Power 14 Bit Analog to Digital Converters MAXIM MAX1065 MAX1066 REFADJ Figure 7 MAX1065 MAX 1066 Reference Adjust Circuit Re
11. OG 5V DIGITAL MAXIM MAX1065 REFADJ AGND DND MAKIM gt gt gt gt a gt dh d al dh Low Power 14 Bit Analog to Digital Converters with Parallel Interface Parallel Interface High Speed 165ksps Sample Rate Accurate 1LSB DNL max 1LSB INL max 4 096V 35ppm C Internal Reference External Reference Range 3 8V to 5 25V Single 4 75V to 5 25V Analog Supply Voltage 2 7V to 5 25V Digital Supply Voltage Low Supply Current 1 8mA External Reference 2 7mA Internal Reference Features 14 Bit Wide MAX1065 and Byte Wide MAX1066 0 1mA AutoShutdown Mode 10ksps External Reference Small Footprint 28 Pin TSSOP Package 14 Bit Wide 20 Pin TSSOP Package Byte Wide PART Ordering Information TEMP RANGE PIN PACKAGE MAX1065ACUI 0 C to 70 C 28 TSSO MAX1065BCUI MAX1065CCUI MAX1065AEUI 0 C to 70 C 0 C to 70 C 40 C to 85 C 28 TSSO 28 TSSO 28 TSSO MAX1065BEUI 40 C to 85 C 28 TSSO MAX1065CEUI 40 C to 85 C 28 TSSO MAX1066ACUP 0 C to 70 C 20 TSSO MAX1066BCUP MAX1066CCUP MAX1066AEUP 0 C to 70 C 0 C to 70 C 40 C to 85 C 20 TSSO 20 TSSO 20 TSSO MAX1066BEUP 40 C to 85 C 20 TSSO MAX1066CEUP 40 C to 85 C 20 TSSO Pin Configurations appear at end of data sheet AutoShutdown is a registered trademark of Maxim Integrated P
12. ZS i8 M AX 10654 W ge 19 2466 Rev 0 4 02 General Description The MAX1065 MAX1066 14 bit low power successive approximation analog to digital converters ADCs fea ture automatic power down a factory trimmed internal clock and a high speed 14 bit wide MAX1065 or byte wide MAX1066 parallel interface The devices operate from a single 4 75V to 5 25V analog supply and a 2 7V to 5 25V digital supply The MAX1065 MAX1066 use an internal 4 096V refer ence or an external reference The MAX1065 MAX1066 consume only 1 8mA at a sampling rate of 165ksps with external reference and 2 7mA with internal reference AutoShutdown reduces supply current to 0 1mA at 10ksps The MAX1065 MAX1066 are ideal for high performance battery powered data acquisition applications Excellent dynamic performance and low power con sumption in a small package make the MAX1065 MAX1066 the best choice for circuits with demanding power consumption and space requirements The 14 bit wide MAX1065 is available in a 28 pin TSSOP package and the byte wide MAX1066 is available in a 20 pin TSSOP package Both devices are available in either the 0 C to 70 C commercial or the 40 C to 85 C extended temperature range Applications Cable Harness Tester Accelerometer Measurements Digital Signal Processing Temperature Sensor Monitor Industrial Process Control IO Boards Data Acquisition Systems Typical Operating Circuit 5V ANAL
13. ading the Conversion Result EOC is provided to flag the microprocessor when a con version is complete The falling edge of EOC signals that the data is valid and ready to be output to the bus DO D13 are the parallel outputs of the MAX1065 MAX1066 These three state outputs allow for direct connection to a microcontroller UO bus The outputs remain high impedance during acquisition and conver sion Data is loaded onto the bus with the third falling edge of CS with R C high after toons Bringing CS high forces the output bus back to high impedance The MAX1065 MAX1066 then waits for the next falling edge of CS to start the next conversion cycle Figure 2 The MAX1065 loads the conversion result onto a 14 bit wide data bus while the MAX1066 has a byte wide out put format HBEN toggles the output between the most least significant byte The least significant byte is loaded onto the output bus when HBEN is low and the most significant byte is on the bus when HBEN is high Figure 2 a RESET Toggle RESET with CS high The next falling edge of CS will begin acquisition This reset is an alternative to the dummy conversion explained in the Starting a Conversion section Transfer Function Figure 8 shows the MAX1065 MAX1066 output transfer function The output is coded in standard binary Input Buffer Most applications require an input buffer amplifier to achieve 14 bit accuracy If the input signal is multiplexed the input channel
14. gnal bandwidth under AC condi tions drive AIN with a wideband buffer gt 4MHz that can drive the ADC s input capacitance and settle quickly Power Down Modes Select standby mode or shutdown mode with the R C bit during the second falling edge of CS see Selecting Standby or Shutdown Mode section The MAX1065 MAX1066 automatically enter either standby mode ref erence and buffer on or shutdown reference and buffer off after each conversion depending on the sta tus of R C during the second falling edge of CS 5V ANALOG 5V DIGITAL ANALOG INPUT gt AIN MAXIM MAX1066 EOC Figure 3 Typical Application Circuit for MAX 1066 MAXIM with Parallel Interface Internal Clock The MAX1065 MAX1066 generate an internal conver sion clock This frees the microprocessor from the bur den of running the SAR conversion clock Total conversion time after entering hold mode second falling edge of CS to end of conversion EOC falling is A Zus max Applications Information a B Starting a Conversion CS and R C control acquisition and conversion in the MAX1065 MAX1066 Figure 2 The first falling edge of CS powers up the device and puts it into acquisition mode if R C is low The convert start is ignored if R C is high When powering up from shutdown the MAX1065 MAX1066 needs at least 10ms CREFADJ 0 1uF CREF 1uF for the internal reference to wake up and settle before starting the conversion
15. log to Digital Converters with Parallel Interface Layout Grounding and Bypassing For best performance use printed circuit boards Do not run analog and digital lines parallel to each other and do not lay out digital signal paths underneath the ADC pack age Use separate analog and digital ground planes with only one point connecting the two ground systems ana log and digital as close to the device as possible Route digital signals far away from sensitive analog and reference inputs If digital lines must cross analog lines do so at right angles to minimize coupling digital noise onto the analog lines If the analog and digital sections share the same supply then isolate the digital and ana log supply by connecting them with a low value 10Q resistor or ferrite bead The ADC is sensitive to high frequency noise on the AVpp supply Bypass AVpp to AGND with a 0 1uF capacitor in parallel with a 1uF to 10uF low ESR capacitor and the smallest capacitor closest to the device Keep capacitor leads short to minimize stray inductance Definitions Integral Nonlinearity Integral nonlinearity INL is the deviation of the values on an actual transfer function from a straight line This straight line can be either a best straight line fit or a line drawn between the end points of the transfer function once offset and gain errors have been nullified The static linearity parameters for the MAX1065 MAX1066 are measured using the end p
16. n 4 MAXIM Low Power 14 Bit Analog to Digital Converters with Parallel Interface Typical Operating Characteristics AVpp DVpp 5V external reference 4 096V CREF 1uF CREFADJ 0 1UF Ta 25 C unless otherwise noted lavop Ipvpp SUPPLY CURRENT DNL vs OUTPUT CODE INL vs OUTPUT CODE vs SAMPLE RATE 3 g 10 3 S ZS S 2 8 S a 2 2 S 0 01 a a 0 001 j 0 0001 0 4096 8192 12288 16384 0 4096 8192 12288 16384 um 01 1 10 100 1000 OUTPUT CODE OUTPUT CODE CONVERSION RATE ksps lavop Ipvpp SUPPLY CURRENT lavop lpvpp SHUTDOWN CURRENT INTERNAL REFERENCE vs TEMPERATURE vs TEMPERATURE vs TEMPERATURE s 50 e 4 136 e g 45 2 um g 40 2 8 3 2 54116 S S 4 g3 2 38 Z S 30 S 4108 co 5 25 4096 S 20 ZS 4 086 a S A 5 5 15 E E 4076 1 0 j 4 066 SAMPLE RATE 165ksps 0 4 056 40 20 0 2 40 60 om 40 20 0 2 4 60 80 TEMPERATURE C TEMPERATURE C TEMPERATURE C OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE SINAD vs FREQUENCY 1000 z 0 020 100 z 800 S ET 90 600 A 80 _ Z mg S Z
17. n bit high for lowest current operation 9901 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface AIN CAPACITIVE DAC CswitcH 3pF 4 Coac 32pF AUTO ZERO RAIL Figure 4 Equivalent Input Circuit Standby Mode While in standby mode the supply current is reduced to less than 1mA typ The next falling edge of CS with R C low causes the MAX1065 MAX1066 to exit standby mode and begin acquisition The reference and refer ence buffer remain active to allow quick turn on time Standby mode allows significant power savings while running at the maximum sample rate Shutdown Mode In shutdown mode the reference and reference buffer are shut down between conversions Shutdown mode reduces supply current to 0 5pA typ immediately after the conversion The falling edge of CS with R C low causes the reference and buffer to wake up and enter acquisition mode To achieve 14 bit accuracy allow 10ms CREFADJ 0 1uF CREF 1uF for the internal reference to wake up Increase wakeup time propor tionally when using larger values of CREFADJ and CREF DATA Kee CONVERSION CN REF POWER DOWNBIT BUFFER Figure 5 Selecting Standby Mode 10 Internal and External Reference Internal Reference The internal reference of the MAX1065 MAX1066 is internally buffered to provide 4 096V typ output at REF Bypass REF to AGND and REFADJ to AGN
18. oint method Differential Nonlinearity Differential nonlinearity DNL is the difference between an actual step width and the ideal value of 1LSB A DNL error specification of 1LSB guarantees no missing codes and a monotonic transfer function Aperture Jitter and Delay Aperture jitter is the sample to sample variation in the time between samples Aperture delay is the time between the rising edge of the sampling clock and the instant when the actual sample is taken Signal to Noise Ratio For a waveform perfectly reconstructed from digital samples signal to noise ratio SNR is the ratio of the full scale analog input RMS value to the RMS quanti zation error residual error The ideal theoretical mini mum analog to digital noise is caused by quantization noise error only and results directly from the ADC s res olution N bits SNR 6 02 x N 1 76 dB where N 14 bits 12 In reality there are other noise sources besides quanti zation noise thermal noise reference noise clock jitter etc SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental the first five har monics and the DC offset Signal to Noise Plus Distortion Signal to noise plus distortion SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS equivalent of all the other ADC output signals Signalams Noise Distortion Rus SINAD B
19. pp SV external reference 4 096V CREF 1uF CREFADJ 0 1uF TA TMIN to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS DC ACCURACY Resolution MAX106_A Relative Accuracy Note 1 MAX106_B Differential Nonlinearity MAX106_C No missing codes over temperature Transition Noise i noise RMS noise includes quantization 0 32 Offset Error 0 2 1 Gain Error Note 2 0 002 0 02 Offset Drift Gain Drift DYNAMIC PERFORMANCE fiN SINE WAVE 1kHz Vin 4 096Vp p 165ksps 0 6 Signal to Noise Plus Distortion SINAD Signal to Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Power Bandwidth Full Linear Bandwidth 3dB point SINAD gt 81dB CONVERSION RATE Sample Rate fSAMPLE Aperture Delay Aperture Jitter ANALOG INPUT Input Range VAIN 0 VREF V Input Capacitance CAIN 40 pF 2 dl d Lab Low Power 14 Bit Analog to Digital Converters with Parallel Interface ELECTRICAL CHARACTERISTICS continued AVpp DVpp 5V external reference 4 096V CReF 1uF CREFADJ 0 1UF Ta Tmin to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX INTERNAL REFERENCE REF Output Voltage VREF 4 056 4 096 4 136 REF Output Tempco TCREF 35 REF Short Circuit Current IREFSC 10 Capacitive Bypass a
20. roducts Inc Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 990 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface ABSOLUTE MAXIMUM RATINGS AVpp to AGND 6V DVpp to DGND 6V AGND to DND 0 3V to 0 3V AIN REF REFADJ to AGND 0 3V to AVpp 0 3V CS HBEN R C RESET to DGND 0 3V to 6V Digital Output D13 Do EOC to DGND oiiire 0 3V to DVpp 0 3V Maximum Continuous Current Into Any Pin 50mA Continuous Power Dissipation Ta 70 C 20 Pin TSSOP derate 10 9mW C above 70 C 879mMW 28 Pin TSSOP derate 12 8mW C above 70 C 1026mW Operating Temperature Ranges MAX OG CU inion oriai 0 C to 70 C MCL JEU iienaa 40 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Lead Temperature soldering 1Oei 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS AVpp DV
21. t REFADJ CREFADJ Capacitive Bypass at REF CREF REFADJ Input Leakage Current IREFADJ EXTERNAL REFERENCE REFADJ Buffer Disable Threshold REF Input Voltage Range Internal reference disabled VREF 4 096V fsAMPLE 165ksps To power down the internal reference REF Input Current IREF Shutdown mode DIGITAL INPUTS OUTPUTS CS R C EOC D0 D13 RESET HBEN put High Voltage put Low Voltage put Leakage Current ViH 0 or DVpp put Hysteresis put Capacitance SOURCE 0 5mA Output High Voltage DVpp 2 7V to 5 25V AVpp 5 25V SINK 1 6mA Output Low Voltage DVpp 2 7V to 5 25V AVpp 5 25V Three State Leakage Current DO D13 Three State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Internal reference Analog Supply Current External reference MAXIM 3 9901 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface ELECTRICAL CHARACTERISTICS continued AVpp DVpp 5V external reference 4 096V CREF 1uF CREFADJ 0 1uF TA TmIN to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIO Digital Supply Current IDVDD DO D13 all zeros IAVDD Full power down Shutdown Supply Current IDVDD Note 3 REF and REF IAVDD buffer enabled standby mode
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23. version result 1 Most significant byte available on the data bus 0 Least significant byte available on the data bus Convert Start The first falling edge of CS powers up the device and enables acquire mode when R C is low The second falling edge of CS starts conversion The third falling edge of CS loads the result onto the bus when R C is high Digital Ground Digital Supply Voltage Bypass with a 0 1uF capacitor to DGND o Connection Do Not Connect MAX1065 Three State Digital Data Output MAX1066 o Connection Do Not Connect MAX1065 Three State Digital Data Output MAX1066 Functional Diagram REFADJ HBEN AVpp AGND DVpp DGND REFERENCE OUTPUT E REGISTERS D0 D8 D5 D13 CAPACITIVE MAXIM DAC MAX1065 MAX1066 SUCCESSIVE APPROXIMATION REGISTER AND CONTROL LOGIC BYTE WIDE MAX1066 ONLY 16 BIT WIDE MAX1065 0 MAXIM 7 9901 XVIN S9OLXVIN MAX1065 MAX 1066 Low Power 14 Bit Analog to Digital Converters with Parallel Interface Detailed Description Converter Operation The MAX1065 MAX1066 use a successive approximation SAR conversion technique with an inherent track and hold T H stage to convert an analog input into a 14 bit digital output Parallel outputs provide a high speed inter face to most microprocessors uPs The Functional Diagram
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MAXIM MAX1065/MAX1066 datasheet