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XILINX XC5200 series field programmable gate arrays

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1. XC3000 family The XC5200 family does not provide an GRM GRM on chip crystal oscillator amplifier but it does provide internal oscillator from which variety of frequencies up to Block Block Block 12 MHz are available Architectural Overview Figure 1 presents a simplified conceptual overview of the XC5200 architecture Similar to conventional FPGAs the XC5200 family consists of programmable IOBs program GRM GRM GRM mable logic blocks and programmable interconnect Unlike Versa Versa Versa other FPGAs however the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks Figure 2 General purpose routing connects to the VersaBlock through the General Routing Matrix X4955 GRM VersaRing VersaRing VersaRing Figure 1 5200 Architectural Overview VersaBlock Abundant Local Routing Plus Versatile Logic The basic logic element in each VersaBlock structure is the Logic Cell shown in Figure 3 Each LC contains a 4 input function generator F a storage device FD an
2. NOTE NOTE M2 M1 MO can be shorted M2 M1 MO can be shorted to Ground if not used as I O to VCC not used as vec 3 3 lt 3 3 3 3 23 3 1 M2 gt DIN DOUT gt gt 5200 72 XC3100A XC4000E EX SERIAL 5200 SLAVE SLAVE DIN PROGRAM LDC PROGRAM gt RESET m DONE iNIT RESET OE DONE INIT D P INIT lt gt Low Reset Option Used 4 PROGRAM 1 X9003 01 Figure 28 Master Slave Serial Mode Circuit Diagram CCLK DOUT Output m gt lt 2 gt 5379 Symbol Min Max Units DIN setup 1 20 5 DIN hold 2 0 ns CCLK DIN DOUT 3 Toco 30 ns High time 4 45 5 Low time 5 Toot 45 ns Frequency Foc 10 MHz Note Figure 29 Slave Serial Mode Programming Switching Characteristics 7 114 Configuration must be delayed until the INIT pins of all daisy chained FPGAs are High November 5 1998 Version 5 2 5 XILINX XC5200 Series Field Programmable Gate Arrays Master Serial Mode In Master Serial mode the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input Each rising edge of the CCLK output increments the Serial PROM internal address counter The next
3. Pin Description PC84 PQ100 100 TQ144 PG156 PQ160 Boundary Scan Order 14 yo 141 03 157 129 15 A14 9 1 98 142 B1 158 138 16 A15 10 2 99 143 B2 159 141 VCC 11 3 100 144 160 GND 12 4 1 1 4 1 1 17 GCK1 A16 I O 13 5 2 2 B3 2 150 18 A17 14 6 3 3 Al 3 153 19 4 2 4 159 20 5 5 5 162 21 TDI 15 7 4 6 4 6 165 22 16 8 5 7 7 171 GND 8 C6 10 23 yo 9 5 11 174 24 yo 10 B6 12 177 25 TMS 17 9 6 11 5 13 180 26 18 10 7 12 7 14 183 27 yo 1 13 B7 15 186 28 y o 11 8 14 A6 16 189 29 y o 19 12 9 15 17 195 30 20 13 10 16 8 18 198 GND 21 14 11 17 C8 19 22 15 12 18 20 31 y o 23 16 13 19 C9 21 201 32 yo 24 17 14 20 B9 22 207 33 18 15 21 9 23 210 34 E 1 2 22 B10 24 213 35 25 19 16 23 C10 25 219 36 26 20 17 24 10 26 222 37 25 11 27 225 38 26 11 28 231 GND 27 11 29 1 39 y o 27 21 18 28 B12 32 234 40 y o x 22 19 29 A13 33 237 41 yo 5 30 14 34 240 42 31 12 35 243 43 28 23 20 32 B13 36 246 44 yo 29 24 21 33 B14 37 249 45 M1 I O 30 25 22 34 A15 38 258 GND 31 26 23 35 C13 39 46 32 27 24 36 16 40 261 33 28 25 37 14 41 47 2 I O 34 29 26 38 15 42 264 48 GCk2 I O 35 30 27 39 B16 43 267 49
4. Pin Description Ta144 160 176 PQ208 PG223 BG225 240 Boundary Sean 50 24 20 22 24 28 810 H5 32 330 5t 21 23 25 29 A9 12 33 333 52 10 22 24 26 30 34 339 53 27 381 J3 35 342 54 O 2 28 32 36 345 55 10 Dii 45 38 351 56 10 021 39 354 40 57 10 25 23 25 29 33 K2 41 357 58 10 26 24 26 30 34 A 42 363 59 25 27 31 35 812 J 43 366 6 10 26 28 32 36 O 44 369 GND 27 29 33 37 12 GND 45 61 013 12 46 375 62 10 014 47 378 63 10 48 381 64 10 39 49 387 65 10 30 34 40 A5 5 50 390 66 31 35 41 2 51 393 67 27 28 32 36 42 14 52 399 68 10 29 33 37 43 A16 53 402 69 10 30 34 38 44 815 54 405 70 31 35 39 45 014 55 411 71 10 28 32 36 40 46 Ai7 56 414 72 O 2 33 37 41 47 Bie Pi 57 417 73 30 34 38 42 48 015 58 426 GND 31 35 39 43 49 015 GND 59 74 MO W O 32 36 40 44 55 8 P2 60 429 33 37 41 45 55 016 75 2 10 34 38 42 46 56 62 432 76 GCK2 1 0 35 39 43 47 57 R2 63 435 77 VO HDC
5. Pin Description PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 87 2 5 72 80 17 94 468 88 yo 48 48 45 65 73 81 N16 95 471 89 yo 49 49 46 66 74 82 T17 96 480 90 yo 67 75 83 R17 97 483 91 yo 68 76 84 P16 98 486 92 yo 50 50 47 69 77 85 U18 99 492 93 yo 51 51 48 70 78 86 T16 100 495 GND 52 52 49 71 79 87 R16 101 53 53 50 72 80 88 017 103 VCC 54 54 51 73 81 89 R15 106 PROG 55 55 52 74 82 90 18 108 94 D7 56 56 53 75 83 91 T15 109 504 95 GCK I O 57 57 54 76 84 92 U16 110 507 96 5 5 77 85 93 T14 111 516 97 yo 78 86 94 U15 112 519 98 D6 58 58 55 79 87 95 V17 113 522 99 yo 59 56 80 88 96 V16 114 528 100 I O 89 97 T13 115 531 101 10 90 98 U14 116 534 GND 5 81 91 99 12 119 5 102 10 82 92 100 13 120 540 103 83 93 101 V13 121 543 104 I O D5 59 60 57 84 94 102 U12 122 552 105 CSO 60 61 58 85 95 103 12 123 555 106 1 104 11 124 558 107 105 011 125 564 108 62 59 86 96 106 11 126 567 109 63 60 87 97 107 V10 127 570 110 04 61 64 61 88 98 108 U10 128 576 111 110 62 65 62 89 99 109 T10 129 579 VCC 63 66 63 90 100 110 R10 130 GND 64 67 64 91 101 111 R9 131 112 D3 65 68 65 92 102 112 T9 132 588 113 RS 66 69 66 93 103 113 U9 133 591 114 B 70 67 94
6. XC5200 CCLK SYNC 1 Di Dic XC5200 U2 U3 U4 UCLK_NOSYNC U2 U3 U4 YO XC5200 Di Di 2 UCLK_SYNC GSR Active Di Di 1 Synchronization 4 5 Uncertainty L UCLK Period X6700 Figure 25 Start up Timing November 5 1998 Version 5 2 7 109 XC5200 Series Field Programmable Gate Arrays XILINX Configuration The length counter begins counting immediately upon entry into the configuration state In slave mode operation it is important to wait at least two cycles of the internal 1 MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream Configuration will not begin until the internal configuration logic reset is released which happens two cycles after INIT goes High A master device s configuration is delayed from 32 to 256 us to ensure proper operation with any slave devices driven by the master device The 0010 preamble code included for all modes except Express mode indicates that the following 24 bits repre sent the length count The length count is the total number of configuration clocks needed to load the complete config uration data Four additional configuration clocks are required to complete the configuration process as dis cussed below After the preamble and the length count have been passed through to all devices in the daisy chain DOUT
7. Description Symbol Device ns ns TBUF driving a Longline Tio XC5202 6 0 2 0 TS XC5204 6 4 2 3 9 5206 6 6 27 XC5210 6 6 2 9 to Longline while TS is Low i e buffer is constantly ac XC5215 7 3 3 2 tive TS going Low to Longline going from floating High or Low Ton XC5202 7 8 4 0 to active Low or High XC5204 8 3 4 3 XC5206 8 4 4 4 XC5210 8 4 4 4 XC5215 8 9 4 5 TS going High to going inactive not driving Torr XC52xx 3 0 2 4 Longline Note 1 Die size dependent parameters are based upon XC5215 characterization Production specifications will vary with array size 7 128 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays 5200 CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL M 38510 605 All devices are 100 functionally tested Since many internal timing parameters cannot be measured directly they are derived from benchmark timing patterns The following guidelines reflect worst case values over the recommended operating conditions For more detailed more precise and more up to date timing information use the values provided by the timing calculator and used in the simulator Min Max Min Max Min Max Min Max Description Symbol ns ns ns ns ns ns ns ns Combinatorial Delays F inputs to X output
8. November 5 1998 Version 5 2 7 133 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description VQ64 PC84 100 VQ100 TQ144 PG156 Boundary Scan Order 35 HDC 19 36 31 28 40 014 204 36 32 29 43 14 207 37 LDC 20 37 33 30 44 16 210 GND 45 F14 38 5 38 34 31 48 F16 216 39 21 39 35 32 49 G14 219 40 5 36 33 50 G15 222 41 37 34 51 16 228 42 22 40 38 35 52 H16 231 43 ERR INIT 23 41 39 36 53 15 234 VCC 24 42 40 37 54 H14 GND 25 43 41 38 55 J14 44 26 44 42 39 56 915 240 45 27 45 43 40 57 916 243 46 44 41 58 K16 246 47 45 42 59 15 252 48 y o 28 46 46 43 60 K14 255 49 29 47 47 44 61 116 258 GND 64 L14 50 48 48 45 65 16 264 51 30 49 49 46 66 14 267 52 50 50 47 69 N14 276 53 31 51 51 48 70 816 279 GND 52 52 49 71 P14 DONE 32 53 53 50 72 R15 5 VCC 33 54 54 51 73 P13 PROG 34 55 55 52 74 R14 54 D7 35 56 56 53 75 T16 288 55 GCK3 I O 36 57 57 54 76 T15 291 56 06 37 58 58 55 79 T14 300 57 59 56 80 T13 303 GND 81 P11 58 05 38 59 60 57 84 T10 306 59 y o 50 5 60 61 58 85 P10 312
9. 91 100 110 44 56 62 68 80 18 92 540 101 45 57 63 69 81 Ki7 93 543 102 V0 58 64 70 82 R9 94 546 103 10 59 65 71 83 118 95 552 104 72 84 17 9 96 555 105 1O 73 85 Lie 19 97 558 106 10 115 99 564 107 M15 P10 100 567 101 108 1 0 46 60 66 74 86 102 570 109 10 47 6 67 75 87 7 103 576 110 62 68 76 88 N18 104 579 11 63 69 77 89 8 105 588 GND 64 70 78 90 M16 GND 106 112 110 N15 107 591 113 110 215 NM 108 600 114 110 91 N17 R12 109 603 115 O 92 110 110 606 116 110 71 79 98 2 11 612 117 10 72 80 94 P17 112 615 118 48 65 73 81 95 6 113 618 119 49 66 74 82 96 7117 2 114 624 120 110 67 75 83 97 115 627 121 10 68 76 84 Pie Kio 116 630 122 110 50 69 77 85 9 117 636 128 10 51 70 78 86 100 116 118 639 GND 52 71 79 87 101 R16 GND 19 DONE 53 72 80 88 103 U17 P14 120 73 81 89 106 R15 121 PROG 55 74 82 90 108 12 122 124 O D7 56 78 83 91 109 T15 P15 123 648 125
10. 1786 Figure 27 Readback Schematic Example Readback Options Readback options are Read Capture Read Abort and Clock Select They are set with the bitstream generation software Read Capture When the Read Capture option is selected the readback data stream includes sampled values of CLB and IOB sig nals The rising edge of RDBK TRIG latches the inverted values of the CLB outputs and the IOB output and input sig nals Note that while the bits describing configuration interconnect and function generators are not inverted the CLB and IOB output signals are inverted When the Read Capture option is not selected the values of the capture bits reflect the configuration data originally written to those memory locations The readback signals are located in the lower left corner of the device Read Abort When the Read Abort option is selected a High to Low transition on RDBK TRIG terminates the readback opera tion and prepares the logic to accept another trigger After an aborted readback additional clocks up to one readback clock per configuration frame may be required to re initialize the control logic The status of readback is indi cated by the output control net RDBK RIP RDBK RIP is High whenever a readback is in progress Clock Select CCLK is the default clock However the user can insert another clock on RDBK CLK Readback control and data are clocked on rising edges of RDBK CL
11. 1 16 7 20 225 33 yo 1 13 15 17 8 21 234 34 VO 11 8 14 16 18 22 237 35 y o 19 12 9 15 17 19 B9 23 246 36 20 13 10 16 18 20 9 24 249 GND 21 14 11 17 19 21 09 25 22 15 12 18 20 22 10 26 37 yo 23 16 13 19 21 23 C10 27 255 38 y o 24 17 14 20 22 24 B10 28 258 39 VO 18 15 21 23 25 9 29 261 40 y o 5 22 24 26 10 30 267 41 y o 27 A11 31 270 November 5 1998 Version 5 2 7 139 XC5200 Series Field Programmable Gate Arrays 5 XILINX Pin Description PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 42 y o 28 C11 32 273 43 25 19 16 23 25 29 B11 33 279 44 y o 26 20 17 24 26 30 A12 34 282 45 yo 25 27 31 B12 35 285 46 y o 26 28 32 A13 36 291 GND 27 29 33 C12 37 47 1 gt 1 30 34 15 40 294 48 5 2 5 5 31 35 C13 41 297 49 y o 27 21 18 28 32 36 B14 42 303 50 yo 22 19 29 33 37 A16 43 306 51 yo 30 34 38 B15 44 309 52 yo 31 35 39 C14 45 315 53 yo 28 23 20 32 36 40 A17 46 318 54 y o 29 24 21 33 37 41 B16 47 321 55 M1 I O 30 25 22 34 38 42 15 48 330 31 26 23 35 39 43 015 49 56 32 27 24 36 40 44 18 50 333
12. DO D7 During Master Parallel Peripheral and Express configuration these eight input pins ceive configuration data After configuration they are user programmable I O pins DIN During Slave Serial or Master Serial configuration DIN is the serial configuration data input receiving data on the rising edge of CCLK During Parallel configuration DIN is the DO input After configuration DIN is a user programmable pin DOUT During configuration any mode but Express mode DOUT is the serial configuration data output that can drive the DIN of daisy chained slave FPGAs DOUT data changes on the falling edge of CCLK In Express mode DOUT is the status output that can drive the CS1 of daisy chained FPGAs to enable and disable downstream devices After configuration DOUT is user programmable pin November 5 1998 Version 5 2 7 103 XC5200 Series Field Programmable Gate Arrays XILINX Table 9 Pin Descriptions Continued 1 0 During After Config Config Unrestricted User Programmable I O Pins Pin Description These pins can be configured to be input and or output after configuration is completed Before configuration is completed these pins have an internal high value pull up resis p tor 20 KQ 100 kQ that defines the logic level as High Configuration M1 a
13. 2 I O 43 57 63 19 R2 AE24 531 95 HDC 44 58 64 C19 P3 AD23 540 96 45 59 65 F16 L5 AC22 543 97 46 60 66 17 4 24 546 98 47 61 67 018 AD22 552 99 LDC 48 62 68 C20 P4 AE23 555 November 5 1998 Version 5 2 7 149 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 100 17 22 558 101 G16 AF23 564 102 49 63 69 019 K7 AD20 567 103 50 64 70 18 5 AE21 570 104 65 71 020 R4 AF21 576 105 66 72 G17 N5 AC19 579 106 73 18 5 AD19 582 107 74 H16 16 20 588 108 19 20 591 109 19 18 594 GND 51 67 75 E20 GND GND 110 52 68 76 H17 R5 AD18 600 111 53 69 77 G18 M6 AE19 603 112 54 70 78 19 N6 AC17 606 113 55 71 79 H18 P6 AD17 612 80 20 VCC VCC 114 72 81 16 R6 AE17 615 115 73 82 G20 M7 AE16 618 116 20 16 624 117 18 15 627 118 84 J19 N7 AD15 630 119 85 K16 P7 AE15 636 120 56 74 86 420 7 15 639 121 57 75 87 K17 L7 AD14 642 122 58 7
14. Plast PLCC Plast PQFP Ceram PGA Ceram PGA Ceram PGA Ceram PGA PG156 191 PG223 PG299 84 f 5202 XC5204 of 2 of 100 5206 i olojo Q Q 5210 XC5215 ojojo 7 8 98 Commercial Tj 0 to 85 Industrial 40 C to 100 VQ64 package supports Master Serial Slave Serial and Express configuration modes only User I O Per Package Package Type Device TQ144 PQ160 TQ176 PG191 HQ208 PQ208 BG225 HQ240 PQ240 5202 5204 5206 5210 5215 7 8 98 Ordering Information Example XC5210 6PQ208C Device Type lt Temperature Range Speed Grade Number of Pins Package Type 7 154 November 5 1998 Version 5 2 XILINX 5200 Series Field Programmable Gate Arrays Revisions Version Description 12 97 Rev 5 0 added 3 4 specification 7 98 Rev 5 1 added Spartan family to comparison removed HQ304 11 98 Rev 5 2 All specifications made final November 5 1998 Version 5 2 7 155 WWW ALLDATASHEET COM Copyright Each Manufacturing Company All Datasheets cannot be mo
15. XILINX 5200 Series Field Programmable Gate Arrays When the UCLK_SYNC option is enabled the user can externally hold the open drain DONE output Low and thus stall all further progress in the start up sequence until DONE is released and has gone High This option can be used to force synchronization of several FPGAs to a com mon user clock or to guarantee that all devices are suc cessfully configured before any 1 active If either of these two options is selected no user clock is specified in the design or attached to the device the chip could reach a point where the configuration of the device is complete and the Done pin is asserted but the outputs do not become active The solution is either to recreate the bitstream specifying the start up clock as CCLK or to sup ply the appropriate user clock Start up Sequence The Start up sequence begins when the configuration memory is full and the total number of configuration clocks received since INIT went High equals the loaded value of the length count The next rising clock edge sets a flip flop QO shown Figure 26 is the leading bit of a 5 bit shift register The outputs of this register can be programmed to control three events The release of the open drain DONE output The change of configuration related pins to the user function activating all IOBs The termination of the global Set Reset initialization of and
16. XILINX can also be independently disabled for any flip flop CLR is active High It is not invertible within the CLB STARTUP PAD 02 818 a3 0104 DONEIN X9009 Figure 8 Schematic Symbols for Global Reset Global Reset A separate Global Reset line clears each storage element during power up reconfiguration or when a dedicated Reset net is driven active This global net GR does not compete with other routing resources it uses a dedicated distribution network GR can be driven from any user programmable pin as a global reset input To use this global net place an input pad and input buffer in the schematic or HDL code driving the GR pin of the STARTUP symbol See Figure 9 A specific pin location can be assigned to this input using a LOC attribute or property just as with any other user program mable pad An inverter can optionally be inserted after the input buffer to invert the sense of the Global Reset signal Alternatively GR can be driven from any internal node Using FPGA Flip Flops and Latches The abundance of flip flops in the XC5200 Series invites pipelined designs This is a powerful way of increasing per formance by breaking the function into smaller subfunc tions and executing them in parallel passing on the results through pipeline flip flops This method should be seriously considered wherever throughput is more important than lat
17. Peripheral Modes The two Peripheral modes accept byte wide data from a bus A RDY BUSY status is available as a handshake sig nal In Asynchronous Peripheral mode the internal oscilla tor generates a CCLK burst signal that serializes the byte wide data CCLK can also drive slave devices In the synchronous mode an externally supplied clock input to CCLK serializes the data Slave Serial Mode In Slave Serial mode the FPGA receives serial configura tion data on the rising edge of CCLK and after loading its configuration passes additional data out resynchronized on the next falling edge of CCLK Multiple slave devices with identical configurations can be wired with parallel DIN inputs In this way multiple devices can be configured simultaneously Serial Daisy Chain Multiple devices with different configurations can be con nected together in a daisy chain and a single combined bitstream used to configure the chain of slave devices To configure a daisy chain of devices wire the CCLK pins of all devices in parallel as shown in Figure 28 on page 114 Connect the DOUT of each device to the DIN of the next The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source The header data including the length count is passed through and is captured by each FPGA when it recognizes the 0010 preamble Following the length count data each FPGA outputs a High on
18. V VoL Low level output voltage 10 8 0 V loco Quiescent FPGA supply current Note 1 mA lu Leakage current Input capacitance sample tested pF Pad pull up when selected Vn sample tested mA Note 1 With no output current loads all package pins at Vcc GND either TTL or CMOS inputs and the FPGA configured with a tie option XC5200 Absolute Maximum Ratings Symbol Description Units Voc Supply voltage relative to GND 0 5 to 7 0 V Vin Input voltage with respect to GND 0 5 to Voc 10 5 V Vis Voltage applied to 3 state output 0 5 to 10 5 V Tera Storage temperature ambient 65 to 150 TsoL Maximum soldering temperature 10 s 1 16 in 1 5 mm 260 C Junction temperature plastic packages 125 Junction temperature ceramic packages 150 Note Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability 1 Notwithstanding the definition of the above terms all specifications are subject to change without notice November 5 1998 Version 5 2 7 127 XC5200 Series Field Programmable Gate Ar
19. cascade in CY Initialization of carry chain One Logic Cell X5708 Figure 7 XC5200 CY MUX Used for Decoder Cascade Logic Cascade Function Each CY MUX can be connected to the CY MUX in the adjacent LC to provide cascadable decode logic Figure 7 illustrates how the 4 input function generators can be con figured to take advantage of these four cascaded CY MUXes Note that AND and OR cascading are specific cases of a general decode In AND cascading all bits are decoded equal to logic one while in OR cascading all bits are decoded equal to logic zero The flexibility of the LUT achieves this result The XC5200 library contains gate macros designed to take advantage of this function CLB Flip Flops and Latches The CLB can pass the combinatorial output s to the inter connect network but can also store the combinatorial results or other incoming data in flip flops and connect their outputs to the interconnect network as well The CLB storage elements can also be configured as latches Table 3 CLB Storage Element Functionality active rising edge is shown Mode CK CE CLR D Q Power Up or GR 0 1 0 Flip Flop _ 1 0 0 0 1 1 0 Latch 0 m D D Both X 0 0 X Q Legend X _ Don t care Rising edge 0 Input is Low unconnected default value 1 Input is High or unconnected default value Data Inputs and Outpu
20. storage elements The DONE pin can also be wire ANDed with DONE pins of other FPGAs or with other external signals and can then be used as input to bit Q3 of the start up register This is called Start up Timing Synchronous to Done In and is selected by either CCLK SYNC or UCLK SYNC When DONE is not used as an input the operation is called Start up Timing Not Synchronous to DONE In and is selected by either NOSYNC UCLK NOSYNC As a configuration option the start up control register beyond QO can be clocked either by subsequent CCLK pulses or from an on chip user net called STARTUP CLK These signals can be accessed by placing the STARTUP library symbol Start up from CCLK If CCLK is used to drive the start up QO through pro vide the timing Heavy lines in Figure 25 show the default timing which is compatible with XC2000 and XC3000 devices using early DONE and late Reset The thin lines indicate all other possible timing options Start up from a User Clock STARTUP CLK When instead of CCLK a user supplied start up clock is selected Q1 is used to bridge the unknown phase relation ship between CCLK and the user clock This arbitration causes an unavoidable one cycle uncertainty in the timing of the rest of the start up sequence DONE Goes High to Signal End of Configuration all configuration modes except Express mode XC5200 Series devices read the expected length count from the b
21. Pin Description PC84 PQ100 0100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 2 92 89 128 142 155 44 183 1 A8 3 93 90 129 143 156 J3 184 87 2 9 4 94 91 130 144 157 J2 185 90 3 95 92 131 145 158 J1 186 93 4 96 93 132 146 159 H1 187 99 5 yo 1 160 188 102 6 161 189 105 7 A10 5 97 94 133 147 162 G1 190 111 8 A11 6 98 95 134 148 163 G2 191 114 9 y o 5 135 149 164 1 192 117 10 136 150 165 1 193 123 GND 137 151 166 G3 194 11 yo E 152 168 C1 197 126 12 y o 5 5 1 153 169 2 198 129 13 12 7 99 96 138 154 170 199 138 14 A13 8 100 97 139 155 171 02 200 141 15 y o 140 156 172 B1 201 150 16 y o 5 141 157 173 202 153 17 14 9 1 98 142 158 174 2 203 162 18 A15 10 2 99 143 159 175 204 165 11 3 100 144 160 176 03 205 GND 12 4 1 1 1 1 D4 2 19 1 A16 I O 13 5 2 2 2 2 4 174 20 17 14 6 3 3 3 3 C4 5 177 21 4 4 4 B3 6 183 22 5 5 5 5 7 186 23 TDI 15 7 4 6 6 6 2 8 189 24 I O 16 8 5 7 7 7 B4 9 195 25 8 8 C6 10 198 26 yo z 9 9 11 201 GND gt 8 10 10 C7 14 5 27 yo 5 9 11 11 4 15 207 28 yo E 1 10 12 12 5 16 210 29 5 17 9 6 11 13 13 7 17 213 30 y o 18 10 7 12 14 14 A6 18 219 31 y o 15 19 222 32 yo
22. Readback with the XChecker Cable The XChecker Universal Download Readback Cable and Logic Probe uses the readback feature for bitstream verifi cation It can also display selected internal signals on the PC or workstation screen functioning as a low cost in cir cuit emulator November 5 1998 Version 5 2 7 113 XC5200 Series Field Programmable Gate Arrays XILINX Configuration Timing The seven configuration modes are discussed in detail in this section Timing specifications are included Slave Serial Mode In Slave Serial mode an external signal drives the CCLK input of the FPGA The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge The lead FPGA then presents the preamble data and all data that overflows the lead device on its DOUT pin There is an internal delay of 0 5 CCLK periods which means that DOUT changes on the falling CCLK edge and the next FPGA in the daisy chain accepts data on the sub sequent rising CCLK edge Figure 28 shows full master slave system An XC5200 Series device in Slave Serial mode should be con nected as shown in the third device from the left Slave Serial mode is selected by a lt 111 gt the mode pins M2 M1 Slave Serial is the default mode if the mode pins are left unconnected as they have weak pull up resis tors during configuration
23. 100 VQ100 TQ144 PG156 VCC 2 92 89 128 H3 1 A8 57 3 93 90 129 H1 51 2 A9 58 4 94 91 130 G1 54 3 95 92 131 G2 57 4 gt 96 93 132 G3 63 5 A10 5 97 94 133 F1 66 6 A11 59 6 98 95 134 F2 69 GND 137 12 60 7 99 96 138 78 8 13 61 8 100 97 139 C1 81 9 A14 62 9 1 98 142 B1 90 10 A15 63 10 2 99 143 B2 93 VCC 64 11 3 100 144 C3 GND 12 4 1 1 C4 11 GCK1 A16 1 13 5 2 2 B3 102 12 A17 2 14 6 3 3 Al 105 13 TDI 3 15 7 4 6 B4 111 14 4 16 8 5 7 114 GND 3 8 C6 x 15 TMS 5 17 9 6 11 5 117 16 6 18 10 7 12 7 123 17 13 7 126 18 11 8 14 129 19 19 12 9 15 7 135 20 7 20 13 10 16 8 138 GND 8 21 14 11 17 C8 VCC 9 22 15 12 18 B8 21 23 16 13 19 9 141 22 10 24 17 14 20 9 147 23 18 15 21 9 150 24 22 B10 153 25 VO 25 19 16 23 C10 159 26 11 26 20 17 24 10 162 GND z 27 C11 27 12 27 21 18 28 812 165 28 22 19 29 13 171 29 13 28 23 20 32 B13 174 30 14 29 24 21 33 14 177 31 M1 I O 15 30 25 22 34 A15 186 GND 31 26 23 35 C13 s 32 MO I O 16 32 27 24 36 A16 189 VCC 5 33 28 25 37 14 33 2 17 34 29 26 38 15 192 34 GCk2 I O 18 35 30 27 39 B16 195
24. 104 116 128 150 18 176 846 170 00 DIN 71 105 117 129 151 US 20 177 855 171 VO DOUT 72 106 118 130 182 T4 B15 178 858 CCLK 73 107 119 131 153 Vi ci3 179 74 108 120 132 154 180 172 VO 75 109 121 133 159 U2 181 gt GND 76 110 122 134 160 182 173 A0 WS 77 13 128 135 161 13 183 9 174 10 78 112 124 136 162 Ui 184 15 175 10 118 125 137 163 P3 185 18 176 10 114 126 188 164 R2 Ci2 186 21 177 V O CS1 A2 79 115 127 139 165 T2 187 27 178 80 116 128 10 166 812 188 30 179 P4 F9 189 33 7 146 November 5 1998 Version 5 2 5 XC5200 Series Field Programmable Gate Arrays Pin Description Ta144 160 Ta176 208 PG223 BG225 Boundary Sean 180 10 5 N4 D11 190 39 181 10 117 129 141 167 P2 A12 191 42 182 10 130 142 168 T1 C11 192 45 183 169 R1 B11 193 51 184 10 170 N2 E10 194 54 1 GND 5 GND 118 131 143 171 M3 196 185 110 119 132 144 172 1
25. 11 197 57 186 120 133 145 173 N1 D10 198 66 187 10 M4 C10 199 69 188 1 0 1 14 B10 200 75 201 189 1 0 A4 81 121 134 146 174 2 10 202 78 190 I O A5 82 122 135 147 175 M1 D9 203 81 191 10 148 176 3 C9 205 87 192 1 136 149 177 12 B9 206 90 193 10 123 137 150 178 L1 A9 207 93 194 110 124 138 151 179 K1 E9 208 99 195 1 O A6 83 125 139 152 180 K2 C8 209 102 196 VO A7 84 126 140 153 181 K3 B8 210 105 GND 1 127 141 154 182 GND 211 Additional No Connect N C Connections for PQ208 PQ240 Packages PQ208 240 1 53 105 157 208 22 143 219 3 54 107 158 37 158 51 102 155 206 83 195 52 104 156 207 98 204 Notes Pins labeled are internally bonded to VCC plane within the 82225 package The external pins B2 08 H15 R8 B14 R1 H1 and R15 Pins labeled GND are internally bonded to a ground plane within the BG225 package The external pins are A1 D12 G7 G9 H6 H8 H10 J8 K8 A8 F8 G8 H2 H7 H9 J7 J9 M8 Boundary Scan Bit 0 TDO T Boundary Scan Bit 1 TDO O Boundary Scan Bit 1056 BSCAN UPD Pin Locations for XC5215 Devices The following table may contain pinout information for unsupported device package combinations Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information Pin Description PQ160 HQ208 HQ240
26. 2 XILINX 5200 Field Programmable Gate Arrays November 5 1998 Version 5 2 Product Specification Features Low cost register latch rich SRAM based reprogrammable architecture 0 5um three layer metal CMOS process technology 256 to 1936 logic cells 3 000 to 23 000 gates Price competitive with Gate Arrays System Level Features System performance beyond 50 MHz 6 levels of interconnect hierarchy VersaRing I O Interface for pin locking Dedicated carry logic for high speed arithmetic functions Cascade chain for wide input functions Built in IEEE 1149 1 JTAG boundary scan test circuitry on all I O pins Internal 3 state bussing capability Four dedicated low skew clock or signal distribution nets Versatile I O and Packaging Innovative VersaRing I O interface provides a high logic cell to I O ratio with up to 244 signals Programmable output slew rate control maximizes performance and reduces noise Zero Flip Flop hold time for input registers simplifies system timing Independent Output Enables for external bussing Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series Over 150 device package combinations including advanced BGA TQ and VQ packaging available Fully Supported by Xilinx Development System Automatic place and route software Wide selection of PC and Workstation platforms Over 100 3
27. IIII IT IT FEE a1anod HH H H H H 64445 1V8015 HH III Coos 11 E I FEF HH 11 1 HH 5 H H HH 193410 A MMM 319 6 193410 7 97 Figure 17 Detail of Programmable Interconnect Associated with XC5200 Series November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays XILINX VersaRing Input Output Interface The VersaRing shown in Figure 18 is positioned between the core logic and the pad ring it has all the routing resources of a VersaBlock without the CLB logic The Ver saRing decouples the core logic from the I O pads Each VersaRing Cell provides up to four pad cell connections on one side and connects directly to the CLB ports on the other side VersaRing 2 5705 Figure 18 VersaRing I O Interface Boundary Scan The bed of nails has been the traditional method of testing electronic assemblies This approach has become less appropriate due to closer pin spacing and more sophisti cated assembly methods like surface mount technology and multi layer boards The IEEE boundary scan standard 1149 1 was developed to facilitate board level testing of electronic assemblies Design and test engineers can imbe
28. 145 10 87 97 107 127 vio JM 147 738 146 1O D4 61 88 98 108 128 00 148 744 147 V0 62 89 99 109 129 T10 Hi4 149 747 63 90 100 110 180 VCC 150 GND 64 91 100 113 131 R9 151 148 10 03 65 92 102 112 132 T9 Hi2 152 756 149 10 5 66 93 103 113 133 HM 153 759 150 VO 94 104 114 134 V9 614 154 768 151 110 95 105 115 135 V8 615 155 771 152 10 116 136 08 613 156 780 153 10 117 137 18 612 157 783 154 0 02 67 96 106 18 138 V Gti 159 786 155 1 68 97 107 119 139 07 15 160 792 161 156 108 120 140 V6 162 795 157 10 99 109 121 141 U6 163 798 158 10 R8 010 164 804 159 10 R7 E15 165 807 GND 100 110 122 142 17 GND 166 160 R6 E14 167 810 161 R5 12 168 816 162 143 V5 E13 169 819 163 10 144 015 170 822 164 V0 123 145 US Ff 17 828 165 10 112 124 146 T6 044 172 831 166 0 81 69 101 118 125 147 V3 12 178 834 167 RCLK BUSY RDY 70 102 114 126 148 V2 045 174 840 168 10 108 115 127 149 04 013 175 843 169 10
29. 57 76 84 92 110 016 124 651 126 10 77 85 93 13 111 125 660 127 110 78 86 94 112 115 126 663 128 110 R14 N15 127 666 129 5 R13 128 672 130 06 58 79 87 95 113 vi7 129 675 184 80 88 96 114 vie 112 130 678 132 1 0 89 97 115 118 Mi5 181 684 183 1 0 90 98 116 114 113 132 687 184 110 117 5 133 690 185 10 118 Vi4 KM 134 696 GND 81 91 99 119 112 GND 135 136 10 Ri2 115 136 699 November 5 1998 Version 5 2 7 145 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description Ta144 160 176 208 PG223 BG225 Boundary Sean 187 V0 R KI2 137 708 138 10 82 92 100 120 138 711 139 10 83 93 101 121 vis Ki4 139 714 vcc 140 140 10 D5 59 84 94 102 122 12 K15 141 720 141 50 60 85 95 103 128 Vi2 2 142 723 142 10 104 124 TM Ji8 144 726 143 110 105 125 Uti 145 732 144 10 86 96 106 126 146 735
30. Additional No Connect N C Connections on TQ144 Package TQ144 135 9 41 67 98 117 136 10 42 68 99 119 140 25 46 77 103 120 141 26 47 78 104 4 30 62 82 113 5 31 63 83 114 Notes Boundary Scan Bit 0 TDO T Boundary Scan Bit 1 TDO O Boundary Scan 1056 BSCAN UPD Pin Locations for XC5204 Devices The following table may contain pinout information for unsupported device package combinations Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information Pin Description PC84 PQ100 100 TQ144 PG156 PQ160 Boundary Scan Order 2 92 89 128 142 1 A8 3 93 90 129 H1 143 78 2 A9 4 94 91 130 G1 144 81 3 1 95 92 131 G2 145 87 4 96 93 132 146 90 5 10 5 97 94 133 1 147 93 6 11 6 98 95 134 22 148 99 7 yo E 135 E1 149 102 8 136 2 150 105 GND 5 5 137 F3 151 9 1 5 D1 152 111 10 y o 5 5 02 153 114 11 12 7 99 96 138 154 117 12 13 8 100 97 139 C1 155 123 13 yo 140 C2 156 126 November 5 1998 Version 5 2 7 135 XC5200 Series Field Programmable Gate Arrays XILINX
31. CCLK Low time 60 ns CCLK Frequency Foc 8 MHz Notes 1 Peripheral Synchronous mode can be considered Slave Parallel mode An external CCLK provides timing clocking the first data byte on the second rising edge of CCLK after INIT goes high Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK 2 The RDY BUSY line goes High for one CCLK period after data has been clocked in although synchronous operation does not require such a response 3 The pin name RDY BUSY is a misnomer In synchronous peripheral mode this is really an ACKNOWLEDGE signal 4 Note that data starts to shift out serially on the DOUT pin 0 5 CCLK periods after it was loaded in parallel Therefore additional CCLK pulses are clearly required after the last byte has been loaded Figure 34 Synchronous Peripheral Mode Programming Switching Characteristics November 5 1998 Version 5 2 7 119 XC5200 Series Field Programmable Gate Arrays XILINX Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CSO being Low and RS and CS1 being High to accept byte wide data from a micro processor bus In the lead FPGA this data is loaded into a double buffered UART like parallel to serial converter and is serially shifted into the internal logic The lead FPGA presents the preamble data and all data that overflows t
32. PG299 BG225 BG352 Boundary Scan Order VCC 142 183 212 K1 VCC VCC 1 A8 143 184 213 K2 E8 D14 138 2 A9 144 185 214 K3 B7 C14 141 3 y o 145 186 215 K5 A7 A15 147 4 146 187 216 K4 C7 B15 150 5 188 217 J1 D7 C15 153 6 189 218 7 015 159 7 10 147 190 220 H1 A6 A16 162 November 5 1998 Version 5 2 7 147 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 8 A11 148 191 221 J3 B6 B16 165 9 1 5 5 17 171 10 E G1 18 174 VCC 222 E1 VCC VCC 11 yo 223 H3 C6 C18 177 12 224 G2 F7 D17 183 13 149 192 225 5 20 186 14 150 193 226 5 19 189 GND 151 194 227 1 GND 15 5 19 195 16 G3 D18 198 17 195 228 D1 D6 A21 201 18 E 196 229 G4 C5 B20 207 19 y o 152 197 230 E2 A4 C20 210 20 153 198 231 21 213 21 12 154 199 232 G5 B4 B22 219 22 A13 155 200 233 C1 D5 C21 222 23 1 1 20 225 24 yo 23 234 25 234 D2 A3 D21 237 26 235 2 4 22 243 27 156 201 236 5 B3 B24 246 28 157
33. include the boundary scan locations for each pin Table 8 Boundary Scan Bit Sequence Bit Position I O Pad Location Bit 0 TDO Top edge pads right to left Bit 1 i Left edge pads top to bottom Bottom edge I O pads left to right et Right edge I O pads bottom to top Bit N TDI BSCANT UPD BSDL Boundary Scan Description Language files for XC5200 Series devices are available on the Xilinx web site in the File Download area Including Boundary Scan If boundary scan is only to be used during configuration no special elements need be included in the schematic or HDL code In this case the special boundary scan pins TDI TMS TCK and TDO can be used for user functions after configuration To indicate that boundary scan remain enabled after config uration include the BSCAN library symbol and connect pad symbols to the TDI TMS TCK and TDO pins as shown in Figure 20 Instruction 12 Test Data 1 10 Selected TBO Source 0 0 0 EXTEST DR DR 0 0 1 SAMPLE PR DR Pin Logic ELOAD 0 1 0 USER 1 BSCAN User Logic TDO1 0 1 1 USER 2 BSCAN User Logic TDO2 1 0 0 READBACK Readback Pin Logic Data 1 0 1 CONFIGURE DOUT Disabled 1 1 0 Reserved 1 1 1 BYPASS Bypass Register 7 100 November 5 1998 Version 5 2 5 XILINX XC5200 Series Field Programmable Gate Arrays Optional
34. while oth ers must boot from the top The FPGA is flexible and can load its configuration bitstream from either end of the mem ory Master Parallel Up mode is selected by a lt 100 gt on the mode pins M2 M1 MO The EPROM addresses start at 00000 and increment Master Parallel Down mode is selected by a lt 110 gt on the mode pins The EPROM addresses start at 3FFFF and decrement November 5 1998 Version 5 2 7 115 XC5200 Series Field Programmable Gate Arrays can be shorted to Ground if not used as I O 4 7K VCC DOUT XC5200 Master Parallel PROGRAM DATAB US lt DIN OF OPTIONAL DAISY CHAINED FPGAS TO CCLK OF OPTIONAL DAISY CHAINED FPGAS EPROM 8K x 8 OR LARGER USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS PROGRAM XILINX CCLK XC5200 XC4000E EX Spartan SLAVE PROGRAM Figure 31 Master Parallel Mode Circuit Diagram 7 116 November 5 1998 Version 5 2 X9004_01 XC5200 Series Field Programmable Gate Arrays 0 17 output Address for Byte n 1 Address for Byte n RCLK output CCLK output DOUT output Byte 1 X6078 Description Symbol Min Max Units Delay to Address valid 1 Trac 0 200 ns CCLK Data
35. 5200 Series Field Programmable Gate Arrays to Vcc The configurable pull down resistor is an n channel transistor that pulls to Ground The value of these resistors is 20 100 kQ This high value makes them unsuitable as wired AND pull up resis tors The pull up resistors for most user programmable IOBs are active during the configuration process See Table 13 on page 124 for a list of pins with pull ups active before and during configuration After configuration voltage levels of unused pads bonded or unbonded must be valid logic levels to reduce noise sensitivity and avoid excess current Therefore by default unused pads are configured with the internal pull up resis tor active Alternatively they can be individually configured with the pull down resistor or as a driven output or to be driven by an external source To activate the internal pull up attach the PULLUP library component to the net attached to the pad To activate the internal pull down attach the PULLDOWN library component to the net attached to the pad JTAG Support Embedded logic attached to the IOBs contains test struc tures compatible with IEEE Standard 1149 1 for boundary scan testing simplifying board level testing More informa tion is provided in Boundary Scan on page 98 Oscillator XC5200 devices include an internal oscillator This oscilla tor is used to clock the power on time out clear configura tion memory and source
36. 6 013 1035 211 O 116 150 176 U5 C14 C2 1038 212 DO DIN 117 151 177 V4 F10 D3 1044 213 DOUT 118 152 178 15 4 1047 119 153 179 C13 C3 VCC 120 154 180 VCC VCC 214 121 159 181 U4 A15 D4 0 GND 122 160 182 2 GND 215 A0 WS 123 161 183 w2 A14 B3 9 216 GCK4 I O 124 162 184 v2 B13 C4 15 217 125 163 185 5 11 05 18 218 1 0 126 164 186 T4 C12 A3 21 219 A2 CS1 127 165 187 U3 A13 D6 27 220 128 166 188 812 C6 30 221 R4 85 33 222 4 39 223 189 U2 9 C7 42 224 5 190 T3 D11 B6 45 225 1 0 129 167 191 U1 A12 A6 51 226 130 168 192 4 C11 D8 54 227 169 193 B11 B7 57 228 170 194 5 10 7 63 229 195 2 09 66 230 R2 9 69 GND 131 171 196 T1 GND GND 231 132 172 197 4 11 B8 75 232 VO 133 173 198 P3 D10 D10 78 233 199 P2 C10 C10 81 234 VO 200 N3 B10 B9 87 VCC 201 R1 VCC VCC 7 152 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 235 5 11 90 236 1 11 93 237 A4 134 174 202 1 10 012 99 238 A5 135 175 203 09 C12 102 239 1 176 205 9 12 10
37. 60 y o 62 59 86 R10 315 61 yo 5 63 60 87 79 318 62 D4 39 61 64 61 88 R9 324 63 62 65 62 89 9 327 VCC 40 63 66 63 90 R8 GND 41 64 67 64 91 8 64 D3 42 65 68 65 92 T8 336 65 RS 43 66 69 66 93 T7 339 66 70 67 94 T6 342 67 5 gt 95 R7 348 68 D2 44 67 71 68 96 P7 351 69 y o 68 72 69 97 5 360 GND 100 P6 70 D1 45 69 73 70 101 T3 363 71 70 74 71 102 5 366 RCLK BUSY RDY 72 DO DIN 46 71 75 72 105 P4 372 73 DOUT 47 72 76 73 106 T2 375 7 134 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays Pin Description VQ64 PC84 PQ100 VQ100 TQ144 PG156 CCLK 48 73 77 74 107 R2 VCC 74 78 75 108 P3 74 TDO 49 75 79 76 109 T1 0 GND 76 80 77 110 N3 75 0 WS 50 77 81 78 111 R1 9 76 I O 51 78 82 79 112 P2 15 77 A2 CS1 52 79 83 80 115 P1 18 78 80 84 81 116 N1 21 GND 118 L3 79 A4 81 85 82 121 K3 27 80 A5 53 82 86 83 122 K2 30 81 87 84 123 K1 33 82 gt 88 85 124 J1 39 83 6 54 83 89 86 125 42 42 84 A7 55 84 90 87 126 93 45 GND 56 1 91 88 127 H2 VQ64 package supports Master Serial Slave Serial and Express configuration modes only
38. B2 C3 239 213 11 144 160 176 205 03 240 GND 12 1 1 1 2 04 1 25 1 A16 1 2 2 2 4 C3 D4 2 222 26 VO A17 4 3 3 3 5 4 B1 3 225 27 10 4 4 4 6 B3 C2 4 231 28 5 5 5 7 C5 5 234 29 VO TD 15 6 6 6 8 2 D3 6 237 30 VO TCK 16 7 7 7 9 B4 7 243 31 10 8 8 10 02 8 246 32 V0 5 9 9 11 9 249 33 5 12 B5 E4 10 255 34 10 13 01 11 258 35 10 3 05 12 261 36 10 06 2 13 267 GND 8 10 10 14 C7 GND 14 37 10 9 11 11 15 4 F5 15 270 38 0 10 12 12 16 E1 16 273 39 TMS 7 13 13 17 B7 F4 17 279 40 VO 18 12 14 14 18 18 282 19 41 O 2 07 F2 20 285 42 O D8 F1 21 291 43 10 15 19 23 294 44 O 16 20 7 G3 24 297 45 O 13 15 17 21 B8 G2 25 306 46 O 14 16 18 22 G1 26 309 47 19 15 17 19 23 B9 G5 27 318 48 10 20 16 18 20 24 C9 H3 28 321 GND 21 17 19 21 25 D9 GND 29 22 18 20 22 26 010 30 49 VO 28 19 21 23 27 31 327 November 5 1998 Version 5 2 7 143 XC5200 Series Field Programmable Gate Arrays XILINX
39. CCLK in Master configuration modes The oscillator runs at a nominal 12 MHz frequency that varies with process Vcc and temperature The output CCLK frequency is selectable as 1 MHz default 6 MHz or 12 MHz The XC5200 oscillator divides the internal 12 MHz clock or a user clock The user then has the choice of dividing by 4 16 64 or 256 for the OSC1 output and dividing by 2 8 32 128 1024 4096 16384 or 65536 for the out put The division is specified a DIVIDEn_BY x attribute on the symbol where n 1 for OSC1 or n 2 for OSC2 These frequencies can vary by as much as 50 or 50 The OSC5 macro is used where an internal oscillator is required The CK_DIV macro is applicable when a user clock input is specified see Figure 13 0501 OSCS OSC2 OSC1 CK DIV OSC2 gt 5200 14 Figure 13 5200 Oscillator Macros VersaBlock Routing The General Routing Matrix GRM connects to the Versa Block 24 bidirectional ports 23 Excluding direct connections global nets and 3 statable Longlines VersaBlock inputs and outputs connect to the GRM these 24 ports Four 3 statable unidirectional signals 0 drive out of the VersaBlock directly onto the horizontal and vertical Longlines Two horizontal global nets and two vertical global nets connect directly to every CLB clock pin they can connect to other CLB inputs via the GRM Each CLB also has four unidirectional
40. HDC 36 31 28 40 D14 44 276 50 y o 1 1 1 41 15 45 279 51 2 42 015 46 282 52 1 32 29 43 14 47 288 53 LDC 37 33 30 44 C16 48 291 54 1 1 15 49 294 55 016 50 300 GND 5 45 14 51 56 46 15 52 303 7 136 November 5 1998 Version 5 2 5 XILINX XC5200 Series Field Programmable Gate Arrays Pin Description PC84 PQ100 100 TQ144 PG156 PQ160 Boundary Scan Order 57 47 16 53 306 58 38 34 31 48 F16 54 312 59 39 35 32 49 G14 55 315 60 36 33 50 G15 56 318 61 VO 37 34 51 G16 57 324 62 VO 40 38 35 52 H16 58 327 63 ERR INIT 41 39 36 53 H15 59 330 VCC 42 40 37 54 H14 60 43 41 38 55 14 61 64 44 42 39 56 J15 62 336 65 VO 45 43 40 57 J16 63 339 66 VO 44 41 58 K16 64 348 67 45 42 59 15 65 351 68 VO 46 46 43 60 K14 66 354 69 VO 47 47 44 61 L16 67 360 70 1 0 62 M16 68 363 71 63 115 69 366 64 114 70 72 16 71 372 73 15 72 375 74 48 48 45 65 16 73 378 75 49 49 46 66 M14 74 384 76 67 15 75 387 77 O 68 15 76 390 78 VO 50 50 47 69 N14 77 396 79 VO 51 51 48 70 R16 78 399 GND 52 52 49 71 P14 79
41. P1 915 VCC 100 130 150 X10 VCC GND 101 131 151 X11 GND GND 184 D3 102 132 152 W10 H12 N2 924 185 RS 103 133 153 V10 H11 N4 927 186 104 134 154 10 G14 N3 936 187 105 135 155 010 G15 M1 939 188 136 156 9 G13 M2 942 189 137 157 w9 G12 M3 948 November 5 1998 Version 5 2 7 151 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 190 8 M4 951 191 5 9 L1 954 192 D2 106 138 159 W8 G11 J1 960 193 107 139 160 7 15 963 VCC 161 5 VCC VCC 194 108 140 162 14 42 966 195 109 141 163 W7 13 93 972 196 164 U8 G10 K4 975 197 VO 165 W6 E15 G1 978 GND 110 142 166 X6 GND GND 198 VO T8 H2 984 199 V7 H3 987 200 VO 167 4 14 44 990 201 5 168 U7 12 F1 996 202 VO 143 169 W5 E13 G2 999 203 144 170 V6 D15 G3 1002 204 O 111 145 171 T7 F11 F2 1008 205 112 146 172 X3 D14 2 1011 206 D1 113 147 173 U6 E12 F3 1014 207 RCLK BUSY RDY 114 148 174 V5 C15 G4 1020 208 2 4 02 1023 209 w3 5 4 1032 210 115 149 175
42. access is located near each block along the right and left edges the array The longlines driven by the 3 state buffers have a weak keeper at each end This circuit prevents undefined float ing levels However it is overridden by any driver To ensure the longline goes high when no buffers are on add an additional BUFT to drive the output High during all of the previously undefined states Figure 10 shows how to use the 3 state buffers to imple ment a multiplexer The selection is accomplished by the buffer 3 state signal TS Horizontal X9030 Figure 9 XC5200 3 State Buffers 7 90 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays 2 Weak Keeper Figure 10 3 State Buffers Implement a Multiplexer Input Output Blocks User configurable input output blocks IOBs provide the interface between external package pins and the internal logic Each IOB controls one package pin and can be con figured for input output or bidirectional signals The block shown in Figure 11 consists of an input buffer and an output buffer The output driver is an 8 mA full rail CMOS buffer with 3 state control Two slew rate control modes are supported to minimize bus transients Both the output buffer and th
43. chip as shown in Figure 16 provide a high speed low skew clock network to each of the four global line buffers In addition to the ded icated pad the global lines can be sourced by internal logic PIPs from several routing channels within the Ver saRing can also be configured to drive the global line buff ers Details of all the programmable interconnect for a CLB is shown in Figure 17 GCK4 HP e e o e e s X5704 GCK2 Figure 16 Global Lines 7 96 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays XILINX 5 0106 e ett PH HH 111111111 1171 4 11111112 III 1 3 CEPT TTT ETT ee LLL Reet et H HH EHE M HH T L li IL JI9 NIS PI H H H H II
44. configuration mode by capturing its mode pins and is ready to start the configura tion process A master device waits up to an additional 250 us to make sure that any slaves in the optional daisy chain have seen that INIT is High Start Up Start up is the transition from the configuration process to the intended user operation This transition involves a change from one clock source to another and a change from interfacing parallel or serial configuration data where most outputs are 3 stated to normal operation with I O pins active in the user system Start up must make sure that the user logic wakes up gracefully that the outputs become active without causing contention with the configu ration signals and that the internal flip flops are released from the global Reset at the right time Figure 25 describes start up timing for the three Xilinx fam ilies in detail Express mode configuration always uses either CCLK_SYNC or UCLK_SYNC timing the other con figuration modes can use any of the four timing sequences To access the internal start up signals place the STARTUP library symbol Start up Timing Different FPGA families have different start up sequences The XC2000 family goes through a fixed sequence DONE goes High and the internal global Reset is de activated one CCLK period after the I O become active The XC3000A family offers some flexibility DONE can be programmed to go High one CCLK period before or after
45. data bit is put on the SPROM data output connected to the FPGA DIN pin The lead FPGA accepts this data on the subsequent rising CCLK edge The lead FPGA then presents the preamble data and all data that overflows the lead device on its DOUT pin There is an internal pipeline delay of 1 5 CCLK periods which means that DOUT changes on the falling CCLK edge and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge In the bitstream generation software the user can specify Fast ConfigRate which starting several bits into the first frame increases the CCLK frequency by a factor of twelve CCLK Output Serial Data In Serial DOUT Output The value increases from a nominal 1 MHz to a nominal 12 MHz Be sure that the serial PROM and slaves are fast enough to support this data rate The Medium ConfigRate option changes the frequency to a nominal 6 MHz XC2000 XC3000 A and XC3100A devices do not support the Fast or Medium ConfigRate options The SPROM CE input can be driven from either LDC or DONE Using LDC avoids potential contention on the DIN pin if this pin is configured as but LDC is then restricted to be a permanently High user output after con figuration Using DONE can also avoid contention on DIN provided the DONE before I O enable option is invoked Figure 28 on page 114 shows a full master slave system The leftmost device is in Master Serial mode Master Serial mo
46. direct con nects to each of its four neighboring CLBs These direct connects can also feed directly back to the CLB see Figure 14 In addition each CLB has 16 direct inputs four direct con nections from each of the neighboring CLBs These direct connections provide high speed local routing bypasses the GRM Local Interconnect Matrix The Local Interconnect Matrix LIM is built from input and output multiplexers The 13 CLB outputs 12 LC outputs plus a V GND signal connect to the eight VersaBlock outputs via the output multiplexers which consist of eight fully populated 1340 1 multiplexers Of the eight VersaBlock outputs four signals drive each neighboring CLB directly and provide a direct feedback path to the input multiplexers The four remaining multiplexer outputs can drive the GRM through four TBUFs 0 eight multiplexer outputs can connect to the GRM through the bidirectional MO M23 signals All eight signals also connect to the input multiplexers and are potential inputs to that CLB November 5 1998 Version 5 2 7 93 XC5200 Series Field Programmable Gate Arrays XILINX Global Nets North South PU Input Multiplexers West Direct North Feedback 4 Longlines 4 2 and GRM 0 Output Multiplexers 4 Direct to East Direct West lt 4 4 Vv Direct Sou
47. for mode selection is shown in Table 10 Note that the smallest package VQ64 only supports the Master Serial Slave Serial and Express modes A detailed description of each configuration mode with timing infor mation is included later in this data sheet During configu ration some of the I O pins are used temporarily for the configuration process pins used during configuration are shown in Table 13 on page 124 Master Modes The three Master modes use an internal oscillator to gener ate a Configuration Clock CCLK for driving potential slave devices They also generate address and timing for exter nal PROM s containing the configuration data Master Parallel Up or Down modes generate the CCLK signal and PROM addresses and receive byte parallel data The data is internally serialized into the FPGA data frame format The up and down selection generates starting addresses at either zero or 3FFFF for compatibility with different microprocessor addressing conventions The 7 104 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays Master Serial mode generates CCLK and receives the con figuration data in serial form from a Xilinx serial configura tion PROM CCLK speed is selectable as 1 MHz default 6 MHz or 12 MHz Configuration always starts at the default slow fre quency then can switch to the higher frequency during the first frame Frequency tolerance is 50 to 50
48. for the right edge 1 splitter bit 12 x number of Columns 16 Program Data Bits per Frame x Number of Frames 48 header bits 8 postamble bits 240 fill bits 8 start up bits Bits per Frame x Number of Frames 304 PROM Size Program Data Cyclic Redundancy Check CRC for Configuration and Readback The Cyclic Redundancy Check is a method of error detec tion in data transmission applications Generally the trans mitting system performs a calculation on the serial bitstream The result of this calculation is tagged onto the data stream as additional check bits The receiving system performs an identical calculation on the bitstream and com pares the result with the received checksum Each data frame of the configuration bitstream has four error bits at the end as shown in Table 11 If a frame data error is detected during the loading of the FPGA the con figuration process with a potentially corrupted bitstream is terminated The FPGA pulls the INIT pin Low and goes into a Wait state During Readback 11 bits of the 16 bit checksum are added to the end of the Readback data stream The checksum is computed using the CRC 16 CCITT polynomial as shown in Figure 23 The checksum consists of the 11 most signifi cant bits of the 16 bit code A change in the checksum indi cates a change in the Readback bitstream A comparison to a previous checksum is meaningful only if the readback data is independent of the current
49. is held High to prevent frame start bits from reaching any daisy chained devices In Express mode the length count bits are ignored and DOUT is held Low to disable the next device in the pseudo daisy chain A specific configuration bit early in the first of a mas ter device controls the configuration clock rate and can increase it by a factor of eight Therefore if a fast configu ration clock is selected by the bitstream the slower clock rate is used until this configuration bit is detected Each frame has a start field followed by the frame configu ration data bits and a frame error field If a frame data error is detected the FPGA halts loading and signals the error by pulling the open drain INIT pin Low After all configura tion frames have been loaded into an FPGA DOUT again follows the input data so that the remaining data is passed on to the next device In Express mode when the first device is fully programmed DOUT goes High to enable the next device in the chain Delaying Configuration After Power Up To delay master mode configuration after power up pull the bidirectional INIT pin Low using an open collector open drain driver See Figure 12 Using an open collector or open drain driver to hold INIT Low before the beginning of master mode configuration causes the FPGA to wait after completing the configuration memory clear operation When INIT is no longer held Low externally the device determines its
50. mode does not support CRC error check ing but does support constant field error checking A length count is not used in Express mode In the Express configuration mode an external signal drives the CCLK input s The first byte of parallel configu ration data must be available at the D inputs of the FPGA devices a short set up time before the second rising CCLK edge Subsequent data bytes are clocked in on each con secutive rising CCLK edge See Figure 38 on page 123 Bitstream generation currently generates a bitstream suffi cient to program in all configuration modes except Express Extra CCLK cycles are necessary to complete the configu ration since in this mode data is read at a rate of eight bits per CCLK cycle instead of one bit per cycle Normally the entire start up sequence requires a number of bits that is equal to the number of CCLK cycles needed An additional five CCLKs equivalent to 40 extra bits will guarantee com pletion of configuration regardless of the start up options chosen Multiple slave devices with identical configurations can be wired with parallel 00 07 inputs In this way multiple devices can be configured simultaneously Pseudo Daisy Chain Multiple devices with different configurations can be con nected together in a pseudo daisy chain provided that all of the devices are in Express mode A single combined bit stream is used to configure the chain of Express mode devices but the input data bus
51. must drive 00 07 of each device Tie High the CS1 pin of the first device to be config ured or leave it floating in the XC5200 since it has an inter nal pull up Connect the DOUT pin of each FPGA to the CS1 pin of the next device in the chain The 00 07 inputs are wired to each device in parallel The DONE pins are wired together with one or more internal DONE pull ups activated Alternatively a 4 7 kO external resistor can be used if desired See Figure 37 on page 122 CCLK pins are tied together The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode and only if all devices in the chain are to become active simultaneously All devices in Express mode are synchronized to the DONE pin User for each device become active after the DONE pin for that device goes High The exact timing is determined by options to the bitstream generation soft ware Since the DONE pin is open drain and does not drive a High value tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device in the chain has completed its configu ration cycle The status pin DOUT is pulled LOW two internal oscillator cycles nominally 1 MHz after INIT is recognized as High and remains Low until the device s configuration memory is full Then DOUT is pulled High to signal the next device in the chain to accept the configuration data on the D7 DO bus All devices recei
52. setup time 2 60 ns Data hold time 3 0 ns Note 1 At power up must rise from 2 0 V to min in less then 25 ms otherwise delay configuration by pulling PROGRAM Low until Vcc is Valid 2 The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle rising edge This timing diagram shows that the EPROM requirements are extremely relaxed EPROM access time can be longer than 500 ns EPROM data output has no hold time requirements Figure 32 Master Parallel Mode Programming Switching Characteristics November 5 1998 Version 5 2 7 117 XC5200 Series Field Programmable Gate Arrays 2 XILINX Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode An external signal drives the CCLK input s of the FPGA s The first byte of parallel configura tion data must be available at the Data inputs of the lead FPGA short setup time before the rising CCLK edge Subsequent data bytes are clocked in on every eighth con secutive rising CCLK edge The same CCLK edge that accepts data also causes the RDY BUSY output to go High for one CCLK period The pin name is a misnomer In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal Synchronous operation does not require this response but it is a meaningful signal NOTE for test purposes Note that RDY BUSY is pulled High with a high impedan
53. the I O become active Independent of DONE the internal global Reset is de activated one CCLK period before or after the I O become active The XC4000 XC5200 Series offers additional flexibility The three events DONE going High the internal Reset being de activated and the user I O going active can all occur in any arbitrary sequence Each of them can occur one CCLK period before or after or simultaneous with any of the others This relative timing is selected by means of software options in the bitstream generation software The default option and the most practical one is for DONE to go High first disconnecting the configuration data source and avoiding any contention when the I Os become active one clock later Reset is then released another clock period later to make sure that user operation starts from stable internal conditions This is the most common sequence shown with heavy lines in Figure 25 but the designer can modify it to meet particular requirements Normally the start up sequence is controlled by the internal device oscillator output CCLK which is asynchronous to the system clock XC4000 XC5200 Series offers another start up clocking option UCLK NOSYNC The three events described above need not be triggered by CCLK They can as a con figuration option be triggered by a user clock This means that the device can wake up in synchronism with the user system 7 110 November 5 1998 Version 5 2
54. 04 7 3 6 6 6 6 6 6 gt 5206 72 6 5 6 4 6 3 vine gt 72 65 60 BUFG 5215 6 8 5 7 5 7 5 7 Input Set up Time with delay to Flip Flop Input 5202 8 8 7 7 7 5 7 5 5204 8 6 7 5 7 5 7 5 gu Min 74 Time gt gt gt XC5210 8 5 7 4 7 4 7 3 BUFG XC5215 8 5 7 4 7 2 Input Hold Time with delay to CLB Flip Flop XC52xx 0 0 0 0 Direct Min T Time gt D BUFG EP Note These measurements assume that flip flop uses a direct interconnect to or from the The INREG OUTREG properties or XACT Performance can be used to assure that direct connects are used tpgy applies only to the input DI that bypasses the look up table which only offers direct connects to IOBs on the left and right edges of the die applies to inputs that feed the look up table which offers direct connect IOBs on all four edges as do the Q outputs 2 When testing outputs fast or slew limited half of the outputs on one side of the device are switching 7 130 November 5 1998 Version 5 2 gt XC5200 Series Field Programmable Gate Arrays XC5200 IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL M 38510 605 All devices are 100 func
55. 104 114 V9 134 600 115 10 95 105 115 V8 135 603 116 116 U8 136 612 117 VO 1 5 1 117 8 137 615 118 D2 67 71 68 96 106 118 V7 138 618 119 68 72 69 97 107 119 U7 139 624 120 5 5 98 108 120 V6 140 627 121 10 99 109 121 U6 141 630 GND 1 1 gt 100 110 122 7 142 122 111 123 05 145 636 123 5 gt 1 112 124 T6 146 639 124 VO 01 69 73 70 101 113 125 V3 147 642 125 70 74 71 102 114 126 V2 148 648 RCLK BUSY RD Y 126 p 103 115 127 04 149 651 127 1 104 116 128 5 150 654 128 DO DIN 71 75 72 105 117 129 03 151 660 129 DOUT 72 76 73 106 118 130 152 663 November 5 1998 Version 5 2 7 141 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order CCLK 73 77 74 107 119 131 V1 153 5 VCC 74 78 75 108 120 132 R4 154 5 130 TDO 75 79 76 109 121 133 U2 159 GND 76 80 77 110 122 134 R3 160 131 I O A0 WS 77 81 78 111 123 135 T3 161 9 132 GCK4 A1 I O 78 82 79 112 124 136 162 15 133 110 5 113 125 137 163 18 134 S 114 126 138 R2 164 21 135 A2 CS1 79 83 80 115 127 139 T2 165 27 136 80 84 81 116 128 140 N
56. 149 74 96 114 V19 N12 AF3 768 150 75 97 115 16 5 771 151 76 98 116 T17 K10 AE3 774 152 77 99 117 018 R14 AD4 780 153 78 100 118 20 N13 AC5 783 GND 79 101 119 W20 GND GND DONE 80 103 120 V18 P14 AD3 VCC 81 106 121 X19 VCC VCC PROG 82 108 122 U17 M12 AC4 154 07 83 109 123 W19 P15 AD2 792 155 GCK3 I O 84 110 124 W18 N14 795 156 85 111 125 T15 L11 AB4 804 157 86 112 126 U16 M13 1 807 158 1 127 17 15 4 810 159 5 128 18 14 816 160 015 2 819 161 T14 5 828 162 06 87 113 129 W17 J10 Y3 831 163 88 114 130 16 112 2 834 164 89 115 131 17 15 1 840 165 90 116 132 014 113 WA 843 166 y o 1 117 133 15 114 W3 846 167 118 134 T13 K11 Y2 852 168 W16 1 855 169 15 4 858 GND 91 119 135 X16 GND GND 170 136 13 115 V3 864 171 yo 2 137 V14 K12 W2 867 172 yo 92 120 138 W14 K13 U4 870 173 93 121 139 V13 K14 U3 876 VCC 140 X15 174 05 94 122 141 T12 K15 V2 879 175 CSO 95 123 142 X14 J12 V1 882 176 X13 T1 888 177 yo 1 12 1 R4 891 178 yo 124 144 W12 J13 R3 894 179 125 145 T11 J14 R2 900 180 96 126 146 12 15 903 181 yo 97 127 147 U11 J11 P3 906 182 04 98 128 148 11 H13 P2 912 183 99 129 149 W11 H14
57. 202 237 4 F6 C23 249 29 A14 158 203 238 D3 A2 D22 258 30 A15 159 204 239 C3 C3 C24 261 VCC 160 205 240 A2 VCC GND 1 2 1 B1 GND GND 31 GCK1 A16 I O 2 4 2 D4 04 023 270 32 17 3 5 3 B2 B1 C25 273 33 4 6 4 B3 C2 D24 279 34 y o 5 7 5 5 E23 282 35 TDI 6 8 6 D5 D3 C26 285 36 7 9 7 C4 C1 E24 294 37 5 24 297 38 06 25 303 39 8 10 8 7 2 026 306 40 9 11 9 4 G6 G24 309 41 yo 1 12 10 5 4 225 315 42 yo 13 11 4 D1 F26 318 43 x 12 D7 E3 H23 321 44 y o 13 C6 E2 H24 327 45 8 G25 330 46 5 G26 333 GND 10 14 14 A5 GND GND 47 11 15 15 B6 F5 J23 339 48 12 16 16 08 1 424 342 49 TMS 13 17 17 7 4 25 345 50 14 18 18 7 351 VCC 19 A6 51 20 C8 F2 L24 354 52 21 9 F1 K25 357 53 8 125 363 7 148 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 54 8 126 366 55 19 23 9 G4 M23 369 56 20 24 9 G3 M
58. 24 375 57 15 21 25 10 2 25 378 58 16 22 26 9 G1 M26 381 59 17 23 27 010 G5 N24 390 60 18 24 28 C10 H3 N25 393 GND 19 25 29 A10 GND GND VCC 20 26 30 11 VCC 61 yo 21 27 31 B10 H4 N26 399 62 y o 22 28 32 B11 H5 P25 402 63 23 29 33 C11 J2 P23 405 64 y o 24 30 34 E11 J1 P24 411 65 31 35 011 93 R26 414 66 32 36 12 94 825 417 67 B12 R24 423 68 1 1 13 R23 426 69 5 38 12 45 T26 429 70 39 K1 T25 435 VCC 40 A16 VCC 71 yo 25 33 41 A14 K2 U24 438 72 y o 26 34 42 C13 K3 V25 441 73 27 35 43 14 96 24 447 74 28 36 44 013 L1 U23 450 GND 29 37 45 A15 GND GND 75 1 1 15 Y26 453 76 13 5 W25 459 77 yo 46 14 12 24 462 78 47 17 4 V23 465 79 1 38 48 14 13 26 471 80 1 39 49 16 1 Y25 474 81 30 40 50 15 5 Y24 477 82 31 41 51 14 2 25 483 83 18 5 25 486 84 5 E D15 24 489 85 32 42 52 16 14 Y23 495 86 33 43 53 17 1 26 498 87 34 44 54 18 AA23 501 88 35 45 55 15 2 24 507 89 36 46 56 016 K6 AD25 510 90 37 47 57 C17 1 24 513 91 1 38 48 58 20 23 522 GND 39 49 59 19 GND GND 92 I O 40 50 60 C18 P2 AD24 525 VCC 41 55 61 20 VCC 93 2 I O 42 56 62 D17 M4 AC23 528 94
59. 3 166 30 137 110 5 117 129 141 2 167 33 138 110 1 1 130 142 T1 168 42 GND 118 131 143 171 139 2 5 119 132 144 1 172 45 140 2 120 133 145 1 173 51 141 VO A4 81 85 82 121 134 146 M2 174 54 142 VO 5 82 86 83 122 135 147 M1 175 57 143 148 13 176 63 144 136 149 12 177 66 145 110 87 84 123 137 150 11 178 69 146 2 88 85 124 138 151 K1 179 75 147 I O 83 89 86 125 139 152 K2 180 78 148 A7 84 90 87 126 140 153 K3 181 81 GND 1 91 88 127 141 154 K4 182 5 Additional No Connect N C Connections for PQ208 176 Packages PQ208 TQ176 195 1 39 65 104 143 158 167 196 3 51 66 105 144 169 206 12 52 91 107 155 170 207 13 53 92 117 156 208 38 54 102 118 157 Notes Boundary Scan Bit 0 TDO T Boundary Scan Bit 1 TDO O Boundary Scan Bit 1056 BSCAN UPD Pin Locations for XC5210 Devices The following table may contain pinout information for unsupported device package combinations Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information Pin Description PC84 144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 zc 2 128 142 155 183 44 voor 218 1 A8 3 129 143 156 184 93 213 111 2 A9 4 130 144 157 185 2 87 214 114 3 131 145 158 186 7 215 117 4 1
60. 32 146 159 187 H1 216 123 5 160 188 H2 D7 217 126 6 5 161 189 H3 E7 218 129 7 142 November 5 1998 Version 5 2 5 XC5200 Series Field Programmable Gate Arrays Pin Description Ta144 160 176 208 PG223 BG225 Boundary Sean 7 A10 5 133 147 162 190 Gi A6 220 135 8 A11 6 134 148 163 191 G2 B6 221 188 5 5 222 9 C6 223 141 10 5 G4 F7 224 150 1 185 149 164 192 F1 225 153 12 136 150 165 193 Ei B5 226 162 GND 187 151 166 194 G8 GND 227 13 195 F2 06 228 165 14 167 196 Di C5 229 171 15 152 168 197 1 230 174 16 5 153 169 198 E2 231 177 17 A12 7 138 154 170 199 232 183 18 13 8 139 155 171 200 02 05 233 186 19 110 F4 A3 234 189 20 O 4 235 195 21 O 140 156 172 20 Bi B3 236 198 22 O 14 157 173 202 F6 237 201 28 0 14 9 142 158 174 208 C2 A2 238 210 24 15 10 143 159 175 204
61. 36 40 44 48 58 E16 P3 64 444 78 10 41 45 49 59 617 15 65 447 79 10 42 46 50 60 017 66 450 80 10 43 47 51 61 R3 67 456 81 VO LDC 37 44 48 52 62 7 68 459 82 0 49 53 63 69 462 83 10 50 54 64 5 70 468 84 WO 65 Dis 71 471 85 10 66 NS 72 474 86 10 5 E15 P5 78 480 87 VO Fis L6 74 483 GND 45 51 55 67 016 GND 75 88 46 52 56 68 E18 R5 76 486 89 10 47 53 57 69 F18 M6 7 492 90 38 48 54 58 70 617 78 495 91 39 49 55 59 71 618 P6 79 504 vec 80 92 10 60 72 R6 81 507 93 61 73 H7 M7 82 510 94 10 815 84 516 7 144 November 5 1998 Version 5 2 5 XC5200 Series Field Programmable Gate Arrays Pin Description 84 Ta144 PQ160 TQ176 PQ208 PG223 86225 PQ240 iso 95 5 P7 85 519 96 10 50 56 62 74 R7 86 522 97 5 51 57 63 75 8 17 87 528 98 10 40 52 58 64 76 88 531 99 O ERR INIT 41 53 59 65 7 P8 89 534 42 54 60 66 78 5 90 GND 43 55 61 67 79
62. 4 78 75 108 P3 120 1 108 75 79 76 109 T1 121 0 GND 76 80 77 110 N3 122 109 WS 77 81 78 111 R1 123 9 110 GCKA I O 78 82 79 112 P2 124 15 111 yo 113 N2 125 18 112 yo 114 126 21 113 A2 CS1 79 83 80 115 P1 127 27 114 80 84 81 116 1 128 30 115 5 1 117 2 129 33 116 1 130 39 GND 1 1 118 13 131 1 117 yo 119 12 132 42 118 E 1 1 120 L1 133 45 119 A4 81 85 82 121 K3 134 51 120 A5 82 86 83 122 K2 135 54 121 yo 5 87 84 123 K1 137 57 122 88 85 124 J1 138 63 123 6 83 89 86 125 42 139 66 124 A7 84 90 87 126 93 140 69 GND 1 91 88 127 H2 141 Additional No Connect Connections for 160 Package PQ160 8 30 89 111 136 9 31 90 112 Notes Boundary Scan Bit 0 TDO T Boundary Scan Bit 1 TDO O Boundary Scan 1056 BSCAN UPD 7 138 November 5 1998 Version 5 2 5 XC5200 Series Field Programmable Gate Arrays Pin Locations for XC5206 Devices The following table may contain pinout information for unsupported device package combinations Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information
63. 5 240 yo 136 177 206 L5 B9 A12 111 241 yo 137 178 207 M1 A9 C13 114 242 y o 138 179 208 14 9 B13 117 243 A6 139 180 209 13 C8 A13 126 244 A7 140 181 210 L2 B8 B14 129 GND 141 182 211 L1 GND GND HQ208 HQ240 206 102 219 207 104 22 208 105 37 1 107 83 3 155 98 51 156 143 52 157 158 53 158 204 54 5 5 Additional No Connect N C Connections for 208 240 Packages Notes Pins labeled are internally bonded to VCC plane within the BG225 BG352 packages The external pins for the BG225 are B2 D8 H15 R8 B14 R1 H1 and R15 The external pins for the BG352 are A10 A17 B2 B25 D13 D19 D7 G23 H4 K1 K26 N23 P4 U1 U26 W23 Y4 AC14 AC20 AC8 AE2 AE25 AF10 and AF17 Pins labeled GND are internally bonded to a ground plane within the BG225 and BG352 packages The external pins for the BG225 are A1 D12 G7 G9 H6 H8 H10 J8 K8 A8 F8 G8 H2 H7 H9 J7 J9 M8 The external pins for the BG352 are A2 5 A8 A14 A19 A22 A25 26 B1 B26 E26 H1 26 N1 P26 W1 W26 AB1 AB26 AE1 AE26 AF1 AF13 AF19 AF2 AF22 AF25 AF26 AF5 AF8 Boundary Scan Bit 0 TDO T Boundary Scan Bit 1 TDO O Boundary Scan 1056 BSCAN UPD November 5 1998 Version 5 2 7 153 XC5200 Series Field Programmable Gate Arrays XILINX Product Availability
64. 6 88 K18 N8 AE14 648 123 ERR INIT 59 77 89 K19 P8 AF14 651 60 78 90 120 VCC VCC GND 61 79 91 K20 GND GND 124 62 80 92 119 18 13 660 125 63 81 93 118 9 13 663 126 64 82 94 116 RQ AD13 672 127 65 83 95 117 9 12 675 128 84 96 20 9 12 678 129 85 97 19 19 12 684 130 20 12 687 131 18 AF11 690 132 99 N19 R10 AE11 696 133 100 20 10 11 699 101 T20 VCC VCC 134 66 86 102 N18 N10 9 702 135 67 87 103 19 AD9 708 136 68 88 104 N17 R11 AC10 711 137 69 89 105 819 11 7 714 GND 70 90 106 R20 GND GND 138 N16 720 139 18 AD8 723 140 107 020 10 9 726 141 108 17 N11 AF6 732 142 91 109 19 812 7 735 143 92 110 818 110 7 738 144 71 93 111 16 12 744 145 72 94 112 20 M11 AE5 747 7 150 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order 146 R17 5 AD6 750 147 yo 1 T18 AC7 756 148 73 95 113 U19 R13 AF4 759
65. A 3 I DATA 3 1 DATA 3 DATA 8 RS 2 DATA 2 DATA 2 2 2 1 DATA 1 I DATA 1 I DATA 1 DATA 1 RDY BUSY RDY BUSY RCLK RCLK yo DIN DIN DATA 0 DATA 0 I DATA 0 I DATA 0 DATA 0 DOUT DOUT DOUT DOUT DOUT DOUT DOUT CCLK CCLK CCLK CCLK TDO I O WS 1 AO AO Al A1 GCK4 I O CS1 A2 A2 CS1 1 4 4 yo A5 A5 7 7 yo A8 A8 9 9 10 10 yo A11 A11 y o A12 A12 yo A13 A13 yo A14 A14 y o A15 A15 y o ALL OTHERS Notes 1 shaded table cell represents 20 kQ to 100 kQ pull up resistor before and during configuration 2 l represents an input O represents an output 3 INIT is an open drain output during configuration 7 124 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays Configuration Switching Characteristics fa T por gt RE PROGRAM gt 300ns 1 d gt Ticck a CCLK OUTPUT or INPUT 4 300 ns 2 VALID DONE RESPONSE Required 300 ns 1532 Master Modes Description Symbol Min Max Units Power On Reset Tpor 2 15 ms Prog
66. Bs These pins can also be used as inputs to the CLB logic after configuration is completed If the BSCAN symbol is not placed in the design all boundary scan functions are inhib ited once configuration is completed and these pins become user programmable In this case they must be called out by special schematic definitions To use these pins place the library components TCK and TMS instead of the usual pad symbols put or output buffers must still be used HDC High During Configuration is driven High until the I O go active Itis available a control output indicating that configuration is not yet completed After configuration is a user programmable I O pin LDC Low During Configuration LDC is driven Low until the I O go active It is available as control output indicating that configuration is not yet completed After configuration LDC is a user programmable pin INIT Before during configuration INIT is a bidirectional signal 1 10 external pull up resistor is recommended ____ As an active Low open drain output INIT is held Low during the power stabilization and internal clearing of the configuration memory As an active Low input it can be used to hold the FPGA in the internal WAIT state before the start of configuration Master mode devices stay ina WAIT state an additional 50 to 250 us after INIT has gone High Du
67. DONE 53 53 50 72 815 80 VCC 54 54 51 73 P13 81 5 PROG 55 55 52 74 R14 82 80 D7 56 56 53 75 T16 83 408 81 GCK3 57 57 54 76 T15 84 411 82 5 77 813 85 420 83 78 12 86 423 84 06 58 58 55 79 T14 87 426 85 VO 59 56 80 T13 88 432 GND 5 81 11 91 86 VO 82 R11 92 435 87 83 T11 93 438 88 D5 59 60 57 84 T10 94 444 89 CS0 60 61 58 85 P10 95 447 90 VO 62 59 86 R10 96 450 91 VO 63 60 87 T9 97 456 92 D4 61 64 61 88 R9 98 459 93 62 65 62 89 9 99 462 VCC 63 66 63 90 R8 100 GND 64 67 64 91 P8 101 94 03 65 68 65 92 8 102 468 95 RS 66 69 66 93 7 103 471 96 VO 70 67 94 T6 104 474 97 VO 95 R7 105 480 98 D2 67 71 68 96 7 106 483 November 5 1998 Version 5 2 7 137 XC5200 Series Field Programmable Gate Arrays XILINX Pin Description PC84 PQ100 100 TQ144 PG156 PQ160 Boundary Scan Order 99 68 72 69 97 5 107 486 100 98 R6 108 492 101 1 0 99 T4 109 495 GND 100 110 102 D1 69 73 70 101 T3 113 498 103 70 74 71 102 5 114 504 RCLK BUSY RDY 104 5 103 R4 115 507 105 104 R3 116 510 106 00 DIN 71 75 72 105 P4 117 516 107 DOUT 72 76 73 106 T2 118 519 CCLK 73 77 74 107 R2 119 z VCC 7
68. DOUT it has received its required number of data frames After an FPGA has received its configuration data it passes on any additional frame start bits and configuration data on DOUT When the total number of configuration clocks applied after memory initialization equals the value of the 24 bit length count the FPGAs begin the start up sequence and become operational together FPGA I O are normally released two CCLK cycles after the last configura tion bit is received Figure 25 on page 109 shows the start up timing for an XC5200 Series device The daisy chained bitstream is not simply a concatenation of the individual bitstreams The PROM file formatter must be used to combine the bitstreams for a daisy chained con figuration Multi Family Daisy Chain All Xilinx FPGAs of the XC2000 XC3000 XC4000 and XC5200 Series use a compatible bitstream format and can therefore be connected in a daisy chain in an arbitrary sequence There is however one limitation If the chain contains XC5200 Series devices the master normally can not be an XC2000 or XC3000 device The reason for this rule is shown in Figure 25 on page 109 Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses they all recognize length count match on the same CCLK edge as indicated on the left edge of Figure 25 The master device then generates additional CCLK pulses until it reaches its fi
69. F inputs via transparent latch to Q DI inputs to DO output Logic Cell Feedthrough inputs via F5 to DO output Carry Delays Incremental delay per bit Carry in overhead from DI Carry in overhead from F Carry out overhead to DO Sequential Delays Clock CK to out Q Flip Flop Gate Latch enable going active to out Q Set up Time Before Clock CK F inputs inputs via Fb MUX DI input CE input Hold Times After Clock CK F inputs inputs via Fb MUX DI input CE input Clock Widths Clock High Time Clock Low Time Toggle Frequency MHz Note 3 Reset Delays Width High Delay from CLR to Q Flip Flop Delay from CLR to Q Latch Global Reset Delays Width High Delay from internal GR to Q 14 7 12 1 9 1 8 0 Note 1 The CLB K to output delay of any CLB plus the shortest possible interconnect delay is always longer than the Data In hold time requirement of any on the same die 2 Timing is based upon the XC5215 device For other devices see Timing Calculator 3 Maximum flip flop toggle rate for export control purposes November 5 1998 Version 5 2 7 129 XC5200 Series Field Programmable Gate Arrays 2 XILINX XC5200 Guaranteed Input and Output Parameters Pin to Pin All values listed below are tested directly and guaranteed over the operating conditions The same parameters can a
70. It is this combination of both fine grain and coarse grain architecture attributes that maximize logic uti lization in the XC5200 family This symmetrical structure takes full advantage of the third metal layer freeing the placement software to pack user logic optimally with mini mal routing restrictions VersaRing Interface The interface between the IOBs and core logic has been redesigned in the XC5200 family The IOBs are completely decoupled from the core logic The XC5200 IOBs contain dedicated boundary scan logic for added board level test ability but do not include input or output registers This approach allows a maximum number of IOBs to be placed around the device improving the l O to gate ratio and decreasing the cost per A freeway of interconnect cells surrounding the device forms the VersaRing which provides connections from the IOBs to the internal logic These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock in addition to Longline connections surrounding the device The VersaRing eliminates the historic trade off between high logic utilization and pin placement flexibility These incremental edge resources give users increased flexibility in preassigning i e locking pins before completing their logic designs This ability accelerates time to market since PCBs and other system components can be manu factured concurrent with the logic design General
71. K readback must be inhibited for security reasons the readback control nets are simply not connected Violating the Maximum High and Low Time Specification for the Readback Clock The readback clock has a maximum High and Low time specification In some cases this specification cannot be met For example if a processor is controlling readback an interrupt may force it to stop in the middle of a readback This necessitates stopping the clock and thus violating the specification The specification is mandatory only on clocking data at the end of a frame prior to the next start bit The transfer mech anism will load the data to a shift register during the last six clock cycles of the frame prior to the start bit of the follow ing frame This loading process is dynamic and is the source of the maximum High and Low time requirements Therefore the specification only applies to the six clock cycles prior to and including any start bit including the clocks before the first start bit in the readback data stream At other times the frame data is already in the register and the register is not dynamic Thus it can be shifted out just like a regular shift register The user must precisely calculate the location of the read back data relative to the frame The system must keep track of the position within a data frame and disable inter rupts before frame boundaries Frame lengths and data for mats are listed in Table 11 and Table 12
72. LENGTH COUNT zu CLEAR MEMORY CCLK STARTUP CLK USER NET Figure 26 Start up Logic Release of Global Reset After DONE Goes High By default Global Reset GR is released two CCLK cycles after the DONE pin goes High If CCLK is not clocked twice after DONE goes High all flip flops are held in their initial reset state The delay from DONE High to GR inactive is controlled by an option to the bitstream generation soft ware Configuration Complete After DONE Goes High Three full CCLK cycles are required after the DONE pin goes High as shown in Figure 25 on page 109 If CCLK is not clocked three times after DONE goes High readback cannot be initiated and most boundary scan instructions cannot be used CONFIGURATION BIT OPTIONS SELECTED BY USER X9002 Configuration Through the Boundary Scan Pins XC5200 Series devices can be configured through the boundary scan pins For detailed information refer to the Xilinx application note XAPP017 Boundary Scan in XC4000 and 5200 Devices Readback The user can read back the content of configuration mem ory and the level of certain internal nodes without interfer ing with the normal operation of the device Readback not only reports the downloaded configuration bits but can also include the present state of the device represented by the content of all flip flops and latches in CLBs 7 112 November 5 1998 Version 5 2 XILINX
73. Routing Matrix The GRM is functionally similar to the switch matrices found in other architectures but it is novel in its tight cou pling to the logic resources contained in the VersaBlocks Advanced simulation tools were used during the develop ment of the XC5200 architecture to determine the optimal level of routing resources required The XC5200 family contains six levels of interconnect hierarchy a series of 7 86 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays single length lines double length lines and Longlines all routed through the GRM The direct connects LIM and logic cell feedthrough are contained within each Versa Block Throughout the XC5200 interconnect an effi cient multiplexing scheme in combination with three layer metal TLM was used to improve the overall efficiency of silicon usage Performance Overview The XC5200 family has been benchmarked with many designs running synchronous clock rates beyond 66 MHz The performance of any design depends on the circuit to be implemented and the delay through the combinatorial and sequential logic elements plus the delay in the intercon nect routing A rough estimate of timing can be made by assuming 3 6 ns per logic level which includes direct con nect routing delays depending on speed grade More accurate estimations can be made using the information in the Switching Characteristic Guideline section Ta
74. Series Field Programmable Gate Arrays XILINX XC5200 Family Compared to XC4000 Spartan and XC3000 Series For readers already familiar with the XC4000 Spartan and XC3000 FPGA Families this section describes significant differences between them and the XC5200 family Unless otherwise indicated comparisons refer both XC4000 Spartan and XC3000 devices Configurable Logic Block CLB Resources Each XC5200 CLB contains four independent 4 input func tion generators and four registers which are configured as four independent Logic Cells LCs The registers in each XC5200 LC are optionally configurable as edge triggered D type flip flops or as transparent level sensitive latches The XC5200 CLB includes dedicated carry logic that pro vides fast arithmetic carry capability The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions XC4000 family XC5200 devices have no wide edge decoders Wide decoders are implemented using cascade logic Although sacrificing speed for some designs lack of wide edge decoders reduces the die area and hence cost of the XC5200 XC4000 Spartan family XC5200 dedicated carry logic differs from that of the XC4000 Spartan family in that the sum is generated in an additional function generator in the adjacent column This design reduces XC5200 die size and hence cost for many applications Note however that a loadable up down coun
75. User 4 Figure 20 Boundary Scan Schematic Example Even if the boundary scan symbol is used in a schematic the input pins TMS TCK and TDI can still be used as inputs to be routed to internal logic Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins The simplest way to prevent this is to keep TMS High and then apply whatever signal is desired to TDI and TCK Avoiding Inadvertent Boundary Scan If TMS is used as user I O care must be taken to ensure that at least one of these pins is held constant dur ing configuration In some applications a situation may occur where TMS or TCK is driven during configuration This may cause the device to go into boundary scan mode and disrupt the configuration process To prevent activation of boundary scan during configura tion do either of the following TMS Tie High to put the Test Access Port controller benign RESET state TCK Tie High or Low do not toggle this clock input For more information regarding boundary scan refer to the Xilinx Application Note XAPP 017 Boundary Scan in XC4000 and XC5200 Devices Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and Inside the FPGA a dedicated Vcc and Ground ring sur rounding the logic array provides power to the drivers a
76. VCC 33 28 25 37 41 45 016 55 57 M2 34 29 26 38 42 46 C16 56 336 58 GCK2 I O 35 30 27 39 43 47 B17 57 339 59 HDC 36 31 28 40 44 48 E16 58 348 60 yo 41 45 49 C17 59 351 61 yo 42 46 50 D17 60 354 62 yo 32 29 43 47 51 B18 61 360 63 LDC 37 33 30 44 48 52 E17 62 363 64 yo 49 53 F16 63 372 65 yo 50 54 C18 64 375 GND 45 51 55 G16 67 66 yo 46 52 56 E18 68 378 67 y o 47 53 57 F18 69 384 68 yo 38 34 31 48 54 58 G17 70 387 69 yo 39 35 32 49 55 59 G18 71 390 70 y o 60 H16 72 396 71 y o 61 H17 73 399 72 yo 36 33 50 56 62 H18 74 402 73 yo 37 34 51 57 63 J18 75 408 74 y o 40 38 35 52 58 64 J17 76 411 75 ERR INIT 41 39 36 53 59 65 916 77 414 VCC 42 40 37 54 60 66 J15 78 GND 43 41 38 55 61 67 15 79 76 y o 44 42 39 56 62 68 K16 80 420 7T y o 45 43 40 57 63 69 K17 81 423 78 y o 44 41 58 64 70 K18 82 426 79 y o 45 42 59 65 71 L18 83 432 80 y o 1 1 5 1 72 117 84 435 81 yo 73 L16 85 438 82 46 46 43 60 66 74 M18 86 444 83 47 47 44 61 67 75 17 87 447 84 yo 62 68 76 N18 88 450 85 yo 63 69 77 P18 89 456 GND 64 70 78 M16 90 86 yo 71 79 T18 93 459 7 140 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays
77. X6702 OBUFT Figure 12 Open Drain Output Output Slew Rate The slew rate of each output buffer is by default reduced to minimize power bus transients when switching non criti cal signals For critical signals attach a FAST attribute or property to the output buffer or flip flop For XC5200 devices maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power Ground pin pair For some XC5200 devices additional internal Power Ground pin pairs are connected to special Power and Ground planes within the packages to reduce ground bounce For slew rate limited outputs this total is two times larger for each device type 400 pF for XC5200 devices This maxi mum capacitive load should not be exceeded as it can result in ground bounce of greater than 1 5 V amplitude and more than 5 ns duration This level of ground bounce may cause undesired transient behavior on an output or in the internal logic This restriction is common to all high speed digital ICs and is not particular to Xilinx or the XC5200 Series XC5200 Series devices have a feature called Soft Start up designed to reduce ground bounce when all out puts are turned on simultaneously at the end of configura tion When the configuration process is finished and the device starts up the first activation of the outputs is auto matically slew rate limited Immediately following the initial
78. XC3000 family device are used to generate the additional CCLK pulse required by the XC5200 Series devices When the lead device removes the internal RESET signal the 2 bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period An external connection between this output and CCLK thus creates the extra CCLK pulse November 5 1998 Version 5 2 7 105 XC5200 Series Field Programmable Gate Arrays 5 XILINX Output gt Connected to 0 0 1 0 Active Low Output Active High Output 0 1 X5223 Figure 22 CCLK Generation for XC3000 Master Driving an XC5200 Series Slave Express Mode Express mode is similar to Slave Serial mode except the data is presented in parallel format and is clocked into the target device a byte at a time rather than a bit at a time The data is loaded in parallel into eight different columns it is not internally serialized Eight bits of configuration data are loaded with every CCLK cycle therefore this configuration mode runs at eight times the data rate of the other six modes In this mode the XC5200 family is capable of sup porting a CCLK frequency of 10 MHz which is equivalent to an 80 MHz serial rate because eight bits of configuration data are being loaded per CCLK cycle An XC5210 in the Express mode for instance can be configured in about 2 ms The Express
79. XC5200 Series Field Programmable Gate Arrays Note that in XC5200 Series devices configuration data is not inverted with respect to configuration as it is in XC2000 and XC3000 families Readback of Express mode bitstreams results in data that does not resemble the original bitstream because the bit stream format differs from other modes XC5200 Series Readback does not use any dedicated pins but uses four internal nets RDBK TRIG RDBK DATA RDBK RIP and RDBK CLK that can be routed to any IOB To access the internal Readback sig nals place the READBACK library symbol and attach the appropriate pad symbols as shown in Figure 27 After Readback has been initiated by a Low to High transi tion on RDBK TRIG the RDBK RIP Read In Progress output goes High on the next rising edge of RDBK CLK Subsequent rising edges of this clock shift out Readback data on the RDBK DATA net Readback data does not include the preamble but starts with five dummy bits all High followed by the Start bit Low of the first frame The first two data bits of the first frame are always High Each frame ends with four error check bits They are read back as High The last seven bits of the last frame are also read back as High An additional Start bit Low and an 11 bit Cyclic Redundancy Check CRC signature follow before RDBK RIP returns Low IF UNCONNECTED DEFAULT IS CCLK READ DATA READBACK READ TRIGGER TRIG ge
80. activation of the I O the slew rate of the individual outputs is determined by the individual configuration option for each IOB Global Three State A separate Global 3 State line not shown in Figure 11 forces all FPGA outputs to the high impedance state unless boundary scan is enabled and is executing an EXTEST instruction This global net GTS does not com pete with other routing resources it uses a dedicated distri bution network GTS can be driven from any user programmable pin as a global 3 state input To use this global net place an input pad and input buffer in the schematic or HDL code driving the GTS pin of the STARTUP symbol A specific pin loca tion can be assigned to this input using a LOC attribute property just as with any other user programmable pad An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3 State signal Using GTS is similar to Global Reset See Figure 8 on page 90 for details Alternatively GTS can be driven from any internal node Other IOB Options There are a number of other programmable options in the XC5200 Series IOB Pull up and Pull down Resistors Programmable IOB pull up and pull down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity The con figurable pull up resistor is a p channel transistor that pulls 7 92 November 5 1998 Version 5 2 XILINX
81. al Mode Programming Switching Characteristics November 5 1998 Version 5 2 7 121 XC5200 Series Field Programmable Gate Arrays XILINX Express Mode Express mode is similar to Slave Serial mode except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle An external source is used to drive CCLK while byte wide data is loaded directly into the con figuration data shift registers A CCLK frequency of 10 MHz is equivalent to an 80 MHz serial rate because eight bits of configuration data are loaded per CCLK cycle Express mode does not support CRC error checking but does support constant field error checking In Express mode an external signal drives the CCLK input of the FPGA device The first byte of parallel configuration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge Subse quent data bytes are clocked in on each consecutive rising CCLK edge If the first device is configured in Express mode additional devices may be daisy chained only if every device in the chain is also configured in Express mode CCLK pins are tied together and 00 07 pins are tied together for all devices along the chain A status signal is passed from DOUT to CS1 of successive devices along the chain The lead device in the chain has its CS1 input tied High or float ing since there is an internal pullup Frame data is accepted only when CS1 is High and the d
82. back Clock on page 113 for an explanation of this exception DONE is a bidirectional signal with an optional internal pull up resistor As an output it indicates the completion of the configuration process As an input a Low level on DONE can be configured to delay the global logic initialization and the enabling of out DONE puts The exact timing the clock source for the Low to High transition and the optional pull up resistor are selected as options in the program that creates the configuration bit stream The resistor is included by default PROGRAM an active Low input that forces the FPGA to clear its configuration mem ory It is used to initiate a configuration cycle When PROGRAM goes High the FPGA executes a complete clear cycle before it goes into a WAIT state and releases INIT The PROGRAM pin has an optional weak pull up after configuration User I O Pins That Can Have Special Functions During Peripheral mode configuration this pin indicates when it is appropriate to write another byte of data into the FPGA The same status is also available on D7 in Asyn RDY BUSY chronous Peripheral mode if a read operation is performed when the device is selected After configuration RDY BUSY is a user programmable I O ___ RDY BUSY is pulled High with a high impedance pull up prior to INIT going High During Master Parallel configuration each change on the A0 A17 outputs is preceded by a rising edge on RCLK a r
83. ce pullup prior to INIT going High The lead FPGA serializes the data and presents the pre amble data and all data that overflows the lead device on its DOUT pin There is an internal delay of 1 5 CCLK peri ods which means that DOUT changes on the falling CCLK edge and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge In order to complete the serial shift operation 10 additional CCLK rising edges are required after the last data byte has been loaded plus one more CCLK cycle for each daisy chained device Synchronous Peripheral mode is selected by a 011 on the mode pins M2 M1 MO M2 can be shorted to Ground if not used as N C CLOCK 8 DATA BUS DOUT XC5200 SYNCHRO NOUS PERIPHERAL CONTROL SIGNALS 3 3 PROGRAM 3 3 ra OPTIONAL DAISY CHAINED FPGAs 5200 SLAVE Figure 33 Synchronous Peripheral Mode Circuit Diagram X9005 7 118 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays TccL CCLK CD Tic NETS INIT 2 i pod BYTE 0 OUT gt BYTE 1 OUT DOUT K 7 1 RDY BUSY X6096 Description Symbol Min Max Units INIT High setup time 1 Tic 5 us DO D7 setup time 2 60 ns CCLK DO D7 3 0 ns CCLK High time 50 ns
84. ces gt 51 DOUT DATA BUS vcc XC5200 4 PROGRAM e j INIT _ gt 00 07 gt _ gt PROGRAM INIT DONE Optional Daisy Chained XC5200 CCLK CCLK e Figure 37 Express Mode Circuit Diagram To Additional Optional Daisy Chained Devices X6611 01 7 122 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays CCLK INIT Top 8 2 Serial Data LULL DOUT FPGA Filled Internal INIT RDY BUSY 51 5087 Symbol Min Max Units INIT High Setup time required 1 Tic 5 DIN Setup time required 2 30 ns CCLK DIN required 3 0 ns CCLK High time 30 ns CCLK Low time 30 ns CCLK frequency Foc 10 MHz Note If not driven by the preceding DOUT CS1 must remain high until the device is fully configured Figure 38 Express Mode Programming Switching Characteristics November 5 1998 Version 5 2 7 123 XC5200 Series Field Programmable Gate Arrays XILINX Table 13 Pin Functions During Configuration CONFIGURATION MODE lt 2 1 0 g
85. d a standard test logic structure in their device to achieve high fault coverage for I O and internal logic This structure is easily implemented with a four pin interface on any boundary scan compatible IC IEEE 1149 1 compatible devices may be serial daisy chained together connected in parallel or a combination of the two XC5200 devices support all the mandatory boundary scan instructions specified in the IEEE standard 1149 1 A Test Access Port TAP and registers are provided that imple ment the EXTEST SAMPLE PRELOAD and BYPASS instructions The TAP can also support two USERCODE instructions When the boundary scan configuration option is selected three normal user I O pins become dedicated inputs for these functions Another user output pin becomes the dedicated boundary scan output Boundary scan operation is independent of individual configuration and package type All IOBs are treated as independently controlled bidirectional pins including any unbonded IOBs Retaining the bidirectional test capability after configuration provides flexibility for interconnect test ing Also internal signals can be captured during EXTEST by connecting them to unbonded IOBs or to the unused out puts IOBs used as unidirectional input pins This tech nique partially compensates for the lack of INTEST support The user can serially load commands and data into these devices to control the driving of their outputs and to exam ine t
86. d control logic There are five independent inputs and three outputs to each LC The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register this feature is a first for FPGAs The storage device is configurable as either a D flip flop or a latch The control logic consists of carry logic for fast implementation of arithmetic functions which can Direct Connects X5707 also be configured as a cascade chain allowing decode of very wide input functions Figure 2 VersaBlock CE CK CLR X4956 Figure 3 XC5200 Logic Cell Four LCs per CLB November 5 1998 Version 5 2 7 85 XC5200 Series Field Programmable Gate Arrays XILINX The XC5200 CLB consists of four LCs as shown in Figure 4 Each CLB has 20 independent inputs and 12 independent outputs The top and bottom pairs of LCs can be configured to implement 5 input functions The chal lenge of FPGA implementation software has always been to maximize the usage of logic resources The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect the Local Interconnect Matrix LIM and direct connects These two interconnect resources combined with the CLB form the VersaBlock represented in Figu
87. d in bitstreams ated by the Xilinx software In Express mode only non CRC error checking is sup ported In all other modes a selection of CRC or non CRC error checking is allowed by the bitstream generation soft ware The non CRC error checking tests for a designated end of frame field for each frame For CRC error checking the software calculates a running CRC and inserts a unique four bit partial check at the end of each frame The 11 bit CRC check of the last frame of an FPGA includes the last seven data bits Detection of an error results in the suspension of data load ing and the pulling down of the INIT pin In Master modes CCLK and address signals continue to operate externally The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vcc Table 12 Internal Configuration Data Structure VersaBlock PROM Xilinx Device Array Size Serial PROM bits Needed 5202 8 8 42 416 1765 XC5204 10x12 70 704 XC17128E XC5206 14x14 106 288 XC17128E XC5210 18x 18 165 488 XC17256E XC5215 22 x 22 237 744 XC17256E Bits per Frame 34 x number of Rows 28 for the top 28 for the bottom 4 splitter bits 8 start bits 4 error check bits 4 fill bits 24 extended write bits 34 x number of Rows 100 In the XC5202 8 x 8 there are 8 fill bits per frame not 4 Number of Frames 12 x number of Columns 7 for the left edge 8
88. de is selected by a lt 000 gt on the mode pins M2 M1 Description Symbol Min Max Units CCLK DIN setup 1 Tpsck 20 ns DIN hold 2 0 ns Notes 1 At power up Vcc must rise from 2 0 V to Vcc min in less than 25 ms otherwise delay configuration by pulling PROGRAM Low until Vcc is valid 2 Master Serial mode timing is based on testing in slave mode Figure 30 Master Serial Mode Programming Switching Characteristics In the two Master Parallel modes the lead FPGA directly addresses an industry standard byte wide EPROM and accepts eight data bits just before incrementing or decre menting the address outputs The eight data bits are serialized in the lead FPGA which then presents the preamble data and all data that over flows the lead device on its DOUT pin There is an inter nal delay of 1 5 CCLK periods after the rising CCLK edge that accepts a byte of data and also changes the EPROM address until the falling CCLK edge that makes the LSB DO of this byte appear at DOUT This means that DOUT changes on the falling CCLK edge and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge The PROM address pins can be incremented or decre mented depending on the mode pin settings This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers Some processors must boot from the bottom of memory all zeros
89. device size as described for table 11 Data Stream Format The data stream bitstream format is identical for all con figuration modes with the exception of Express mode In Express mode the device becomes active when DONE goes High therefore no length count is required Addition ally CRC error checking is not supported in Express mode The data stream formats are shown in Table 11 Express mode data is shown with DO at the left and D7 at the right For all other modes bit serial data is read from left to right and byte parallel data is effectively assembled from this serial bitstream with the first bit in each byte assigned to DO The configuration data stream begins with a string of eight ones a preamble code followed by a 24 bit length count and a separator field of ones or 24 fill bits in Express mode This header is followed by the actual configuration data in frames The length and number of frames depends on the device type see Table 12 Each frame begins with a start field and ends with an error check In all modes except Express mode a postamble code is required to sig nal the end of data for a single device In all cases addi tional start up bytes of data are required to provide four clocks for the startup sequence at the end of configuration Long daisy chains require additional startup bytes to shift the last data through the chain All startup bytes are don t cares these bytes are not include
90. device state CLB out puts should not be included Read Capture option not used Statistically one error out of 2048 might go undetec ted November 5 1998 Version 5 2 7 107 XC5200 Series Field Programmable Gate Arrays 2 XILINX x2 X15 X16 6 71819 10 1112 13 14 gt 15 gt T 1 1 a sse 1 1 1 1 1 1511411311211111019 8 7 615 LAST DATA FRAME lt CRC CHECKSUM gt START o Readback Data Stream Figure 23 Circuit for Generating CRC 16 Configuration Sequence There are four major steps in the XC5200 Series power up configuration sequence Power On Time Out Initialization Configuration Start Up The full process is illustrated in Figure 24 Power On Time Out An internal power on reset circuit is triggered when power is applied When reaches the voltage at which portions of the FPGA begin to operate i e performs a write and read test of a sample pair of configuration mem ory bits the programmable buffers are 3 stated with active high impedance pull up resistors A time out delay nominally 4 ms is initiated to allow the power supply voltage to stabilize For correct operation the power supply must reach V min b
91. dified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
92. e 3 state control are invertible The input buffer has globally selected CMOS or TTL input thresholds The input buffer is invertible and also provides a programmable delay line to assure reliable chip to chip set up and hold times Minimum ESD protection is 3 KV using the Human Body Model Slew Rate Control Figure 11 XC5200 I O Block Input Signals The XC5200 inputs can be globally configured for either TTL 1 2V or CMOS thresholds using an option in the bit stream generation software There is a slight hysteresis of about 300mV The inputs of XC5200 Series 5 Volt devices can be driven by the outputs of any 3 3 Volt device if the 5 Volt inputs are in TTL mode Supported sources for XC5200 Series device inputs are shown in Table 5 X6466 Table 5 Supported Sources for XC5200 Series Device Inputs XC5200 Input Mode 5V 5V SENSE TTL CMOS Any device Vcc 3 3 V 4 CMOS outputs Unreliable Any device Vcc 5 4 Data TTL outputs Any device Vcc 5 4 CMOS outputs Optional Delay Guarantees Zero Hold Time XC5200 devices do not have storage elements in the 1085 However XC5200 IOBs can be efficiently routed to CLB flip flops or latches to store the I O signals The data input to the register can optionally be delayed by several nanoseconds With the delay enabled the setup time of the input flip flop is increased so that normal clock routing does no
93. edundant output signal RCLK is useful for clocked PROGRAM RCLK ix PROMs It is rarely used during configuration After configuration RCLK is a user pro grammable I O pin As Mode inputs these pins are sampled before the start of configuration to determine the configuration mode to be used After configuration MO M1 and M2 become us MO M1 M2 lO er programmable O During configuration these pins have weak pull up resistors For the most popular con figuration mode Slave Serial the mode pins can thus be left unconnected A pull down resistor value of 3 3 kO is recommended for other modes If boundary scan is used this pin is the Test Data Output If boundary scan is not used this pin is a 3 state output after configuration is completed TDO O O This pin can be user output only when called out by special schematic definitions To use this pin place the library component TDO instead of the usual pad symbol An out put buffer must still be used 7 102 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays Table 9 Pin Descriptions Continued Pin Name TDI TCK TMS y o During Config yo After Config Pin Description If boundary scan is used these pins are Test Data In Test Clock and Test Mode Select inputs respectively They come directly from the pads bypassing the IO
94. ency To include flip flop place the appropriate library symbol For example FDCE is a D type flip flop with clock enable and asynchronous clear The corresponding latch symbol is called LDCE In XC5200 Series devices the flip flops can be used as registers or shift registers without blocking the function generators from performing a different perhaps unrelated task This ability increases the functional capacity of the devices The CLB setup time is specified between the function gen erator inputs and the clock input CK Therefore the speci fied CLB flip flop setup time includes the delay through the function generator Three State Buffers The XC5200 family has four dedicated Three State Buffers TBUFs or BUFTs in the schematic library per CLB see Figure 9 The four buffers are individually configurable through four configuration bits to operate as simple non inverting buffers or in 3 state mode When in 3 state mode the CLB output enable TS control signal drives the enable to all four buffers Each TBUF can drive up to two horizontal and or two vertical Longlines These 3 state buff ers can be used to implement multiplexed or bidirectional buses on the horizontal or vertical longlines saving logic resources The 3 state buffer enable is an active High 3 state i e an active Low enable as shown in Table 4 Table 4 Three State Buffer Functionality Another 3 state buffer with similar
95. eristic Guidelines The following guidelines reflect worst case values over the recommended operating conditions They are expressed in units of nanoseconds and apply to all XC5200 devices unless otherwise noted Speed Grade Description Symbol Setup and Hold Input TDI to clock setup time Input TDI to clock TrckTDI hold time Input TMS to clock TCK setup time Input TMS to clock hold time Propagation Delay Clock TCK to Pad TDO Clock Clock TCK High Clock Low Fmax MHz FMAx Note 1 Input pad setup and hold times are specified with respect to the internal clock 7 132 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays Device Specific Pinout Tables Device specific tables include all packages for each XC5200 Series device They follow the pad locations around the die and include boundary scan register locations Pin Locations for XC5202 Devices The following table may contain pinout information for unsupported device package combinations Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information Pin Description VQ64 PC84
96. evice s configu ration memory is not already full The status pin DOUT is pulled Low two internal oscillator cycles after INIT is recog nized as High and remains Low until the device s configu ration memory is full DOUT is then pulled High to signal the next device in the chain to accept the configuration data on the 00 07 bus The DONE pins of all devices in the chain should be tied together with one or more active internal pull ups large number of devices are included in the chain deacti vate some of the internal pull ups since the Low driving DONE pin of the last device in the chain must sink the cur rent from all pull ups in the chain The DONE pull up is activated by default It can be deactivated using an option in the bitstream generation software XC5200 devices in Express mode are always synchronized to DONE The device becomes active after DONE goes High DONE is an open drain output With the DONE pins tied together therefore the external DONE signal stays low until all devices are configured then all devices in the daisy chain become active simultaneously If the DONE pin of a device is left unconnected the device becomes active as soon as that device has been configured Express mode is selected by a 010 on the mode pins M2 M1 MO NOTE M2 M1 MO can be shorted to Ground if not used as 3 3 CS1 DOUT To Additional Optional Daisy Chained Devi
97. ffers on all four sides The direct connects are ideal for developing customized RPM cells Using direct connects improves the macro per formance and leaves the other routing channels intact for improved routing Direct connects can also route through a CLB using one of the four cell feedthrough paths General Routing Matrix The General Routing Matrix shown in Figure 15 provides flexible bidirectional connections to the Local Interconnect 7 94 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays Matrix through a hierarchy of different length metal seg ments in both the horizontal and vertical directions A pro Six Levels of Routing Hierarchy 1 gt Single length Lines 2 XX Double length Lines 3 Direct Connects 4 Longlines and Global Lines 5 LIM Local Interconnect Matrix Logic Cell Feedthrough 6 Path Contained within each Logic Cell X4963 Direct Connects Figure 15 5200 Interconnect Structure grammable interconnect point PIP establishes an electri associated routing segments combine to provide a power cal connection between two wire segments The PIP con ful interconnect hierarchy sisting of a pass transistor switch controlled by a memory element provides bidirectional in some cases unidirec tional connection between two adjoining wires A co
98. gline and global line connections to the general routing matrix are unidirectional with the signal direction from these lines toward the routing matrix Longlines Longlines are used for high fan out signals 3 state busses low skew nets and faraway destinations Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half lines Longlines are driven by the 3 state buffers in each CLB and are driven by similar buff ers at the periphery of the array from the VersaRing Interface Bus oriented designs are easily implemented by using Lon glines in conjunction with the 3 state buffers in the CLB and in the VersaRing Additionally weak keeper cells at the periphery retain the last valid logic level on the Longlines when all buffers are in 3 state mode Longlines connect to the single length or double length lines or to the logic inside the CLB through the General Routing Matrix The only manner in which a Longline can be driven is through the four 3 state buffers therefore a Longline to Longline or single line to Longline connection through PIPs in the General Routing Matrix is not possible Again as a general rule long and global line connections to the General Routing Matrix are unidirectional with the signal direction from these lines toward the routing matrix The XC5200 family has no pull ups on the ends of the Lon glines sou
99. he lead device on its DOUT pin The RDY BUSY output from the lead FPGA acts as a hand shake signal to the microprocessor RDY BUSY goes Low when a byte has been received and goes High again when the byte wide input buffer has transferred its information into the shift register and the buffer is ready to receive new data A new write may be started immediately as soon as the RDY BUSY output has gone Low acknowledging receipt of the previous data Write may not be terminated until RDY BUSY is High again for one CCLK period Note that RDY BUSY is pulled High with a high impedance pull up prior to INIT going High The length of the BUSY signal depends on the activity in the UART If the shift register was empty when the new byte was received the BUSY signal lasts for only two CCLK periods If the shift register was still full when the new byte was received the BUSY signal can be as long as nine CCLK periods Note that after the last byte has been entered only seven of its bits are shifted out CCLK remains High with DOUT equal to bit 6 the next to last bit of the last byte entered RDY BUSY The READY BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaran teed to be longer than 10 CCLK periods Status Read The logic AND condition of the CSO CS1 and RS inputs puts the device status on the Data bus D7 High indicates Ready D7 L
100. heir inputs This method is an improvement over bed of nails testing It avoids the need to over drive device outputs and it reduces the user interface to four pins An optional fifth pin a reset for the control logic is described in the standard but is not implemented in Xilinx devices The dedicated on chip logic implementing the IEEE 1149 1 functions includes a 16 state machine an instruction regis ter and a number of data registers The functional details can be found in the IEEE 1149 1 specification and are also discussed in the Xilinx application note XAPP 017 Bound ary Scan XC4000 and XC 5200 Series devices Figure 19 on page 99 is a diagram of the XC5200 Series boundary scan logic It includes three bits of Data Register per IOB the IEEE 1149 1 Test Access Port controller and the Instruction Register with decodes The public boundary scan instructions are always available prior to configuration After configuration the public instruc tions and any USERCODE instructions are only available if specified in the design While SAMPLE and BYPASS are available during configuration it is recommended that boundary scan operations not be performed during this transitory period In addition to the test instructions outlined above the boundary scan circuitry can be used to configure the FPGA device and to read back the configuration data All of the XC4000 boundary scan modes are supported in the XC5200 family Three addi
101. itstream and store it in an internal register The length count varies according to the number of devices and the composition of the daisy chain Each device also counts the number of CCLKs during configuration Two conditions have to be met in order for the DONE pin to go high the chip s internal memory must be full and the configuration length count must be met exactly This is important because the counter that determines when the length count is met begins with the very first CCLK not the first one after the preamble Therefore if a stray bit is inserted before the preamble or the data source is not ready at the time of the first CCLK the internal counter that holds the number of will be one ahead of the actual number of data bits read At the end of configuration the configuration memory will be full but the number of bits in the internal counter will not match the expected length count As a consequence a Master mode device will continue to send out CCLKs until the internal counter turns over to zero and then reaches the correct length count a second time This will take several seconds 224 CCLK period which is sometimes interpreted as the device not config uring at all If it is not possible to have the data ready at the time of the first CCLK the problem can be avoided by increasing the number in the length count by the appropriate value In Express mode there is no length count The DONE pi
102. king Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system This capability gives the sys tem designer a new degree of freedom not available with any other type of logic Hardware can be changed as easily as software Design updates or modifications are easy and can be made to products already in the field An FPGA can even be recon figured dynamically to perform different functions at differ ent times Reconfigurable logic can be used to implement system self diagnostics create systems capable of being reconfig ured for different environments or operations or implement multi purpose hardware for a given application As an added benefit using reconfigurable FPGA devices simpli fies hardware design and debugging and shortens product time to market Detailed Functional Description Configurable Logic Blocks CLBs Figure 4 shows the logic in the XC5200 CLB which con sists of four Logic Cells LC 3 0 Each Logic Cell consists of an independent 4 input Lookup Table LUT and a D Type flip flop or latch with common clock clock enable and clear but individually selectable clock polarity Addi tional logic features provided in the CLB are An independent 5 LUT by combining two 4 input LUTs High speed carry propagate logic High speed pattern decoding High speed direct connection to flip flop D inputs Individual selection of ei
103. llec tion of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments A hierarchy of PIPs and Forty bidirectional single length segments CLB provide ten routing channels to each of the four neighboring CLBs in four directions Sixteen bidirectional double length segments provide four routing channels to each of four other non neighboring CLBs in four directions Eight horizontal and eight vertical bidirectional Longline November 5 1998 Version 5 2 7 95 XC5200 Series Field Programmable Gate Arrays 5 XILINX segments span the width and height of the chip respectively Two low skew horizontal and vertical unidirectional glo bal line segments span each row and column of the chip respectively Single and Double Length Lines The single and double length bidirectional line segments make up the bulk of the routing channels The dou ble length lines hop across every other CLB to reduce the propagation delays in speed critical nets Regenerating the signal strength is recommended after traversing three or four such segments Xilinx place and route software auto matically connects buffers in the path of the signal as nec essary Single and double length lines cannot drive onto Longlines and global lines Longlines and global lines can however drive onto single and double length lines As a general rule Lon
104. lly 2 us The master device waits an additional 32 us to 256 us nominally 64 128 to provide adequate time for all of the slave devices to recognize the release of INIT as well Then the master device enters the Configuration phase Boundary Scan Instructions Available Generate One Time Out Pulse EXTEST SAMPLE PRELOAD BYPASS Completely Clear Configuration CONFIGURE Memory 1 3 per Frame only when PROGRAM High INIT High if laster _ Yes Sample Mode Lines Master CCLK Goes Active after 50 to 250 0 1 Configuration Data Frame Yes INIT Low and Stop No LDC Output SAMPLE PRELOAD BYPASS Pass Configuration Data to DOUT Start Up Sequence EXTEST SAMPLE PRELOAD BYPASS 10 Active USER 1 If Boundary Scan USER 2 is Selected CONFIGURE X9017 READBACK Figure 24 Configuration Sequence 7 108 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays V Length Count Match CCLK Period 9 Global Reset Finished no more DONE configuration clocks needed XC3000 Daisy chain lead device must have latest F VO Heavy lines describe default timing XC5200 CCLK_NOSYNC 2 4 DONE IN F DONE C1 2 xow o
105. lso be derived indirectly from the Global Buffer specifications The delay calculator uses this indirect method and may overestimate because of worst case assumptions When there is a discrepancy between these two methods the values listed below should be used and the derived values should be considered conservative overestimates Speed Grade 6 5 4 3 Description Symbol Device no ino Global Clock to Output Pad fast Tickor 5202 16 9 15 1 10 9 9 8 5204 17 1 15 3 9 9 Max XC5206 11 9 10 8 gt XC5210 12 8 11 2 Global Clock to Output Beta 5215 128 17 Global Clock to Output Pad slew limited 5202 12 6 11 5 5204 13 3 11 9 BUFG Connec N i 5206 13 6 12 5 D gt 5210 21 7 19 0 12 9 Global Clock to Output Delay 2 XC5215 24 3 21 2 13 1 Input Set up Time no delay to CLB Flip Flop 5202 1 9 1 9 IOB NODELAY 5204 1 9 1 9 Input 4 Min 5206 1 9 19 Set up 2 BUFG XC5215 1 7 1 7 Input Hold Time no delay to CLB Flip Flop XC5202 3 5 3 5 IOB NODELAY Direct 5204 3 8 3 6 al 2 Min XC5206 4 4 43 ime 2 gt gt 5210 49 48 5215 5 7 5 6 Input Set up Time with delay to Flip Flop DI Input XC5202 7 3 6 6 6 6 IOB 52
106. n for each device goes High when the device has received its quota of configuration data Wiring the DONE pins of sev eral devices together delays start up of all devices until all are fully configured Note that DONE is an open drain output and does not go High unless an internal pull up is activated or an external pull up is attached The internal pull up is activated as the default by the bitstream generation software Release of User After DONE Goes High By default the user I O are released one CCLK cycle after the DONE pin goes High If CCLK is not clocked after DONE goes High the outputs remain in their initial state 3 stated with a 20 kO 100 kO pull up The delay from November 5 1998 Version 5 2 7 111 XC5200 Series Field Programmable Gate Arrays XILINX DONE High to active user I O is controlled by an option to the bitstream generation software Q3 STARTUP Q2 DONE IOBs OPERATIONAL PER CONFIGURATION GLOBAL RESET OF POTETE 1 GR ENABLE GR INVERT STARTUP GR STARTUP GTS GTS INVERT GTS ENABLE ALL CLB FLIP FLOPS LATCHES CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC SEE LIBRARIES GUIDE GLOBAL 3 STATE OF ALL IOBs e X lt DONE FINISHED ENABLES BOUNDARY SCAN READBACK AND CONTROLS THE OSCILLATOR Qo Q1 Q2 Q3 Q4 FULL
107. nd inputs There are three self loading Master Configuration is the process of loading design specific pro gramming data into one or more FPGAs to define the func tional operation of the internal blocks their interconnections This is somewhat like loading the com mand registers of a programmable peripheral chip XC5200 Series devices use several hundred bits of config uration data per CLB and its associated interconnects Each configuration bit defines the state of a static memory cell that controls either a function look up table bit a multi plexer input or an interconnect pass transistor The devel opment system translates the design into a netlist file It automatically partitions places and routes the logic and generates the configuration data in PROM format Special Purpose Pins Three configuration mode pins M2 M1 MO are sampled prior to configuration to determine the configuration mode After configuration these pins can be used as auxiliary connections The development system does not use these resources unless they are explicitly specified in the design entry This is done by placing a special pad symbol called MD2 1 or MDO instead of the input or output pad sym bol In XC5200 Series devices the mode pins have weak pull up resistors during configuration With all three mode pins High Slave Serial mode is selected which is the most popular configuration mode Therefore for the most com mon co
108. nfiguration mode the mode pins can be left uncon nected Note however that the internal pull up resistor value can be as high as 100 After configuration these pins can individually have weak pull up or pull down resis tors as specified in the design A pull down resistor value of 3 3kQ is recommended These pins are located in the lower left chip corner and are near the readback nets This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of MO RT M1 RD is desired Configuration Modes XC5200 devices have seven configuration modes These modes are selected by a 3 bit input code applied to the M2 modes two Peripheral modes and a Serial Slave mode Table 10 Configuration Modes Mode 2 1 Master Serial 0 0 0 output Bit Serial Slave Serial 1 1 1 input Bit Serial Master 1 0 0 output Byte Wide Parallel Up increment from 00000 Master 1 1 0 output Byte Wide Parallel Down decrement from 3FFFF Peripheral 0 1 1 input Byte Wide Synchronous Peripheral 1 0 1 output Byte Wide Asynchronous Express 0 1 0 input Byte Wide Reserved 0 0 1 Note Peripheral Synchronous can be considered byte wide Slave Parallel which is used primarily for daisy chained devices The sev enth mode called Express mode is an additional slave mode that allows high speed parallel configuration The coding
109. nish point F The different families generate or require different numbers of additional CCLK pulses until they reach F Not reaching F means that the device does not really finish its configuration although DONE may have gone High the outputs became active and the internal reset was released For the XC5200 Series device not reaching F means that read back cannot be initiated and most boundary scan instruc tions cannot be used The user has some control over the relative timing of these events and can therefore make sure that they occur at the proper time and the finish point F is reached Timing is con trolled using options in the bitstream generation software XC5200 devices always have the same number of CCLKs in the power up delay independent of the configuration mode unlike the XC3000 XC4000 Series devices To guar antee all devices in a daisy chain have finished the power up delay tie the INIT pins together as shown in Figure 27 XC3000 Master with an XC5200 Series Slave Some designers want to use an XC3000 lead device in peripheral mode and have the pins of the XC5200 Series devices all available for user Figure 22 provides a solution for that case This solution requires one CLB one IOB and pin and an internal oscillator with a frequency of up to 5 MHz as a clock source The XC3000 master device must be config ured with late Internal Reset which is the default option One CLB and one IOB in the lead
110. nput buffer Output Signals Output signals can be optionally inverted within the IOB and pass directly to the pad As with the inputs a CLB flip flop or latch can be used to store the output signal An active High 3 state signal can be used to place the out put buffer in a high impedance state implementing 3 state outputs or bidirectional Under configuration control the output OUT and output 3 state T signals can be inverted The polarity of these signals is independently configured for each IOB The XC5200 devices provide a guaranteed output sink cur rent of 8 mA Supported destinations for XC5200 Series device outputs are shown in Table 6 For a detailed discussion of how to interface between 5 V and 3 3 V devices see the 3V Prod ucts section of The Programmable Logic Data Book An output can be configured as open drain open collector by placing an OBUFT symbol in a schematic or HDL code then tying the 3 state pin T to the output signal and the input pin to Ground See Figure 12 Table 6 Supported Destinations for XC5200 Series Outputs XC5200 Output Mode 5 Destination XC5200 device 3 3 V 4 CMOS threshold inputs Any typical device Voc 3 3 V CMOS threshold inputs Any device 5 V 4 TTL threshold inputs Any device 5 1 CMOS threshold inputs 1 Only if destination device has 5 V tolerant inputs
111. onfiguration process are 3 stated and pulled high with a 20 kQ 100 kQ pull up resistor After configuration if an IOB is unused it is configured as an input with a 20 kQ 100 kQ pull up resistor Device pins for XC5200 Series devices are described in Table 9 Pin functions during configuration for each of the seven configuration modes are summarized in Pin Func November 5 1998 Version 5 2 7 101 XC5200 Series Field Programmable Gate Arrays XILINX tions During Configuration on page 124 in the Configura tion Timing section Table 9 Pin Descriptions 1 0 During After Config Config Pin Description Permanently Dedicated Pins Five or more depending on package connections to the nominal 5 V supply voltage VCC All must be connected and each must be decoupled with 0 01 0 1 uF capacitor to Ground GND Four or more depending on package type connections to Ground All must be con nected During configuration Configuration Clock CCLK is an output in Master modes or Asyn chronous Peripheral mode but is an input in Slave mode Synchronous Peripheral mode and Express mode After configuration CCLK has a weak pull up resistor and CCLK be selected as the Readback Clock There is CCLK High time restriction on XC5200 Series devices except during Readback See Violating the Maximum High and Low Time Specification for the Read
112. ons such as counters adders etc A carry multiplexer CY_MUX sym bol is used to indicate the XC5200 carry logic This symbol represents the dedicated 2 1 multiplexer in each LC that performs the one bit high speed carry propagate per logic cell four bits per CLB While the carry propagate is performed inside the LC an adjacent LC must be used to complete the arithmetic func tion Figure 6 represents an example of an adder function The carry propagate is performed on the CLB shown which also generates the half sum for the four bit adder An adjacent CLB is responsible for XORing the half sum with the corresponding carry out Thus an adder or counter requires two LCs per bit Notice that the carry chain requires an initialization stage which the XC5200 family accomplishes using the carry initialize CY_INIT macro and one additional LC The carry chain can propagate ver tically up a column of CLBs The XC5200 library contains a set of Relationally Placed Macros RPMs and arithmetic functions designed to take advantage of the dedicated carry logic Using and modify ing these macros makes it much easier to implement cus 7 88 November 5 1998 Version 5 2 XILINX 5200 Series Field Programmable Gate Arrays tomized RPMs freeing the designer from the need to become an expert on architectures cascade out out D Q FD X LC3 DO D Q FD x LC2 DO D Q FD X Lc1 Q FD
113. ow indicates Busy through D6 go unconditionally High It is mandatory that the whole start up sequence be started and completed by one byte wide input Otherwise the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the final byte transfer If this transfer does not occur the start up sequence is not com pleted all the way to the finish point F in Figure 25 on page 109 In this case at worst the internal reset is not released At best Readback and Boundary Scan are inhibited The length count value as generated by the software ensures that these problems never occur Although RDY BUSY is brought out as a separate signal microprocessors can more easily read this information on one of the data lines For this purpose D7 represents the RDY BUSY status when RS is Low WS is High and the two chip select lines are both active Asynchronous Peripheral mode is selected by a lt 101 gt on the mode pins M2 M1 OPTIONAL DAISY CHAINED FPGAs XC5200 ASYNCHRO NOUS XC4000E EX A PERIPHERAL 5200 SLAVE ADDRESS ADDRESS DECODE BUS 4 7 47 RS ws CONTROL lt SIGNALS REPROGRAM 33 X9006 Figure 35 Asynchronous Peripheral Mode Circuit Diagram 7 120 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays Wri
114. pin in the FPGA bonded or not it includes three bits for In Out and 3 State Control Non lOB pins have appropriate partial bit population for In or Out only PROGRAM CCLK and DONE are not included in the boundary scan register Each EXTEST CAPTURE DR state captures all In Out and 3 State pins The data register also includes the following non pin bits TDO T and TDO O which are always bits 0 and 1 of the data register respectively and BSCANT UPD which is always the last bit of the data register These three bound ary scan bits are special purpose Xilinx test signals The other standard data register is the single flip flop BYPASS register It synchronizes data being passed through the FPGA to the next downstream boundary scan device The FPGA provides two additional data registers that can be specified using the BSCAN macro The FPGA provides two user pins BSCAN SEL1 and BSCAN SEL2 which are the decodes of two user instructions USER1 and USER2 For these instructions two corresponding pins BSCAN TDO1 BSCAN TDO2 allow user scan data to be shifted out on TDO The data register clock BSCAN DRCK is available for control of test logic which the user may wish to implement with CLBs The NAND of TCK and RUN TEST IDLE is also provided BSCAN IDLE Instruction Set The XC5200 Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data The instruction set i
115. ram Latency Tpi 6 70 us per CLB column CCLK output Delay Ticck 40 375 us period slow 640 3000 5 period fast 100 375 ns Slave and Peripheral Modes Description Symbol Min Max Units Power On Reset Tpor 2 15 ms Program Latency Tp 6 70 us per CLB column CCLK input Delay required 5 us period required 100 5 Note must rise from 2 0 to Vcc in less than 15 ms otherwise delay configuration using PROGRAM until cc 5 valid November 5 1998 Version 5 2 7 125 XC5200 Series Field Programmable Gate Arrays XC5200 Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL M 38510 605 All devices are 100 functionally tested Internal timing parameters are not measured directly They are derived from benchmark timing patterns that are taken at device introduction prior to any process improvements 2 XILINX The following guidelines reflect worst case values over the recommended operating conditions Finished Internal Net tdbk TRIG 0 TRTRC lt 2 sa TRCH f rdbk RIP 5 TRCRR rdbk DATA DUMMY DUMMY VALID N TRCRD e X1790 Description Symbol Min Max Units rdbk TRIG rdbk TRIG setup to initiate and abo
116. rays XILINX XC5200 Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL M 38510 605 All devices are 100 functionally tested Since many internal timing parameters cannot be measured directly they are derived from benchmark timing patterns The following guidelines reflect worst case values over the recommended operating conditions For more detailed more precise and more up to date timing information use the values provided by the timing calculator and used in the simulator Speed Grade 6 5 4 3 Description Symbol Device pm en Global Signal Distribution Tura 5202 9 1 8 5 8 0 6 9 From pad through global buffer to any clock XC5204 z 7 XC5206 9 4 7 XC5210 9 4 7 7 55215 33 1 88 96 XC5200 Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL M 38510 605 All devices are 100 functionally tested Since many internal timing parameters cannot be measured directly they are derived from benchmark timing patterns The following guidelines reflect worst case values over the recommended operating conditions For more detailed more precise and more up to date timing information use the values provided by the timing calculator and used in the simulator Speed Grade 6 5 4 3 T
117. rced by TBUFs unlike the XC4000 Series Con sequently wired functions WAND WORAND and wide multiplexing functions requiring pull ups for undefined states i e bus applications must be implemented in a dif ferent way In the case of the wired functions the same functionality can be achieved by taking advantage of the carry cascade logic described above implementing a wide logic function in place of the wired function In the case of 3 state bus applications the user must insure that all states of the multiplexing function are defined This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated Global Lines Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines as shown in Figure 16 This network is intended for high fanout clocks or other control signals to maximize speed and min imize skewing while distributing the signal to many loads The XC5200 family has a total of four global buffers BUFG symbol in the library each with its own dedicated routing channel Two are distributed vertically and two horizontally throughout the FPGA The global lines provide direct input only to the CLB clock pins The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals Four clock input pads at the corners of the
118. rd party Alliance interfaces Supported by shrink wrap Foundation software Description The XC5200 Field Programmable Gate Array Family is engineered to deliver low cost Building on experiences gained with three previous successful SRAM FPGA fami lies the XC5200 family brings a robust feature set to pro grammable logic design The VersaBlock logic module the VersaRing interface and a rich hierarchy of inter connect resources combine to enhance design flexibility and reduce time to market Complete support for the XC5200 family is delivered through the familiar Xilinx soft ware environment The XC5200 family is fully supported on popular workstation and PC platforms Popular design entry methods are fully supported including ABEL sche matic capture VHDL and Verilog HDL synthesis Design ers utilizing logic synthesis can use their existing tools to design with the XC5200 devices Table 1 XC5200 Field Programmable Gate Array Family Members Device XC5202 XC5204 XC5206 XC5210 XC5215 Logic Cells 256 480 784 1 296 1 936 Max Logic Gates 3 000 6 000 10 000 16 000 23 000 Typical Gate Range 2 000 3 000 4 000 6 000 6 000 10 000 10 000 16 000 15 000 23 000 VersaBlock Array 8x8 10 x 12 14x14 18x 18 22x22 CLBs 64 120 196 324 484 Flip Flops 256 480 784 1 296 1 936 84 124 148 196 244 TBUFs per Longline 10 14 16 20 24 November 5 1998 Version 5 2 7 83 XC5200
119. re 2 LC3 DI t F4 t FD D 3 2 LC2 3 2 1 H FD D LC1 1 1 DI 1 1 DI LCO t FD F3 34 gt 1 1 F4 t FD F3 9 4 2 4 4957 Figure 4 Configurable Logic Block The LIM provides 100 connectivity of the inputs and out puts of each LC in a given CLB The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB The LIM connects to the GRM via 24 bidirectional nodes The direct connects allow immediate connections to neigh boring CLBs once again without using any of the general interconnect These two layers of local routing resource improve the granularity of the architecture effectively mak ing the XC5200 family a sea of logic cells Each Versa Block has four 3 state buffers that share a common enable line and directly drive horizontal and vertical Lon glines creating robust on chip bussing capability The VersaBlock allows fast local implementation of logic func tions effectively implementing user designs in a hierarchi cal fashion These resources also minimize local routing congestion and improve the efficiency of the general inter connect which is used for connecting larger groups of logic
120. ring configuration a Low on this output indicates that a configuration data error has occurred After the I O go active INIT is user programmable pin GCK1 GCK4 Weak Pull up Lor Four Global inputs each drive a dedicated internal global net with short delay and min imal skew These internal global nets can also be driven from internal logic If not used to drive a global net any of these pins is a user programmable pin The GCK1 GCK4 pins provide the shortest path to the four Global Buffers Any input pad symbol connected directly to the of a BUFG symbol is automatically placed on one of these pins CSO CS1 WS RS These four inputs used in Asynchronous Peripheral mode The is selected when 50 is Low 1 is High While the chip is selected a Low on Write Strobe WS loads the data present on the DO D7 inputs into the internal data buffer A Low on Read Strobe RS changes D7 into a status output High if Ready Low if Busy and drives 00 D6 High In Express mode CS1 is used as a serial enable signal for daisy chaining WS and RS should be mutually exclusive but if both are Low simultaneously the Write Strobe overrides After configuration these are user programmable pins 17 During Master Parallel configuration these 18 output pins address the configuration EPROM After configuration they are user programmable pins
121. rt Readback 1 200 5 5 rdbk TRIG hold to initiate and abort Readback 2 TRCRT 50 ns 1 rdbk DATA delay 7 250 ns rdbk RIP delay 6 TRCRR 250 ns High time 5 TRCH 250 500 ns Low time 4 250 500 ns Note 1 Timing parameters apply to all speed grades Note 2 rdbk TRIG is High prior to Finished Finished will trigger the first Readback 7 126 November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays XC5200 Switching Characteristics Definition of Terms In the following tables some specifications may be designated as Advance or Preliminary These terms are defined as follows Advance Initial estimates based on simulation and or extrapolation from other speed grades devices or device families Use as estimates not for production Preliminary Based on preliminary characterization Further changes are not expected Unmarked Specifications not identified as either Advance or Preliminary are to be considered Final XC5200 Operating Conditions Supply voltage relative to GND Industrial 40 C to 100 C junction High level input voltage TTL configuration Low level input voltage TTL configuration Low level input voltage CMOS configuration 0 20 Voc Input signal transition time 250 ns Symbol Description Min Max Units Vou High level output voltage 8 0 mA Veg
122. s coded as shown in Table 7 Table 7 Boundary Scan Instructions Bit Sequence The bit sequence within each IOB is 3 State Out In The data register cells for the TAP pins TMS TCK and TDI have an OR gate that permanently disables the output buffer if boundary scan operation is selected Conse quently it is impossible for the outputs in IOBs used by TAP inputs to conflict with TAP operation TAP data is taken directly from the pin and cannot be overwritten by injected boundary scan data The primary global clock inputs PGCK1 PGCK4 are taken directly from the pins and cannot be overwritten with boundary scan data However if necessary it is possible to drive the clock input from boundary scan The external clock source is 3 stated and the clock net is driven with boundary scan data through the output driver in the clock pad IOB If the clock pad IOBs are used for non clock signals the data may be overwritten normally Pull up and pull down resistors remain active during boundary scan Before and during configuration all pins are pulled up After configuration the choice of internal pull up or pull down resistor must be taken into account when designing test vectors to detect open circuit PC traces From a cavity up view of the chip as shown in XDE or Epic starting in the upper right chip corner the boundary scan data register bits are ordered as shown in Table 8 The device specific pinout tables for the XC5200 Series
123. s shown in Figure 21 An independent matrix of Vcc and Ground lines supplies the interior logic of the device This power distribution grid provides a stable supply and ground for all internal logic providing the external package power pins are all connected and appropriately decoupled Typically a 0 1 uF capacitor connected near the Vcc and Ground pins of the package will provide adequate decou pling Output buffers capable of driving sinking the specified 8 mA loads under specified worst case conditions may be capa ble of driving sinking up to 10 times as much current under best case conditions Noise can be reduced by minimizing external load capaci tance and reducing simultaneous output transitions in the same direction It may also be beneficial to locate heavily loaded output buffers near the Ground pads The I O Block output buffers have a slew rate limited mode default which should be used where output rise and fall times are not speed critical GND Ground Ring for Drivers Logic Power Grid X5422 Figure 21 XC5200 Series Power Distribution Pin Descriptions There are three types of pins in the XC5200 Series devices Permanently dedicated pins e User I O pins that can have special functions Unrestricted user programmable pins Before and during configuration all outputs not used for the c
124. t USER SLAVE MASTER SER SYN PERIPH ASYN PERIPH MASTER HIGH MASTER LOW EXPRESS OPERATION lt 1 1 1 gt lt 0 0 0 gt lt 0 1 1 gt lt 1 0 1 gt lt 1 1 0 gt lt 1 0 0 gt lt 0 1 0 gt 16 16 GCK1 I O A17 A17 y o TDI TDI TDI TDI TDI TDI TDI TDI I O TCK TCK 5 5 5 5 5 5 5 TMS I O M1 HIGH M1 LOW I M1 HIGH M1 LOW M1 HIGH M1 LOW M1 HIGH 1 MO HIGH LOW I MO HIGH MO HIGH MO LOW I MO LOW MO LOW I M2 HIGH M2 LOW 2 LOW M2 HIGH M2 HIGH M2 HIGH M2 LOW 2 HDC HIGH HDC HIGH HDC HIGH HDC HIGH HDC HIGH VO LDC LOW LDC LOW LDC LOW LDC LOW LDC LOW LDC LOW LDC LOW INIT ERROR INIT ERROR INIT ERROR INIT ERROR INIT ERROR INIT ERROR INIT ERROR DONE DONE DONE DONE DONE DONE DONE DONE PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM 1 PROGRAM DATA 7 DATA 7 DATA 7 7 7 GCK3 I O DATA 6 DATA 6 DATA 6 DATA 6 DATA 6 5 5 5 5 5 CSO 1 4 DATA 4 DATA 4 4 4 3 DAT
125. t result in a positive hold time requirement A positive hold time requirement can lead to unreliable temperature or processing dependent operation The input flip flop setup time is defined between the data measured at the device I O pin and the clock input at the CLB not at the clock pin Any routing delay from the device clock pin to the clock input of the CLB must there fore be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins A short specified setup time might therefore result in a negative setup time at the device pins a positive hold time requirement When a delay is inserted on the data line more clock delay can be tolerated without causing a positive hold time requirement Sufficient delay eliminates the possibility of a data hold time requirement at the external pin The maxi mum delay is therefore inserted as the software default The XC5200 IOB has a one tap delay element either the delay is inserted default or it is not The delay guarantees a zero hold time with respect to clocks routed through any of the XC5200 global clock buffers See Global Lines on page 96 for a description of the global clock buffers in the XC5200 For a shorter input register setup time with November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays XILINX non zero hold attach a NODELAY attribute or property to the flip flop or i
126. te to LCA Read Status WS CSO RS CS0 RS CS1 WS CS1 D0 D7 D7 CCLK RDY BUSY X6097 Description Symbol Min Max Units Effective Write time 1 100 ns Writ CSO WS Low RS CS1 High DIN setup time 2 Tie 60 ns DIN hold time 3 Tep 0 ns RDY BUSY delay after end of 4 60 5 Write or Read RDY BUSY active after beginning 7 60 ns RDY of Read RDY BUSY Low output Note 4 6 2 9 CCLK periods Notes 1 Configuration must be delayed until INIT pins of all daisy chained FPGAs are high 2 The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of internal timing generator for CCLK 3 CCLK and DOUT timing is tested in slave mode 4 indicates that the double buffered parallel to serial converter is not yet ready to receive new data The shortest occurs when byte is loaded into an empty parallel to serial converter The longest Tgysy occurs when a new word is loaded into the input register before the second level buffer has started shifting out data This timing diagram shows very relaxed requirements Data need not be held beyond the rising edge of WS RDY BUSY will go active within 60 ns after the end of WS A new write may be asserted immediately after RDY BUSY goes Low but write may not be terminated until RDY BUSY has been High for one CCLK period Figure 36 Asynchronous Peripher
127. ter requires the same number of function generators in both families XC3000 has no dedi cated carry XC4000 Spartan family XC5200 lookup tables are opti mized for cost and hence cannot implement RAM Input Output Block Resources The XC5200 family maintains footprint compatibility with the XC4000 family but not with the XC3000 family To minimize cost and maximize the number of I O per Logic Cell the XC5200 I O does not include flip flops or latches For high performance paths the XC5200 family provides direct connections from each IOB to the registers in the adjacent in order to emulate registers Each XC5200 Pin provides a programmable delay ele ment to control input set up time This element can be used to avoid potential hold time problems Each XC5200 Pin is capable of 8 mA source and sink currents IEEE 1149 1 type boundary scan is supported in each XC5200 I O Table 2 Xilinx Field Programmable Gate Array Families Parameter XC5200 Spartan XC4000 XC3000 a enr CLB inputs 20 9 9 5 CLB outputs 12 4 4 2 Global buffers 4 8 8 2 User RAM no yes yes no Edge decoders no no yes no Cascade chain yes no no no Fast carry logic yes yes yes no Internal 3 state yes yes yes yes Boundary scan yes yes yes no Slew rate control yes yes yes yes Routing Resources The XC5200 family provides a flexible coupling of logic and local routing reso
128. th Figure 14 VersaBlock Details CLB inputs have several possible sources the 24 signals from the GRM 16 direct connections from neighboring VersaBlocks four signals from global low skew buffers and the four signals from the CLB output multiplexers Unlike the output multiplexers the input multiplexers are not fully populated i e only a subset of the available sig nals can be connected to a given CLB input The flexibility of LUT input swapping and LUT mapping compensates for this limitation For example if 2 input gate is required it can be mapped into any of the four LUTs and use any two of the four inputs to the LUT Direct Connects The unidirectional direct connect segments are connected to the logic input output pins through the CLB input and out put multiplexer arrays and thus bypass the general routing matrix altogether These lines increase the routing channel utilization while simultaneously reducing the delay incurred in speed critical connections X5724 The direct connects also provide a high speed path from the edge CLBs to the VersaRing input output buffers and thus reduce pin to pin set up time clock to out and combi national propagation delay Direct connects from the input buffers to the CLB DI pin direct flip flop input are only available on the left and right edges of the device CLB look up table inputs and combinatorial registered outputs have direct connects to input output bu
129. ther a transparent level sensitive latch or a D flip flop Four 3 state buffers with a shared Output Enable 5 Input Functions Figure 5 illustrates how the outputs from the LUTs from LCO and LC1 can be combined with a 2 1 multiplexer F5_MUX to provide a 5 input function The outputs from the LUTs of LC2 and be similarly combined DI FD cE cK 100 5 Input Function M Figure 5 Two LUTs in Parallel Combined to Create 5 input Function November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays 2 XILINX A carry out A3 DO or gt FD F4 A3 and B3 to any two d x half sum3 F1 x sum3 gt gt LC3 LC3 A2 2 or B2 D Q FD F4 A2 and B2 to any two x half sum2 x 2 gt LC2 LC2 1 carry1 1 mm po Bi D Q FA FD A1 and B1 F2 to any two x half sumi gt sum1 gt gt LI DI FD 4 i E t t F2 o any two x half sumO m X gt LCO Initialization of carry chain One Logic Cell cl CE CK LCO X5709 Figure 6 XC5200 CY_MUX Used for Adder Carry Propagate Carry Function The XC5200 family supports a carry logic feature that enhances the performance of arithmetic functi
130. tional outputs for the User Register are provided Reset Update and Shift repre November 5 1998 Version 5 2 XILINX XC5200 Series Field Programmable Gate Arrays senting the decoding of the corresponding state of the boundary scan internal state machine DATA IN sd i e IOB O IOB T 8 4 IOB I IOB O IOB T 1 n 8 ety o 1 de IOB I o LE IOB O DATAOUT UPDATE EXTEST SHIFT CLOCK DATA CAPTURE REGISTER 1523 01 Figure 19 XC5200 Series Boundary Scan Logic November 5 1998 Version 5 2 7 99 XC5200 Series Field Programmable Gate Arrays XILINX XC5200 Series devices can also be configured through the boundary scan logic See XAPP 017 for more information Data Registers The primary data register is the boundary scan register For each IOB
131. tionally tested Since many internal timing parameters cannot be measured directly they are derived from benchmark timing patterns The following guidelines reflect worst case values over the recommended operating conditions For more detailed more precise and more up to date timing information use the values provided by the timing calculator and used in the simulator Speed Grade Description Symbol Input Propagation Delays from CMOS or TTL Levels Pad to no delay Pad to with delay Output Propagation Delays to CMOS or TTL Levels Output O to Pad fast Output O to Pad slew limited From clock CK to output pad fast using direct connect between Q and output O From clock CK to output pad slew limited using direct connect be tween Q and output O 3 state to Pad active fast 3 state to Pad active slew limited Internal GTS to Pad active Trsows Terts Note 1 Timing is measured at pin threshold with 50 pF external capacitance loads Slew limited output rise fall times are approximately two times longer than fast output rise fall times 2 Unused and unbonded IOBs are configured by default as inputs with internal pull up resistors 3 Timing is based upon the 5215 device For other devices see Timing Calculator November 5 1998 Version 5 2 7 131 XC5200 Series Field Programmable Gate Arrays XILINX XC5200 Boundary Scan JTAG Switching Charact
132. ts The source of a storage element data input is programma ble It is driven by the function F or by the Direct In DI block input The flip flops or latches drive the Q CLB out puts Four fast feed through paths from DI to DO are available as shown in Figure 4 This bypass is sometimes used by the automated router to repower internal signals In addi tion to the storage element Q and direct DO outputs there is a combinatorial output X that is always sourced by the Lookup Table The four edge triggered D type flip flops or level sensitive latches have common clock CK and clock enable CE inputs Any of the clock inputs can also be permanently enabled Storage element functionality 15 described in Table 3 Clock Input The flip flops can be triggered on either the rising or falling clock edge The clock pin is shared by all four storage ele ments with individual polarity control Any inverter placed on the clock input is automatically absorbed into the CLB Clock Enable The clock enable signal CE is active High The CE pin is shared by the four storage elements If left unconnected for any the clock enable for that storage element defaults to the active state CE is not invertible within the CLB Clear An asynchronous storage element input CLR can be used to reset all four flip flops or latches in the CLB This input November 5 1998 Version 5 2 7 89 XC5200 Series Field Programmable Gate Arrays
133. urces called the VersaBlock The 5200 VersaBlock element includes the CLB a Local Interconnect Matrix LIM and direct connects to neighboring Versa Blocks The XC5200 provides four global buffers for clocking or high fanout control signals Each buffer may be sourced by means of its dedicated pad or from any internal source Each XC5200 TBUF can drive up to two horizontal and two vertical Longlines There are no internal pull ups for 5200 Longlines Configuration and Readback The XC5200 supports a new configuration mode called Express mode XC4000 Spartan family The XC5200 family provides a global reset but not a global set 5200 devices use a different configuration process than that of the XC3000 family but use the same process as the 4000 and Spartan families XC3000 family Although their configuration processes dif fer XC5200 devices may be used in daisy chains with XC3000 devices XC3000 family The XC5200 PROGRAM pin is a sin gle function input pin that overrides all other inputs The PROGRAM pin does not exist in XC3000 7 84 November 5 1998 Version 5 2 XC5200 Series Field Programmable Gate Arrays XC3000 family XC5200 devices support an additional pro gramming mode Peripheral Synchronous Input Output Blocks 1088 XC3000 family The XC5200 family does support Power down but offers a Global 3 state input that does not reset any flip flops VersaRing
134. ve and recognize the six bytes of pre amble and length count irrespective of the level on CS1 but subsequent frame data is accepted only when CS1 is High and the device s configuration memory is not already full Setting CCLK Frequency For Master modes CCLK can be generated in one of three frequencies In the default slow mode the frequency is nominally 1 MHz In fast CCLK mode the frequency is nominally 12 MHz In medium CCLK mode the frequency is nominally 6 MHz The frequency range is 5096 to 5090 The frequency is selected by an option when running the bitstream generation software If an XC5200 Series Master is driving an XC3000 or XC2000 family slave slow CCLK mode must be used Slow mode is the default Table 11 XC5200 Bitstream Format Data Type Value Occurrences Fill Byte 11111111 Once per bit Preamble 11110010 stream Length Counter COUNT 23 0 Fill Byte 11111111 7 106 November 5 1998 Version 5 2 XILINX 5200 Series Field Programmable Gate Arrays Table 11 XC5200 Bitstream Format Data Type Value Occurrences Start Byte 11111110 Once per data Data Frame DATA N 1 0 frame Cyclic Redundancy Check CRC 3 0 or Constant Field Check 0110 Fill Nibble 1111 Extend Write Cycle FFFFFF Postamble 11111110 Once per de Fill Bytes 30 Start Up Byte FF Once per bit stream Bits per Frame N depends on
135. y the end of the time out and must not dip below it thereafter There is no distinction between master and slave modes with regard to the time out delay Instead the INIT line is used to ensure that all daisy chained devices have com pleted initialization Since XC2000 devices do not have this signal extra care must be taken to guarantee proper oper ation when daisy chaining them with XC5200 devices For proper operation with XC3000 devices the RESET signal which is used in XC3000 to delay configuration should be connected to INIT If the time out delay is insufficient configuration should be delayed by holding the INIT pin Low until the power supply has reached operating levels This delay is applied only on power up It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin Low During all three phases Power on Initialization and Configuration DONE is held Low HDC LDC and INIT are active DOUT is driven and all buffers are dis abled Initialization This phase clears the configuration memory and estab lishes the configuration mode The configuration memory is cleared at the rate of one frame per internal clock cycle nominally 1 MHz An open drain bidirectional signal INIT is released when the configuration memory is completely cleared The device then tests for the absence of an external active low level on INIT The mode lines are sampled two internal clock cycles later nomina

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